RT6551B_技术文档

®

RT6551A/B

Complete DDR Memory Power Supply Controller

General Description

The RT6551A/B provides a complete power supply for

DDR2/DDR3/DDR3L/LPDDR3/DDR4 memory systems. It

integrates a synchronous PWM Buck controller with a

1.5Asink/source tracking linear regulator and buffered low

noise reference.

RT6551A/B supports all of the sleep state controls placing

VTT at high-Z in S3 and discharging VDDQ, VTT and

VTTREF (soft-off) in S4/S5.

The RT6551A/B provides protections including OVP, UVP,

and thermal shutdown. The RT6551A/B is available in the

WQFN-20L 3x3 package.

The PWM controller provides the low quiescent current,

high efficiency, excellent transient response, and highDC

output accuracy needed for stepping down high-voltage

batteries to generate low-voltage chipset RAM supplies

in notebook computers. The constant on-time PWM

control scheme handles wide input/output voltage ratios

with ease and provides 100ns “instant-on” response to

load transients while maintaining a relatively constant

switching frequency.

Applications

 DDR2/DDR3/DDR3L/LPDDR3/DDR4 Memory Power

Supplies

 Notebook computers

 SSTL18, SSTL15 and HSTL bus termination

Pin Configurations

The RT6551A/B achieves high efficiency at a reduced cost

by eliminating the current-sense resistor found in

traditional current mode PWMs. Efficiency is further

enhanced by its ability to drive very large synchronous

rectifier MOSFETs. The Buck conversion allows this device

to directly step down high-voltage batteries for the highest

possible efficiency.

(TOP VIEW)

20 19 18 17 16

1

2

3

4

5

15

14

13

12

11

VTTGND

VTTSNS

GND

VTTREF

VDDQ

LGATE

PGND

CS

VDD

VID

GND

21

6

7

8

9 10

The 1.5A sink/source LDO maintains fast transient

response only requiring a 10μF ceramic output capacitor.

In addition, the LDO supply input is available externally

to significantly reduce the total power losses. The

WQFN-20L 3x3

Simplified Application Circuit

V

IN

VDD

TON

V

VDD

RT6551A/B

UGATE

BOOT

PGOOD

VTT

PHASE

LGATE

V

VDDQ

V

TT

VTTSNS

CS

FB

VTTREF

VDDQ

S3

S5

VID

VLDOIN

GND

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is a registered trademark of Richtek Technology Corporation.

DS6551A/B-00 May 2015

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1

RT6551A/B

Features

Ordering Information

RT6551A/B

 PWM Controller

^Adjustable Current Limit with Low-Side R_DS(ON)

Sensing

Package Type

QW : WQFN-20L 3x3 (W-Type)

^Low Quiescent Supply Current

Lead Plating System

^Quick Load-Step Response within 100ns

^1% V_VDDQAccuracy Over Line and Load

^Adjustable 0.675V to 3.3V Output Range for 1.8V

(DDR2), 1.5V (DDR3), 1.35V (DDR3L), 1.2V (LPDDR3)

and 1.2V (DDR4)

G : Green (Halogen Free and Pb Free)

VDDQ and VTT Discharge Control

A : Tracing Mode

B : Non-Tracking Mode

Note :

Richtek products are :

^4.5V to 26V Battery Input Range

 RoHS compliant and compatible with the current require-

ments of IPC/JEDEC J-STD-020.

^Resistor Adjustable Frequency

^Over-/Under-Voltage Protection

 Suitable for use in SnPb or Pb-free soldering processes.

^Internal Voltage Ramp Soft-Start

^Drives Large Synchronous Rectifier MOSFETs

^Power Good Indicator

Marking Information

RT6551AGQW

 1.5A LDO (VTT), Buffered Reference (VTTREF)

^Capable to Sink and Source Up to 1.5A

^LDO Input Available to Optimize Power Losses

^Requires Only 10μF Ceramic Output Capacitor

^Integrated Divider Tracks 1/2 VDDQ for both VTT

and VTTREF

8N= : Product Code

YMDNN : Date Code

8N=YM

DNN

^Accuracy 20mV for both VTTREF and VTT

^Supports High-Z in S3 and Soft-Off in S4/S5

 RoHS Compliant and Halogen Free

RT6551BGQW

8M= : Product Code

YMDNN : Date Code

8M=YM

DNN

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2

DS6551A/B-00 May 2015

RT6551A/B

Functional Pin Description

Pin No.

Pin Name

Pin Function

1

VTTGND

Power Ground for the VTT LDO.

Voltage Sense Input for the VTT LDO. Connect to the terminal of the VTT_LDO

output capacitor.

2

VTTSNS

GND

3, 21

(Exposed Pad)

The exposed pad must be soldered to a large PCB and connected to GND for

maximum power dissipation.

4

5

VTTREF

VDDQ

VTTREF Buffered Reference Output.

Reference Input for VTT and VTTREF.

Feedback Voltage Input. Connect to a resistive voltage divider from VDDQ to

GND to adjust the output voltage.

6

FB

7

8

9

S3

VTT LDO Enable Control Input. Do not leave this pin floating.

PWM Enable Control Input. Do not leave this pin floating.

S5

TON

Set the UGATE On-Time Through a Pull-Up Resistor Connecting to VIN.

Power Good Open-Drain Output. In high state when VDDQ output voltage is

within the target range.

10

PGOOD

11

12

VID

Internal Reference Voltage Setting.

VDD

Supply Voltage Input for the Analog Supply and LGATE Gate Driver.

Current Limit Threshold Setting Input. Connect to GND through the voltage

setting resistor.

13

CS

14

15

PGND

Power Ground for Low-Side MOSFET.

Low-Side Gate Driver Output for VDDQ.

LGATE

Switch Node. External inductor connection for VDDQ and behave as the current

sense comparator input for Low-Side MOSFET R_DS(ON)sensing.

16

PHASE

17

18

19

20

UGATE

BOOT

VLDOIN

VTT

High-Side Gate Driver Output for VDDQ.

Bootstrap Supply for High-Side Gate Driver.

Power Supply for VTT LDO.

Power Output for the VTT LDO.

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3

RT6551A/B

Function Block Diagram

Buck Controller

TRIG

BOOT

On-Time

1-SHOT

V

VDDQ

TON

R

S

Comp

+

-

REF

UGATE

PHASE

Q

Latch

S1

Min. T

OFF

TRIG

+

OV

UV

VDD

Q

115%V

-

REF

Latch

S1

LGATE

PGND

FB

+

-

0.45V

DEM

-

+

85% V

REF

5µA

+

-

SS Int

Thermal

Shutdown

SS Timer

1/10

CS

Reference

Voltage

S5

V

REF

Selector

VDD

VID

PGOOD

VTT LDO

VDDQ

S5

S3

Non-Tracking

Discharge

VTTREF

VLDOIN

Thermal

Shutdown

+

-

+

-

GND

VTTSNS

+

-

VTT

+

-

VTTGND

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4

DS6551A/B-00 May 2015

RT6551A/B

Operation

Over-Voltage Protection (OVP) & Under-Voltage

Protection (UVP)

The RT6551A/B is a constant on-time synchronous step-

down controller. In normal operation, the high-side

N-MOSFET is turned on when the output voltage is lower

than VREF, and is turned off after the internal one-shot

timer expires. While the high-side N-MOSFET is turned

off, the low-side N-MOSFET is turned on to conduct the

inductor current until next cycle begins.

The output voltage is continuously monitored for over-

voltage and under-voltage protection. When the output

voltage exceeds its set voltage threshold( 115% of V_OUT),

UGATE goes low and LGATE is forced high. When the

feedback voltage is less than 0.45V, under-voltage

protection is triggered and then both UGATE and LGATE

gate drivers are forced low. The controller is latched until

VDDis re-supplied and exceeds the POR rising threshold

voltage or S5 is reset.

Soft-Start (SS)

For internal soft-start function, an internal current source

charges an internal capacitor to build the soft-start ramp

voltage. The output voltage will track the internal ramp

voltage during soft-start interval.

VTT Linear Regulator and VTTREF

This VTT linear regulator employs ultimate fast response

feedback loop so that small ceramic capacitors are enough

for keeping track of VTTREF within 40mV at all conditions,

including fast load transient. The VTTREF block consists

of on-chip 1/2 divider, LPF and buffer. This regulator also

has sink and source capability up to 10mA. Bypass

VTTREF toGNDwith a 33nF ceramic capacitor for stable

operation.

PGOOD

The power good output is an open-drain architecture. When

the soft-start is finished, the PGOOD open-drain output

will be high impedance.

Current Limit

The current limit circuit employs a unique “valley” current

sensing algorithm. If the magnitude of the current sense

signal at PHASE is above the current limit threshold, the

PWM is not allowed to initiate a new cycle. The current

limit threshold can be set with an external voltage setting

resistor on the CS pin.

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5

RT6551A/B

Absolute Maximum Ratings (Note 1)

 Supply Input Voltage, TON to GND------------------------------------------------------------------------------------ −0.3V to 32V

 BOOT to PHASE ---------------------------------------------------------------------------------------------------------- −0.3V to 6V

 PHASE to GND

DC----------------------------------------------------------------------------------------------------------------------------- −0.3V to 32V

< 20ns ----------------------------------------------------------------------------------------------------------------------- −8V to 38V

 LGATE toGND

DC----------------------------------------------------------------------------------------------------------------------------- −0.3V to 6V

< 20ns ----------------------------------------------------------------------------------------------------------------------- −2.5V to 7.5V

 UGATE to PHASE

DC----------------------------------------------------------------------------------------------------------------------------- −0.3V to 6V

< 20ns ----------------------------------------------------------------------------------------------------------------------- −5V to 7.5V

 VDD, CS, S3, S5, VTTSNS, VDDQ, VID, VTTREF, VTT, VLDOIN, FB, PGOOD to GND---------------- −0.3V to 6V

 PGND, VTTGNDtoGND ------------------------------------------------------------------------------------------------- −0.3V to 0.3V

 Other Pins------------------------------------------------------------------------------------------------------------------- −0.3V to 6.5V

 PowerDissipation, P_D@ T_A= 25°C

WQFN-20L 3x3 ------------------------------------------------------------------------------------------------------------ 3.33W

 Package Thermal Resistance (Note 2)

WQFN-20L 3x3, θ_JA------------------------------------------------------------------------------------------------------- 30°C/W

WQFN-20L 3x3, θ_JC------------------------------------------------------------------------------------------------------ 7.5°C/W

 Junction Temperature ----------------------------------------------------------------------------------------------------- 150°C

 Lead Temperature (Soldering, 10 sec.)------------------------------------------------------------------------------- 260°C

 Storage Temperature Range -------------------------------------------------------------------------------------------- −65°C to 150°C

 ESD Susceptibility (Note 3)

HBM (Human Body Model)---------------------------------------------------------------------------------------------- 2kV

Recommended Operating Conditions (Note 4)

 Input Voltage, VIN --------------------------------------------------------------------------------------------------------- 4.5V to 26V

 Control Voltage, VDD ----------------------------------------------------------------------------------------------------- 4.5V to 5.5V

 Junction Temperature Range-------------------------------------------------------------------------------------------- −40°C to 125°C

 Ambient Temperature Range-------------------------------------------------------------------------------------------- −40°C to 85°C

Electrical Characteristics

(V_DD= 5V, V_IN= 12V, R_TON= 620kΩ, T_A= 25°C, unless otherwise specified)

Parameter

Symbol

Test Conditions

Min

Typ

Max

Unit

PWM Controller

FB Forced above the Regulation Point,

Quiescent Supply Current

--

135

--

A

V

_S5= 5V, V_S3= 0V, Not Switching

TON Operating Current

I_VLDOINBIAS Current

I_VLDOINStandby Current

R_TON= 620k, V_IN= 12V

--

19

1

--

A

V_S5= V_S3= 5V, VTT = No Load

V_S5= 5V, V_S3= 0, VTT = No Load

0.1

10

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DS6551A/B-00 May 2015

RT6551A/B

Parameter

Symbol

Test Conditions

Min

--

Typ

0.1

0.5

Max

10

5

Unit

A

VDD

TON

--

Shutdown Current

(V = V = 0V)

I

S5/S3

VLDOIN

VID

1

--

1

SHDN

S5

S3

1

--

1

FB Error Comparator

Threshold

V

= 0.675V/0.75V

REF

1

0.675

320

250

--

0

--

1

%

V

REF

VDDQ Voltage Range

Switch Frequency

Minimum Off-Time

3.3

480

550

--

R

V

= 620k, V = 12V,

IN

TON

f

400

15

kHz

ns



SW

= 1.5V, I

= 20A (Note 5)

DDQ

OUT

VDDQ Shutdown Discharge

Resistance

V

= 0V, V = 0V

S5

S3

Current Sensing

CS Pin Source Current

Zero Crossing Threshold

Fault Protection

4.5

5

5.5

10

A

GND  PHASE

5

--

mV

Current Limit (Positive)

GND  PHASE, R = 160k

70

0.4

--

80

0.45

30

90

0.5

--

mV

V

CS

V

Falling. For both VID is high or

FB

Output UV Threshold

UVP Latch Delay

OVP Threshold

V

UVP

low.

FB Forced below UV Threshold

s

%

With Respect to Error Comparator

Threshold

V

OVP

110

--

115

5

120

--

OVP Latch Delay

VDD POR Threshold

FB Forced above OV Threshold

s

Rising Edge, Hysteresis = 120mV,

PWM Disabled below this Level

3.9

4.2

4.5

V

Voltage Ramp Soft-Start Time

UV Blank Time

From S5 Going High to V = 0.675V

--

1

5

--

mS

C

FB

From S5 Signal Going High

Thermal Shutdown

T

SD

165

Driver On-Resistance

UGATE Gate Driver Source

UGATE Gate Driver Sink

LGATE Gate Driver Source

LGATE Gate Driver Sink

R

BOOT PHASE Forced to 5V

BOOT  PHASE Forced to 5V

DL, High State

--

2.5

1.5

2.5

0.8

40

5

3



UGATEsr

R

UGATEsk

R

5

LGATEsr

R

DL, Low State

1.6

--

LGATEsk

LGATE Rising (Phase = 1.5V)

UGATE Rising

Dead Time

ns

40

--

Internal Boost Charging Switch

On-Resistance

VDD to BOOT, 10mA

--

80



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RT6551A/B

Parameter

Logic I/O

Symbol

Test Conditions

Min Typ Max Unit

Logic-High

0.85

--

0

--

0.4

1

S3, S5 Input

Voltage

V

Logic-Low

Logic Input Current

S3, S5 = VDD / GND

1

750

--

A

mV

Logic-High

Logic-Low

--

VID Input

Threshold Voltage

300

PGOOD (Upper Side Threshold Decide by OV Threshold)

Measured at FB, with Respect to

Reference, No Load. Hysteresis = 2%

Trip Threshold (Falling)

Fault Propagation Delay

20

15

10

%

Falling Edge, FB Forced below

PGOOD Trip Threshold

--

5

--

s

Output Low Voltage

Leakage Current

VTT LDO

I_SINK= 1mA

--

0.4

1

V

I_LEAK

High State, Forced to 5V

A

V

_DDQ= V_LDOIN= 1.2V/1.35V/1.5V/

20

30

40

--

20

30

40

1.8V, |I_VTT| = 0A

V_DDQ= V_LDOIN= 1.2V/1.35V/1.5V/

1.8V, |I_VTT| < 1A

VTT Output Tolerance

V_VTTTOL

mV

V_DDQ= V_LDOIN= 1.2V/1.35V,

|I_VTT| < 1.2A

V_DDQ= V_LDOIN= 1.5V/1.8V,

|I_VTT| < 1.5A

VTT Source Current Limit

VTT Sink Current Limit

I_VTTOCLSRCV_TT= 0V

1.6

2.6

3.6

A

I_VTTOCLSNKV_TT= V_DDQ

V













VDDQ

2

VTT Leakage Current

VTTSNS Leakage Current

VTT Discharge Current

I_VTTLK

S5 = 5V, S3 = 0V, VTT =

I_SINK= 1mA

V_DDQ= 0V, V_TT= 0.5V, S5 = S3 = 0V

10

1

--

10

1

A

I_VTTSNSLK

I_DSCHRG

10

30

--

mA

V













VDDQ

2

V_VTT

=

,

V

=

VTTREF

VTTREF Output Voltage

V_VTTREF

--

0.75

--

V

V_VDDQ= 1.5V

V_LDOIN= V_VDDQ= 1.5V,

|I_VTTREF| < 10mA

15

15

VDDQ/2, VTTREF Output

Voltage Tolerance

V_VTTREFTOL

mV

mA

V_LDOIN= V_VDDQ= 1.8V,

|I_VTTREF| < 10mA

18

--

18

80

VTTREF Source Current Limit I_VTTREFOCLV_VTTREF= 0V

10

40

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8

DS6551A/B-00 May 2015

RT6551A/B

Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are

stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in

the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may

affect device reliability.

Note 2. θ_JAis measured at T_A= 25°C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. θ_JCis

measured at the exposed pad of the package.

Note 3. Devices are ESD sensitive. Handling precaution is recommended.

Note 4. The device is not guaranteed to function outside its operating conditions.

Note 5. Not production tested. Test condition refer to electrical characteristics using application circuit.

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RT6551A/B

Typical Application Circuit

V

R3

IN

RT6551A/B

(Optional)

12

620k

9

VDD

TON

V

VDD

C1

1µF

C3

10µF x 2

17

R1

100k

UGATE

BOOT

Q1

886N03LS

R4

0

10

20

PGOOD

18

PGOOD

VTT

L1

C4

V

1µH

TT

0.1µF

16

15

V

1.35V

VDDQ

0.675V

C2

10µF

PHASE

LGATE

2

VTTSNS

CS

R2

270k

R7

C7

C5

220µF

13

Q2

R5

16k

C8

886N03LS

C9

6

4

5

7

8

FB

VTTREF

VDDQ

S3

S5

VTT Control

R6

20k

VDDQ Control

C6

33nF

1

14

3,

VTTGND

PGND

GND

19

11

VLDOIN

VID

Low

21 (Exposed Pad)

Figure 1. Typical Application Circuit with POSCAP Solution

V

R3

IN

RT6551A/B

(Optional)

620k

9

12

VDD

TON

V

VDD

C1

1µF

C3

10µF x 2

17

R1

100k

UGATE

BOOT

Q1

886N03LS

R4

0

10

20

PGOOD

18

PGOOD

VTT

L1

C4

V

1µH

TT

0.1µF

16

15

V

1.35V

VDDQ

0.675V

C2

PHASE

LGATE

2

10µF

VTTSNS

CS

R2

270k

R7

C7

C5

22µF x 4

13

Q2

R5

16k

C8

886N03LS

C9

6

4

5

7

8

FB

VTTREF

VDDQ

S3

S5

VTT Control

R6

20k

VDDQ Control

C6

33nF

1

14

3,

VTTGND

PGND

GND

19

11

VLDOIN

VID

Low

21 (Exposed Pad)

Figure 2. Typical Application Circuit with Pure MLCC Solution

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DS6551A/B-00 May 2015

RT6551A/B

Typical Operating Characteristics

Switching Frequency vs. Load Current

500

450

400

350

300

250

200

150

100

50

DDR3L, V_IN= 7.4V, V_DDQ= 1.35V,

S3 = GND, S5 = 5V, R_TON= 620kΩ

DDR3L, V_IN= 12V, V_DDQ= 1.35V,

S3 = GND, S5 = 5V, R_TON= 620kΩ

450

400

350

300

250

200

150

100

50

0

0.01

0.1

1

10

0.01

0.1

1

10

Load Current (A)

Switching Frequency vs. Load Current

500

450

400

350

300

250

200

150

100

50

500

450

400

350

300

250

200

150

100

50

DDR3L, V_IN= 19V, V_DDQ= 1.35V,

S3 = GND, S5 = 5V, R_TON= 620kΩ

DDR4, V_IN= 7.4V, V_DDQ= 1.2V,

S3 = GND, S5 = 5V, R_TON= 620kΩ

0

0.01

0.1

1

0.01

0.1

1

10

Load Current (A)

Load Current(A)

Switching Frequency vs. Load Current

500

450

400

350

300

250

200

150

100

50

500

450

400

350

300

250

200

150

100

50

DDR4, V_IN= 12V, V_DDQ= 1.2V,

S3 = GND, S5 = 5V, R_TON= 620kΩ

DDR4, V_IN= 19V, V_DDQ= 1.2V,

S3 = GND, S5 = 5V, R_TON= 620kΩ

0

0.01

0.1

1

0.01

0.1

1

10

Load Current (A)

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RT6551A/B

Efficiency vs. Load Current

100

90

80

70

60

50

40

30

20

10

0

100

90

80

70

60

50

40

30

20

10

0

DDR3L, V_IN= 7.4V, V_DDQ= 1.35V, S3 = S5 = 5V

DDR3L, V_IN= 12V, V_DDQ= 1.35V, S3 = S5 = 5V

0.001

0.010

0.100

1.000

10.000

0.001

0.010

0.100

1.000

10.000

Load Current (A)

Efficiency vs. Load Current

100

90

80

70

60

50

40

30

20

10

0

100

90

80

70

60

50

40

30

20

10

0

DDR3L, V_IN= 19V, V_DDQ= 1.35V, S3 = S5 = 5V

DDR4, V_IN= 7.4V, V_DDQ= 1.2V, S3 = S5 = 5V

0.001

0.010

0.100

1.000

10.000

0.001

0.010

0.100

1.000

10.000

Load Current (A)

Efficiency vs. Load Current

100

90

80

70

60

50

40

30

20

10

0

100

90

80

70

60

50

40

30

20

10

0

DDR4, V_IN= 12V, V_DDQ= 1.2V, S3 = S5 = 5V

DDR4, V_IN= 19V, V_DDQ= 1.2V, S3 = S5 = 5V

0.001

0.010

0.100

1.000

10.000

0.001

0.010

0.100

1.000

10.000

Load Current (A)

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RT6551A/B

VDDQ Output Voltage vs. Load Current

1.40

1.39

1.38

1.37

1.36

1.35

1.34

1.33

1.32

1.31

1.30

1.25

1.24

1.23

1.22

1.21

1.20

1.19

1.18

1.17

1.16

1.15

DDR4, V_IN= 12V, V_DDQ= 1.2V, S3 = S5 = 5V

DDR3L, V_IN= 12V, V_DDQ= 1.35V, S3 = S5 = 5V

0.01

0.1

1

10

0.01

0.1

1

10

Load Current (A)

VTT Output Voltage vs. Load Current

0.700

0.695

0.690

0.685

0.680

0.675

0.670

0.665

0.660

0.655

0.650

0.625

0.620

0.615

0.610

0.605

0.600

0.595

0.590

0.585

0.580

0.575

DDR4, V_IN= 12V, V_TT= 0.6V, S3 = S5 = 5V

-1.5 -1.2 -0.9 -0.6 -0.3 0.3 0.6 0.9 1.2 1.5

DDR3L, V_IN= 12V, V_TT= 0.675V, S3 = S5 = 5V

-1.5 -1.2 -0.9 -0.6 -0.3 0.3 0.6 0.9 1.2 1.5

0

Load Current (A)

Quiescent Current vs. Input Voltage

Shutdown Current vs. Input Voltage

150

148

146

144

142

140

138

136

134

132

130

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0.0

No Switching, S3 = GND, S5 = 5V

S3 = S5 = GND

4

6

8

10 12 14 16 18 20 22 24 26

Input Voltage (V)

4

6

8

10 12 14 16 18 20 22 24 26

Input Voltage (V)

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RT6551A/B

VTT Voltage vs. Temperature

VDDQ Voltage vs. Temperature

1.25

1.24

1.23

1.22

1.21

1.20

1.19

1.18

1.17

1.16

1.15

0.625

0.620

0.615

0.610

0.605

0.600

0.595

0.590

0.585

0.580

0.575

DDR4, V_IN= 12V, V_DDQ= 1.2V, S3 = S5 = 5V

-25 25 50 75 100 125

DDR4, V_IN= 12V, V_TT= 0.6V, S3 = S5 = 5V

-50

0

-50

-25

0

25

50

75

100

125

Temperature (°C)

VDDQ and VTT Start Up

VDDQ Start Up

V_DDQ

(1V/Div)

V_DDQ

(1V/Div)

V_TT

(1V/Div)

V_TT

(1V/Div)

S5

(5V/Div)

PHASE

(10V/Div)

PGOOD

(5V/Div)

PGOOD

(5V/Div)

No Load, V_IN= 12V, V_DDQ= 1.2V, S3 = S5 = 5V

Time (1ms/Div)

V_IN= 12V, V_DDQ= 1.2V, S3 = S5 = 5V, I_Load= 10A

Time (1ms/Div)

Non-Tracking Discharge Shutdown

Tracking Discharge Shutdown

V_DDQ

(1V/Div)

V_DDQ

(1V/Div)

V_TT

(1V/Div)

V_TT

(1V/Div)

V_TTREF

(1V/Div)

V_TTREF

(1V/Div)

S5

(5V/Div)

S5

(5V/Div)

No Load, V_IN= 12V, V_DDQ= 1.2V, S3 = S5 = 5V

Time (200μs/Div)

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RT6551A/B

VTT Load Transient Response

VDDQ Load Transient Response

DDR4, V_IN= 12V

V_DDQ

(50mV/Div)

V_TT

(20mV/Div)

UGATE

(20V/Div)

V_TTREF

(20mV/Div)

LGATE

(5V/Div)

DDR4, V_IN= 12V

I_VTT

(2A/Div)

I_L

(10A/Div)

V_DDQ= 1.2V, S3 = S5 = 5V, I_Load= −1.5A to 1.5A

Time (50μs/Div)

V_DDQ= 1.2V, S3 = S5 = 5V, I_Load= 0.1A to 10A

Time (40μs/Div)

Under Voltage Protection

Over Voltage Protection

V_DDQ

(1V/Div)

V_DDQ

(1V/Div)

UGATE

(20V/Div)

PHASE

(5V/Div)

LGATE

(5V/Div)

LGATE

(5V/Div)

PGOOD

(5V/Div)

PGOOD

(5V/Div)

No Load, V_IN= 12V, V_DDQ= 1.2V, S3 = S5 = 5V

V_IN= 12V, V_DDQ= 1.2V, S3 = S5 = 5V

Time (40μs/Div)

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RT6551A/B

Application Information

This input voltage proportional current is used to charge

an internal on-time capacitor. The on-time is the time

required for the voltage on this capacitor to charge from

zero volts to V_VDDQ, thereby making the on-time of the

high-side switch directly proportional to the output voltage

and inversely proportional to the input voltage. This

implementation results in a nearly constant switching

frequency without the need of a clock generator, as shown

below :

The RT6551A/B PWM controller provides the high

efficiency, excellent transient response, and highDC output

accuracy needed for stepping down high voltage batteries

to generate low voltage chipset RAM supplies in notebook

computers. Richtek's Mach Response^TMtechnology is

specifically designed for providing 100ns “instant-on”

response to load steps while maintaining a relatively

constant operating frequency and inductor operating point

over a wide range of input voltages. The topology solves

the poor load transient response timing problems of fixed-

frequency current mode PWMs, and avoids problems

caused by widely varying switching frequencies in

conventional constant-on-time and constant- off-time PWM

schemes. The DRV^TMmode PWM modulator is

specifically designed to have better noise immunity for

such a single output application.

t

 3.85p x R

x V

/ (V 0.5) + R

x 1

TON





ON

TON

VDDQ

IN

And then the switching frequency is :

f  V_VDDQ/ (V x t_ON

)

IN

where R_TONis the resistor connected from V_INto the TON

pin. Note that the setting on-time must be longer than

100ns (typ.) of the minimum on-time and shorter than 3μs

(typ.) of the maximum on-time.

The 1.5A sink/source LDO maintains fast transient

response, only requiring 10μF of ceramic output

capacitance. In addition, the LDO supply input is available

externally to significantly reduce the total power losses.

The RT6551A/B supports all of the sleep state controls,

placing VTT at high-Z in S3 and discharging VDDQ, VTT

and VTTREF (soft-off) in S4/S5.

Diode Emulation Mode

In diode emulation mode, the RT6551A/B automatically

reduces switching frequency at light load conditions to

maintain high efficiency. As the output current decreases

from heavy load condition, the inductor current will also

be reduced and eventually come to the point where its

valley touches zero current, which is the boundary between

continuous conduction and discontinuous conduction

modes. To emulate the behavior of diodes, the low-side

MOSFET allows only partial negative current to flow when

the inductor freewheeling current reaches negative.As the

load current is further decreased, it takes longer and longer

time to discharge the output capacitor to the level that

requires the next “ON” cycle. The on-time is kept the

same as that in the heavy load condition. In contrast, when

the output current increases from light load to heavy load,

the switching frequency increases to the preset value as

the inductor current reaches the continuous condition. The

transition load point to the light load operation is shown in

Figure 3 and can be calculated as follows :

PWM Operation

The Mach Response^TMDRV^TMmode controller relies on

the output filter capacitor's Effective Series Resistance

(ESR) to act as a current-sense resistor, so the output

ripple voltage provides the PWM ramp signal. Referring to

the function block diagrams of the RT6551A/B, the

synchronous high-side MOSFET is turned on at the

beginning of each cycle. After the internal one-shot timer

expires, the MOSFET will be turned off. The pulse width

of this one-shot is determined by the converter's input

and output voltages to keep the frequency fairly constant

over the entire input voltage range.Another one-shot sets

a minimum off-time (400ns typ.).

V

_IN V_VDDQ

On-Time Control

I_LOAD(SKIP)



x t_ON

2L

where t_ONis the on-time.

The on-time one-shot comparator has two inputs. One

input looks at the output voltage, while the other input

samples the input voltage and converts it to a current.

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DS6551A/B-00 May 2015

RT6551A/B

I

L

The RT6551A/B uses the on resistance of the synchronous

rectifier as the current sense element and supports

temperature compensated MOSFET R_DS(ON)sensing. The

setting resistor, R_ILIM, between the CS pin and VDD sets

the current limit threshold. The CS pin sources an internal

5μA (typ.) current source at room temperature. This current

has a 4700ppm/°C temperature slope to compensate the

temperature dependency of R_DS(ON). When the voltage

drop across the low-side MOSFET equals the voltage

across the R_ILIMsetting resistor, the positive current limit

will activate. The high-side MOSFET will not be turned on

until the voltage drop across the low-side MOSFET falls

below the current limit threshold.

Slope = (V - V

) / L

VDDQ

IN

I

PEAK

I

= I

PEAK

/ 2

LOAD

t

0

t

ON

Figure 3. Boundary Condition of CCM/DCM

The switching waveforms may appear noisy and

asynchronous when light load causes diode-emulation

operation, but this is a normal operating condition that

results in high light load efficiency. Trade offs in DEM

noise vs. light load efficiency is made by varying the

inductor value. Generally, low inductor values produce a

broader efficiency vs. load curve, while higher values result

in higher full load efficiency (assuming that the coil

resistance remains fixed) and less output voltage ripple.

The disadvantages for using higher inductor values include

larger physical size and degraded load transient response

(especially at low input voltage levels).

Choose a current limit setting resistor via the following

equation :

R

 I

x R

10/ 5μA

LIMIT

DS(ON)

And then the CS pin voltage is

V_CS= R_LIMITx 5μA

Note that the V_CSshould be set from 0.4V to 3V.

Carefully observe the PCB layout guidelines to ensure

that noise andDC errors do not corrupt the current-sense

signal seen by PHASE and PGND.

Current Limit Setting for VDDQ (CS)

The RT6551A/B provides cycle-by-cycle current limit

control. The current limit circuit employs a unique “valley”

current sensing algorithm. If the magnitude of the current

sense signal at PHASE is above the current limit

threshold, the PWM is not allowed to initiate a new cycle

(Figure 4). The actual peak current is greater than the

current limit threshold by an amount equal to the inductor

ripple current. Therefore, the exact current limit

characteristic and maximum load capability are a function

of the sense resistance, inductor value, battery and output

voltage.

Current Protection for VTT

The LDO has an internally fixed constant over-current limit

of 2.6A while operating at normal condition. From then

on, when the output voltage exceeds 20% of its set

voltage, the internal power good signal will transit from

high to low.

MOSFET Gate Driver (UGATE, LGATE)

The high-side driver is designed to drive high current, low

R_DS(ON)N-MOSFET(s). When configured as a floating

driver, 5V bias voltage is delivered from the VDD supply.

The average drive current is proportional to the gate charge

at V_GS= 5V times switching frequency. The instantaneous

drive current is supplied by the flying capacitor between

the BOOT and PHASE pins.

I

L

I

PEAK

I

LOAD

LIM

A dead-time to prevent shoot through is internally

generated between high-side MOSFET off to low-side

MOSFET on, and low-side MOSFET off to high-side

MOSFET on.

t

0

Figure 4. “Valley” Current Limit

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RT6551A/B

The low-side driver is designed to drive high current, low

R_DS(ON)N-MOSFET(s). The internal pull down transistor

that drives LGATE low is robust, with a 0.8Ω typical on-

resistance. A 5V bias voltage is delivered from the VDD

supply. The instantaneous drive current is supplied by the

flying capacitor between VDDand PGND.

begins once the chip is enabled. During soft-start, internal

bandgap circuit gradually ramps up the reference voltage

from zero. The maximum reference value is set externally

as described in Table 1.

The soft-start function of VTT is achieved by the current

limit and VTTREF voltage through the internal RC delay

ramp up after S3 is high. During VTT startup, the current

limit level is 2.6A. This allows the output to start up

smoothly and safely under enough source/sink ability.

For high current applications, some combinations of high-

and low-side MOSFETs may cause excessive gate drain

coupling, which leads to efficiency killing, EMI producing

shoot through currents. This is often remedied by adding

a resistor in series on BOOT, which increases the turn-

on rising time of the high-side MOSFET without degrading

the turn-off time (Figure 5).

While TSS is the rising period of VTT , the formula used

to calculated this rising period is TSS = (V_TTx C_VTT)/

I_VTTOCL, it's base on the value of output capacitor C_VTT, the

settled output voltage VTT and the output current limit

V

IN

I_VTTOCL

.

R

VDDQ

VTTREF

S3

BOOT

TSS

UGATE

PHASE

Figure 5. Increasing the UGATE Rise Time

VTT

TSS = (V x C

)/I

VTT VTTOCL

TT

Power Good Output (PGOOD)

The power good output is an open drain output that requires

a pull-up resistor. When the output voltage is 15% below

its set voltage, PGOOD will be pulled low. It is held low

until the output voltage returns to 87% of its set voltage

once more. During soft-start, PGOODis actively held low

and only allowed to be pulled high after soft-start is over

and the output reaches 87% of its set voltage. There is a

5μs delay built into PGOOD circuitry to prevent false

transition.

Output Over-Voltage Protection (OVP)

The output voltage can be continuously monitored for over-

voltage condition. If the output exceeds 15% of its set

voltage threshold, over voltage protection will be triggered

and the LGATE low-side gate driver will be forced high.

This activates the low-side MOSFET switch which rapidly

discharges the output capacitor and reduces the output

voltage. There is a 5μs latch delay built into the over-

voltage protection circuit. The RT6551A/B will be latched

if the output voltage remains above the OV threshold after

the latch delay period. The latched OVP will pull low

PGOODand can only be released by VDDpower on reset

or S5.

POR Protection

The RT6551A/B has a VDD supply power on reset

protection (POR). When the VDD voltage is higher than

4.2V (typ.), VDDQ, VTT and VTTREF will be activated.

This is a non-latch protection.

Note that latching the LGATE high will cause the output

voltage to dip slightly negative when energy has been

previously stored in the LC tank circuit. For loads that

cannot tolerate a negative voltage, place a power Schottky

diode across the output to act as a reverse polarity clamp.

Soft-Start

The RT6551A/B provides an internal soft-start function to

prevent large inrush current and output voltage overshoot

when the converter starts up. Soft-start (SS) automatically

If the over voltage condition is caused by a shorted high-

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RT6551A/B

side switch, turning the low-side MOSFET on 100% will

create an electrical shorted circuit between the battery

andGND, to blow the fuse and disconnecting the battery

from the output.

Table 1. VID and Reference Voltage Setting

VID

High

Low

Reference Voltage (V)

0.675

0.75

Output Under-Voltage Protection (UVP)

When the reference voltage is changed from 0.75V to

0.675V, the OVP latch will be masked for 120μs to prevent

an unexpected shutdown.

The output voltage can be continuously monitored for under-

voltage condition. When UVP is enabled, the under voltage

protection is triggered if the FB is less than 0.45V. Then,

both UGATE and LGATE gate drivers will be forced low

until next VDDor S5 reset. During soft-start, the UVP has

a blanking time around 5ms.

VTT Linear Regulator and VTTREF

The RT6551A/B integrates a high performance low dropout

linear regulator that is capable of sourcing and sinking

currents up to 1.5A. This VTT linear regulator employs

ultimate fast response feedback loop so that small ceramic

capacitors are enough for keeping track of VTTREF within

40mV at all conditions, including fast load transient. To

achieve tight regulation with minimum effect of wiring

resistance, a remote sensing terminal, VTTSNS, should

be connected to the positive node of the VTT output

capacitor(s) as a separate trace from the VTT pin. For

stable operation, total capacitance of the VTT output

terminal can be equal to or greater than 10μF. It is

recommended to attach two 10μF ceramic capacitors in

parallel to minimize the effect of ESR and ESL. If ESR of

the output capacitor is greater than 2mΩ, insert an RC

filter between the output and VTTSNS input to achieve

loop stability. The RC filter time constant should be almost

the same or slightly lower than the time constant made

by the output capacitor and its ESR. The VTTREF block

consists of on-chip 1/2 divider, LPF and buffer. This regulator

also has sink and source capability up to 10mA. Bypass

VTTREF toGNDwith a 33nF ceramic capacitor for stable

operation.

Thermal Protection

The RT6551A/B features a thermal protection function. If

the temperature exceeds the threshold, 165°C (typ.), the

PWM output, VTTREF and VTT will be shut down. The

RT6551A/B is latched once thermal shutdown is triggered

and can only be released by VDD power on reset or S5.

Output Voltage Setting (FB)

Connect a resistive voltage divider at FB between VDDQ

andGNDto adjust the respective output voltage between

0.675V and 3.3V (Figure 6). Choose R2 to be

approximately 10kΩ and solve for R1 using the equation

as follows :



R1 





V

 V

x 1

VDDQ (Valley)

REF







R2







where V_REFis 0.75V or 0.675V depends on the VID setting

in Table 1.

Note that when the RT6551A/B operates from CCM to

DEM, the reference voltage will add 10mV offset.

V

IN

V

VDDQ

Output Management by S3, S5 Control

UGATE

PHASE

LGATE

In DDR2/DDR3 memory applications, it is important to

always keep VDDQ higher than VTT/VTTREF, even during

start-up and shutdown. The RT6551A/B provides this

management by simply connecting both S3 and S5

terminals to the sleep-mode signals such as SLP_S3 and

SLP_S5 in notebook PC system. All VDDQ, VTTREF and

VTT are turned on at S0 state (S3 = S5 = high). In S3

state (S3 = low, S5 = high), VDDQ and VTTREF voltages

are kept on while VTT is turned off and left at high

R1

VDDQ

FB

R2

GND

Figure 6. Setting VDDQ with a Resistive Voltage Divider

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RT6551A/B

impedance (high-Z) state. The VTT output is floated and

does not sink or source current in this state. In S4/S5

states (S3 = S5 = low), all of the three outputs are disabled

and discharged to ground. The code of each state

represents the following: S0 = full ON, S3 = suspend to

RAM (STR), S4 = suspend to disk (STD), S5 = soft OFF.

(See Table 2)

Output Inductor Selection

The switching frequency (on-time) and operating point (%

ripple or L_IR) determine the inductor value as follows :

t

x (V  V

)

ON

IN

VDDQ

x I

LOAD(MAX)

L 

L

IR

where L_IRis the ratio of the peak-to-peak ripple current to

the maximum average inductor current.

Table 2. S3 and S5 truth table

Find a low loss inductor having the lowest possible DC

resistance that fits in the allotted dimensions. Ferrite cores

are often the best choice, although powdered iron is

inexpensive and can work well at 200kHz. The core must

be large enough and not saturate at the peak inductor

current (I_PEAK) :

STATE S3 S5

VDDQ

VTTREF

VTT

S0

S3

Hi Hi

Lo Hi

On

Off

On

Off

Off (Hi-Z)

Off

S4/S5 Lo Lo

(Discharge) (Discharge) (Discharge)





I_PEAK I_LOAD(MAX) (L_IR/2) x I_LOAD(MAX)





VDDQ and VTT Discharge Control

This inductor ripple current also impacts transient-response

performance, especially at low V_IN− V_VDDQdifferences.

Low inductor values allow the inductor current to slew

faster, replenishing charge removed from the output filter

capacitors by a sudden load step. The peak amplitude of

the output transient (V_SAG) is also a function of the output

transient. V_SAGalso features a function of the maximum

duty factor, which can be calculated from the on-time and

minimum off-time :

The RT6551A/B discharges VDDQ, VTTREF and VTT

outputs when S5 is low or in the S4/S5 state. The two

discharge modes can be selected from different part no.

as shown in Table 3.

Table 3. Discharge Selection

Part No.

RT6551A

RT6551B

Discharge Mode

Tracking discharge

Non-tracking discharge

V

SAG

2

(I

) x L x (t  t

)

LOAD

ON

OFF(MIN)

When in tracking discharge mode, the RT6551A

discharges outputs through the internal VTT regulator

transistors and VTT output tracks half of the VDDQ voltage

during this discharge. Note that the VDDQ discharge

current flows via VLDOINto VTTGND; thus VLDOINmust

be connected to VDDQ in this mode. The internal LDO

can handle up to 1.5A and discharge quickly.







)

OFF(MIN)

2 x C

x V x t  V

x (t  t

OUT

IN

ON

VDDQ

ON





where minimum off-time, t_OFF(MIN), is 400ns typically.

Output Capacitor Selection

The output filter capacitor must have low enough ESR to

meet output ripple and load-transient requirements, yet

have high enough ESR to satisfy stability requirements.

Also, the capacitance must be high enough to absorb the

inductor energy going from a full-load to no-load condition

without tripping the OVP circuit.

When in non-tracking discharge mode, the RT6551B

discharges outputs using internal MOSFETs which are

connected to VDDQ and VTT. The current capability of

these MOSFETs is limited to discharge slowly. Note that

the VDDQ discharge current flows from VDDQ to GND in

this mode. In order to discharge smoothly, the RT6551B

provides a special function that the low-side MOSFET

will switch periodically as phase pin with remaining

voltage.

For CPU core voltage converters and other applications

where the output is subject to violent load transients, the

output capacitor's size depends on how much ESR is

needed to prevent the output from dipping too low under a

load transient. Ignoring the sag due to finite capacitance :

V

PP

LOAD(MAX)

ESR 

I

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DS6551A/B-00 May 2015

RT6551A/B

In non-CPU applications, the output capacitor's size

depends on how much ESR is needed to maintain an

acceptable level of output voltage ripple :

3.6

3.0

2.4

1.8

1.2

0.6

0.0

Four-Layer PCB

V

PP

ESR 

L

x I

LOAD(MAX)

IR

where V_P−Pis the peak-to-peak output voltage ripple.

Organic semiconductor capacitor(s) or specialty polymer

capacitor(s) are recommended.

The amount of overshoot due to stored inductor energy

can be calculated as :

0

25

50

75

100

125

(I_PEAK)²x L

V_SOAR



Ambient Temperature (°C)

2 x C_OUTx V_VDDQ

Figure 7.Derating Curve of Maximum PowerDissipation

where I_PEAKis the peak inductor current.

Thermal Considerations

Layout Considerations

For continuous operation, do not exceed absolute

maximum junction temperature. The maximum power

dissipation depends on the thermal resistance of the IC

package, PCB layout, rate of surrounding airflow, and

difference between junction and ambient temperature. The

maximum power dissipation can be calculated by the

following formula :

Layout is very important in high frequency switching

converter design. If designed improperly, the PCB could

radiate excessive noise and contribute to the converter

instability. Certain points must be considered before

starting a layout for the RT6551A/B.

 Keep current limit setting network as close as possible

to the IC. Routing of the network should avoid coupling

to high voltage switching node.

P_D(MAX)= (T_J(MAX)− T_A) / θ_JA

where T_J(MAX)is the maximum junction temperature, T_Ais

the ambient temperature, and θ_JAis the junction to ambient

thermal resistance.

 Connections from the drivers to the respective gate of

the high-side or the low-side MOSFET should be as

short as possible to reduce stray inductance.

For recommended operating condition specifications, the

maximum junction temperature is 125°C. The junction to

ambient thermal resistance, θ_JA, is layout dependent. For

WQFN-20L 3x3 package, the thermal resistance, θ_JA, is

30°C/W on a standard JEDEC 51-7 four-layer thermal test

board. The maximum power dissipation at T_A= 25°C can

be calculated by the following formula :

 All sensitive analog traces and components such as

VDDQ, FB, PGND, PGOOD, CS, VDD, and TONshould

be placed away from high voltage switching nodes such

as PHASE, LGATE, UGATE, and BOOT to avoid

coupling. Use internal layer(s) as ground plane(s) and

shield the feedback trace from power traces and

components.

P_D(MAX)= (125°C − 25°C) / (30°C/W) = 3.33W for

WQFN-20L 3x3 package

 VLDOINshould be connected to VDDQ output with short

and wide trace. If different power source is used for

VLDOIN, an input bypass capacitor should be placed as

close as possible to the pin with short and wide trace.

The maximum power dissipation depends on the operating

ambient temperature for fixed T_J(MAX)and thermal

resistance, θ_JA. The derating curves in Figure 7 allow the

designer to see the effect of rising ambient temperature

on the maximum power dissipation.

 The output capacitor for VTT should be placed close to

the pin with short and wide connection in order to avoid

additional ESR and/or ESL of the trace.

©

is a registered trademark of Richtek Technology Corporation.

DS6551A/B-00 May 2015

www.richtek.com

21

RT6551A/B

 It is strongly recommended to connect VTTSNS to the

positive node of VTT output capacitor(s) as a separate

trace from the high current power line to avoid additional

ESR and/or ESL. If it is needed to sense the voltage of

the point of the load, it is recommended to attach the

output capacitor(s) at that point. It is also recommended

to minimize any additional ESR and/or ESL of ground

trace between theGNDpin and the output capacitor(s).

 Current sense connections must always be made using

Kelvin connections to ensure an accurate signal, with

the current limit resistor located at the device.

 Power sections should connect directly to ground

plane(s) using multiple vias as required for current

handling (including the chip power ground connections).

Power components should be placed as close to the IC

as possible to minimize loops and reduce losses.

©

is a registered trademark of Richtek Technology Corporation.

www.richtek.com

22

DS6551A/B-00 May 2015

RT6551A/B

Outline Dimension

1

2

1

2

DETAILA

Pin #1 ID and Tie Bar Mark Options

Note : The configuration of the Pin #1 identifier is optional,

but must be located within the zone indicated.

Dimensions In Millimeters

Dimensions In Inches

Symbol

Min

Max

Min

Max

A

A1

A3

b

0.700

0.000

0.175

0.150

2.900

1.650

2.900

1.650

0.800

0.050

0.250

3.100

1.750

3.100

1.750

0.028

0.000

0.007

0.006

0.114

0.065

0.114

0.065

0.031

0.002

0.010

0.122

0.069

0.122

0.069

D

D2

E

E2

e

0.400

0.016

L

0.350

0.450

0.014

0.018

W-Type 20L QFN 3x3 Package

Richtek Technology Corporation

14F, No. 8, Tai Yuen 1^stStreet, Chupei City

Hsinchu, Taiwan, R.O.C.

Tel: (8863)5526789

Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should

obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot

assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be

accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third

parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.

DS6551A/B-00 May 2015

www.richtek.com

23


型号：	RT6551B
厂家：	RICHTEK TECHNOLOGY CORPORATION
描述：	暂无描述
文件：	总23页 (文件大小：284K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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