RT8126A [RICHTEK]
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| 型号： | RT8126A |
| 厂家： | 
RICHTEK TECHNOLOGY CORPORATION |
| 描述： | 暂无描述 |
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| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
RT8126A/B/C
High Efficiency Single Synchronous Buck PWM Controller
General Description
Features
VCC Input Range : 4.5V to 13.2V
VOUT Operating Range : 0.6V to 5V
Power Stage Input Range : 2.5V to 24V
Shutdown Current <10μA
Operating Frequency : Fixed 300kHz
Diode Emulation Mode (RT8126A)
Audio Skipping Mode (RT8126B)
VIN Detection
The RT8126A/B/C PWM controller provides high efficiency,
excellent transient response, and highDC output accuracy
needed for stepping down high voltage batteries to
generate low voltage CPU core, I/O, and chipset RAM
supplies in notebook computers.
The constant on-time PWM control scheme handles wide
input/output voltage ratios with ease and provides 100ns
“instant-on” response to load transients while maintaining
a relatively constant switching frequency.
Pinless LGATE Over Current Setting (LGOCS)
Power Good Indication
The RT8126A/B/C achieves high efficiency at a reduced
cost by eliminating the current sense resistor found in
traditional current mode PWMs. Efficiency is further
enhanced by its ability to drive very large synchronous
rectifier MOSFETs. To eliminate noise in audio
applications, the RT8126B providesAudio-Skipping mode,
which maintains the switching frequency above 25kHz.
The buck conversion allows this device to directly step
down high voltage batteries at the highest possible
efficiency. The RT8126A/B/C is intended for CPU core,
chipset, DRAM, or other low voltage supplies as low as
0.6V.
Embedded Bootstrap Switch
Current Limit with Low Side Current Sense Scheme
1% High Accuracy Internal VREF = 0.6V
Enable Function
Differential Output Sense
OVP/UVP/OTP/Pre-OVP/OCP
Applications
Chipset/RAM Supply as Low as 0.6V
GenericDC/DC Power Regulator
Simplified Application Circuit
V
IN
RT8126A/B/C
VCC
UGATE
BOOT
VCC
V
OUT
4.7µF
PHASE
100k
LGATE/
OCSET
5V
PGOOD
EN
PGOOD
FB
Load
Enable
GND
FBG
Copyright 2017 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
DS8126A/B/C-02 July 2017
www.richtek.com
1
RT8126A/B/C
Ordering Information
RT8126A/B/C
Marking Information
RT8126AGQW
Package Type
0W= : Product Code
QW : WDFN-10L 3x3 (W-Type)
YMDNN : Date Code
0W=YM
Lead Plating System
G : Green (Halogen Free and Pb Free)
DNN
A : Diode Emulation Mode
B : Audio Skipping Mode
C : FCCM
RT8126BGQW
3X= : Product Code
Note :
YMDNN : Date Code
3X=YM
Richtek products are :
DNN
RoHS compliant and compatible with the current require-
ments of IPC/JEDEC J-STD-020.
RT8126CGQW
Suitable for use in SnPb or Pb-free soldering processes.
3W= : Product Code
Pin Configurations
YMDNN : Date Code
3W=YM
DNN
(TOP VIEW)
1
2
3
4
5
10
BOOT
UGATE
PGOOD
PHASE
EN
9
8
7
6
FB
FBG
VCC
GND
LGATE/OCSET
11
WDFN-10L 3x3
Functional Pin Description
Pin No.
Pin Name
Pin Function
Supply Input for High Side Driver. Connect a capacitor between the BOOT
pin and PHASE pin.
1
BOOT
2
3
UGATE
Gate Drive Output for the High Side External MOSFET.
PGOOD
Open-drain Power Good Indicator. High impedance indicates power is good.
Ground. Connect this pin directly to the low side MOSFET source and
ground plane with the lowest impedance. The exposed pad must be
soldered to a large PCB and connected to GND for maximum power
dissipation.
4,
GND
11 (Exposed pad)
Gate Drive Output for the Low Side External MOSFET. This pin is also used
to set the OCP threshold. Please refer the application information.
5
6
LGATE/OCSET
VCC
Control Voltage Input. It supports the power for the PWM controller, the low
side driver and the bootstrap circuit for high side driver. Bypass to GND with
a 4.7F ceramic capacitor.
7
8
FBG
FB
Output Voltage Feedback Negative Input.
Output Voltage Feedback Positive Input. Connect FB and FBG to a resistive
voltage divider to set the output voltage level. The internal reference voltage
is 0.6V typically.
9
EN
Active-High Enable Input. Pull low to GND to disable the PWM controller.
External Inductor Connection Pin for PWM Converter. It behaves as the
current sense comparator input for low side MOSFET RDS(ON) sensing and
reference voltage for on time generation.
10
PHASE
Copyright 2017 Richtek Technology Corporation. All rights reserved.
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is a registered trademark of Richtek Technology Corporation.
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2
DS8126A/B/C-02 July 2017
RT8126A/B/C
Functional Block Diagram
BOOT
On-time
One-Shot
PHASE
R
S
COMP
Latch
+
-
+
-
FBG
V
UGATE
PHASE
REF
Q
Min T
OFF
VCC
OV
UV
+
-
S1
Q
125% V
REF
REF
SS
LGATE/OCSET
GND
Latch
S1
FB
-
+
Q
67.5% V
Thermal
Shutdown
VCC
POR
REF
50µA
EN
PGOOD
Sample
and Hold
V
REF
+
gm
+
-
-
Operation
The RT8126 series controller is suitable for low external
component count configuration with appropriate amount
of Equivalent Series Resistance (ESR) capacitor(s) at the
output. The output ripple valley voltage is monitored at a
feedback point voltage. Refer to the function block diagrams
of the RT8126A/B/C, the synchronous high side MOSFET
is turned on at the beginning of each cycle. After the
internal one-shot timer expires, the MOSFET is turned
off. The pulse width of this one-shot is determined by the
converter's input and output voltages to keep the frequency
fairly constant over the entire input voltage range.Another
one-shot sets a minimum off-time (400ns typ.).
and inversely proportional to the input voltage. The
implementation results in a nearly constant switching
frequency without the need of a clock generator.
The RT8126B operates in audio skipping mode with a
minimum switching frequency of 25kHz. This mode
eliminates audio frequency modulation that would
otherwise be present when a lightly loaded controller
automatically skips pulses. In audio skipping mode, the
low side switch gate driver signal is ORed with an internal
oscillator (>25kHz). Once the internal oscillator is
triggered, the audio skipping controller pulls LGATE logic
high, turning on the low side MOSFET to induce a negative
inductor current.After the output voltage rises above VREF,
the controller turns off the low side MOSFET (LGATE
pulled logic low) and triggers a constant on-time operation
(UGATE driven logic high). When the on-time operation
expires, the controller re-enables the low side MOSFET
until the inductor current drops below the zero crossing
threshold.
The on-time one-shot comparator has two inputs. One
input looks at the output voltage, while the other input
samples the input voltage and converts it to a current.
This input voltage proportional current is used to charge
an internal on-time capacitor. The on-time is the time
required for the voltage on this capacitor to charge from
zero volts to VOUT, thereby making the on-time of the
high side switch directly proportional to the output voltage
Copyright 2017 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
DS8126A/B/C-02 July 2017
www.richtek.com
3
RT8126A/B/C
Absolute Maximum Ratings (Note 1)
VCC toGND--------------------------------------------------------------------------------------------------------------−0.3V to 15V
PGOOD, FB, EN -------------------------------------------------------------------------------------------------------−0.3V to 6.5V
BOOT toGND
DC-------------------------------------------------------------------------------------------------------------------------- −0.3V to 40V
<100ns -------------------------------------------------------------------------------------------------------------------- −0.3V to 45V
BOOT to PHASE
DC-------------------------------------------------------------------------------------------------------------------------- −0.3V to 15V
<100ns -------------------------------------------------------------------------------------------------------------------- −0.3V to 20V
PHASE toGND
DC--------------------------------------------------------------------------------------------------------------------------−5V to 25V
<100ns --------------------------------------------------------------------------------------------------------------------−10V to 30V
UGATE toGND
DC--------------------------------------------------------------------------------------------------------------------------- −0.3V to 40V
<100ns --------------------------------------------------------------------------------------------------------------------- −10V to 45V
UGATE to PHASE
DC--------------------------------------------------------------------------------------------------------------------------−0.3V to 15V
<100ns --------------------------------------------------------------------------------------------------------------------−5V to 20V
LGATE toGND
DC--------------------------------------------------------------------------------------------------------------------------−0.3V to 15V
<100ns --------------------------------------------------------------------------------------------------------------------−5V to 20V
PowerDissipation, PD @ TA = 25°C
WDFN-10L 3x3 ----------------------------------------------------------------------------------------------------------3.27W
Package Thermal Resistance (Note2)
WDFN-10L 3x3, θJA ----------------------------------------------------------------------------------------------------30.5°C/W
WDFN-10L 3x3, θJC ----------------------------------------------------------------------------------------------------7.5°C/W
Lead Temperature (Soldering, 10 sec.) ----------------------------------------------------------------------------260°C
Junction Temperature --------------------------------------------------------------------------------------------------150°C
Storage Temperature Range ------------------------------------------------------------------------------------------ −65°C to 150°C
ESD Susceptibility (Note 3)
HBM (Human Body Model) ------------------------------------------------------------------------------------------- 2kV
MM (Machine Model)---------------------------------------------------------------------------------------------------200V
Recommended Operating Conditions (Note 4)
Input Voltage, VIN ------------------------------------------------------------------------------------------------------- 2.5V to 24V
Supply Voltage, VCC ---------------------------------------------------------------------------------------------------4.5V to 13.2V
Junction Temperature Range -----------------------------------------------------------------------------------------−40°C to 125°C
Ambient Temperature Range ----------------------------------------------------------------------------------------- −40°C to 85°C
Copyright 2017 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
4
DS8126A/B/C-02 July 2017
RT8126A/B/C
Electrical Characteristics
(VCC = 5V, VIN = 15V, VEN = 5V, TA = 25°C, unless otherwise specified)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
PWM Controller
V
Quiescent Supply
FB forced above the regulation point,
CC
I
I
--
0.5
1.25
mA
Q
Current
V
EN
= 5V
Rising edge, hysteresis = 120mV, PWM
disable below this level
V
CC
POR Threshold
3.8
--
4
--
4.2
10
V
V
CC
Shutdown Current
V
CC
V
CC
V
FB
current, V = 0V
A
mV
SHDN
EN
Feedback Threshold
(Note 5)
V
I
= 4.5 to 13.2V
= 0.6V
588
594
600
FB
FB Input Bias Current
Output Voltage Range
Switching Frequency
OCSET Current
1
0.6
270
45
6
22
--
--
--
1
5
A
V
FB
V
OUT
OSC
f
I
(Note 6)
300
50
--
330
55
8
kHz
A
OCSET
Zero Crossing Threshold
ASM Minimum Frequency
TSS
mV
kHz
ms
f
--
--
ASM
3
--
Protection Function
Current Limit Threshold
Offset
20
--
--
20
mV
mV
Current Limit Threshold
Setting Range
50
400
UV Threshold
UVP detect, FB falling edge
OVP detect, FB rising edge
60
120
--
--
75
130
--
%
%
OVP Threshold
125
140
Thermal Shutdown
Driver On-Resistance
C
V
V
= 12V,
BOOT
PHASE
UGATE Driver (Source)
R
--
1.5
3
UG_SRC
source current = 100mA
UGATE Driver (Sink)
LGATE Driver (Source)
LGATE Driver (Sink)
Dead Time
R
R
R
V
V
V
V
= 0.1V, I = 50mA
SNK
--
--
--
--
--
2.25
1.5
1
4
3
UG_SNK
LG_SRC
LG_SNK
UGATE
PHASE
= 12V, source current = 100mA
CC
LGATE SNK
, I
= 50mA
2
LGATE rising (V
= 1.5V)
30
30
--
--
ns
ns
PHASE
Dead Time
UGATE rising
Internal Boost Charging
Switch On-Resistance
VCC to BOOT, 10mA
--
--
80
EN Threshold
Logic-High
V
V
--
0.4
--
--
--
--
2.4
--
IH
EN Threshold
Voltage
V
Logic-Low
IL
EN Current
High State, forced to 5V
10
A
PGOOD (Upper Side Threshold Decided by OV Threshold)
PGOOD Blanking Time
Output Low Voltage
Leakage Current
PGOOD rising edge from enable
= 4mA
--
--
--
--
--
--
10
0.3
1
ms
V
I
SINK
High state, forced to 5V
A
Copyright 2017 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
DS8126A/B/C-02 July 2017
www.richtek.com
5
RT8126A/B/C
Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in
the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may
affect device reliability.
Note 2. θJA is measured under natural convection (still air) at TA = 25°C with the component mounted on a high effective-
thermal-conductivity four-layer test board on a JEDEC 51-7 thermal measurement standard. θJC is measured at the
exposed pad of the package.
Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
Note 5. The reference voltage shift −6mV from 0.6V for offset canceling under feedback valley control.
Note 6. No production tested. Test condition VIN = 12V, VOUT = 1.5V, IOUT = 10A using application circuit.
Typical Application Circuit
V
IN
RT8126A
UGATE
6
2
1
VCC
VCC
V
OUT
4.7µF
BOOT
10
5
PHASE
100k
LGATE/
OCSET
5V
3
9
PGOOD
EN
PGOOD
8
7
FB
Load
Enable
4, 11 (Exposed Pad)
GND
FBG
Copyright 2017 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
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DS8126A/B/C-02 July 2017
RT8126A/B/C
Typical Operating Characteristics
Efficiency vs. Load Current
Output Voltage vs. Load Current
100
1.54
1.53
1.52
1.51
1.50
1.49
1.48
1.47
1.46
1.45
90
80
70
60
RT8126A
RT8126B
RT8126C
50
40
30
20
10
0
RT8126C
RT8126A
RT8126B
VIN = VCC = 12V, VOUT = 1.5V
VIN = VCC = 12V
0.01
0.1
1
10
100
0
2
4
6
8
10 12 14 16 18 20
Load Current (A)
Load Current (A)
TON vs. Temperature
Frequency vs. Load Current
500
480
460
440
420
400
380
360
450
400
350
300
250
200
150
100
50
RT8126C
RT8126A
RT8126B
VIN = VCC = 12V, VOUT = 1.5V, No Load
VIN = VCC = 12V, VOUT = 1.5V
8 10 12 14 16 18 20
0
-50
-25
0
25
50
75
100
125
0
2
4
6
Temperature (°C)
Load Current (A)
Output Voltage vs. Temperature
Power On from EN
1.54
1.53
1.52
1.51
1.50
1.49
1.48
1.47
1.46
1.45
RT8128A
EN
(5V/Div)
VOUT
(1V/Div)
PGOOD
(10V/Div)
UGATE
(20V/Div)
VIN = VCC = 12V, No Load
VIN = VCC = 12V, IOUT = 50mA
Time (2ms/Div)
-50
-25
0
25
50
75
100
125
Temperature (°C)
Copyright 2017 Richtek Technology Corporation. All rights reserved.
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is a registered trademark of Richtek Technology Corporation.
DS8126A/B/C-02 July 2017
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7
RT8126A/B/C
Power On from EN
Power On from EN
RT8126B
RT8126A
RT8126C
RT8126C
EN
(5V/Div)
EN
(5V/Div)
VOUT
(1V/Div)
VOUT
(1V/Div)
PGOOD
(10V/Div)
PGOOD
(10V/Div)
UGATE
(20V/Div)
UGATE
(20V/Div)
VIN = VCC = 12V, IOUT = 50mA
Time (2ms/Div)
VIN = VCC = 12V, IOUT = 50mA
Time (2ms/Div)
Power Off from EN
Power Off from EN
RT8126B
EN
(5V/Div)
EN
(5V/Div)
VOUT
(1V/Div)
VOUT
(1V/Div)
PGOOD
(10V/Div)
PGOOD
(10V/Div)
UGATE
(20V/Div)
UGATE
(20V/Div)
VIN = VCC = 12V, IOUT = 50mA
Time (5ms/Div)
VIN = VCC = 12V, IOUT = 50mA
Time (5ms/Div)
Load Transient Response
Power Off from EN
RT8126A
VOUT (100mV/Div)
EN
(5V/Div)
IOUT (10A/Div)
VOUT
(1V/Div)
PGOOD
(10V/Div)
UGATE
(20V/Div)
VIN = VCC = 12V, VOUT = 1.5V
VIN = VCC = 12V, IOUT = 50mA
Time (2ms/Div)
Time (200μs/Div)
Copyright 2017 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
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DS8126A/B/C-02 July 2017
RT8126A/B/C
Load Transient Response
Load Transient Response
RT8126B
RT8126C
VOUT (100mV/Div)
VOUT (100mV/Div)
IOUT (10A/Div)
IOUT (10A/Div)
VIN = VCC = 12V, VOUT = 1.5V
VIN = VCC = 12V, VOUT = 1.5V
Time (200μs/Div)
Time (200μs/Div)
OVP
UVP
VFB
(1V/Div)
VOUT
(1V/Div)
VOUT
(2V/Div)
PGOOD
(5V/Div)
UGATE
(20V/Div)
LGATE
LGATE
(10V/Div)
(10V/Div)
VIN = VCC = 12V, VOUT = 1.5V
VIN = VCC = 12V, VOUT = 1.5V
Time (100μs/Div)
Time (20μs/Div)
OCP
Short Circuit before Power On
VOUT
VOUT
(2V/Div)
(1V/Div)
IL
IL
(20A/Div)
(20A/Div)
UGATE
UGATE
(20V/Div)
(20V/Div)
LGATE
LGATE
(10V/Div)
(10V/Div)
VIN = VCC = 12V, VOUT = 1.5V
VIN = VCC = 12V, VOUT = 1.5V
Time (1ms/Div)
Time (20μs/Div)
Copyright 2017 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
DS8126A/B/C-02 July 2017
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9
RT8126A/B/C
Applications Information
greater than 2V when UGATE is turned off more than 3
times cycle, VIN is recognized as ready. Then, the
controller will initiate soft-start operation.
The RT8126A/B/C PWM controller provides high efficiency,
excellent transient response, and highDC output accuracy
needed for stepping down high voltage batteries to
generate low voltage CPU core, I/O, and chipset RAM
supplies in notebook computers. Richtek Mach
ResponseTM technology is specifically designed for
providing 100ns “instant-on” response to load steps while
maintaining a relatively constant operating frequency and
inductor operating point over a wide range of input voltages.
The topology circumvents the poor load transient timing
problems of fixed frequency current mode PWMs while
avoiding the problems caused by widely varying switching
frequencies in conventional constant on-time and constant
off-time PWM schemes. The RT8126 series controller is
specifically designed to have better noise immunity for
such a single output application.
Internal Soft-Start
The RT8126A/B/C provides an internal soft-start function.
The soft-start function is used to prevent large inrush
current and output voltage overshoot while the converter
is being powered-up. The soft-start function automatically
begins once the chip is enabled.An internal current source
charges the internal soft-start capacitor such that the
internal soft-start voltage ramps up uniformly. The FB
voltage will track the internal soft-start voltage during the
soft-start interval. Therefore, the PWM pulse width
increases gradually to limit the input current. After the
internal soft-start voltage exceeds the reference voltage,
the FB voltage no longer tracks the soft-start voltage but
rather follows the reference voltage. Therefore, the duty
cycle of the UGATE signal as well as the input current at
power up are limited.
Supply Voltage and Power On Reset (POR)
The input voltage range for VCC is from 4.5V to 13.2V
with respect toGND.An internal linear regulator regulates
the supply voltage for internal control logic circuit. A
minimum 0.1μF ceramic capacitor is recommended to
bypass the supply voltage. Place the bypassing capacitor
physically near the IC. VCC also supplies the integrated
MOSFET drivers. A bootstrap diode is embedded to
facilitate PCB design and reduce the total BOM cost. No
external Schottky diode is required in real applications.
Over Current Protection
The RT8126A/B/C provides lossless over current protection
by detecting the voltage drop across the low side MOSFET
when it is turned on. The over current trip threshold is set
by an external resistor, ROCSET, at LGATE.During the initial
stage when LGATE is turned on, the RT8126A/B/C
samples and holds the phase voltage. The sample and
hold voltage represents the valley inductor current and is
compared to the OCP threshold. If the sensed phase
voltage is lower than the OCP threshold, OCP will be
triggered. When OCP is triggered, LGATE will turn on to
prevent inductor current increasing until the OCP condition
is released.
The Power On Reset (POR) circuit monitors the supply
voltage at the VCC pin. If VCC exceeds the POR rising
threshold voltage (typ. 4V), the controller resets and
prepares the PWM for operation. If VCC falls below the
POR falling threshold during normal operation, all
MOSFETs stop switching. The POR rising and falling
threshold has a hysteresis (typ. 0.12V) to prevent
unintentional noise based reset.
LGATE Over Current Setting (LGOCS)
Over current threshold is externally programmed by adding
a resistor (ROCSET) between LGATE andGND. Once VCC
exceeds the POR threshold, an internal current source
IOCSET flows through ROCSET. The voltage across ROCSET is
VIN Detection
Once VCC exceeds its Power On Reset (POR) rising
threshold voltage, UGATE will output continuous pulses
and LGATE will be forced low for converter input voltage
VIN detection. If the voltage pulses at the PHASE pin is
stored as the over current protection threshold VOCSET
.
Copyright 2017 Richtek Technology Corporation. All rights reserved.
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is a registered trademark of Richtek Technology Corporation.
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DS8126A/B/C-02 July 2017
RT8126A/B/C
V
OUT
After that, the current source is switched off. ROCSET can
be determined using the following equation :
IVALLEY RLGDS(ON)
R
FB1
FB2
FB
ROCSET
=
IOCSET
R
where IVALLEY represents the desired inductor OCP trip
current (valley inductor current). If ROCSET is not present,
there is no current path for IOCSET to build the OCP
threshold. In this situation, the OCP threshold is internally
preset to 50mV (typ.).
FBG
Figure 1. Output Voltage Setting
V
V
OUT
Over Voltage Protection (OVP)
V
V
OUT
FB
The output voltage is scaled by the divider resistors and
fed back to the FB pin. The voltage on the FB pin will be
compared to the internal reference voltage VREF for
voltage related protection functions, including over voltage
protection and under voltage protection. If the FB voltage
is higher than the OVP threshold during operation, OVP
will be triggered. When OVP is triggered, UGATE will go
low and LGATE will go high to discharge the output
capacitor. Once OVPis triggered, controller will be latched
unless VCC POR is detected again.
t
t
ON
Figure 2. Output Voltage Waveform
According to the resistor divider network above, the output
voltage is set as :
RFB1
VOUT
VOUT = V 1
FB
RFB2
2
Pre-OVP Function
Note that the reference voltage at DEM is exceeds than
The RT8128A/B/C provides pre-OVP function to prevent
output over voltage before chip enable. When EN signal
is low, the pre-OVP circuit senses the PHASE voltage.
Once the PHASE voltage exceeds 0.2V, LGATE will
deliver 10% duty pulse to discharge the output voltage for
protecting the load. Pre-OVP protection is not latch mode.
Once the PHASE voltage is less than 0.2V, LGATE will
terminate the discharge pulse immediately.
CCM 1%.
MOSFET Drivers
The RT8126A/B/C integrates high current gate drivers for
the two N-MOSFETs to obtain high efficiency power
conversion in synchronous buck topology. Adead time is
used to prevent crossover conduction for the high side
and low side MOSFETs. Because both gate signals are
off during dead time, the inductor current freewheels
through the body diode of the low side MOSFET. The
freewheeling current and the forward voltage of the body
diode contribute to power loss. The RT8126A/B/C employs
constant dead time control scheme to ensure safe operation
without sacrificing efficiency. Furthermore, elaborate logic
circuit is implemented to prevent cross conduction.
Under Voltage Protection (UVP)
The voltage on the FB pin is monitored for under voltage
protection. Controller begins detecting UVP after soft-start
finish. If the FB voltage is lower than the UVP threshold
during normal operation, UVP will be triggered. When the
UVP is triggered, both UGATE and LGATE go low and
latched.
For high output current applications, two or more power
MOSFETs are usually paralleled to reduce RDS(ON). The
gate driver needs to provide more current to switch on/off
these paralleled MOSFETs.Gate driver with lower source/
sink current capability results in longer rising/falling time
in gate signals, and therefore higher switching loss.
Output Voltage Setting
The RT8126A/B/C allows the output voltage of theDC/DC
converter to be adjusted from 0.6V to 5V via an external
resistive divider. It will try to maintain the feedback pin at
internal reference voltage (0.6V).
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RT8126A/B/C
The RT8126A/B/C embeds high current gate drivers to
obtain high efficiency power conversion. The embedded
drivers contribute to the majority of the power dissipation
of the controller. Therefore, WDFNpackage is chosen for
its power dissipation rating. If no gate resistor is used,
the power dissipation of the controller can be approximately
calculated using the following equation :
Input Capacitor Selection
Voltage rating and current rating are the key parameters
when selecting an input capacitor. Conservatively speaking,
an input capacitor should have a voltage rating 1.5 times
greater than the maximum input voltage to be considered
a safe design. The input capacitor is used to supply the
input RMS current, which can be approximately calculated
using the following equation :
PDRIVER = fSW (QG VBOOT
QG_LOW SIDE VDRIVER_LOW SIDE
)
VOUT
VOUT
V
IRMS = IOUT
1
V
IN
IN
where VBOOT represents the voltage across the bootstrap
capacitor and fSW is the switching frequency. It is important
to ensure the package can dissipate the switching loss
and have enough room for safe operation.
The next step is to select a proper capacitor for the RMS
current rating. Using more than one capacitor with low
Equivalent Series Resistance (ESR) in parallel to form a
capacitor bank is a good design. Placing the ceramic
capacitor close to the drain of the high side MOSFET can
also be helpful in reducing the input voltage ripple at heavy
load.
Inductor Selection
The inductor plays an important role in step-down
converters because it stores the energy from the input
power rail and then releases the energy to the load. From
the viewpoint of efficiency, the DC Resistance (DCR) of
the inductor should be as small as possible to minimize
the conduction loss. In addition, the inductor covers a
significant proportion of the board space, so its size is
also important. Low profile inductors can save board space
especially when the height has a limitation. However, low
DCR and low profile inductors are usually cost ineffective.
Output Capacitor Selection
The output filter capacitor must have low enough ESR to
meet output ripple and load-transient requirements, yet
have high enough ESR to satisfy stability requirements.
Also, the capacitance must be high enough to absorb the
inductor energy going from a full-load to no-load condition
without tripping the OVP circuit.
Additionally, larger inductance results in lower ripple
current, which translates into the lower power loss.
However, the inductor current rising time increases with
inductance value. This means the transient response will
be slower. Therefore, the inductor design is a trade-off
among performance, size and cost.
For CPU core voltage converters and other applications
where the output is subject to violent load transients, the
output capacitor's size depends on how much ESR is
needed to prevent the output from dipping too low under a
load transient. Ignoring the sag due to finite capacitance :
VPP
ESR
In general, inductance is chosen such that the ripple
current ranges between 20% to 40% of the full load current.
The inductance can be calculated using the following
equation :
ILOAD(MAX)
In non-CPU applications, the output capacitor's size
depends on how much ESR is needed to maintain an
acceptable level of output voltage ripple :
V
IN VOUT
VOUT
L(MIN)
=
VPP
ESR
fSW kIOUT_Full Load
V
IN
LIR x ILOAD(MAX)
where k is the ratio between inductor ripple current and
rated output current.
where VP−P is the peak-to-peak output voltage ripple.
Organic semiconductor capacitor(s) or specialty polymer
capacitor(s) are recommended.
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DS8126A/B/C-02 July 2017
RT8126A/B/C
For low input-to-output voltage differentials (VIN / VOUT
<
with an AC current probe. Do not allow more than one
cycle of ringing after the initial step-response under- or
over-shoot.
2), additional output capacitance is required to maintain
stability and good efficiency in ultrasonic mode.
The amount of overshoot due to stored inductor energy
MOSFET Selection
can be calculated as :
(IPEAK )2 x L
The majority of power loss in the step-down power
conversion is due to the loss in the power MOSFETs. For
low voltage high current applications, the duty cycle of
the high side MOSFET is small. Therefore, the switching
loss of the high side MOSFET is of concern. Power
MOSFETs with lower total gate charge are preferred in
such kind of application. However, the small duty cycle
means the low side MOSFETis on for most of the switching
cycle. Therefore, the conduction loss tends to dominate
the total power loss of the converter. To improve the overall
efficiency, MOSFETs with low RDS(ON) are preferred in the
circuit design. In some cases, more than one MOSFET
are connected in parallel to further decrease the on-state
resistance. However, this depends on the low side
MOSFET driver capability and the budget.
VSOAR
2 x COUT x VOUT
where IPEAK is the peak inductor current.
Output Capacitor Stability
Stability is determined by the value of the ESR zero relative
to the switching frequency. The point of instability is given
by the following equation :
fSW
4
1
fESR
2 x x ESR x COUT
Do not put high value ceramic capacitors directly across
the outputs without taking precautions to ensure stability.
Large ceramic capacitors can have a high ESR zero
frequency and cause erratic, unstable operation. However,
it is easy to add enough series resistance by placing the
capacitors a couple of inches downstream from the
inductor and connecting VOUT or the FB voltage-divider
close to the inductor.
Thermal Considerations
The junction temperature should never exceed the
absolute maximum junction temperature TJ(MAX), listed
under Absolute Maximum Ratings, to avoid permanent
damage to the device. The maximum allowable power
dissipation depends on the thermal resistance of the IC
package, the PCB layout, the rate of surrounding airflow,
and the difference between the junction and ambient
temperatures. The maximum power dissipation can be
calculated using the following formula :
Unstable operation manifests itself in two related and
distinctly different ways : double-pulsing and feedback loop
instability.
Double-pulsing occurs due to noise on the output or
because the ESR is so low that there is not enough voltage
ramp in the output voltage signal. This “fools” the error
comparator into triggering a new cycle immediately after
the 400ns minimum off-time period has expired. Double
pulsing is more annoying than harmful, resulting in nothing
worse than increased output ripple. However, it may
indicate the possible presence of loop instability, which
is caused by insufficient ESR.
PD(MAX) = (TJ(MAX) − TA) / θJA
where TJ(MAX) is the maximum junction temperature, TA is
the ambient temperature, and θJA is the junction-to-ambient
thermal resistance.
For continuous operation, the maximum operating junction
temperature indicated under Recommended Operating
Conditions is 125°C. The junction-to-ambient thermal
resistance, θJA, is highly package dependent. For a
WDFN-10L 3x3, the thermal resistance, θJA, is 30.5°C/W
on a standard JEDEC 51-7 high effective-thermal-
conductivity four-layer test board. The maximum power
dissipation at TA = 25°C can be calculated as below :
Loop instability can result in oscillations at the output in
the form of line or load perturbations, which can trip the
over-voltage protection latch or cause the output voltage
to fall below the tolerance limit.
The easiest method for checking stability is to apply a
very fast zero-to-max load transient and carefully observe
the output-voltage-ripple envelope for overshoot and ringing.
It helps to simultaneously monitor the inductor current
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RT8126A/B/C
PD(MAX) = (125°C − 25°C) / (30.5°C/W) = 3.27W for a
WDFN-10L 3x3 package.
Keep the high current loops as short as possible.During
high speed switching, the current transition between
MOSFETs usually causes di/dt voltage spike due to
the parasitic components on PCB trace. Therefore,
making the trace length between power MOSFETs and
inductors wide and short can reduce the voltage spike
and EMI.
The maximum power dissipation depends on the operating
ambient temperature for the fixed TJ(MAX) and the thermal
resistance, θJA. The derating curves in Figure 3 allows
the designer to see the effect of rising ambient temperature
on the maximum power dissipation.
Make MOSFET gate driver path as short as possible.
Since the gate driver uses narrow-width high current
pulses to switch on/off power MOSFET, the driver path
must be short to reduce the trace inductance. This is
especially important for low side MOSFET, because this
can reduce the possibility of shoot-through.
3.5
Four-Layer PCB
3.0
2.5
2.0
1.5
1.0
0.5
0.0
Providing enough copper area around power MOSFETs
to help heat dissipation. Using thick copper also
reduces the trace resistance and inductance to have
better performance.
The output capacitors should be placed physically close
to the load. This can minimize the trace parasitic
components and improve transient response.
0
25
50
75
100
125
Ambient Temperature (°C)
Figure 3. Derating Curve of Maximum PowerDissipation
All small signal components should be located close
to the controller. The small signal components include
the feedback voltage divider resistors, function setting
components and high frequency bypass capacitors. The
feedback voltage divider resistor must be placed close
to FB pin, because the FB pin is inherently noise-
sensitive.
Layout Considerations
PCB layout is critical to high current high-frequency
switching converter designs. A good layout can help the
controller to function properly and achieve expected
performance. On the other hand, PCB without a careful
layout can radiate excessive noise, having more power
loss and even malfunction in the controller. In order to
avoid the above condition, the general guidelines can be
followed in PCB layout.
Voltage feedback path must be away from switching
nodes. The noisy switching node is, for example, the
interconnection among high side MOSFET, low side
MOSFET and inductor. Feedback path must be away
from this kind of noisy node to avoid noise pick-up.
Power stage components should be placed first. Place
the input bulk capacitors close to the high side power
MOSFETs, and then locate the output inductor and finally
the output capacitors.
A multi layer PCB design is recommended. Make use
of one single layer as the ground and have separate
layers for power rail or signal is suitable for PCB design.
Placing the ceramic capacitor physically close to the
drain of the high side MOSFET. This can reduce the
input voltage drop when high side MOSFET is turned
on. If more than one MOSFET is paralleled, each should
have its own individual ceramic capacitor.
Copyright 2017 Richtek Technology Corporation. All rights reserved.
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is a registered trademark of Richtek Technology Corporation.
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DS8126A/B/C-02 July 2017
RT8126A/B/C
Outline Dimension
D2
D
L
E
E2
SEE DETAIL A
1
e
b
2
1
2
1
A
A3
DETAILA
Pin #1 IDand Tie Bar Mark Options
A1
Note : The configuration of the Pin #1 identifier is optional,
but must be located within the zone indicated.
Dimensions In Millimeters
Dimensions In Inches
Symbol
Min
Max
Min
Max
0.031
0.002
0.010
0.012
0.120
0.104
0.120
0.069
A
A1
A3
b
0.700
0.000
0.175
0.180
2.950
2.300
2.950
1.500
0.800
0.050
0.250
0.300
3.050
2.650
3.050
1.750
0.028
0.000
0.007
0.007
0.116
0.091
0.116
0.059
D
D2
E
E2
e
0.500
0.020
L
0.350
0.450
0.014
0.018
W-Type 10L DFN 3x3 Package
Richtek Technology Corporation
14F, No. 8, Tai Yuen 1st Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: (8863)5526789
Richtek products are sold by description only. Customers should obtain the latest relevant information and data sheets before placing orders and should verify
that such information is current and complete. Richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek
product. Information furnished by Richtek is believed to be accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use;
nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent
or patent rights of Richtek or its subsidiaries.
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