RT8153C [RICHTEK]
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| 型号： | RT8153C |
| 厂家： | 
RICHTEK TECHNOLOGY CORPORATION |
| 描述： | 暂无描述 CD |
| 文件： | 总29页 (文件大小：388K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
RT8153C/D
Single Phase PWM Controller for CPU Core Power Supply
General Description
Features
z Single Phase PWM Controller with Integrated
The RT8153C/D is a single phase PWM controller with
integrated MOSFET drivers. Moreover, it is compliant with
Intel IMVP6.5 Voltage Regulator Specification to fulfill its
mobile CPU core and Render core voltage regulator
requirements. The RT8153C/D adopts G-NAVP (Green
Native AVP), which is a Richtek proprietary topology
derived from finiteDC gain compensator constant on-time
mode, making it an easy setting PWM controller which
meets all Intel AVP (Active Voltage Positioning) mobile
CPU/Render requirements. The output voltage of the
RT8153C/D is set by a 7-bit VID code. The built in high
accuracyDAC converts the VIDcode into a voltage ranging
from 0V to 1.5V with 12.5mV per step. The system
accuracy of the controller can reach 1.5%.
MOSFET Driver
z G-NAVPTM Control Topology
z 7-bit DAC with 0.8% DAC Accuracy
z 1.5% or 11.5mV System Accuracy
z Fixed VBOOT 1.1V (Only for RT8153C CPU Core Only)
z Fixed VBOOT 1.2V (Only for RT8153D CPU Core Only)
z Current Monitor Output
z Built-in Offset Programming for Platform
z Differential Remote Voltage Sensing
z Diode Emulation Mode at Light Load Condition
z Programmable Output Transition Slew Rate Control
z System Thermal Compensated AVP
z Fast Transient Response
z Load Line Enable/Disable
The part supports VIDon the fly and mode change on the
fly functions that are fully compliant with IMVP6.5
specification. It operates in single phase and diode
emulation modes. It can reach up to 90% efficiency in
different modes according to different loading conditions.
z Power Good Indicator
z Clock Enable Output (For CPU Core Only)
z Thermal Throttling
z Switching Frequency Up to 1MHz
z OVP, UVP, OCP, OTP, UVLO, NVP
z RoHS Compliant and Halogen Free
The RT8153C/Dincludes power good and thermal throttling
indicator and an additional clock enabling for CPU core
specification. The soft-start and output transition slew rate
is programmable by an external capacitor. It also features
complete fault protection functions including over voltage,
under voltage, negative voltage, over current and thermal
shutdown. The RT8153C/Dis available in WQFN-32L 5x5
and WQFN-32L 4x4 small foot print packages.
Ordering Information
RT8153C/D
Package Type
QW : WQFN-32L 5x5 (W-Type)
QW : WQFN-32L 4x4 (W-Type)
Lead Plating System
G : Green (Halogen Free and Pb Free)
Z : ECO (Ecological Element with
Halogen Free and Pb free)
Applications
z IMVP 6.5 VCORE/Render
Package Size
L : 5x5
z AVP Step-Down Converter
z Notebook / Desktop Computer / Servers
S : 4x4
VBOOT
C : 1.1V
D : 1.2V
Note :
Richtek products are :
` RoHS compliant and compatible with the current require-
ments of IPC/JEDEC J-STD-020.
` Suitable for use in SnPb or Pb-free soldering processes.
DS8153C/D-05 April 2011
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1
RT8153C/D
Marking Information
RT8153CLGQW
RT8153DLGQW
RT8153CLGQW : Product Number
YMDNN : Date Code
RT8153DLGQW : Product Number
YMDNN : Date Code
RT8153CL
GQW
RT8153DL
GQW
YMDNN
YMDNN
RT8153CLZQW
RT8153DLZQW
RT8153CLZQW : Product Number
YMDNN : Date Code
RT8153DLZQW : Product Number
YMDNN : Date Code
RT8153CL
ZQW
RT8153DL
ZQW
YMDNN
YMDNN
RT8153CSGQW
RT8153DSGQW
EH= : Product Code
YMDNN : Date Code
EJ= : Product Code
YMDNN : Date Code
EH=YM
DNN
EJ=YM
DNN
RT8153CSZQW
RT8153DSZQW
EH : Product Code
YMDNN : Date Code
EJ : Product Code
YMDNN : Date Code
EH YM
DNN
EJ YM
DNN
Pin Configurations
(TOP VIEW)
32 31 30 29 28 27 26 25
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
NTC
OCSET
DPRSLPVR
VRON
BOOT
UGATE
PHASE
PGND
LGATE
PVDD
OFS
GND
PGOOD
CLKEN
VCC
33
SOFT
TON
9
10 11 12 13 14 15 16
WQFN-32L 5x5 / WQFN-32L 4x4
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DS8153C/D-05 April 2011
RT8153C/D
Typical Application Circuit
V
IN
5V to 25V
RT8153C/D
R2
R3
C3
C4
R1
17
7
TON
VCC
5V
C5
C1
19
31
30
PVDD
R4
24
23
BOOT
Q1
C2
VID0
VID1
VID0
UGATE
L1
R5
R8
22
20
VID1
VID2
VID3
VID4
VID5
VID6
PHASE
LGATE
V
OUT
29
28
27
26
Q2
VID2
VID3
VID4
VID5
C7
R6*
C6*
R7
D1*
C
OUT
21
16
15
PGND
ISEN
R14 R20
NTC1
ISEN_N
25
3
VID6
R13
11
DPRSLPVR
VRON
CMSET
VSEN
FB
DPRSLPVR
VRON
R21
4
R22
12
13
C9
5
6
PWRGD
PGOOD
CLKEN
CLKEN
VRTT
C12
C13
R19
32
VRTT
R18
14
R10
R9
R11
COMP
CP
U V
CC_SENSE
SS_SENSE
V
CCP
9
3.3V
RGND
SOFT
CM
CPU V
C10
R15
NTC2
8
1
2
R12
C11
V
CC
NTC
10
R24
R23
CM
18
OFS
R16
V
CC
OCSET
R17
GND
33 (Exposed Pad)
* = Optional
Figure 1. IMVP 6.5 CPU Core Application Circuit
DS8153C/D-05 April 2011
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3
RT8153C/D
V
IN
5V to 25V
RT8153C/D
R2
R3
C3
C4
R1
17
7
TON
VCC
5V
C5
C1
19
31
30
PVDD
R4
24
23
BOOT
Q1
C2
VID0
VID1
VID0
UGATE
PHASE
LGATE
PGND
L1
R5
R8
22
20
VID1
VID2
VID3
VID4
VID5
VID6
V
OUT
29
28
27
26
Q2
VID2
VID3
VID4
VID5
C7
R6*
C6*
R7
D1*
C
OUT
21
16
15
R14 R20
NTC1
ISEN
ISEN_N
25
3
VID6
R13
11
DPRSLPVR
VRON
CMSET
VSEN
FB
DPRSLPVR
VRON
R21
4
R22
12
13
C9
5
6
PWRGD
CLKEN
PGOOD
CLKEN
C12
C13
R19
32
VRTT
VRTT
R18
14
R10
R9
R11
COMP
C
PU V
CC_SENSE
V
CCP
9
3.3V
RGND
SOFT
CM
CPU V
SS_SENSE
C10
R15
NTC2
8
1
2
R12
C11
V
CC
NTC
10
R24
R23
CM
18
OFS
1V to 1.6V
R16
V
OCSET
CC
R17
GND
33 (Exposed Pad)
* = Optional
Figure 2. IMVP 6.5 CPU Core with Offset Application Circuit
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DS8153C/D-05 April 2011
RT8153C/D
V
IN
5V to 25V
RT8153C/D
R2
R3
C3
C4
R1
17
7
TON
VCC
5V
C5
C1
19
31
30
PVDD
R4
24
23
BOOT
Q1
C2
VID0
VID1
VID0
UGATE
PHASE
LGATE
L1
R5
R8
22
20
VID1
VID2
VID3
VID4
VID5
VID6
V
OUT
29
28
27
26
Q2
VID2
VID3
VID4
VID5
C7
R6*
C6*
R7
D1*
C
OUT
21
16
15
PGND
ISEN
R14 R20
NTC1
ISEN_N
25
3
VID6
R13
11
DPRSLPVR
VRON
CMSET
VSEN
FB
DPRSLPVR
VRON
R21
4
R22
12
13
C9
5
PWRGD
VRTT
PGOOD
C12
C13
R19
32
VRTT
R9
R11
R18
14
COMP
U V
GP
CC_SENSE
V
CCP
6
1
CLKEN
NTC
3.3V
9
RGND
SOFT
CM
GPU V
SS_SENSE
C10
R15
NTC2
8
R12
C11
V
CC
10
R24
R23
CM
18
OFS
R16
2
V
CC
OCSET
R17
GND
33 (Exposed Pad)
* = Optional
Figure 3. IMVP 6.5 Render Application Circuit
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5
RT8153C/D
V
IN
5V to 25V
RT8153C/D
R2
R3
C3
C4
R1
17
7
TON
VCC
5V
C5
C1
19
31
30
PVDD
R4
24
23
BOOT
Q1
C2
VID0
VID1
VID0
UGATE
PHASE
LGATE
L1
R5
R8
22
20
VID1
VID2
VID3
VID4
VID5
V
OUT
29
28
27
26
Q2
VID2
VID3
VID4
VID5
C7
R6*
C6*
R7
D1*
C
OUT
21
16
15
PGND
ISEN
R14 R20
NTC1
ISEN_N
25
3
VID6
VID6
DPRSLPVR
VRON
R13
11
DPRSLPVR
VRON
CMSET
VSEN
FB
4
R21 R22
12
13
C9
5
PWRGD
VRTT
PGOOD
C12
R18
C13
R19
32
VRTT
R9
R11
14
COMP
GP
U V
CC_SENSE
V
CCP
6
1
CLKEN
NTC
3.3V
9
RGND
SOFT
CM
GPU V
SS_SENSE
C10
R15
NTC2
8
R12
C11
V
CC
10
R24
R23
CM
18
OFS
1V to 1.6V
R16
2
V
CC
OCSET
R17
GND
33 (Exposed Pad)
* = Optional
Figure 4. IMVP 6.5 Render with Offset Application Circuit
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DS8153C/D-05 April 2011
RT8153C/D
Functional Pin Description
Pin No.
Pin Name
Pin Function
Thermal Detection Input for VRTT Circuit. Connect this pin with a resistor divider
from VCC using NTC on the top to set the thermal management threshold level.
Furthermore, this pin provides load line enable/disable function.
1
NTC
Over Current Protection Setting. Connect a resistor voltage divider from VCC to
ground, the joint of the resistive voltage divider is connected to the OCSET pin,
2
OCSET
with a voltage VOCSET, to set the over current threshold ILIM
.
3
4
5
DPRSLPVR
VRON
Deeper Sleep Mode Signal.
Voltage Regulator Enabler.
PGOOD
Power Good Indicator.
Inverted Clock Enable. Pull high by a resistor for CPU core application. This
open-drain pin is an output indicating the start of the PLL locking of the clock
chip. Connect to GND for Render application.
CLKEN
VCC
6
7
Chip Power.
Soft-Start. This pin provides soft-start function and slew rate controller. The
capacitance of the slew rate control capacitor is restricted to be larger than 10nF.
The feedback voltage of the converter follows the ramping voltage on the SOFT
pin during soft-start and other voltage transitions according to different mode of
operation and VID change.
8
SOFT
Return Ground. This pin is the negative node of the differential remote voltage
sensing.
9
RGND
CM
Current Monitor Output. This pin outputs a voltage proportional to the output
current.
10
Current Monitor Output Gain Externally Setting. Connect this pin with one resistor
to VSEN the while CM pin is connected to ground with another resistor. In such a
way, the current monitor output gain can be set by the ratio of these two resistors.
11
CMS ET
Positive Voltage Sensing Pin. This pin is the positive node of the differential
voltage sensing.
12
VSEN
13
14
15
16
17
18
19
20
21
FB
Feedback. This is the negative input node of the error amplifier.
Compensation Pin. This pin is the output node of the error amplifier.
Negative Input of the Current Sense.
COMP
ISEN_N
ISEN
Positive Input of the Current Sense.
TON
Connect this Pin to VIN with One Resistor.
Output Voltage Offset Setting.
OFS
PVDD
LGATE
PGND
Driver Power.
Lower Gate Drive. This pin drives the gate of the low side MOSFETs.
Driver Ground.
This pin is the return node of the high side MOSFET driver. Connect this pin to
the high side MOSFET sources together with the low side MOSFET drains and
the inductor.
22
PHASE
23
24
UGATE
BOOT
Upper Gate Drive. This pin drives the gate of the high side MOSFETs.
Bootstrap Power Pin. This pin powers the high side MOSFET drivers. Connect
this pin to bootstrap capacitor.
To be continued
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7
RT8153C/D
Pin No.
Pin Name
Pin Function
Voltage ID. DAC voltage identification inputs for IMVP6.5.
VID6 to VID0 The logic threshold is 30% of VCC as the maximum value for low state and
70% of the VCC as the minimum value for the high state.
25 to 31
Voltage Regulator Thermal Throttling. This open drain output pin will be
pulled low when the preset temperature level is exceeded.
32
VRTT
33
Ground. The exposed pad must be soldered to a large PCB and connected to
GND for maximum power dissipation.
GND
(Exposed Pad)
Function Block Diagram
NTC
PGOOD
VRON
VCC
DPRSLPVR
OCSET
TON
CLKEN
VRTT
SOFT
VCC
Power
Saving
mode
Power On Reset
&
Central Logic
OCP
Setting
Mode
Selection
+
-
GND
BOOT
+
-
UGATE
PHASE
PVDD
-
NVP Trip
Point
0LL
2V
+
-
Driver
Logic
Control
+
+
-
1.1V for RT8153C
1.2V for RT8153D
OTP
LGATE
PWMCP
VID0
VID1
VID2
VID3
VID4
VID5
VID6
PGND
+
-
DAC
MUX
OVP Trip
Point
-
ISEN_N
ISEN
+
-
10
UVP Trip
Point
+
0LL
RGND
OFS
Soft Start/Slew
Rate
Control/Offset
Control
ERROR
AMP
DPRSLPVR
+
SOFT
FB
Offset Cancellation
-
CM
CM
CMSET
COMP
VSEN
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DS8153C/D-05 April 2011
RT8153C/D
Table 1. IMVP6.5 VID Code Table
VID6 VID5 VID4 VID3 VID2 VID1 VID0 Output VID6 VID5 VID4 VID3 VID2 VID1 VID0 Output
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1.5000V
1.4875V
1.4750V
1.4625V
1.4500V
1.4375V
1.4250V
1.4125V
1.4000V
1.3875V
1.3750V
1.3625V
1.3500V
1.3375V
1.3250V
1.3125V
1.3000V
1.2875V
1.2750V
1.2625V
1.2500V
1.2375V
1.2250V
1.2125V
1.2000V
1.1875V
1.1750V
1.1625V
1.1500V
1.1375V
1.1250V
1.1125V
1.1000V
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1.0875V
1.0750V
1.0625V
1.0500V
1.0375V
1.0250V
1.0125V
1.0000V
0.9875V
0.9750V
0.9625V
0.9500V
0.9375V
0.9250V
0.9125V
0.9000V
0.8875V
0.8750V
0.8625V
0.8500V
0.8375V
0.8250V
0.8125V
0.8000V
0.7875V
0.7750V
0.7625V
0.7500V
0.7375V
0.7250V
0.7125V
0.7000V
0.6875V
To be continued
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9
RT8153C/D
VID6 VID5 VID4 VID3 VID2 VID1 VID0 Output
VID6 VID5 VID4 VID3 VID2 VID1 VID0 Output
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0.6750V
0.6625V
0.6500V
0.6375V
0.6250V
0.6125V
0.6000V
0.5875V
0.5750V
0.5625V
0.5500V
0.5375V
0.5250V
0.5125V
0.5000V
0.4875V
0.4750V
0.4625V
0.4500V
0.4375V
0.4250V
0.4125V
0.4000V
0.3875V
0.3750V
0.3625V
0.3500V
0.3375V
0.3250V
0.3125V
0.3000V
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0.2875V
0.2750V
0.2625V
0.2500V
0.2375V
0.2250V
0.2125V
0.2000V
0.1875V
0.1750V
0.1625V
0.1500V
0.1375V
0.1250V
0.1125V
0.1000V
0.0875V
0.0750V
0.0625V
0.0500V
0.0375V
0.0250V
0.0125V
0.0000V
0.0000V
0.0000V
0.0000V
0.0000V
0.0000V
0.0000V
0.0000V
www.richtek.com
10
DS8153C/D-05 April 2011
RT8153C/D
Absolute Maximum Ratings (Note 1)
z VCC to GND -------------------------------------------------------------------------------------------------------- −0.3V to 6.5V
z RGND, PGNDtoGND ------------------------------------------------------------------------------------------- −0.3V to 0.3V
z VIDx to GND ------------------------------------------------------------------------------------------------------- −0.3V to (VCC + 0.3V)
z DPRSLPVR, VRON to GND ----------------------------------------------------------------------------------- −0.3V to (VCC + 0.3V)
z PGOOD, CLKEN, VRTT toGND------------------------------------------------------------------------------ −0.3V to (VCC + 0.3V)
z VSEN, FB, COMP, SOFT, OCSET, CM, CMSET, NTC to GND --------------------------------------- −0.3V to (VCC + 0.3V)
z ISEN, ISEN_NtoGND ------------------------------------------------------------------------------------------ −0.3V to (VCC + 0.3V)
z PVDDto PGND --------------------------------------------------------------------------------------------------- −0.3V to 6.5V
z LGATE to PGND
DC-------------------------------------------------------------------------------------------------------------------- −0.3V to (PVDD + 0.3V)
<20ns --------------------------------------------------------------------------------------------------------------- −2.5V to 7.5V
z PHASE to PGND
DC-------------------------------------------------------------------------------------------------------------------- −0.3V to 30V
<20ns --------------------------------------------------------------------------------------------------------------- −8V to 38V
z BOOT to PHASE ------------------------------------------------------------------------------------------------- −0.3V to 6.5V
z UGATE to PHASE
DC-------------------------------------------------------------------------------------------------------------------- −0.3V to (PVDD + 0.3V)
<20ns --------------------------------------------------------------------------------------------------------------- −5V to 7.5V
z TONtoGND ------------------------------------------------------------------------------------------------------- −0.3V to 30V
z Power Dissipation, PD @ TA = 25°C
WQFN−32L 5x5 --------------------------------------------------------------------------------------------------- 2.778W
WQFN−32L 4x4 --------------------------------------------------------------------------------------------------- 1.923W
z Package Thermal Resistance (Note 2)
WQFN−32L 5x5, θJA --------------------------------------------------------------------------------------------- 36°C/W
WQFN−32L 5x5, θJC --------------------------------------------------------------------------------------------- 6°C/W
WQFN−32L 4x4, θJA --------------------------------------------------------------------------------------------- 52°C/W
WQFN−32L 4x4, θJC --------------------------------------------------------------------------------------------- 7°C/W
z Junction Temperature -------------------------------------------------------------------------------------------- 150°C
z Storage Temperature Range ----------------------------------------------------------------------------------- −65°C to 150°C
z Lead Temperature (Soldering, 10 sec.)---------------------------------------------------------------------- 260°C
z ESD Susceptibility (Note 3)
HBM (Human Body Mode) ------------------------------------------------------------------------------------- 2kV
MM (Machine Mode) --------------------------------------------------------------------------------------------- 200V
Recommended Operating Conditions (Note 4)
z Supply Voltage, VCC --------------------------------------------------------------------------------------------- 4.5V to 5.5V
z Battery Voltage, VIN --------------------------------------------------------------------------------------------- 5V to 25V
z Junction Temperature Range----------------------------------------------------------------------------------- −40°C to 125°C
z Ambient Temperature Range----------------------------------------------------------------------------------- −40°C to 85°C
DS8153C/D-05 April 2011
www.richtek.com
11
RT8153C/D
Electrical Characteristics
(VCC = 5V, TA = 25°C, unless otherwise specified)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
OFS Function (Only for RT8153C/D)
Enable
OFS Threshold Offset
VOFS > 0.92V before VRON rising
0.92
1.2
--
V
Voltage
Disable
Offset
VOFS connected to GND before VRON
rising
No Offset Voltage
Offset 400mV
Offset −200mV
--
--
--
1
1.2
1.6
1
--
--
--
--
Set OFS voltage
VOFS
ROFS
V
Impedance
--
MΩ
OLL Function
Pulse sinking current source NTC
resistor at VRON rising edge.
Detect and Latch voltage at NTC pin at
VRON rising edge.
I0LL
--
2
80
--
--
--
μA
NTC
V0LL
V
V
NTC < V0LL, enable 0 Load Line
Function.
Supply Input
Supply Voltage
VCC
4.5
--
5
5.5
10
V
IVCC
IPVCC
+
Supply Current
VRON = 3.3V, Not Switching
--
mA
ICC
IPVCC
Soft-Start/Slew Rate Control (based on 10nF CSS
+
Shutdown Current
V
RON = 0V
--
--
5
μA
)
Soft-Start / Soft-Shutdown ISS1
VSOFT = 1.5V
--
20
50
--
μA
μA
Normal VID change slew
current
ISS2
VSOFT = 1.5V
VSOFT = 1.5V
40
60
Deeper Sleep Exit/VID
Change Slew Current
(only at IMVP6.5 Render
ISS3
80
100
120
μA
application)
Reference and DAC
VVID = 0.7500 − 1.5000
(No Load, Active Mode )
−0.5
0
0.5
%VID
mV
DC Accuracy
Boot Voltage
VFB
VVID = 0.5000 − 0.7500
For RT8153C VCORE
For RT8153D VCORE
−7.5
1.089
1.188
0
7.5
1.1
1.2
1.111
1.212
VBOOT
V
Error Amplifier
Input Offset Voltage
DC Gain
VOSEA
−2
70
--
--
2
--
--
mV
dB
RL = 47kΩ
80
10
Gain Bandwidth Product
GBW
CLOAD = 5pF
MHz
C
LOAD = 10pF (Gain = −4,
Slew Rate
SRCOMP
VCOMP
--
5
--
V/μs
RF = 47kΩ, VOUT = 0.5V − 3V)
Output Voltage Range
RL = 47kΩ
0.5
--
3.6
V
To be continued
www.richtek.com
12
DS8153C/D-05 April 2011
RT8153C/D
Parameter
Symbol
Test Conditions
VCOMP = 2V
Min
200
20
Typ
250
--
Max Unit
Maximum Source
Current
--
--
μA
IOUTEA_COMP
Maximum Sink Current
Current Sense Amplifier
Input Offset Voltage
VCOMP = 2V
mA
VOSCS
−1
1
--
--
1
--
--
--
1
mV
MΩ
MΩ
V/V
%
Impedance at Neg. Input RISEN_N
Impedance at Pos Input RISEN
DC Gain
1
--
1 Phase Operating
--
10
VISEN Linearity
VISEN_ACC
−30mV < ISEN_IN < 50mV
−1
DEM TON Setting
TON Pin Output Voltage VTON
ITON = 80μA, VTON = VVID = 0.75
IRTON = 80μA
−5
--
0
350
--
5
--
%
ns
μA
DEM ON-Time Setting
RTON Current Range
tON
IRTON
25
280
Protection
Under Voltage Lock out
Threshold
UVLO Hysteresis
VUVLO
Falling Edge.
4.1
--
4.3
200
1.7
4.5
--
V
mV
V
Absolute Over Voltage
Protection Threshold
Absolute Over Voltage
Offset
Relative Over Voltage
Protection Threshold
VOVABS
(Respect to 1.7V, ±50mV)
1.65
1.75
VOVABS_OFS (Respect to 2V, ±50mV)
1.95
250
2
2.05
350
V
VOV
(Respect to VDAC, ±50mV)
300
mV
Measured at VSEN with respect to
Unloaded Output Voltage (UOV)
(for 0.8 < UOV < 1.5)
Under Voltage Protection
Threshold
VUV
−450 −400 −350
mV
Negative Voltage
Protection Threshold
Current Limit Threshold
Voltage
Thermal Shut Down
Threshold
Measured at VSEN with Respect to
GND
VISEN − VISEN_N = VILIM,
VNV
−100
45
--
--
50
--
55
--
mV
mV
°C
VILIMIT
TSD
VOCSET = 2.4V, 48 x VILIMT = VOCSET
160
10
Thermal Shut Down
Hysteresis
ΔTSD
--
--
°C
Logic Inputs
VIH
VIL
Respect to 1.05V, 70%
Respect to 1.05V, 30%
0.735
--
--
--
--
VRON Threshold
V
μA
V
0.315
Leakage Current of
VRON
−1
--
1
VIH
VIL
Respect to 1.05V, 70%
Respect to 1.05V, 30%
0.735
--
--
--
--
DAC (VID0 to VID6) and
DPRSLPVR
0.315
Leakage Current of DAC
(VID0 to VID6), PSI and
DPRSLPVR
−1
--
1
μA
To be continued
DS8153C/D-05 April 2011
www.richtek.com
13
RT8153C/D
Parameter
Power Good
Symbol
Test Conditions
Min
Typ
Max Unit
PGOOD Low Voltage
PGOOD Delay
V
t
I
= 4mA
--
3
--
--
0.4
20
V
PGOOD
PGOOD
ms
CLK_EN Low to PGOOD High
= 4mA (only for V )
CORE
PGD
Clock Enable
V
I
--
--
0.4
V
CLKEN Low Voltage
Thermal Throttling
CLKEN
CLKEN
Thermal Throttling
Threshold
V
Measure at NTC Respect to V
--
80
--
%VDD
OT
CC
Thermal Throttling
Threshold Hysteresis
V
V
At V = 5V
--
--
230
--
--
mV
V
OT_HY
VRTT
CC
I
= −40mA
0.4
VRTT
VRTT Output Voltage
Current Monitor
Current Monitor Output
Voltage in Operating
Range
Current Monitor Maximum
Output Voltage
V
R
− V
= 18kΩ, R
= 20mV,
ISEN
ISEN_N
450
--
480
--
510
mV
V
= 12kΩ
CM
CMSET
1.15
Gate Driver
V
− V
− V
= 5V
PHASE
= 1V
LGATE
BOOT
Upper Driver Source
R
--
1
--
Ω
UGATEsr
V
BOOT
Upper Driver Sink
Lower Driver Source
Lower Driver Sink
R
V
= 1V
1
1
Ω
Ω
Ω
UGATEsk
UGATE
R
V
PVDD
= 5V, V
− V = 1V
LGATE
--
--
--
--
LGATEsr
PVDD
R
V
LGATE
= 1V
0.5
LGATEsk
Upper Driver Source/Sink
Current
Lower Driver Source
Current
V
− V
= 5V
BOOT
PHASE
I
--
2
--
A
UGATE
V
= 2.5V
= 2.5V
LGATE
UGATE
I
V
--
--
--
2
4
--
--
--
A
A
Ω
LGATEsr
Lower Driver Sink Current I
V
LGATE
= 2.5V
LGATEsk
Internal Boot Charging
Switch On Resistance
R
PVDD to BOOT
30
BOOT
Note 1. Stresses listed as the above “Absolute Maximum Ratings” may cause permanent damage to the device. These are for
stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may remain possibility to affect device reliability.
Note 2. θJA is measured in natural convection at TA = 25°C on a high effective thermal conductivity four-layers test board of
JEDEC 51-7 thermal measurement standard. The measurement case position of θJC is on the exposed pad of the
package.
Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
www.richtek.com
14
DS8153C/D-05 April 2011
RT8153C/D
Typical Operating Characteristics
CCM VCC_SENSE vs. Load Current
CCM Efficiency vs. Load Current
1.16
1.14
1.12
1.10
1.08
1.06
1.04
100
90
80
VIN = 8V
VIN = 12V
VIN = 19V
70
60
50
40
30
20
10
0
VIN = 8V
VIN = 12V
VIN = 19V
VID= 1.15V, RTON= 120kΩ,DPRSLPVR =GND
VID= 1.15V, RTON= 120kΩ,DPRSLPVR =GND
0
5
10
15
20
25
30
0
5
10
15
20
25
30
Load Current (A)
Load Current (A)
CCM VCC_SENSE vs. Load Current
CCM Efficiency vs. Load Current
100
90
80
70
60
50
40
30
20
10
0
0.94
0.92
0.90
0.88
0.86
0.84
0.82
VIN = 8V
VIN = 12V
VIN = 19V
VIN = 8V
VIN = 12V
VIN = 19V
VID= 0.9375V, RTON = 120kΩ,DPRSLPVR =GND
10 15 20 25 30
VID= 0.9375V, RTON = 120kΩ, DPRSLPVR =GND
10 15 20 25 30
0
5
0
5
Load Current (A)
Load Current (A)
VCM vs. Load Current
DEM Efficiency vs. Load Current
90
85
80
75
70
65
60
55
50
1200
1000
800
600
400
200
0
VIN = 8V
VIN = 12V
VIN = 19V
VIN = 8V
VIN = 12V
VIN = 19V
VID= 0.85V, RTON= 120kΩ,DPRSLPVR = High
0.5 1.5 2.5 3
VID= 0.9375V, RTON= 120kΩ,DPRSLPVR =GND
10 15 20 25 30
0
5
0
1
2
Load Current (A)
Load Current (A)
DS8153C/D-05 April 2011
www.richtek.com
15
RT8153C/D
Render Mode Power On
CPU Mode Power On
VCC_SENSE
(1V/Div)
VCC_SENSE
(1V/Div)
PGOOD
(5V/Div)
PGOOD
(5V/Div)
VRON
(5V/Div)
VRON
(5V/Div)
CLKEN
(5V/Div)
CLKEN
(5V/Div)
VID = 0.9375V, CLKEN Pull High to 3.3V
Time (1ms/Div)
VID = 0.9375V, CLKEN Pull low to GND
Time (1ms/Div)
CPU Mode Power Down
CCM VID Change Down
VCC_SENSE
(100mV/Div)
VCC_SENSE
(1V/Div)
UGATE
(20V/Div)
PGOOD
(5V/Div)
VRON
(5V/Div)
LGATE
(5V/Div)
VIN = 12V, DPRSLPVR = GND, No Load
CLKEN
(5V/Div)
VID0
(2V/Div)
VID = 0.9375V, CLKEN Pull High to 3.3V
VID change from 0.9375V to 0.85V
Time (100μs/Div)
Time (20μs/Div)
CPU-DEM VID Change Down
CCM VID Change Up
VCC_SENSE
(100mV/Div)
VCC_SENSE
(100mV/Div)
UGATE
(20V/Div)
UGATE
(20V/Div)
LGATE
(5V/Div)
LGATE
(5V/Div)
VIN = 12V, DPRSLPVR = GND, No Load
VIN = 12V, DPRSLPVR = High, No Load
VID0
VID0
(2V/Div)
(2V/Div)
VID change from 0.85V to 0.9375V
VID change from 0.9375V to 0.85V
Time (20μs/Div)
Time (20μs/Div)
www.richtek.com
16
DS8153C/D-05 April 2011
RT8153C/D
CCM Load Transient Response
CCM Load Transient Response
VIN = 12V, VID = 0.9375V, ILOAD = 5A to 28A
DPRSLPVR =GND
VIN = 12V, VID = 0.9375V, ILOAD = 28A to 5A
DPSLPVR = High
VCC_SENSE
(100mV/Div)
VCC_SENSE
(100mV/Div)
UGATE
(20V/Div)
UGATE
(20V/Div)
LGATE
(5V/Div)
LGATE
(5V/Div)
Time (10μs/Div)
Time (10μs/Div)
Over Voltage Protection
Over Current Protection
VIN = 12V, VID= 0.9375V, DPRSLPVR =GND
VCC_SENSE
(1V/Div)
VCC_SENSE
(1V/Div)
ILOAD
(20A/Div)
UGATE
(20V/Div)
PHASE
(10V/Div)
LGATE
(10V/Div)
VIN = 12V, VID = 0.9375V, DPRSLPVR = GND
PGOOD
(2V/Div)
PGOOD
(2V/Div)
Time (10μs/Div)
Time (10μs/Div)
Under Voltage Protection
VCC_SENSE
(1V/Div)
UGATE
(20V/Div)
LGATE
(5V/Div)
PGOOD
(2V/Div)
VIN = 12V, VID = 0.9375, VDPRSLPVR = GND
Time (10μs/Div)
DS8153C/D-05 April 2011
www.richtek.com
17
RT8153C/D
Application Information
Differential Remote Sense Connection
The RT8153C/D is a single-phase PWM controller with
embedded gate driver. It is compliant with Intel IMVP6.5
Voltage Regulator Specification to fulfill its mobile CPU
and Render voltage regulator power supply requirement.
Inductor current are continuously sensed for loop control,
droop tuning, and over current protection. The 7-bit VID
DAC and low offset differential amplifier allow the controller
to maintain high regulating accuracy to meet Intel’s
IMVP6.5 specification.
The RT8153C/D includes differential, remote-sense inputs
to eliminate the effects of voltage drops along the PC
board traces, CPU internal power routes, and socket
contacts. CPU contains on-die sense pins VCC_SENSE and
VSS_SENSE. Connect RGND to VSS_SENSE. Connect FB to
VCC_SENSE with a resistor to build the negative input path
of the error amplifier. Connect VSEN to VCC_SENSE for
CLKEN, PGOOD, OVP, and UVP detection. The 7 bit VID
DAC and the precision voltage reference are referred to
RGNDfor accurate remote sensing.
Design Tool
To help users to reduce the efforts and errors caused by
manual calculations using the design concept below, a
user-friendly design tool is now available on request.
Current Sense Setting
The RT8153C/D is continuously sensing the inductor
current. Therefore, the controller can be less noise
sensitive. Low offset amplifiers are used for loop control
and over current detection. The internal current sense
amplifier gain (AI) is fixed to be 10. ISEN and ISEN_N
denote the positive and negative inputs of the current sense
amplifier.
This design tool calculates all necessary design
parameters by entering user's requirements. Please
contact Richtek's representatives for details.
Operation Modes
Table 2 shows the RT8153C/D operation modes. When
VRON is enabled (=1), the RT8153C/D will detect CLKEN
within 10μs to determine which operation mode is applied.
If CLKEN is low, the RT8153C/D will operate in Render
core voltage regulator mode. If CLKEN is high, the IC will
operate in CPU core voltage regulator mode.
Users can either use a current-sense resistor or the
inductor'sDCR for current sensing. Using inductor'sDCR
allows higher efficiency as shown in Figure 5. If
L
= R × C
(1)
X
X
DCR
then the transient performance will be optimum. For
example, choose L = 0.36μH with 1mΩ DCR and
CX = 100nF, to yield for RX :
DPRSLPVR determines whether the operation mode of
the controller operation is in CCM orDEM. The controller
enters DEM (Diode Emulation Mode) when DPRSLPVR
= 1 and enters CCM when DPRSLPVR = 0.
0.36μH
(2)
R
=
= 3.6kΩ
X
1m Ω ×1 0 0n F
Table 2. Control Signal Truth Table for Operation
Modes of the RT8153C/D
V
OUT
L
DCR
CLKEN DPRSLPVR Operation Mode
PHASE
C
R
X
X
0
(GND)
1
0
1
0
1
Render CCM
Render DEM
CPU CCM
+ V
-
X
ISEN
ISEN_N
(Pull High)
CPU DEM
Figure 5. Lossless Inductor Current Sensing
www.richtek.com
18
DS8153C/D-05 April 2011
RT8153C/D
so
Considering the inductance tolerance, the resistor, RX, has
to be tuned on board by examining the transient voltage.
If the output voltage transient has an initial dip below the
minimum load line requirement with a slow recovery, RX
is chosen too small. Vice-versa, with a resistance too
large, the output voltage transient has only a small initial
dip and the recovery become too fast, causing a ring-back.
R
R R − (mR
+ mR )R − mR
R
NTC
P
X
NTC
P
X
NTC P
R =
S
(7)
(−R
−R )R + m(R
+ R )
NTC
P
X
NTC P
RX can be expressed by :
−b ± b2 − 4ac
(8)
R
=
X
2a
where
a =ATHCTL −ATLCTH
Since theDCR of inductor is highly temperature dependent,
it affects the output accuracy, current monitor and over
current protection accuracy at hot conditions. Temperature
compensation is recommended for the lossless inductor
DCR current sense method. Figure 6 shows a simple but
effective way of compensating the temperature variations
of the sense resistor using an NTC thermistor at DCR
sensing network.
b =ATHDTL − BTLCTH − ATLDTH
c = BTLDTH − BTHDTL
where
ATH = RNTC_THRP − mTHRNTC_TH − mTHRP
ATL = RNTC_TLRP − mTLRNTC_TL − mTLRP
BTH = RNTC_THRP
V
OUT
L
DCR
PHASE
BTL = RNTC_TLRP
C
X
R
X
CTH = − RNTC_TH − RP
R
S
R
P
ISEN
CTL = − RNTC_TL − RP
R
NTC
DTH = mTH (RNTC_TH + RP)
DTL = mTL (RNTC_TL + RP)
ISEN_N
Figure 6. Lossless Inductor Current Sensing withNTC
Compensation
where XTH denotes the value of this variable at high
temperature, and XTL denotes the value of this variable at
low temperature.
Usually, RP is set to equal RNTC(25°C). RS is selected to
linearize theNTC's temperature characteristic. For a given
NTC, design is to get RS and RX to compensate the
temperature variations of the sense resistor.
Using current sense resistor in series with the inductor
can have better accuracy, but the efficiency is a trade-off.
Considering the equivalent inductance (LESL) of the current
sense resistor, a RC filter is recommended. The RC filter
calculation method is similar to the above-mentioned
inductorDCR sensing method.
Let
Requ = RS + (RP / /RNTC
)
(3)
(4)
Then, according to above circuit,
Loop Control
R
equ
L
DCR
= C
x
X
The RT8153C/Dadopts Richtek's proprietaryG-NAVPTM
topology. G-NAVPTM is based on the finite-gain current
mode with CCRCOT (Constant Current Ripple Constant
On Time) topology. The output voltage, VOUT, will decrease
with increasing output load current. The control loop
consists of PWM modulator with power stage, current
sense amplifier and error amplifier as shown in Figure 7.
R + R
X equ
Next, let
L
m =
(5)
DCR x CX
Then
R
×R
R
R
+ R
+ R
⎛
⎞
⎟
⎛
⎞
⎟
NTC
P
NTC
P
m× R + R +
= R × R +
X S
⎜
X
S
⎜
R
NTC
+ R
⎝
P ⎠
⎝
NTC
P ⎠
(6)
DS8153C/D-05 April 2011
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19
RT8153C/D
V
IN
whereAI is the internal current sense amplifier gain. RSENSE
is the current sense resistor. If no external sense resistor
present, it is the DCR of the inductor. RDROOP is the
resistive slope value of the converter output and is the
desired static output impedance.
RT8153C/D
UGATE
V
OUT
HS_FET
CCRCOT
PWM
Logic
L
R
X
C
LGATE
X
C
LS_FET
CMP
+
ISEN
V
COMP2
CS
+
-
A
ISEN_N
I
V
OUT
C2
R2
C1
R1
A
V2
> A
V1
COMP
V
V
CC_SENSE
FB
-
Offset
Cancellation
EA
SOFT
+
C
SOFT
A
A
V2
V1
10nF
RGND
V
DAC
SS_SENSE
Figure 7. Simplified Schematic for Droop and Remote
Sense in CCM
0
Load Current
Figure 8. ErrorAmplifierGain (AV) Influence on VOUT
The HS_FET on-time is determined by CCRCOT On-Time
generator. When load current increases, VCS increases,
the steady-state COMP voltage also increases and makes
VOUT decrease, achieving AVP. A near-DC offset
cancellation is added to the output of EA to cancel the
inherent output offset of finite-gain current mode controller.
As shown in Figure 9, whenDCR sensing network is used
for NTC thermistor temperature compensation, the error
amplifier gain can be calculated as :
A ×R
Z2
Z1
I
SENSE
(11)
A
=
=
×K
V
R
DROOP
where K is the dividing ratio of DCR sensing as shown
below :
In RFM, HS_FET is turned on with constant tON when VCS
is lower than VCOMP2. Once HS_FET is turned off, LS_FET
is turned on automatically. With Ringing-Free Technique,
LS_FET allows only partial negative current when the
inductor free-wheeling current reaches negative. The
switching frequency will be proportionately reduced, thus
the conduction and switching losses will be greatly
reduced.
Z2
Z1+ Z2
K =
(12)
V
OUT
L
DCR
PHASE
ISEN
C
X
Z1
Z2
Output Voltage Droop Setting (with Temperature
Compensation)
It's very easy to achieveActive Voltage Positioning (AVP)
by properly setting the error amplifier gain due to the native
droop characteristics. The target is to have
ISEN_N
Figure 9. Using anNTC Thermistor atDCR Sensing
Network
VOUT = VDAC − ILOAD x RDROOP
(9)
, then solving the switching condition VCOMP = VCS in Figure
7 yields the desired error amplifier gain as
Loop Compensation
Optimized compensation of the RT8153C/D allows for best
possible load step response of the regulator's output. A
compensator with one pole and one zero is adequate for
a proper compensation. Figure 7 shows the compensation
circuit. Prior design procedure shows how to determine
A ×R
R2
R1
I
SENSE
A
=
=
(10)
V
R
DROOP
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20
DS8153C/D-05 April 2011
RT8153C/D
the resistive feedback components of error amplifier gain.
The C1 and C2 must be calculated for the compensation.
The target is to achieve constant resistive output impedance
over the widest possible frequency range.
time by a period equal to the HS-FET rising dead time.
For better efficiency of the given load range, the maximum
switching frequency is suggested to be :
1
fS(MAX)
=
×
(17)
tON − tHS-Delay
The pole frequency of the compensator must be set to
compensate the output capacitor ESR zero :
⎡
⎤
VDAC(MAX) +ILOAD(MAX) × RON_LS-FET + DCRL − RDROOP
⎣
⎦
⎡ ⎤
+ILOAD(MAX) × RON_LS-FET − RON_HS-FET
V
IN(MAX)
1
⎣
⎦
fP =
(13)
2× π× C×RC
where
where C is the capacitance of output capacitor and RC is
the ESR of output capacitor. C2 can be calculated as
follows :
` fsMAX is the maximum switching frequency
` tHS- Delay is the turn on delay of HS-FET
` VDAC(MAX) is the maximum VDAC of application
` VINMAX is the maximum application Input voltage
` ILOAD(MAX) is the maximum load of application
` RON_LS-FET is the Low side FET RDS(ON)
` RON_HS-FET is the High side FET RDS(ON)
` DCRL is the inductorDCR
C×R
R2
C
C2 =
(14)
The zero of compensator has to be placed at half of the
switching frequency to filter the switching-related noise,
such that,
1
C1 =
(15)
R1b + R1a // R
× π× f
SW
(
)
NTC, 25
` RDROOP is the load line setting
TON Setting
High frequency operation optimizes the application for the
smaller component size, trading off efficiency due to higher
switching losses. This may be acceptable in ultra-portable
devices where the load currents are lower and the
controller is powered from a lower voltage supply. Low
frequency operation offers the best overall efficiency at
the expense of component size and board space. Figure
10 shows the On-Time setting circuit. Connect a resistor
(RTON) between VINand TONto set the on-time of UGATE:
R
TON
R1
C1
TON
V
IN
CCRCOT
On-Time
Generator
V
DAC
On-Time
Figure 10. On-Time setting with RC Filter
14.5×10−12 ×R
(V − V
× 2
Soft-Start and Mode Transition Slew Rates
TON
(16)
t
=
ON
)
The RT8153C/D uses 3 slew rates for various modes of
operation. The three slew rates are internally determined
by commanding one of three bi-directional current sources
(ISS) into the SOFT pin. The 7 bit VIDDAC and the precision
voltage reference are referred to RGNDfor accurate remote
sensing. Hence, connect a capacitor (CSOFT) from SOFT
pin to RGND for controlling the slew rate as shown in
Figure 7. The capacitance of capacitor is restricted to be
larger than 10nF. The voltage (VSOFT) on the SOFT pin is
the reference voltage of the error amplifier and is, therefore,
the commanded system voltage.
IN
DAC
where tON is UGATE turn on period, VIN is input voltage of
converter, VDAC isDAC voltage.
On-time translates only roughly to switching frequencies.
The on-times guaranteed in the Electrical Characteristics
are influenced by switching delays in external HS-FET.
Also, the dead-time effect increases the effective on-time,
reducing the switching frequency. It occurs only in CCM
(DPRSLPVR = 0) and during dynamic output voltage
transitions when the inductor current reverses at light or
negative load currents. With reversed inductor current,
PHASE goes high earlier than normal, extending the on-
The first current is typically 20μA used to charge or
discharge the CSOFT during soft-start, and soft-shutdown.
DS8153C/D-05 April 2011
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21
RT8153C/D
The second current is typically 50μA used during other
voltage transitions, including VID change and transitions
between operation modes. The third current is typically
100μA used during Render DEM with VID change up
transitions.
Power Up Sequence
When the controller's VCC voltage rises above the UVLO
threshold (typ. 4.3V), the power up sequence begins when
VRON goes high. If CLKEN = 1 (Pull High), the
RT8153C/D will enter CPU mode power-up sequence. If
CLKEN = 0 (Connect to GND), the controller will enter
Render mode power up sequence.
The IMVP−6.5 specification specifies the critical timing
associated with regulating the output voltage. The symbol,
SLEWRATE, as given in the IMVP−6.5 specification will
determine the choice of the SOFT capacitor, CSOFT, by the
following equation :
After the RT8153C/D enters CPU mode, VSEN starts
ramping up to VBOOT within 1ms. The slew rate during
power-up is 20μA/CSOFT. The RT8153C/Dpulls CLKENlow
after VSENgets across VBOOT − 0.1V for 73μs. Right after
CLKENgoes low, VSENstarts ramping to first VDAC value.
After CLKENgoes low for approximately 4.7ms, PGOOD
is asserted HIGH. DPRSLPVR is valid right after PGOOD
is asserted. UVP is masked as long as VSEN is less than
VBOOT − 0.1V.
ISS
CSOFT
=
(18)
SLEWRATE
4.3V
VCC
4.1V
UVLO
VRON
VID
XX
Valid
xx
V
BOOT
V
BOOT
- 0.1V
VSEN
0.2V
PWM
Hi-Z
CCM
XX
CCM
Pull Down
XX
DPRSLPVR Defined
Valid
DPRSLPVR
CLKEN
PGOOD
73µs typ.
4.7ms typ.
Figure 11. CPU Mode TimingDiagram for Power Up and PowerDown
After the RT8153C/Denters Render mode, VSENstarts ramping up to VDAC within 1ms. The slew rate during power-up
is 20μA/CSOFT. PGOOD is asserted HIGH after VSEN exceeds VDAC − 100mV for 4.77ms (typ.). DPRSLPVR is valid
right after PGOOD is asserted. UVP is masked as long as VSEN is less than VDAC − 100mV.
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22
DS8153C/D-05 April 2011
RT8153C/D
4.3V
4.1V
VCC
POR
VRON
VID
xx
XX
Valid
VDAC
VDAC-100mV
VSEN
PWM
0.2V
Hi-Z
CCM
Pull Down
XX
DPRSLPVR Defined
Valid
CCM
DPRSLPVR
XX
PGOOD
4.77ms typ.
Figure 12. Render Mode TimingDiagram for Power Up and PowerDown
Power Down
the joint of the voltage divider connected to OCSET pin as
shown in Figure 13. For a given ROC2, then
When VRONgoes low, the RT8153C/Denters low power
shutdown mode. PGOOD is pulled low immediately and
the VSOFT ramps down with slew rate of 20μA/CSOFT. VSEN
also ramps down following VSOFT.After VVSEN is lower than
200mV, the RT8153C/D turns off high side FETs and low
side FETs. An internal discharge resistor at VSEN will be
enabled and the analog part will be turned off.
V
⎛
⎞
CC
(20)
R
= R
×
OC2
−1
⎟
OC1
⎜
⎝
V
OCSET
⎠
V
CC
R
OC1
OCSET
R
OC2
Deeper Sleep Mode Transitions
AfterDPRSLPVR goes high, the RT8153C/Denters deeper
sleep mode operation. If the VIDs are set to a lower voltage
setting, the output drops at a rate determined by the load
and the output capacitance. The internal target VSOFT still
ramps as before, and UVP, OCP and OVP are masked for
73μs.
Figure 13. OCP Setting Without Temperature
Compensation
The RT8153C/D provides current limit function and over
current protection. The current limit function is triggered
when inductor current exceeds the current limit threshold,
ILIM, defined by VOCSET. When current limit function is
tripped, high side MOSFET will be forced off until the over
current condition is cleared.
Over Current Protection Setting
The RT8153C/Dcompares a programmable current limit
set point to the voltage from the current sense amplifier
output for over current protection (OCP). The voltage applied
to OCSET pin defines the desired current limit threshold
If the current limit function is triggered for 15 switching
cycles, OCP will be tripped. Once OCP is tripped, both
high side and low side MOSFET will be turned off, and the
internal discharge resistor at the VSEN pin will be enabled
to discharge output capacitors. OCP is a latched
protection, it can only be reset by cycling VRON or VCC.
ILIM
:
VOCSET = 48 x ILIM x RSENSE
(19)
Connect a resistive voltage divider from VCC toGND, with
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23
RT8153C/D
Over Voltage Protection (OVP)
state and the discharging resistor at VSEN pin will be
enabled. A reset can be executed by cycling VCC or
VRON.
The OVP circuit is triggered under two conditions (without
offset mode):
` Condition 1 : When VVSEN exceeds 1.7V.
Thermal Throttling Control
` Condition 2 : When VVSEN exceeds VDAC by 300mV
Intel IMVP-6.5 technology supports thermal throttling of
the processor to prevent catastrophic thermal damage.
The RT8153C/D includes a thermal monitoring circuit to
detect an exceeded user-defined temperature on a VR
point. The thermal monitoring circuit senses the voltage
change acrossNTC pin. Figure 14 shows the principle of
setting the temperature threshold. Connect an external
resistive voltage divider between Vcc andGND. This divider
uses aNegative Temperature Coefficient (NTC) thermistor
and a resistor. The joint of the voltage divider is connected
to the NTC pin in order to generate a voltage that is
inversely proportional to temperature. The RT8153C/D
pulls VRTT low if the voltage on the NTC pin is greater
than 0.8 x VCC. The internal VRTT comparator has a
hysteresis of 200mV (typ.) to prevent high frequency VRTT
oscillation when the temperature is near the setting point.
The minimum assertion/de-assertion time for VRTT toggling
is 1.6ms (typ.).
(typ.).
When offset mode, the relative over voltage protection is
disable and the over circuit is triggered until VVSEN exceeds
2V.
If either condition is valid, the RT8153C/D latches the
LGATE = 1 and UGATE = 0 as crowbar to the output
voltage of VR. Turning on all LS_FETs can lead to very
large reverse inductor current and potentially result in
negative output voltage of VR. To prevent the CPU from
damage by negative voltage. The RT8153C/Dturns off all
LS_FETs when VVSEN falls below −100mV.
Under Voltage Protection (UVP)
If VVSEN is lower than VDAC by 400mV (typ.) a UVP fault
will be tripped. Once UVP is tripped, both high side and
low side MOSFET will be turned off and the internal
discharge resistor at VSEN pin will be enabled. UVP is a
latched protection; it can only be reset by cycling VRON
or VCC.
V
CC
VRTT
NTC
NTC
CMP
+
-
Negative Voltage Protection (NVP)
R
TT
During the state when VVSEN is lower than −100mV, the
controller will force LGATE = 0 and UGATE = 0 to prevent
negative voltage. Once VVSEN recovers to be higher than
0V,NVP will be suspended and LGATE = 1 will be enabled
again.
+
0.8 x V
CC
Figure 14. Thermal Throttling Setting Principle
Furthermore, this pin also provides load line enable/disable
function in which the zero load line regulation can be
implemented through NTC pin. The NTC pin will sink a
80μA current pulse inward the IC at VRON rising edge
and the IC will detect the voltage of NTC pin at the same
time to determine whether the zero load line function is
enabled or not. Figure 15 is the recommended setting
network of zero load line. The 100kΩ NTC resistor is
recommended in this setting network for zero load line
application and the resistance of R1 is set to be the same
value as the resistor at 25°C. In addition, the resistance
of both R2 and R3 can be obtained by solving the equations
21 and 22.
Over Temperature Protection (OTP)
Over Temperature Protection prevents the VR from
damage. OTP is considered to be the final protection stage
against overheating of the VR. The thermal throttling VRTT
is set to be asserted prior to OTP to manage the VR power.
When this measure becomes insufficient to keep the die
temperature of the controller below the OTP threshold,
OTP will be asserted and latched. The die temperature of
the controller is monitored internally by a temperature
sensor. As a result of OTP triggering, a soft shutdown will
be launched and VVSEN will be monitored. When VVSEN is
less than 200mV, the driver remains in high impedance
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24
DS8153C/D-05 April 2011
RT8153C/D
for 120°C
VNTC
I
(MAX) = 30A, DCR = 1mΩ,
R3
=
x VCC = 4V
VCM = 1V, RCMSET = 10kΩ
(R1/ /RNTCHT ) + R2 + R3
(21)
(22)
⇒
RCM = 20.8kΩ
for − 20°C
VNTC
R3
=
x VCC = 1.5V
(R1/ /RNTCLT ) + R2 + R3
VSEN
V
Current
Monitor
Generator
CC_SENSE
R
CMSET
CMSET
CM
VRTT
V
CM
VCC
R
CM
C1
RGND
NTC
R1
Figure 16. Current Monitor Setting Principle
R2
NTC
CMP
+
-
When DCR sensing network is used for NTC thermistor
temperature compensation, the current monitor indication
voltage, VCM, can be calculated as below :
R3
0.8 x V
CC
Figure15. For Zero Load LineNetwork
Current Monitor
16×I
×DCR×R ×K
CM
LOAD
V
CM
=
(25)
R
CMSET
To find RCM and RCMSET follow below equation :
Figure 16 shows the current monitor setting principle.
Current monitor needs to meet IMVP6.5 specification. The
RT8153C/Dis based on the relation between RDROOP and
load current to provide an easy setting and high accuracy
current monitor indicator.
V
V
CM(MAX)
CM
=
(26)
R
16×I
×DCR×R ×K
CMSET
(MAX) CM
where, K is dividing ration of DCR sensing.
The current monitor indication voltage, VCM, is calculated
as :
No Load Offset
The RT8153C/D feature no-load offset function which
provides the possibility of wide range positive/negative
offset. The no-load offset function can be implemented
through OFS pin. To enable no-load offset function, the
voltage of the OFS pin should be higher than 0.9V at the
VRON raising edge. It is recommended to set the OFS
pin at 1.2V before VRON rising edge. The no-load offset
range can be from 400mV to −200mV while OFS pin
voltage varying from 1.6V to 1V. The output offset voltage
magnitude is equaled to the voltage difference between
OFS pin and the 1.2V. For example, the OFS pin should
be set to 1.4V if the target offset voltage is 200mV and
OFS pin should be set to 1.1V to have −100mV output
offset voltage. The accuracy of this offset voltage is 10mV
at no-offset point which OFS pin is 12V and the linearity
of no-load offset function is higher than 95% in the 400mV
16×I
×DCR×R
LOAD
CM
(23)
V
CM
=
R
CMSET
where ILOAD is the output load current, DCR is the load
line setting of applications, and RCM and RCMSET are the
current monitor current setting resistors.
To find RCM and RCMSET, follow below equation :
RCM
VCM
=
(24)
RCMSET 16×I(MAX) ×DCR
VCM must be kept equal to 1V and I(MAX) needs to follow
the setting current of the IMVP6.5 definition with various
CPU. VCM is clamped not higher than 1.15V.
For an example of current monitor setting, the following
design parameters are given :
DS8153C/D-05 April 2011
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25
RT8153C/D
to −200mV range. Furthermore, the offset function has
clamp mechanism to prevent the output voltage run-away.
The lower limit of the offset function is −300mV which
means the output offset voltage magnitude will keep exactly
−300mV even if the OFS pin voltage is lower than 0.9V. In
another hand, the upper limit of the offset function is about
600mV which means the output offset voltage magnitude
will keep about 600mV even if the OFS pin voltage is
higher than 1.8V.
maximum power dissipation can be calculated by the
following formula :
PD(MAX) = (TJ(MAX) − TA) / θJA
where TJ(MAX) is the maximum junction temperature, TAis
the ambient temperature, and θJA is the junction to ambient
thermal resistance.
For recommended operating condition specifications of
the RT8153C/D, the maximum junction temperature is
125°C and TA is the ambient temperature. The junction to
ambient thermal resistance, θJA, is layout dependent. For
WQFN-32L 4x4 packages, the thermal resistance, θJA, is
52°C/W on a standard JEDEC 51-7 four-layer thermal test
board. For WQFN-32L 5x5 packages, the thermal
resistance, θJA, is 36°C/W on a standard JEDEC 51-7
four-layer thermal test board. The maximum power
dissipation at TA = 25°C can be calculated by the following
formulas :
Inductor Selection
The switching frequency and ripple current determine the
inductor value as follows :
V
IN − VOUT
L(MIN)
=
× tON
(27)
IRipple−MAX
where tON is the UGATE turn on period.
Higher inductance yields in less ripple current and hence
in higher efficiency. The flaw is the slower transient
response of the power stage to load transients. This might
increase the need for more output capacitors driving the
cost up. Find a low-loss inductor having the lowest possible
DC resistance that fits in the allotted dimensions. The
core must be large enough not to be saturated at the
peak inductor current.
PD(MAX) = (125°C − 25°C) / (36°C/W) = 2.778W for
WQFN-32L 5x5 package
PD(MAX) = (125°C − 25°C) / (52°C/W) = 1.923W for
WQFN-32L 4x4 package
The maximum power dissipation depends on the operating
ambient temperature for fixed TJ(MAX) and thermal
resistance, θJA. For the RT8153C/Dpackages, the derating
curves in Figure 17 allow the designer to see the effect of
rising ambient temperature on the maximum power
dissipation.
Output Capacitor Selection
Output capacitors are used to obtain high bandwidth for
the output voltage beyond the bandwidth of the converter
itself. Usually, the CPU manufacturer recommends a
capacitor configuration. Two different kinds of output
capacitors can be found including, bulk capacitors closely
located to the inductors and ceramic output capacitors in
close proximity to the load. Latter ones are for mid-
frequency decoupling with especially small ESR and ESL
values while the bulk capacitors have to provide enough
stored energy to overcome the low frequency bandwidth
gap between the regulator and the CPU.
3.00
Four Layers PCB
2.80
2.60
2.40
2.20
2.00
1.80
1.60
1.40
1.20
1.00
0.80
0.60
0.40
0.20
0.00
WQFN-32L 5x5
WQFN-32L 4x4
Thermal Considerations
For continuous operation, do not exceed absolute
maximum junction temperature. The maximum power
dissipation depends on the thermal resistance of the IC
package, PCB layout, rate of surrounding airflow, and
difference between junction and ambient temperature. The
0
25
50
75
100
125
Ambient Temperature (°C)
Figure 17.Derating Curve for RT8153C/DPackage
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26
RT8153C/D
Layout Considerations
Careful PC board layout is critical to achieve low switching
losses and clean, stable operation. The switching power
stage requires particular attention. If possible, mount all
of the power components on the top side of the board
with their ground terminals flush against one another.
Follow these guidelines for optimum PC board layout :
` Keep the high current paths short, especially at the
ground terminals.
` Keep the power traces and load connections short. This
is essential for high efficiency.
` The slew rate control capacitor should be connected
from SOFT to RGND.
` When trade-offs in trace lengths must be made, it’s
preferable to allow the inductor charging path to be made
longer than the discharging path.
` Place the current sense component close to the
controller. ISENand ISEN_Nconnections for current limit
and voltage positioning must be made using Kelvin sense
connections to guarantee the current sense accuracy.
The PCB trace from the sense nodes to controller should
be parallel to each other.
` Route high-speed switching nodes away from sensitive
analog areas (SOFT, COMP, FB, VSEN, ISEN, ISEN_N,
CM, etc...)
DS8153C/D-05 April 2011
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27
RT8153C/D
Outline Dimension
D
D2
SEE DETAIL A
L
1
E
E2
1
2
1
2
e
b
DETAILA
A
Pin #1 ID and Tie Bar Mark Options
A3
A1
Note : The configuration of the Pin #1 identifier is optional,
but must be located within the zone indicated.
Dimensions In Millimeters
Dimensions In Inches
Symbol
Min
Max
Min
Max
A
A1
A3
b
0.700
0.000
0.175
0.180
4.950
3.400
4.950
3.400
0.800
0.050
0.250
0.300
5.050
3.750
5.050
3.750
0.028
0.000
0.007
0.007
0.195
0.134
0.195
0.134
0.031
0.002
0.010
0.012
0.199
0.148
0.199
0.148
D
D2
E
E2
e
0.500
0.020
L
0.350
0.450
0.014
0.018
W-Type 32L QFN 5x5 Package
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28
DS8153C/D-05 April 2011
RT8153C/D
1
2
1
2
DETAILA
Pin #1 ID and Tie Bar Mark Options
Note : The configuration of the Pin #1 identifier is optional,
but must be located within the zone indicated.
Dimensions In Millimeters
Dimensions In Inches
Symbol
Min
Max
Min
Max
A
A1
A3
b
0.700
0.000
0.175
0.150
3.900
2.650
3.900
2.650
0.800
0.050
0.250
0.250
4.100
2.750
4.100
2.750
0.028
0.000
0.007
0.006
0.154
0.104
0.154
0.104
0.031
0.002
0.010
0.010
0.161
0.108
0.161
0.108
D
D2
E
E2
e
0.400
0.016
L
0.300
0.400
0.012
0.016
W-Type 32L QFN 4x4 Package
Richtek Technology Corporation
Headquarter
Richtek Technology Corporation
Taipei Office (Marketing)
5F, No. 20, Taiyuen Street, Chupei City
Hsinchu, Taiwan, R.O.C.
5F, No. 95, Minchiuan Road, Hsintien City
Taipei County, Taiwan, R.O.C.
Tel: (8863)5526789 Fax: (8863)5526611
Tel: (8862)86672399 Fax: (8862)86672377
Email: marketing@richtek.com
Information that is provided by Richtek Technology Corporation is believed to be accurate and reliable. Richtek reserves the right to make any change in circuit
design, specification or other related things if necessary without notice at any time. No third party intellectual property infringement of the applications should be
guaranteed by users when integrating Richtek products into any application. No legal responsibility for any said applications is assumed by Richtek.
DS8153C/D-05 April 2011
www.richtek.com
29
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