RT8165B_技术文档

®

RT8165B

Dual Single-Phase PWM Controller for CPU and GPU Core

Power Supply

General Description

Features

^Dual Single-Phase PWM Controller for CPU Core

The RT8165B is a dual single-phase PWM controller with

integrated MOSFET drivers, compliant with Intel IMVP7

Pulse Width Modulation Specification to support both

CPU core andGPU core power. This part adoptsG-NAVP^TM

(Green-NativeAVP), which is a Richtek proprietary topology

derived from finite DC gain compensator in constant on-

time control mode. G-NAVP^TMmakes this part an easy

setting PWM controller to meet all Intel AVP (Active

Voltage Positioning) mobile CPU/GPU requirements. The

RT8165B uses SVIDinterface to control an 8-bitDAC for

output voltage programming. The built-in high accuracy

DAC converts the received VID code into a voltage value

ranging from 0V to 1.52V with 5mV step voltage. The

system accuracy of the controller can reach 0.8%. The

RT8165B operates in continuous conduction mode or

diode emulation mode, according to the SVIDcommand.

The maximum efficiency can reach up to 90% in different

operating modes according to different load conditions.

The droop function (load line) can be easily programmed

by setting the DC gain of the error amplifier. With proper

compensation, the load transient response can achieve

optimized AVP performance.

and GPU Core Power

^IMVP7 Compatible Power Management States

^Serial VID Interface

^G-NAVP^TMTopology

^AVP for CPU VR Only

^0.5% DAC Accuracy

^0.8% System Accuracy

^Differential Remote Voltage Sensing

^Built-in ADC for Platform Programming

 SETINI/SETINIA for CPU/GPU Core VR Initial

Startup Voltage

 TMPMAX to Set Platform Maximum Temperature

 ICCMAX/ICCMAXA for CPU/GPU Core VR

Maximum Current

 Power Good Indicator : VR_READY/VRA_READY for

CPU/GPU Core Power

 Thermal Throttling Indicator : VRHOT

 Diode Emulation Mode at Light Load Condition

 Fast Line/Load Transient Response

 Switching Frequency up to 1MHz per Phase

 OVP, UVP, NVP, OTP, UVLO, OCP

 Small 40-Lead WQFN Package

 RoHS Compliant and Halogen Free

The output voltage transition slew rate is set via the SVID

interface. The RT8165B supports both DCR and sense

resistor current sensing. The RT8165B provides

VR_READY and thermal throttling output signals for

IMVP7 CPU and GPU core. This part also features

complete fault protection functions including over voltage,

under voltage, negative voltage, over current and thermal

shutdown.

Applications

 IMVP7 Intel CPU/GPU Core Power Supply

 Laptop Computers

 AVP Step-Down Converter

The RT8165B is available in a WQFN-40L 5x5 small

footprint package.

©

is a registered trademark of Richtek Technology Corporation.

DS8165B-03 November 2013

www.richtek.com

1

RT8165B

Ordering Information

RT8165B

Pin Configurations

(TOP VIEW)

Package Type

QW : WQFN-40L 5x5 (W-Type)

Lead Plating System

G : Green (Halogen Free and Pb Free)

Z : ECO (Ecological Element with

Halogen Free and Pb free)

40 39 38 37 36 35 34 33 32 31

30

29

1

2

ISENAP

ISENAN

COMPA

FBA

RGNDA

VCLK

VDIO

ALERT

VRA_READY

VR_READY

BOOT1

TONSET

ISEN1P

ISEN1N

COMP

FB

RGND

GFXPS2

VCC

28

27

26

25

24

23

22

21

3

Note :

4

5

GND

Richtek products are :

6

 RoHS compliant and compatible with the current require-

ments of IPC/JEDEC J-STD-020.

7

8

41

9

 Suitable for use in SnPb or Pb-free soldering processes.

10

SETINIA

11 12 13 14 15 16 17 18 19 20

Marking Information

RT8165BGQW

RT8165BGQW : Product Number

WQFN-40L 5x5

RT8165B

GQW

YMDNN

YMDNN : Date Code

RT8165BZQW

RT8165BZQW : Product Number

YMDNN : Date Code

RT8165B

ZQW

YMDNN

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2

DS8165B-03 November 2013

RT8165B

Typical Application Circuit

R1

2.2

V

RT8165B

TONSET

R2

130k

R3

5.1

CC

9

V

IN

5V to 25V

2

VCC

5V

C1

1µF

C2

0.1µF

C3

V

R4

0

Q1

CCP

40

10µF

UGATE1

R6 R7 R8 R9 R10 R11

130 130 150 10k 10k 75

DCR = 7.6m

V

CORE

C4

0.1µF

0

R5

1

L1

BOOT1

Optional

1µH

39

25

24

23

22

21

20

PHASE1

VCLK

VDIO

ALERT

VRA_READ

VR_READY

VRHOT

VCLK

VDIO

ALERT

C26

C5

R12

0

Q2

38

37

R13

C7

330µF

/9m

330

µF

C6

0.068µF

LGATE1

PVCC

R14

3.9k

/9m

Y

VRA_READ

VR_READY

VRHOT

Y

5V

NTC

C8

1µF

1

R15

4.7k

R16

2.4k

ß = 3500

V

CC

3

4

ISEN1P

ISEN1N

R17

27k

R18

R19 R20

Optional

C10

8.7k 10k

10k

C9

Optional

C11

6

Optional

CORE V SEN

FB

18

OCSETA

OCSET

SETINIA

SETINI

16

10

11

OCSET

SETINIA

SETINI

SE

CC

R23

100

R22

10k

R21

71k

5

7

COMP

RGND

V

CORE

CORE V SENSE

SS

R24

10k

R25

R26

10k

R27

NC

R28

100

R34

5.1

R33

130k

V

31

IN

TONSETA

V

5V to 25V

CC

C12

0.1µF

R29

51k

R30

R31

R32

NC

0

Q3

R35

R36

150k 100k

C14

10µF

34

33

UGATEA

BOOTA

12

13

14

TMPMAX

ICCMAX

ICCMAXA

GFXPS2

TMPMAX

ICCMAX

ICCMAXA

GFXPS2

C13

0.1µF

m

DCR = 14.6

V

GFX

L2

2µH

Optional

8

35

36

PHASEA

C27

330µF

/15m

C17

C16

0.1µF

R43

11k

330µF

/15m

R42

C15

R37 R38

33k

R39 R40

1.6k 10k

R41

0

Q4

LGATEA

5.1k

NTC

A

R44

1k

R45

1.2k

1k

V

CC

ß = 3650

30

29

ISENAP

ISENAN

NTC

TA

R46

12k

NTC

R47

12k

T1

10k

ß = 3380

C18

ß = 3380

Optional

C19

Optional

C20

27

FBA

R71

750

R72

750

NSE

GFX V SE

CC

17

15

19

TSENA

TSEN

IBIAS

R48

42k

R49

10k

R50

100

28

26

COMPA

RGNDA

V

GFX

R52

1k

GFX V SENSE

SS

R53

1k

R54

53.6k

R51

100

41 (Exposed P

ad)

GND

32

Chip Enable

EN

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DS8165B-03 November 2013

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RT8165B

Table 1. IMVP7/VR12 Compliant VID Table

VID7

0

VID6

0

VID5

0

1

VID4

0

1

0

VID3

0

1

0

1

0

VID2

0

1

0

1

0

1

0

1

0

VID1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

VID0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

H1

0

1

2

H0

0

VDAC Voltage

0.000

0.250

0.255

0.260

0.265

0.270

0.275

0.280

0.285

0.290

0.295

0.300

0.305

0.310

0.315

0.320

0.325

0.330

0.335

0.340

0.345

0.350

0.355

0.360

0.365

0.370

0.375

0.380

0.385

0.390

0.395

0.400

0.405

0.410

0.415

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

0

1

2

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DS8165B-03 November 2013

RT8165B

VID7

0

VID6

0

1

VID5

1

0

VID4

0

1

0

VID3

0

1

0

1

0

VID2

0

1

0

1

0

1

0

1

0

1

VID1

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

VID0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

H1

2

3

4

H0

3

DAC Voltage

0.420

0.425

0.430

0.435

0.440

0.445

0.450

0.455

0.460

0.465

0.470

0.475

0.480

0.485

0.490

0.495

0.500

0.505

0.510

0.515

0.520

0.525

0.530

0.535

0.540

0.545

0.550

0.555

0.560

0.565

0.570

0.575

0.580

0.585

0.590

4

5

6

7

8

9

A

B

C

D

E

F

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

0

1

2

3

4

5

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RT8165B

VID7

0

VID6

1

VID5

0

1

VID4

0

1

0

VID3

0

1

0

1

0

1

VID2

1

0

1

0

1

0

1

0

1

0

VID1

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

VID0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

H1

4

5

6

H0

6

DAC Voltage

0.595

0.600

0.605

0.610

0.615

0.620

0.625

0.630

0.635

0.640

0.645

0.650

0.655

0.660

0.665

0.670

0.675

0.680

0.685

0.690

0.695

0.700

0.705

0.710

0.715

0.720

0.725

0.730

0.735

0.740

0.745

0.750

0.755

0.760

0.765

0.770

7

8

9

A

B

C

D

E

F

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

0

1

2

3

4

5

6

7

8

9

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DS8165B-03 November 2013

RT8165B

VID7

0

1

VID6

1

0

VID5

1

0

VID4

0

1

0

VID3

1

0

1

0

1

VID2

0

1

0

1

0

1

0

1

0

1

VID1

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

VID0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

H1

6

7

8

H0

A

B

C

D

E

F

0

DAC Voltage

0.775

0.780

0.785

0.790

0.795

0.800

0.805

0.810

0.815

0.820

0.825

0.830

0.835

0.840

0.845

0.850

0.855

0.860

0.865

0.870

0.875

0.880

0.885

0.890

0.895

0.900

0.905

0.910

0.915

0.920

0.925

0.930

0.935

0.940

0.945

0.950

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

0

1

2

3

4

5

6

7

8

9

A

B

C

D

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RT8165B

VID7

1

VID6

0

VID5

0

1

VID4

0

1

0

1

VID3

1

0

1

0

1

0

VID2

1

0

1

0

1

0

1

0

1

0

VID1

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

VID0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

H1

8

H0

E

F

0

DAC Voltage

0.955

0.960

0.965

0.970

0.975

0.980

0.985

0.990

0.995

1.000

1.005

1.010

1.015

1.020

1.025

1.030

1.035

1.040

1.045

1.050

1.055

1.060

1.065

1.070

1.075

1.080

1.085

1.090

1.095

1.100

1.105

1.110

1.115

1.120

1.125

1.130

8

9

1

9

2

9

3

9

4

9

5

9

6

9

7

9

8

9

A

B

C

D

E

F

0

9

A

B

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

0

1

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RT8165B

VID7

1

VID6

0

1

VID5

1

0

VID4

1

0

1

VID3

0

1

0

1

0

VID2

0

1

0

1

0

1

0

1

0

1

VID1

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

VID0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

H1

B

C

D

H0

2

DAC Voltage

1.135

1.140

1.145

1.150

1.155

1.160

1.165

1.170

1.175

1.180

1.185

1.190

1.195

1.200

1.205

1.210

1.215

1.220

1.225

1.230

1.235

1.240

1.245

1.250

1.255

1.260

1.265

1.270

1.275

1.280

1.285

1.290

1.295

1.300

1.305

1.310

3

4

5

6

7

8

9

A

B

C

D

E

F

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

0

1

2

3

4

5

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RT8165B

VID7

1

VID6

1

VID5

0

VID4

1

VID3

0

VID2

1

VID1

1

VID0

0

H1

D

E

H0

6

DAC Voltage

1.315

1.320

1.325

1.330

1.335

1.340

1.345

1.350

1.355

1.360

1.365

1.370

1.375

1.380

1.385

1.390

1.395

1.400

1.405

1.410

1.415

1.420

1.425

1.430

1.435

1

0

1

0

1

7

1

0

1

0

8

1

0

1

0

1

9

1

0

1

0

1

0

A

B

C

D

E

F

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

2

1

0

1

3

1

0

1

0

4

1

0

1

0

1

5

1

0

1

0

6

1

0

1

7

1

0

1

0

8

1

0

1

0

1

9

1

0

1

0

1

0

A

B

C

D

E

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

E

F

0

1

2

3

4

5

6

7

8

1.440

1.445

1.450

1.455

1.460

1.465

1.470

1.475

1.480

1.485

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DS8165B-03 November 2013

RT8165B

VID7

VID6

VID5

VID4

VID3

VID2

VID1

VID0

H1

F

H0

9

DAC Voltage

1.490

1

0

1

0

1

0

1

0

1

0

1

0

1

F

A

1.495

F

B

1.500

F

C

D

E

1.505

F

1.510

F

1.515

F

1.520

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is a registered trademark of Richtek Technology Corporation.

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RT8165B

Functional Pin Description

Pin No.

Pin Name

Pin Function

CPU VR Bootstrap Power Pin. This pin powers the high side MOSFET drivers.

Connect this pin to the PHASE1 pin with a bootstrap capacitor.

1

BOOT1

Single-Phase CPU VR On-Time Setting Pin. Connect this pin to V_INwith a

resistor to set ripple size in PWM mode.

2

TONSET

3

4

ISEN1P

ISEN1N

Positive Current Sense Input Pin of CPU VR.

Negative Current Sense Input Pin of CPU VR.

5

6

COMP

FB

CPU VR Compensation Pin. This pin is the output of the error amplifier.

CPU VR Feedback Pin. This pin is the inverting input node of the error amplifier.

Return Ground for CPU VR. This pin is the inverting input node for differential

remote voltage sensing.

Set Pin for GPU VR Operation Mode. Logic-high on this pin will force the GPU VR

to enter DCM.

Controller Power Supply Pin. Connect this pin to GND via a ceramic capacitor

larger than 1F.

7

8

9

RGND

GFXPS2

VCC

10

11

12

13

14

15

SETINIA

SETINI

ADC Input for Single-Phase GPU VR VBOOT Voltage Setting.

ADC Input for Single-Phase CPU VR VBOOT Voltage Setting.

ADC Input for Single-Phase CPU VR Maximum Temperature Setting.

ADC Input for Single-Phase CPU VR Maximum Current Setting.

ADC Input for Single-Phase GPU VR Maximum Current Setting.

Thermal Monitor Sense Input Pin for CPU VR.

TMPMAX

ICCMAX

ICCMAXA

TSEN

Set Pin for Single-Phase CPU VR Over Current Protection Threshold.

Connect a resistive voltage divider from VCC to ground, and connect the joint of

the voltage divider to the OCSET pin. The voltage, V_OCSET, at this pin sets the

over current threshold, I_LIMIT, for CPU VR.

16

17

18

OCSET

TSENA

OCSETA

Thermal Monitor Sense Input for GPU VR.

Set Pin for Single-Phase GPU VR Over Current Protection Threshold.

Connect a resistive voltage divider from VCC to ground, and connect the joint of

the voltage divider to the OCSETA pin. The voltage, V_OCSETA, at this pin sets the

over current threshold, I_LIMIT, for GPU VR.

Internal Bias Current Setting. Connect a 53.6k resistor from this pin to GND to

set the internal bias current.

19

IBIAS

20

21

22

Thermal Monitor Output Pin (active low).

VRHOT

VR_READY

CPU VR Voltage Ready Indicator. This pin has an open drain output.

VRA_READY GPU VR Voltage Ready Indicator. This pin has an open drain output.

23

24

25

Alert Line of SVID Interface (active low). This pin has an open drain output.

Data Transmission Line of SVID Interface.

Clock Signal Line of SVID Interface.

ALERT

VDIO

VCLK

Return Ground for Single-Phase GPU VR.

26

27

28

RGNDA

FBA

This pin is the inverting input node for differential remote voltage sensing.

GPU VR Feedback Pin. This pin is the inverting input node of the error amplifier.

Single-Phase GPU VR Compensation Pin. This pin is the output of the error

amplifier.

COMPA

29

30

ISENAN

ISENAP

Negative Current Sense Input Pin of Single-Phase GPU VR.

Positive Current Sense Input Pin of Single-Phase GPU VR.

Single-Phase GPU VR On-Time Setting Pin. Connect this pin to VIN with a

resistor to set ripple size in PWM mode.

31

TONSETA

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RT8165B

Pin No.

Pin Name

EN

Pin Function

Voltage Regulator Enable Signal Input Pin.

32

GPU VR Bootstrap Power Pin. This pin powers the high side MOSFET drivers.

Connect this pin to the PHASEA pin with a bootstrap capacitor.

Upper Gate Driver of GPU VR. This pin drives the high side MOSFET of GPU

VR.

33

34

BOOTA

UGATEA

Switch Node of GPU VR. This pin is the return node of the high side MOSFET

35

PHASEA driver for GPU VR. Connect this pin to the joint of the source of high side

MOSFET, drain of the low side MOSFET, and the output inductor.

Lower Gate Driver of GPU VR. This pin drives the low side MOSFET of GPU

36

37

38

LGATEA

VR.

MOSFET Driver Power Supply Pin. Connect this pin to GND via a ceramic

capacitor larger than 1F.

PVCC

Lower Gate Driver of CPU VR. This pin drives the low side MOSFET of CPU

LGATE1

VR.

Switch Node of CPU VR. This pin is the return node of the high side driver for

39

40

PHASE1

UGATE1

CPU VR. Connect this pin to the joint of the source of high side MOSFET, drain

of the low side MOSFET, and the output inductor.

Upper Gate Driver of CPU VR. This pin drives the high side MOSFET of CPU

VR.

Ground of Low Side MOSFET Driver. The exposed pad must be soldered to a

large PCB and connected to GND for maximum power dissipation.

41 (Exposed Pad) GND

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RT8165B

Function Block Diagram

UVLO

Control & Protection Logic

PWM CMP

MUX

ADC

From Control Logic

SVID XCVR

GFXPS2

DAC

RGNDA

TON Time

Generator

TONSETA

ERROR

AMP

Soft-Start & Slew

Rate Control

V

REFA

+

-

Offset

Cancellation

+

-

FBA

BOOTA

COMPA

UGATEA

PHASEA

PVCC

Driver Logic

Control

IBIAS

LGATEA

From Control Logic

DAC

To Protection Logic

ISENAP

ISENAN

+

10

-

RGND

OVP/UVP/NVP

OCP

OCSETA

TONSET

ERROR

AMP

Soft-Start & Slew

Rate Control

V

REF

TON Time

Generator

PWM CMP

+

-

Offset

Cancellation

+

-

FB

COMP

BOOT1

UGATE1

PHASE1

LGATE1

Driver Logic

Control

To Protection Logic

ISEN1P

ISEN1N

+

OCP

OVP/UVP/NVP

10

-

OCSET

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DS8165B-03 November 2013

RT8165B

Absolute Maximum Ratings (Note 1)

 PVCC, VCC to GND ------------------------------------------------------------------------------------- −0.3V to 6.5V

 RGNDx toGND ------------------------------------------------------------------------------------------- −0.3V to 0.3V

 TONSETx toGND ---------------------------------------------------------------------------------------- −0.3V to 28V

 Others ------------------------------------------------------------------------------------------------------- −0.3V to (V_CC+ 0.3V)

 BOOTx to PHASEx -------------------------------------------------------------------------------------- −0.3V to 6.5V

 PHASEx to GND

DC------------------------------------------------------------------------------------------------------------ −3V to 28V

<20ns ------------------------------------------------------------------------------------------------------- −8V to 32V

 UGATEx to PHASEx

DC------------------------------------------------------------------------------------------------------------ −0.3V to (BOOTx − PHASEx)

<20ns ------------------------------------------------------------------------------------------------------- −5V to 7.5V

 LGATEx toGND

DC------------------------------------------------------------------------------------------------------------ −0.3V to (PVCC + 0.3V)

<20ns ------------------------------------------------------------------------------------------------------- −2.5V to 7.5V

 Power Dissipation, P_D@ T_A= 25°C

WQFN−40L 5x5 ------------------------------------------------------------------------------------------- 2.778W

 Package Thermal Resistance (Note 2)

WQFN−40L 5x5, θ_JA------------------------------------------------------------------------------------- 36°C/W

WQFN−40L 5x5, θ_JC------------------------------------------------------------------------------------- 6°C/W

 Junction Temperature ------------------------------------------------------------------------------------ 150°C

 Lead Temperature (Soldering, 10 sec.)-------------------------------------------------------------- 260°C

 Storage Temperature Range --------------------------------------------------------------------------- −65°C to 150°C

 ESD Susceptibility (Note 3)

HBM (Human Body Mode) ----------------------------------------------------------------------------- 2kV

MM (Machine Mode) ------------------------------------------------------------------------------------- 200V

Recommended Operating Conditions (Note 4)

 Supply Voltage, V_CC------------------------------------------------------------------------------------- 4.5V to 5.5V

 Input Voltage, V_IN----------------------------------------------------------------------------------------- 5V to 25V

 Junction Temperature Range--------------------------------------------------------------------------- −40°C to 125°C

 Ambient Temperature Range--------------------------------------------------------------------------- −40°C to 85°C

Electrical Characteristics

(V_CC= 5V, T_A= 25°C, unless otherwise specified)

Parameter

Supply Input

Symbol

Test Conditions

Min

Typ Max Unit

V_CC/V_PVCC

V_IN

_VCC+ I_PVCC

V_EN= 1.05V, Not Switching

Battery Input Voltage

4.5

5

5.5

25

V

Input Voltage Range

--

Supply Current

(V_CC+ PVCC)

Supply Current

(TONSETx)

I

V_EN= 1.05V, Not Switching

--

12

20

--

mA

I_TONSETx

V_FB=1V, V_IN= 12V, R_TON= 100k

110

A

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RT8165B

Parameter

Symbol

Test Conditions

Min

Typ

Max

Unit

Shutdown Current

I

VCC_SHDN

V

= 0V

--

5

A

EN

(PVCC + V

)

+ I

CC

PVCC_SHDN

Shutdown Current

(TONSETx)

I

V

EN

--

5

A

TONSETx_SHDN

TON Setting

TONSETx Voltage

On-Time

V

I

= 80A, V

= 1V

0.95

315

1.075

350

1.2

0V

ns

TONSETx

RTON

FBx

t

I

= 80A, V

385

ON

RTON

FBx

TONSETx Input

Current Range

V

= 1.1V

25

--

280

--

A

RTON

FBx

Minimum Off-Time

T

350

ns

OFF_MIN

GFX VR Forced DEM

GFXPS2x Enable

Threshold

GFXPS2x Disable

Threshold

V

4.3

--

V

GFXPS

0.7

References and System Output Voltage

VID

OFS

Setting = 1.000V~1.520V

SVID

0.5

5

0

0.5

5

%VID

mV

Setting = 0V

SVID

VID

OFS

Setting = 0.800V~1.000V

SVID

Setting = 0V

SVID

DAC Accuracy

(PS0/PS1)

VID

OFS

Setting = 0.500V~0.800V

SVID

V

8

8

FBx

Setting = 0V

SVID

VID

OFS

Setting = 0.250V~0.500V

SVID

8

8

Setting = 0V

SVID

VID

OFS

Setting = 1.100V

SVID

10

10

Setting =0.640V~0.635V

SVID

V

= 0V, V

= 0V

0

0.3125 0.5125

INI_CORE

INI_GFX

V

= 0.9V, V

= 0.9V

INI_GFX

0.7375 0.9375 1.1375

1.3625 1.5625 1.7625

INI_CORE

SETINIx Voltage

IBIAS Pin Voltage

V

SETINIx

IBIAS

V

= 1V, V

= 1V

INI_CORE

INI_GFX

V

= 1.1V, V

= 1.1V

INI_GFX

2.6125

2.09

2.5

--

5

INI_CORE

R

= 53.6k

2.14

3.125

12.5

2.19

3.75

15

V

IBIAS

SetVID Slow

SetVID Fast

Dynamic VID Slew

Rate

SR

mV/s

DVID

10

Error Amplifier

DC Gain

A

R = 47k (Note5)

70

--

80

10

--

dB

DC

L

Gain-Bandwidth

Product

GBW

SR

C

LOAD

= 5pF

(Note5)

MHz

C

R

= 10pF (Gain = 4,

= 47k, V =

COMPx

LOAD

Slew Rate

--

5

--

V/s

COMP

LOAD_COMP

0.5V to 3V)

Output Voltage

Range

MAX Source/Sink

Current

V

I

R = 47k

0.5

--

3.6

V

COMP

L

V

COMP

= 2V

--

1

250

--

A

COMP

Impedance of FBx

R

M

FBx

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RT8165B

Parameter

Symbol

Test Conditions

Min

Typ

Max Unit

Current Sense Amplifier

Input Offset Voltage

V

1

1

--

1

--

mV

M

OFS_CSA

Impedance of Neg. Input R

ISENxN

Impedance of Pos. Input

R

1

ISENxP

Current Sense

Differential Input Range

V

= 1.1V,

= V

FBx

V

CSDIx

50

--

100

mV

V

CSDIx

 V

ISENxN

ISENxP

Current Sense DC Gain

(Loop)

A

V

= 1.1V, 30mV < V

= 1.1V 30mV < V

< 50mV

--

10

--

1

V/V

%

I

FBx

CSDIx

V

ISEN

Linearity

V

DAC

< 50mV

1

ISEN_ACC

ISEN_IN

Gate Driver

V

_BOOTx V

= 5V

PHASEx

= 0.1V

UGATEx

Upper Driver Source

R

--

1

--



UGATEx_sr

V_BOOTx V

Upper Driver Sink

Lower Driver Source

Lower Driver Sink

R

V

= 0.1V

--

1

--



UGATEx_sk

UGATEx

R

PVCC = 5V, PVCC  V

= 0.1V

LGATEx

LGATEx_sr

R

V

= 0.1V

0.5

LGATEx_sk

LGATEx

Internal Boot Charging

Switch On-Resistance

R

PVCC to BOOTx

= GND  V

--

30

10

--



BOOTx

Zero Current Detection

Threshold

V

mV

ZCD_TH

PHASEx

Protection

Under Voltage Lock-out

Threshold

V

VCC Falling edge

4.04 4.24

--

V

UVLO

Under Voltage Lock-out

Hysteresis

V

--

100

150

mV

V/V

UVLO

Over Voltage Protection

Threshold

Respect to VOUT_MAX

filter time

, with 1s

SVID

V

OVP

100

200

Under Voltage Protection

Threshold

V

= V

 V

, 0.8V < V

REFx REFx

UVP

ISENxN

V

UVP

350 300 250

<1.52V, with 3s filter time

Negative Voltage

Protection Threshold

V

NVP

V

NVP

= V_ISENxN GND

100 50

--

Current Sense Gain for

Over Current Protection

V

= 2.4V

OCSET

A

OC

--

48

V

 V

= 50mV

ISENxP

ISENxN

Logic Inputs

Logic-High

Logic-Low

V

With respect to 1V, 70%

With respect to 1V, 30%

0.7

--

EN Input

Threshold

Voltage

IH

V

IL

0.3

Leakage Current of EN

1

0.65

--

1

--

A

V

With respect to Intel Spec.

IH

VCLK,VDIO Input

Threshold Voltage

V

IL

0.45

Leakage Current of

VCLK, VDIO

I

1

--

1

A

LEAK_IN

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RT8165B

Parameter

ALERT

Symbol

V_ALERT

Test Conditions

Min

Typ

Max

Unit

ALERT Low Voltage

VR Ready

I_{ALERT_ SINK}= 4mA

--

0.4

V

VRx_READY Low Voltage V_{VRx_READY}I_{VRx_READY_ SINK}= 4mA

--

0.4

V

VRx_READY Delay

Thermal Throttling

VRHOT Output Voltage

t_{VRx_READY}V_ISENxN= V_BOOTto V_{VRx_READY}high

70

100

160

s

V_VRHOT

I_{VRHOT_SINK}= 40mA

--

0.4

--

1

V

High Impedance Output

ALERT, VRx_READY,

VRHOT

I_{LEAK_OUT}

1

A

Temperature Zone

TSEN Threshold for

Tmp_Zone [7] transition

100°C

97°C

94°C

91°C

88°C

85°C

82°C

75°C

--

1.8725

1.8175

1.7625

1.7075

1.6525

1.5975

1.5425

--

V

TSEN Threshold for

Tmp_Zone [6] transition

TSEN Threshold for

Tmp_Zone [5] transition

V_TSENx

TSEN Threshold for

Tmp_Zone [4] transition

TSEN Threshold for

Tmp_Zone [3] transition

TSEN Threshold for

Tmp_Zone [2] transition

TSEN Threshold for

Tmp_Zone [1] transition

V_TSENx

TSEN Threshold for

Tmp_Zone [0] transition

--

1.4875

1600

--

V

Update Period

ADC

t_TSEN

s

Latency

t_LAT

--

29

61

125

5

--

32

400

35

s

C_ICCMAX1

C_ICCMAX2

C_ICCMAX3

V_ICCMAX= 0.637V

V_ICCMAX= 1.2642V

V_ICCMAX= 2.5186V

decimal

Digital Code of ICCMAX

64

67

128

8

131 decimal

C_ICCMAXA1V_ICCMAXA= 0.1666V

11

19

35

88

decimal

Digital Code of ICCMAXA C_ICCMAXA2V_ICCMAXA= 0.3234V

C_ICCMAXA3V_ICCMAXA= 0.637V

13

29

82

97

122

16

32

C_TMPMAX1

Digital Code of TMPMAX C_TMPMAX2

C_TMPMAX3

V_TMPMAX= 1.6758V

V_TMPMAX= 1.9698V

V_TMPMAX= 2.4598V

85

100

125

103 decimal

128 decimal

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DS8165B-03 November 2013

RT8165B

Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are

stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in

the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may

affect device reliability.

Note 2. θ_JAis measured at T_A= 25°C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. θ_JCis

measured at the exposed pad of the package.

Note 3. Devices are ESD sensitive. Handling precaution is recommended.

Note 4. The device is not guaranteed to function outside its operating conditions.

Note 5. Guaranteed by design.

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RT8165B

Typical Operating Characteristics

CORE VR Power Off from EN

CORE VR Power On from EN

V_CORE

(500mV/Div)

V_CORE

(500mV/Div)

EN

(2V/Div)

EN

(2V/Div)

VR_READY

(2V/Div)

VR_READY

(2V/Div)

UGATE

(20V/Div)

UGATE

(20V/Div)

Boot VID = 1V

Time (100μs/Div)

CORE VR OCP

CORE VR OVP and NVP

V_CORE

(1V/Div)

I_LOAD

LGATE

(10A/Div)

(10V/Div)

VR_READY

(1V/Div)

VR_READY

(1V/Div)

UGATE

(20V/Div)

UGATE

(20V/Div)

VID = 1.1V

Time (100μs/Div)

Time (40μs/Div)

CORE VR Dynamic VID Up

CORE VR Dynamic VID Down

V_CORE

(500mV/Div)

VCLK

(2V/Div)

VCLK

(2V/Div)

VDIO

(2V/Div)

VDIO

(2V/Div)

ALERT

(2V/Div)

0.7V to 1.2V, Slew Rate = Slow, I_LOAD= 4A

1.2V to 0.7V, Slew Rate = Slow, I_LOAD= 4A

Time (40μs/Div)

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RT8165B

CORE VR Dynamic VID Down

CORE VR Dynamic VID Up

V_CORE

(500mV/Div)

VCLK

(2V/Div)

VCLK

(2V/Div)

VDIO

(2V/Div)

VDIO

(2V/Div)

ALERT

(2V/Div)

0.7V to 1.2V, Slew Rate = Fast, I_LOAD= 4A

1.2V to 0.7V, Slew Rate = Fast, I_LOAD= 4A

Time (10μs/Div)

CORE VR Load Transient

V_CORE

(20mV/Div)

8

I_LOAD

(A/Div)

1

VID = 1.1V, I_LOAD= 1A to 8A, Slew Time = 150ns

VID = 1.1V, I_LOAD= 8A to 1A, Slew Time = 150ns

Time (100μs/Div)

CORE VR Mode Transition

V_CORE

(20mV/Div)

VCLK

(1V/Div)

VCLK

(1V/Div)

LGATE

(10V/Div)

UGATE

(20V/Div)

VID = 1.1V, PS0 to PS2, I_LOAD= 0.2A

VID = 1.1V, PS2 to PS0, I_LOAD= 0.2A

Time (100μs/Div)

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RT8165B

CORE VR Thermal Monitoring

CORE VR V_REFvs. Temperature

1.006

1.004

1.002

1.000

0.998

0.996

0.994

0.992

0.990

1.9

1.7

TSEN

(V/Div)

VRHOT

(500mV/Div)

TSEN Sweep from 1.7V to 1.9V

Time (10ms/Div)

-50

-25

0

25

50

75

100

125

Temperature (°C)

GFX VR Power On from EN

GFX VR Power Off from EN

V_GFX

(500mV/Div)

V_GFX

(500mV/Div)

EN

(2V/Div)

EN

(2V/Div)

VRA_READY

(2V/Div)

VRA_READY

(2V/Div)

UGATEA

(20V/Div)

UGATEA

(20V/Div)

Boot VID = 1V

Time (100μs/Div)

GFX VR OCP

GFX VR OVP and NVP

V_GFX

(1V/Div)

VRA_READY

(1V/Div)

I_LOAD

(5A/Div)

LGATEA

(10V/Div)

VRA_READY

(1V/Div)

UGATEA

(20V/Div)

UGATEA

(20V/Div)

VID = 1.1V

Time (100μs/Div)

Time (40μs/Div)

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RT8165B

GFX VR Dynamic VID

V_GFX

(500mV/Div)

VCLK

(2V/Div)

VCLK

(2V/Div)

VDIO

(2V/Div)

VDIO

(2V/Div)

ALERT

(2V/Div)

0.7V to 1.2V, Slew Rate = Slow, I_LOAD= 1.25A

1.2V to 0.7V, Slew Rate = Slow, I_LOAD= 1.25A

Time (40μs/Div)

GFX VR Dynamic VID

V_GFX

(500mV/Div)

VCLK

(2V/Div)

VCLK

(2V/Div)

VDIO

(2V/Div)

VDIO

(2V/Div)

ALERT

(2V/Div)

0.7V to 1.2V, Slew Rate = Fast, I_LOAD= 1.25A

1.2V to 0.7V, Slew Rate = Fast, I_LOAD= 1.25A

Time (10μs/Div)

GFX VR Load Transient

V_GFX

(20mV/Div)

4

I_LOAD

(A/Div)

1

VID = 1.1V, I_LOAD= 1A to 4A, Slew Time = 150ns

VID = 1.1V, I_LOAD= 4A to 1A, Slew Time = 150ns

Time (100μs/Div)

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RT8165B

GFX VR Mode Transition

V_GFX

(20mV/Div)

VCLK

(1V/Div)

VCLK

(1V/Div)

LGATEA

(10V/Div)

LGATEA

(10V/Div)

UGATEA

(20V/Div)

UGATEA

(20V/Div)

VID = 1.1V, PS0 to PS2, I_LOAD= 0.1A

VID = 1.1V, PS2 to PS0, I_LOAD= 0.1A

Time (100μs/Div)

GFX VR V_REFvs. Temperature

GFX VR Thermal Monitoring

1.006

1.004

1.002

1.000

0.998

0.996

0.994

0.992

0.990

0.988

1.9

TSENA

(V/Div)

1.7

VRHOT

(500mV/Div)

TSENA Sweep from 1.7V to 1.9V

Time (10ms/Div)

-50

-25

0

25

50

75

100

125

Temperature (°C)

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DS8165B-03 November 2013

RT8165B

Application Information

The RT8165B is a VR12/IMVP7 compliant, dual single-

phase synchronous Buck PWM controller for the CPU

CORE VR and GFX VR. The gate drivers are embedded

to facilitate PCB design and reduce the total BOM cost. A

serial VID (SVID) interface is built-in in the RT8165B to

communicate with Intel VR12/IMVP7 compliant CPU.

The RT8165B supports VR12/IMVP7 compatible power

management states and VIDon-the-fly function. The power

management states includeDEM in PS2/PS3 and Forced-

CCM in PS1/PS0. The VID on-the-fly function has three

different slew rates : Fast, Slow andDecay. The RT8165B

integrates a high accuracy ADC for platform setting

functions, such as no-load offset and over current level.

The controller supports both DCR and sense-resistor

current sensing. The RT8165B provides VR ready output

signals of both CORE VR and GFX VR. It also features

complete fault protection functions including over voltage,

under voltage, negative voltage, over current and under

voltage lockout. The RT8165B is available in a WQFN-

48L 6x6 small foot print package.

The RT8165B adopts G-NAVP^TM(Green Native AVP),

which is Richtek's proprietary topology derived from finite

DC gain compensator, making it an easy setting PWM

controller to meet AVP requirements. The load line can

be easily programmed by setting the DC gain of the error

amplifier. The RT8165B has fast transient response due

to the G-NAVP^TMcommanding variable switching

frequency.

G-NAVP^TMtopology also represents a high efficiency

system with green power concept. With G-NAVP^TM

topology, the RT8165B becomes a green power controller

with high efficiency under heavy load, light load, and very

light load conditions. The RT8165B supports mode

transition function between CCM andDEM. These different

operating states allow the overall power system to have

low power loss. By utilizing the G-NAVP^TMtopology, the

operating frequency of RT8165B varies with output voltage,

load and VINto further enhance the efficiency even in CCM.

Design Tool

To help users reduce efforts and errors caused by manual

calculations, a user-friendly design tool is now available

on request. This design tool calculates all necessary

design parameters by entering user's requirements.

Please contact Richtek's representatives for details.

Serial VID (SVID) Interface

SVIDis a three-wire serial synchronous interface defined

by Intel. The three wire bus includes VDIO, VCLK and

ALERT signals. The master (Intel's VR12/IMVP7 CPU)

initiates and terminates SVID transactions and drives the

VDIO, VCLK, andALERT during a transaction. The slave

(RT8165B) receives the SVID transactions and acts

accordingly.

The built-in high accuracy DAC converts the SVID code

ranging from 0.25V to 1.52V with 5mV per step. The

differential remote output voltage sense and high accuracy

DAC allow the system to have high output voltage accuracy.

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RT8165B

Standard Serial VID Command

Master Payload

Slave Payload

Contents

Code

00h

Commands

Description

N/A

Contents

not supported

SetVID_Fast

N/A

Set new target VID code, VR jumps to new VID

target with controlled default “fast” slew rate

12.5mV/s.

Set new target VID code, VR jumps to new VID

target with controlled default “slow” slew rate

3.125mV/s.

Set new target VID code, VR jumps to new VID

target, but does not control the slew rate. The

output voltage decays at a rate proportional to

the load current

01h

02h

VID code

N/A

SetVID_Slow

N/A

03h

SetVID_Decay

VID code

Byte indicating

power states

04h

05h

06h

SetPS

N/A

Set power state

Pointer of registers

in data table

SetRegADR

SetReg DAT

Set the pointer of the data register

Write the contents to the data register

New data register

content

Specified

Register

Contents

Pointer of registers

in data table

Slave returns the contents of the specified

register as the payload

07h

GetReg

08h

-

not supported

N/A

1Fh

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RT8165B

Data and Configuration Register

Description

Index Register Name

Access

Default

1Eh

00h

01h

02h

05h

Vendor ID

Vendor ID, default 1Eh.

RO, Vendor

Product ID

Product ID.

65h

Product Revision

Protocol ID

Product Revision.

01h

SVID Protocol ID.

01h

Bit mapped register, identifies the SVID VR capabilities

and which of the optional telemetry register are

supported.

06h

VR_Capability

RO, Vendor

81h

10h

11h

Status_1

Status-2

Data register containing the status of VR.

R-M, W-PWM

00h

Data register containing the status of transmission.

Temperature

Zone

Data register showing temperature zone that have been

entered.

12h

R-M, W-PWM

00h

Data register showing direct ADC conversion of

averaged output current.

15h

1Ch

Output_Current

R-M, W-PWM

00h

Status_2_lastread The register contains a copy of the status_2.

Data register containing the maximum ICC of platform

21h

22h

ICC_Max

supports.

RO, Platform

--

Binary format in Amp, IE 64h = 100A.

Data register containing the temperature max the

platform supports.

Binary format in °C, IE 64h = 100°C

Only for CORE VR

Temp_Max

Data register containing the capability of fast slew rate

the platform can sustains. Binary format in mV/s, IE 0Ah

= 10mV/s.

24h

SR-Fast

RO

0Ah

Data register containing the capability of slow slew rate.

Binary format in mV/s IE 02h = 2.5mV/s.

25h

30h

SR-Slow

RO

02h

The register is programmed by the master and sets the

maximum VID.

VOUT_Max

RW, Master

FBh

31h

32h

33h

VID Setting

Power State

Offset

Data register containing currently programmed VID.

RW, Master

00h

Register containing the current programmed power state.

Set offset in VID steps.

Bit mapped data register which configures multiple VRs

behavior on the same bus.

34h

Multi VR Config

Pointer

RW, Master

00h

30h

Scratch pad register for temporary storage of the

SetRegADR pointer register.

35h

Notes :

RO = Read Only

RW = Read/Write

R-M = Read by Master

W-PWM = Write by PWM only

Vendor = hard coded by VR vendor

Platform = programmed by platform

Master = programmed by the master

PWM = programmed by the VR control IC

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RT8165B

Power Ready Detection and Power On Reset (POR)

ICCMAX, ICCMAXA and TMPMAX

During start-up, the RT8165B detects the voltage on the

The RT8165B provides ICCMAX, ICCMAXAand TMPMAX

pins for platform users to set the maximum level of output

current or VR temperature: ICCMAX for CORE VR

maximum current, ICCMAXA for GFX VR maximum

current, and TMPMAX for CORE VR maximum

temperature.

voltage input pins : VCC and EN. When VCC > V_UVLO

,

the RT8165B will recognize the power state of system to

be ready (POR = high) and wait for enable command at

EN pin. After POR = high and EN > V_ENTH, the RT8165B

will enter start-up sequence for both CORE VR and GFX

VR. If the voltage on any voltage pin drops below POR

threshold (POR = low), the RT8165B will enter power down

sequence and all the functions will be disabled. SVIDwill

be invalid within 300μs after chip becomes enabled. All

the protection latches (OVP, OCP, UVP, OTP) will be

cleared only after POR = low. EN = low will not clear

these latches.

To set ICCMAX, ICCMAXA and TMPMAX, platform

designers should use resistive voltage dividers on these

three pins. The current of the divider should be several

milli-Amps to avoid noise effect. The three items share

the same algorithms : theADC divides 5V into 255 levels.

Therefore, LSB = 5/255 = 19.6mV, which means 19.6mV

applied to ICCMAX pin equals to 1Asetting. For example,

if a platform designer wants to set TMPMAX to 120°C, the

voltage applied to TMPMAX should be 120 x 19.6mV =

2.352V. The ADC circuit inside these three pins will

decode the voltage applied and store the maximum current/

temperature setting into ICC_MAX and Temp_Max

registers. The ADC monitors and decodes the voltage at

these three pins only after EN = high. If EN = low, the

RT8165B will not take any action even when the VR output

current or temperature exceeds its maximum setting at

these ADC pins. The maximum level settings at these

ADC pins are different from over current protection or over

temperature protection. That means, these maximum level

setting pins are only for platform users to define their

system operating conditions and these messages will only

be utilized by the CPU.

VCC

EN

+

-

POR

V

UVLO

+

-

Chip EN

ENTH

Figure 3. Power Ready Detection and Power On Reset

(POR)

Precise Reference Current Generation

The RT8165B includes extensive analog circuits inside

the controller. These analog circuits need very precise

reference voltage/current to drive these analog devices.

The RT8165B will auto-generate a 2.14V voltage source

at IBIAS pin, and a 53.6kΩ resistor is required to be

connected between IBIAS and analog ground. Through

this connection, the RT8165B generates a 40μA current

from IBIAS pin to analog ground and this 40μAcurrent will

be mirrored inside the RT8165B for internal use. Other

types of connection or other values of resistance applied

at the IBIAS pin may cause failure of the RT8165B's analog

circuits. Thus a 53.6kΩ resistor is the only recommended

component to be connected to the IBIAS pin. The

resistance accuracy of this resistor is recommended to

be at least 1%.

V

CC

ICCMAX

A/D

Converter

ICCMAXA

TMPMAX

Figure 5. ADC Pins Setting

V_{INI_CORE}and V_{INI_GFX}Setting

The initial start up voltage (V_{INI_CORE}, V_{INI_GFX}) of the

RT8165B can be set by platform users through SETINI

and SETINIApins. Voltage divider circuit is recommended

Current

Mirror

2.14V

+

-

to be applied to SETINI and SETINIApins. The V_{INI_CORE}

/

IBIAS

V_{INI_GFX}relate to SETINI/SETINIA pin voltage setting as

shown in Figure 6. Recommended voltage setting at SETINI

and SETINIA pins are also shown in Figure 6.

53.6k

Figure 4. IBIAS Setting

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RT8165B

VCC (5

V)

V_{INI_CORE}

Recommended

V

=

= 1.1

1.1V

V_{INI_GFX}SETINI/SETINIA Pin Voltage

INI_CORE

V

INI_GFX

5

8

1.1V

1V

x VCC≒3.125V or VCC

3

8

x VCC≒1.875V

1/2 VCC

V

= 1V

INI_CORE

INI_GFX

3

V

0.9V

0V

x VCC≒0.9375V

16

1/4 VCC

1/8 VCC

GND

1

16

V

=

0.9V

INI_CORE

x VCC≒0.3125V or GND

V

= 0.9V

INI_GFX

V

= 0V

INI_CORE

INI_GFX

V

Figure 6. SETINI and SETINIA Pin Voltage Setting

Start Up Sequence

Power Down Sequence

The RT8165B utilizes internal soft-start sequence which

strictly follows Intel VR12/IMVP7 start up sequence

specifications. After POR = high and EN = high, a 300μs

delay is needed for the controller to determine whether all

the power inputs are ready for entering start up sequence.

If pin voltage of SETINI/SETINIA is zero, the output voltage

of CORE/GFX VR is programmed to stay at 0V. If pin

voltage of SETINI/SETINIA is not zero, VR output voltage

will ramp up to initial boot voltage (V_{INI_CORE},V_{INI_GFX}) after

both POR = high and EN = high. After the output voltage

of CORE/GFX VR reaches target initial boot voltage, the

controller will keep the output voltage at the initial boot

voltage and wait for the next SVID commands. After the

RT8165B receives valid VID code (typically SetVID_Slow

command), the output voltage will ramp up/down to the

target voltage with specified slew rate. After the output

voltage reaches the target voltage, the RT8165B will send

out VR_READY signal to indicate the power state of the

RT8165B is ready. The VR_READY circuit is an open-

drain structure so a pull-up resistor is recommended for

connecting to a voltage source.

Similar to the start up sequence, the RT8165B also utilizes

a soft shutdown mechanism during turn-off. After POR =

low, the internal reference voltage (positive terminal of

compensation EA) starts ramping down with 3.125mV/μs

slew rate, and output voltage will follow the reference

voltage to 0V. After output voltage drops below 0.2V, the

RT8165B shuts down and all functions are disabled. The

VR_READY will be pulled down immediately after POR =

low.

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RT8165B

VCC

POR

EN

EN Chip

(Internal Signal)

SVID

Valid

xx

XX

Off

300µs

0.2V

Off

V

CORE

CORE VR

Operation Mode

CCM

SVID defined

V

GFX

0.2V

Off

GFX VR

Operation Mode

CCM

SVID defined

100µs

VR_READY

VRA_READY

100µs

Figure 7 (a). Power sequence for RT8165B (V_{INI_CORE}= V_{INI_GFX}= 0V)

VCC

POR

EN

EN Chip

(Internal Signal)

300µs

SVID

xx

Valid

XX

250µs

V

INI_CORE

0.2V

Off

V

CORE

CORE VR

Operation Mode

Off

CCM

SVID defined

100µs

VR_READY

50µs

V

INI_GFX

V

GFX

0.2V

Off

GFX VR

Operation Mode

Off

CCM

SVID defined

CCM

100µs

VRA_READY

Figure 7 (b). Power sequence for RT8165B (V_{INI_CORE}0, V

0V)



INI_GFX

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RT8165B

Disable GFX VR : Before EN = High

Similar to the valley current mode control with finite

compensator gain, the high side MOSFET on-time is

determined by the CCRCOT PWM generator. When load

current increases, V_CSincreases, the steady state COMP

voltage also increases which makes the output voltage

decrease, thus achieving AVP.

GFX VR enable or disable is determined by the internal

circuitry that monitors the ISENAN voltage during start

up. Before EN= high,GFX VR detects whether the voltage

of ISENAN is higher than “VCC − 1V” to disable GFX

VR. The unused driver pins can be connected to GND or

left floating.

Droop Setting (with Temperature Compensation)

GFX VR Forced-DEM Function Enable : After

VRA_Ready = High

It's very easy to achieve the Active Voltage Positioning

(AVP) by properly setting the error amplifier gain due to

the native droop characteristics. The target is to have

The GFX VR's forced-DEM function can be enabled or

disabled with GFXPS2 pin. The RT8165B detects the

voltage ofGFXPS2 for forced-DEM function. If the voltage

atGFXPS2 pin is higher than 4.3V, theGFX VR operates

in forced-DEM. If this voltage is lower than 0.7V, theGFX

VR follows SVID power state command.

V_OUT= V_REFx− I_LOADx R_DROOP

(1)

Then solving the switching condition V_COMPx= V_CSxin

Figure 8 yields the desired error amplifier gain as

A R

R

R2

R1

I

SENSE

DROOP

(2)

A



V

where A_Iis the internal current sense amplifier gain and

R_SENSEis the current sense resistance. If no external sense

resistor is present, the DCR of the inductor will act as

R_SENSE. R_DROOPis the resistive slope value of the converter

output and is the desired static output impedance.

Loop Control

Both CORE and GFX VR adopt Richtek's proprietary G-

NAVP^TMtopology. G-NAVP^TMis based on the finite-gain

valley current mode with CCRCOT (Constant Current

Ripple Constant On Time) topology. The output voltage,

V_COREor V_GFX, will decrease with increasing output load

current. The control loop consists of PWM modulator with

power stage, current sense amplifier and error amplifier

as shown in Figure 8.

V

OUT

A

> A

V1

V2

A

V2

V1

V

IN

V

OUT

/V

0

High Side

MOSFET

UGATEx

PHASEx

Load Current

(V

)

CORE GFX

GFX/CORE VR

CCRCOT

Driver

Logic

L

Figure 9. ErrorAmplifierGain (A_V) Influence on V_OUT

Accuracy

PWM Generator

Control

R

C

LGATEx

Low Side

MOSFET

R

X

C

X

C

Since the DCR of inductor is temperature dependent, it

affects the output accuracy in high temperature conditions.

Temperature compensation is recommended for the

lossless inductor DCR current sense method. Figure 10

shows a simple but effective way of compensating the

temperature variations of the sense resistor using anNTC

thermistor placed in the feedback path.

CMP

ISENxP

ISENxN

V

CSx

+

Ai

-

C

Byp

C2

R2

C1

R1

CORE/GFX VR

COMPx

FBx

V

CC_SENSE

C2

C1

-

EA

CORE/GFX VR

RGNDx

+

V

R2

R1a

NTC

SS_SENSE

R1b

COMPx

V

VREFx

CC_SENSE

FBx

-

EA

RGNDx

V

+

SS_SENSE

Figure 8. Simplified Schematic for Droop and Remote

Sense in CCM

VREFx

Figure 10. Loop Setting with Temperature Compensation

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RT8165B

Usually, R1a is set to equal R_NTC(25°C), while R1b is

selected to linearize theNTC's temperature characteristic.

For a given NTC, the design would be to obtain R1b and

R2 and then C1 and C2. According to (2), to compensate

the temperature variations of the sense resistor, the error

amplifier gain (A_V) should have the same temperature

coefficient with R_SENSE. Hence

Loop Compensation

Optimized compensation of the CORE VR allows for best

possible load step response of the regulator's output. A

type-I compensator with one pole and one zero is adequate

for a proper compensation. Figure 10 shows the

compensation circuit. It was previously mentioned that to

determine the resistive feedback components of error

amplifier gain, C1 and C2 must be calculated for the

compensation. The target is to achieve constant resistive

output impedance over the widest possible frequency

range.

A

R

SENSE, HOT

V, HOT

(3)



A

R

SENSE, COLD

V, COLD

From (2), we can haveAv at any temperature (T) as

R2

A



(4)

V, T

The pole frequency of the compensator must be set to

R1a / /R

 R1b

NTC, T

compensate the output capacitor ESR zero :

1

The standard formula for the resistance ofNTC thermistor

as a function of temperature is given by :

(9)

f_P



2  CR_C

where C is the capacitance of the output capacitor and R_C

is the ESR of the output capacitor. C2 can be calculated

as follows :



1

298









 















T+273

(5)

R_{NTC, T} R_{NTC, 25}

e

where R_{NTC, 25}is the thermistor's nominal resistance at

room temperature, β (beta) is the thermistor's material

constant in Kelvins, and T is the thermistor's actual

temperature in Celsius.

CR

R2

C

(10)

C2 

The zero of compensator has to be placed at half of the

switching frequency to filter the switching-related noise.

Such that,

TheDCR value at different temperatures can be calculated

using the equation below :

1

C1 

(11)

R1b  R1a // R

  f

SW





NTC, 25C

DCR_T= DCR₂₅x [1+0.00393 x (T-25)]

(6)

TON Setting

where 0.00393 is the temperature coefficient of copper.

For a givenNTC thermistor, solving (4) at room temperature

(25°C) yields

High frequency operation optimizes the application by

trading off efficiency due to higher switching losses with

smaller component size. This may be acceptable in ultra-

portable devices where the load currents are lower and

the controller is powered from a lower voltage supply. Low

frequency operation offers the best overall efficiency at

the expense of component size and board space. Figure

11 shows the on-time setting circuit. Connect a resistor

(R_TONSETx) between V_INand TONSETx to set the on-time

of UGATEx :

R2 = A_{V, 25}x (R1b + R1a // R_{NTC, 25}

)

(7)

whereA_{V, 25°C}is the error amplifier gain at room temperature

obtained from (2). R1b can be obtained by substituting

(7) to (3),

R1b 

R_{SENSE, HOT}

(R1a //R_{NTC, HOT})  (R1a//R_{NTC, COLD}

)

R_{SENSE, COLD}

R_{SENSE, HOT}













-12

2810 R

1

TONSETx

(12)

t

(V

REFx

 1.2V) 

R_{SENSE, COLD}

(8)

ONx

V

 V

REFx

IN

where t_ONxis the UGATEx turn on period, VINis the input

voltage of converter, and V_REFxis the internal reference

voltage.

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DS8165B-03 November 2013

RT8165B

When V_REFxis larger than 1.2V, the equivalent switching

frequency may be over the maximum design range, making

it unacceptable. Therefore, the VR implements a pseudo-

constant-frequency technology to avoid this disadvantage

of CCRCOT topology. When V_REFxis larger than 1.2V,

the on-time equation will be modified to :

Differential Remote Sense Setting

The CORE/GFX VR includes differential, remote-sense

inputs to eliminate the effects of voltage drops along the

PC board traces, CPU internal power routes and socket

contacts. The CPU contains on-die sense pins CORE/

GFX V_{CC_SENSE}and V_{SS_SENSE}. Connect RGNDx to CORE/

GFX V_{SS_SENSE}. Connect FBx to CORE/GFX V_{CC_SENSE}

with a resistor to build the negative input path of the error

amplifier. The precision voltage reference V_REFxis referred

to RGND for accurate remote sensing.

t_ONx(V_REFx 1.2V)

23.3310^-12R_TONSETx V_REFx

(13)



V_IN V_REFx

On-time translates roughly to switching frequencies. The

on-times guaranteed in the Electrical Characteristics are

influenced by switching delays in external high side

MOSFET.Also, the dead-time effect increases the effective

on-time, reducing the switching frequency. It occurs only

in CCM during dynamic output voltage transitions when

the inductor current reverses at light or negative load

currents. With reversed inductor current, PHASEx goes

high earlier than normal, extending the on-time by a period

equal to the high side MOSFET rising dead time.

Current Sense Setting

The current sense topology of the CORE/GFX VR is

continuous inductor current sensing. Therefore, the

controller can be less noise sensitive. Low offset amplifiers

are used for loop control and over current detection. The

internal current sense amplifier gain (A_I) is fixed to be 10.

The ISENxP and ISENxNdenote the positive and negative

input of the current sense amplifier.

Users can either use a current sense resistor or the

inductor'sDCR for current sensing. Using inductor'sDCR

allows higher efficiency as shown in Figure 12. To let

For better efficiency of the given load range, the maximum

switching frequency is suggested to be :

1

f_S(MAX)(kHz) 



(15)

L

DCR

t_ON t_HSDelay

 R  C

X





V_REFx(MAX)I_LOAD(MAX) R_{ON_LSFET} DCR R_DROOPthen the transient performance will be optimum. For





example, choose L = 0.36μH with 1mΩ DCR and

C_X= 100nF, to yields for R_X:

0.36H





V

I_LOAD(MAX) R_{ON_LSFET}R_{ON_HSFET}

IN(MAX)





(14)

R



 3.6k

X

(16)

1m 10 0nF

where f_S(MAX)is the maximum switching frequency, t_HS-

_Delayis the turn on delay of high side MOSFET, V_REFx(MAX)

is the maximum application DAC voltage of application,

V_IN(MAX)is the maximum application input voltage,

I_LOAD(MAX)is the maximum load of application, R_{ON_LS-FET}

is the low side MOSFET R_DS(ON), R_{ON_HS-FET}is the high

side MOSFET R_DS(ON), DCR_Lis the inductor DCR, and

R_DROOPis the load line setting.

V

OUT

(V

/V

)

CORE GFX

L

DCR

PHASEx

C

X

R

X

ISENxP

ISENxN

+

V

CSx

A

I

-

C

Byp

Figure 12. Lossless Inductor Sensing

R

R1

C1

TONSETx

VREFx

GFX/CORE

VR CCRCOT

PWM

V

IN

Generator

On-Time

Figure 11. On-Time Setting with RC Filter

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RT8165B

V

Considering the inductance tolerance, the resistor R_Xhas

to be tuned on board by examining the transient voltage.

If the output voltage transient has an initial dip below the

minimum load line requirement with a slow recovery, R_X

is too small. Vice versa, if the resistance is too large the

output voltage transient will only have a small initial dip

and the recovery will be too fast, causing a ring-back.

CC

R

1

R

NTC

R

2

TSENx

R

3

Using current-sense resistor in series with the inductor

can have better accuracy, but the efficiency is a trade-off.

Considering the equivalent inductance (L_ESL) of the current

sense resistor, a RC filter is recommended. The RC filter

calculation method is similar to the above-mentioned

inductorDCR sensing method.

Figure 13. Thermal Monitoring Circuit

To meet Intel's VR12/IMVP7 specification, platform users

have to set the TSEN voltage to meet the temperature

variation of VR from 75% to 100% VR max temperature.

For example, if the VR max temperature is 100°C, platform

users have to set the TSEN voltage to be 1.4875V when

VR temperature reaches 75°C and 1.8725V when VR

temperature reaches 100°C. Detailed voltage setting

versus temperature variation is shown in Table 2.

Thermometer code is implemented in the Temperature

Zone register.

Operation Mode Transition

The RT8165B supports operation mode transition function

in CORE/GFX VR for the SetPS command of Intel's VR12/

IMVP7 CPU. The default operation mode of the RT8165B's

CORE/GFX VR is PS0, which is CCM operation. The other

operation mode is PS2 (DEM operation).

After receiving SetPS command, the CORE/GFX VR will

immediately change to the new operation state. When

VR receives SetPS command of PS2 operation mode,

the VR operates as a DEM controller.

Table 2. Temperature Zone Register

Comparator Trip Points

SVID Temperatures Scaled to maximum =

Thermal 100%

VRHOT

Alert Voltage Represents Assert bit

Minimum Level

If VR receives dynamic VID change command (SetVID),

VR will automatically enter PS0 operation mode. After

output voltage reaches target voltage, VR will stay at PS0

state and ignore former SetPS command. Only by

re-sending SetPS command after SetVID command will

VR be forced into PS2 operation state again.

b7

100%

b6

b5

b4

b3

b2

b1

b0

97% 94% 91% 88% 85% 82% 75%

1.745 1.69 1.635 1.58 1.52 1.47

1.855V 1.8V

V

5V

V

Temperature_Zone

Register Content

1111_1111

TSEN Pin Voltage

1.855  V_TSEN

Thermal Monitoring and Temperature Reporting

1.800  V_TSEN 1.835

1.745  V_TSEN 1.780

1.690  V_TSEN 1.725

1.635  V_TSEN 1.670

1.580  V_TSEN 1.615

1.525  V_TSEN 1.560

1.470  V_TSEN 1.505

V_TSEN 1.470

0111_1111

CORE/GFX VR provides thermal monitoring function via

sensing TSEN pin voltage. Through the voltage divider

resistors R1, R2, R3 and R_NTC, the voltage of TSEN will

be proportional to VR temperature. When VR temperature

rises, the TSENx voltage also rises. The ADC circuit of

VR monitors the voltage variation at TSENx pin from 1.47V

to 1.89V with 55mV resolution, and this voltage is decoded

into digital format and stored into the Temperature Zone

register.

0011_1111

0001_1111

0000_1111

0000_0111

0000_0011

0000_0001

0000_0000

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is a registered trademark of Richtek Technology Corporation.

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34

DS8165B-03 November 2013

RT8165B

V

CC

The RT8165B supports two temperature reporting,

VRHOT(hardware reporting) and ALERT(software

reporting), to fulfill VR12/IMVP7 specification. VRHOT is

an open-drain structure which sends out active-low VRHOT

signals. When TSEN voltage rises above 1.855V (100%

of VR temperature), the VRHOT signal will be set to low.

When TSEN voltage drops below 1.8V (97% of VR

temperature), the VRHOT signal will be reset to high. When

TSEN voltage rises above 1.8V (97% of VR temperature),

The RT8165B will update the bit1 data from 0 to 1 in the

Status_1 register and assertALERT. When TSENvoltage

drops below 1.745V (94% of VR temperature), VR will

update the bit1 data from 1 to 0 in the Status_1 register

and assertALERT.

R

OC1

OCSETx

R

OC2

Figure 14. OCP Setting without Temperature

Compensation

The current limit is triggered when inductor current

exceeds the current limit threshold I_LIMIT, defined by

V_OCSET. The driver will be forced to turn off UGATE until

the over current condition is cleared. If the over current

condition remains valid for 15 PWM cycles, VR will trigger

OCP latch. Latched OCP forces both UGATE and LGATE

to go low. When OCP is triggered in one of VRs, the

other VR will enter into soft shutdown sequence. The OCP

latch mechanism will be masked when VRx_READY =

low, which means that only the current limit will be active

when V_OUTis ramping up to initial voltage (or V_REFx).

The temperature reporting function for theGFX VR can be

disabled by pulling TSENA pin to VCC in case the

temperature reporting function for theGFX VR is not used

or the GFX VR is disabled. When the GFX VR's

temperature reporting function is disabled, the RT8165B

will reject the SVID command of getting the

Temperature_Zone register content of the GFX VR.

However, note that the temperature reporting function for

the CORE VR is always active. CORE VR's temperature

reporting function can not be disabled by pulling TSEN

pin to VCC.

If inductorDCR is used as the current sense component,

then temperature compensation is recommended for

protection under all conditions. Figure 15 shows a typical

OCP setting with temperature compensation.

V

CC

R

OC1a

NTC

OC1b

Over Current Protection

The CORE/GFX VR compares a programmable current

limit set point to the voltage from the current sense amplifier

output for Over Current Protection (OCP). The voltage

applied to OCSETx pin defines the desired peak current

R

OCSETx

R

OC2

limit threshold I_LIMIT

:

Figure 15. OCP Setting with Temperature Compensation

V_OCSET= 48 x I_LIMITx R_SENSE

(17)

Connect a resistive voltage divider from VCC toGND, with

the joint of the resistive divider connected to OCSET pin

as shown in Figure 14. For a given R_OC2, then

Usually, R_OC1ais selected to be equal to the thermistor's

nominal resistance at room temperature. Ideally, V_OCSET

is assumed to have the same temperature coefficient as

R_SENSE(InductorDCR) :

V





CC

(18)

R

 R



OC2

1



OC1





V

OCSET



V

R

SENSE, HOT

OCSET, HOT



(19)

V

R

SENSE, COLD

OCSET, COLD

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DS8165B-03 November 2013

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35

RT8165B

According to the basic circuit calculation, V_OCSETcan be

obtained at any temperature :

Negative Voltage Protection (NVP)

During OVP latch state, both CORE/GFX VRs also monitor

ISENxN pin for negative voltage protection. Since the OVP

latch will continuously turn on low side MOSFET of VR,

VR may suffer negative output voltage. Therefore, when

the voltage of ISENxN drops below −0.05V after triggering

OVP, VR will turn off low side MOSFETs while high side

MOSFETs remain off. TheNVP function will be active only

after OVP is triggered.

R_OC2

V_{OCSET, T} V_CC



R_OC1a/ /R_{NTC, T} R_OC1b R_OC2

(20)

Re-write (19) from (20), to get V_OCSETat room temperature

R

//R

 R

R

SENSE, HOT

OC1a

NTC, COLD

OC1b

OC2



R

//R

R

SENSE, COLD

OC1a

NTC, HOT

OC1b

OC2

(21)

Under Voltage Protection (UVP)

V_{OCSET, 25}

V_CC



R_OC2

Both CORE/GFX VR implement Under Voltage Protection



(22)

R_OC1a/ /R_{NTC, 25} R_OC1b R_OC2

(UVP). If ISENxNis less than V_REFxby 300mV + V_OFFSET

,

VR will trigger UVP latch. The UVP latch will turn off both

high side and low side MOSFETs. When UVP is triggered

by one of the VRs, the other VR will enter into soft

shutdown sequence. The UVP mechanism is masked

when VRx_READY = low.

Solving (21) and (22) yields R_OC1band R_OC2

R_OC2



 R_{EQU, HOT}R_{EQU, COLD} (1 )R_{EQU, 25}

V_CC

V_{OCSET, 25}

(1 )

(23)

(24)

R_OC1b



Under Voltage Lock Out (UVLO)

( 1)R2   R_{EQU, HOT}R_{EQU, COLD}

(1 )

During normal operation, if the voltage at the VCC pin

drops below UVLO falling edge threshold, both VR will

trigger UVLO. The UVLO protection forces all high side

MOSFETs and low side MOSFETs off to turn off.

where

 

R_{SENSE, HOT}

DCR₂₅[1 0.00393(T_HOT 25)]



R_{SENSE, COLD}DCR₂₅[1 0.00393(T_COLD 25)]

(25)

(26)

Inductor Selection

The switching frequency and ripple current determine the

inductor value as follows :

R_{EQU, T}= R_OC1a// R_{NTC, T}

V

_IN V_OUT

L_MIN



 t_ON

(27)

I_Ripple(MAX)

Over Voltage Protection (OVP)

where t_ONis the UGATE turn on period.

The over voltage protection circuit of CORE/GFX VR

monitors the output voltage via the ISENxN pin. The

supported maximum operating VID of VR (V_(MAX)) is stored

in the Vout_Max register. Once V_ISENxNexceeds “V_(MAX)

+ 200mV”, OVP is triggered and latched. VR will try to

turn on low side MOSFETs and turn off high side

MOSFETs to protect CPU. When OVP is triggered by

the one of the VRs, the other VR will enter soft shutdown

sequence. A 1μs delay is used in OVP detection circuit

to prevent false trigger.

Higher inductance induces less ripple current and hence

higher efficiency. However, the tradeoff is a slower transient

response of the power stage to load transients. This might

increase the need for more output capacitors, thus driving

up the cost. Find a low-loss inductor having the lowest

possibleDC resistance that fits in the allotted dimensions.

The core must be large enough not to be saturated at the

peak inductor current.

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36

DS8165B-03 November 2013

RT8165B

Output Capacitor Selection

 The capacitor connected to the ISEN1N/ISENANfor noise

decoupling is optional and it should also be placed close

to the ISEN1N/ISENAN pin.

Output capacitors are used to obtain high bandwidth for

the output voltage beyond the bandwidth of the converter

itself. Usually, the CPU manufacturer recommends a

capacitor configuration. Two different kinds of output

capacitors can be found, bulk capacitors closely located

to the inductors and ceramic output capacitors in close

proximity to the load. Latter ones are for mid-frequency

decoupling with very small ESR and ESL values while the

bulk capacitors have to provide enough stored energy to

overcome the low-frequency bandwidth gap between the

regulator and the CPU.

 The NTC thermistor should be placed physically close

to the inductor for better DCR thermal compensation.

Layout Consideration

Careful PC board layout is critical to achieving low

switching losses and clean, stable operation. The

switching power stage requires particular attention. If

possible, mount all of the power components on the top

side of the board with their ground terminals flushed

against one another. Follow these guidelines for optimum

PC board layout :

 Keep the high current paths short, especially at the

ground terminals.

 Keep the power traces and load connections short. This

is essential for high efficiency.

 When trade-offs in trace lengths must be made, it's

preferable to allow the inductor charging path to be made

longer than the discharging path.

 Place the current sense component close to the

controller. ISENxP and ISENxNconnections for current

limit and voltage positioning must be made using Kelvin

sense connections to guarantee the current sense

accuracy. The PCB trace from the sense nodes should

be parallel to the controller.

 Route high-speed switching nodes away from sensitive

analog areas (COMPx, FBx, ISENxP, ISENxN, etc...)

 Special attention should be paid in placing the DCR

current sensing components. TheDCR current sensing

capacitor and resistors must be placed close to the

controller.

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DS8165B-03 November 2013

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37

RT8165B

Outline Dimension

SEE DETAIL A

D

D2

L

1

E2

E

1

2

1

2

e

b

DETAILA

A

Pin #1 ID and Tie Bar Mark Options

A3

A1

Note : The configuration of the Pin #1 identifier is optional,

but must be located within the zone indicated.

Dimensions In Millimeters

Dimensions In Inches

Symbol

Min

Max

Min

Max

A

A1

A3

b

0.700

0.000

0.175

0.150

4.950

3.250

4.950

3.250

0.800

0.050

0.250

5.050

3.500

5.050

3.500

0.028

0.000

0.007

0.006

0.195

0.128

0.195

0.128

0.031

0.002

0.010

0.199

0.138

0.199

0.138

D

D2

E

E2

e

0.400

0.016

L

0.350

0.450

0.014

0.018

W-Type 40L QFN 5x5 Package

Richtek Technology Corporation

14F, No. 8, Tai Yuen 1^stStreet, Chupei City

Hsinchu, Taiwan, R.O.C.

Tel: (8863)5526789

Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should

obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot

assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be

accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third

parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.

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38

DS8165B-03 November 2013


型号：	RT8165B
厂家：	RICHTEK TECHNOLOGY CORPORATION
描述：	暂无描述
文件：	总38页 (文件大小：496K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

RT8165B [RICHTEK]

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