RT9024PE [RICHTEK]
Low-Dropout Linear Regulator Controller with PGOOD Indication; 低压差线性稳压器控制器的PGOOD指示
| 型号： | RT9024PE |
| 厂家： | 
RICHTEK TECHNOLOGY CORPORATION |
| 描述： | Low-Dropout Linear Regulator Controller with PGOOD Indication |
| 文件： | 总9页 (文件大小：218K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Preliminary
RT9024
Low-Dropout Linear Regulator Controller with PGOOD
Indication
General Description
Features
z 3.8V to 13.5V Operation Voltage
z 0.8V 2% High Accuracy Voltage Reference
z Quick Transient Response
The RT9024 is a low-dropout voltage regulator controller
with a specific PGOOD indicating scheme. The part could
drive an externalN-MOSFET for various applications. The
part is operated with VCC power ranging from 3.8V to
13.5V. With such a topology, it's with advantages of
flexible and cost-effective. The part comes to a small
footprint package of SOT-23-6.
z Power Good Indicator with Delay
z Enable Control
z Small Footprint Package SOT-23-6
z RoHS Compliant and 100% Lead (Pb)-Free
Applications
z DSC
Ordering Information
RT9024
Package Type
E : SOT-23-6
z DSLR
Operating Temperature Range
P : Pb Free with Commercial Standard
G : Green (Halogen Free with Commer-
cial Standard)
Pin Configurations
(TOP VIEW)
VCC DRI PGOOD
Note :
6
1
5
2
4
3
RichTek Pb-free and Green products are :
`RoHS compliant and compatible with the current require-
ments of IPC/JEDEC J-STD-020.
EN GND
FB
`Suitable for use in SnPb or Pb-free soldering processes.
`100%matte tin (Sn) plating.
SOT-23-6
Marking Information
Note : There is no pin1 indicator on top mark for SOT-23-6
type, and pin 1 will be lower left pin when reading top mark
from left to right.
For marking information, contact our sales representative
directly or through a RichTek distributor located in your
area, otherwise visit our website for detail.
Typical Application Circuit
V
V
IN
CC
Ccc
Chip Enable
1
6
5
EN
VCC
DRI
C
C
IN
2
3
RT9024
Q1
GND
FB
R
PGOOD
4
V
PGOOD
OUT
R1
OUT
PGOOD
R1+ R2
R2
R2
VOUT = 0.8
DS9024-01 March 2007
www.richtek.com
1
Preliminary
RT9024
Test Circuit
V
CC
V
IN
12V
V
CC
12V
Ccc
1uF
Chip Enable
C
1
6
5
IN
EN
VCC
DRI
Ccc
1uF
Chip Enable
5V
100uF
6
5
4
1
2
3
EN
VCC
DRI
2
3
RT9024
Q1
PHD3055
GND
FB
RT9024
V
100k
DRI
A
GND
FB
4
V
OUT
PGOOD
R
PGOOD
C
OUT
V
PGOOD
FB
PGOOD
100uF
R1
1k
C
FB
V
V
= 1V for current sink at DRI
FB
FB
R1+ R2
R2
2k
= 0.6V for current source at DRI
VOUT = 0.8
R2
Figure 1. Typical Test Circuit
Figure 2. DRI Source/Sink Current Test Circuit
Functional Pin Description
Pin No. Pin Name
Pin Function
1
2
3
4
5
6
EN
Chip Enable (Active High).
GND
FB
Ground.
Output Voltage Feedback.
Power Good Open Drain Output.
Driver Output.
PGOOD
DRI
VCC
Power Supply Input.
Function Block Diagram
EN
VCC
Reference
Voltage
0.8V
+
DRI
-
0.7V
Driver
PGOOD
GND
+
-
3ms
Delay
FB
www.richtek.com
2
DS9024-01 March 2007
Preliminary
Absolute Maximum Ratings (Note 1)
RT9024
z Supply Input Voltage, VCC ------------------------------------------------------------------------------------------- 15V
z Enable Voltage --------------------------------------------------------------------------------------------------------- 7V
z PowerGood Output Voltage ---------------------------------------------------------------------------------------- 7V
z Power Dissipation, PD @ TA = 25°C
SOT-23-6 ---------------------------------------------------------------------------------------------------------------- 0.4W
z Package Thermal Resistance (Note 4)
SOT-23-6, θJA ----------------------------------------------------------------------------------------------------------- 250°C/W
z Lead Temperature (Soldering, 10 sec.)--------------------------------------------------------------------------- 260°C
z Junction Temperature ------------------------------------------------------------------------------------------------- 150°C
z Storage Temperature Range ---------------------------------------------------------------------------------------- −65°C to 150°C
z ESD Susceptibility (Note 2)
HBM (Human Body Mode) ------------------------------------------------------------------------------------------ 2kV
MM (Machine Mode) -------------------------------------------------------------------------------------------------- 200V
Recommended Operating Conditions (Note 3)
z Supply Input Voltage, VCC ------------------------------------------------------------------------------------------- 3.8V to 13.5V
z Enable Voltage --------------------------------------------------------------------------------------------------------- 0V to 5.5V
z Junction Temperature Range---------------------------------------------------------------------------------------- −40°C to 125°C
z Ambient Temperature Range---------------------------------------------------------------------------------------- −40°C to 85°C
Electrical Characteristics
(VCC = 5V/12V, TA = 25°C, unless otherwise specified)
Parameter
Symbol
Test Conditions
Input Range
Min
Typ
Max Units
V
Operation Voltage Range
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
3.8
3.15
0.1
--
--
3.4
0.2
0.3
--
13.5
3.65
0.3
0.8
--
V
CC
POR Threshold
POR Hysteresis
Rising
V
Falling
= 12V
V
V
Supply Current
mA
mA
mA
V
CC
Driver Source Current
Driver Sink Current
= 12V, V
= 12V, V
= 12V, V
= 6V
= 6V
= 5V
5
DRI
DRI
DRI
5
--
--
Reference Voltage (V
)
0.784 0.8
0.816
6
FB
Reference Line Regulation (V
Amplifier Voltage Gain
PSRR at 100Hz, No Load
Power Good
)
= 4.5V to 15V
= 12V, No Load
= 12V, No Load
--
--
3
70
--
mV
dB
dB
FB
--
50
--
Rising Threshold
Hysteresis
V
CC
V
CC
V
CC
V
CC
V
CC
= 12V
85
--
--
1
90
15
0.2
3
95
--
%
%
= 12V
Sink Capability
= 12V @ 1mA
= 12V
0.4
10
20
V
Delay Time
ms
us
Falling Delay
= 12V
--
15
To be Continued
DS9024-01 March 2007
www.richtek.com
3
Preliminary
RT9024
Parameter
Test Conditions
Min
Typ
Max Units
Chip Enable
EN Rising Threshold
EN Hysteresis
V
CC
V
CC
V
CC
= 12V
= 12V
--
--
--
0.7
30
--
1
--
5
V
mV
uA
Standby Current
= 12V, V = 0V
EN
Note 1. Stresses listed as the above “Absolute Maximum Ratings” may cause permanent damage to the device. These are for
stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may remain possibility to affect device reliability.
Note 2. Devices are ESD sensitive. Handling precaution recommended.
Note 3. The device is not guaranteed to function outside its operating conditions.
Note 4. θJA is measured in the natural convection at TA = 25°C on a low effective thermal conductivity test board of
JEDEC 51-3 thermal measurement standard.
www.richtek.com
4
DS9024-01 March 2007
Preliminary
Typical Operating Characteristics
RT9024
Feedback Voltage vs. Temperature
Quiescent Current vs. Temperature
0.50
0.48
0.45
0.43
0.40
0.38
0.35
0.33
0.30
0.9
0.85
0.8
0.75
0.7
VIN = 1.5V, VCC = 12V, RPGOOD = 100k
CIN = COUT = 100uF, R1 = 1k, R2 = 2k
VIN = 1.5V, VCC = 12V, RPGOOD = 100k
CIN = COUT = 100uF, R1 = 1k, R2 = 2k
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
(°C)
Temperature
(°C)
Temperature
DRI Source Current vs. Temperature
DRI Sink Current vs. Temperature
60
30
27
24
21
18
15
12
55
50
45
40
35
VFB = 1V, VCC = 12V, VDRI = 6V
-50 -25 25 50
VFB = 0.6V, VCC = 12V, VDRI = 6V
-50 -25 25 50
0
75
100
125
0
75
100
125
(°C)
Temperature
(°C)
Temperature
DRI Sink Current vs. DRI Voltage
PGOOD Delay Time vs. Temperature
4
3.5
3
25
20
15
10
5
VIN = 1.5V, VCC = 12V
RPGOOD = 100k
R1 = 1k, R2 = 2k
2.5
2
TA = 25°C
1.5
0
-50
-25
0
25
50
75
100
125
0
0.5
1
1.5
2
2.5
3
(°C)
Temperature
DRI Voltage (V)
DS9024-01 March 2007
www.richtek.com
5
Preliminary
RT9024
PGOOD Delay Time
PGOOD Delay Time
VCC = 12V, ILOAD = 1A
CIN = COUT = 100uF
VCC = 12V, CIN = COUT = 100uF, ILOAD = 100mA
VOUT
VOUT
ILoad (A)
VPGOOD
VPGOOD
VEN (V)
VEN (V)
Time (500us/Div)
Time (500us/Div)
PGOOD Off
Enable Threshold Voltage vs. Temperature
1
VCC = 12V
VIN = 1.5V, VCC = 12V, RPGOOD = 100kΩ
VOUT
C
IN = COUT = 100uF
C
IN = COUT = 100uF, R1 = 1k, R2 = 2k
0.95
0.9
Turn on
0.85
0.8
ILoad (A)
Turn off
0.75
0.7
VPGOOD
VEN (V)
0.65
0.6
-50
-25
0
25
50
75
100
125
Time (50us/Div)
Temperature
(°C)
Load Transient Response
Line Transient Response
VIN = 2.5V, VOUT = 1.2V
CIN = COUT = 100uF
VIN = 1.5V to 2.5V, ILOAD = 100mA
IN = 2.2uF, COUT = 100uF
C
20
0
10
0
-20
-10
5
0
2.5
1.5
Time (250us/Div)
Time (100us/Div)
www.richtek.com
6
DS9024-01 March 2007
Preliminary
RT9024
Application Information
Capacitors Selection
MOSFET Selection
Careful selection of the external capacitors for RT9024 is
highly recommended in order to remain high stability and
performance.
The RT9024 are designed to driver external N-MOSFET
pass element. MOSFET selection criteria include
threshold voltage VGS (VTH), maximum continuous drain
current ID, on-resistance RDS(ON) ,maximum drain-to-
Regarding the supply voltage capacitor, connecting a
capacitor which is ≥ 1μF between VCC and ground is a
must. The capacitor improves the supply voltage stability
for proper operation.
source voltage VDS and package thermal resistance θ(JA)
.
The most critical specification is the MOSFET RDS(ON).
Calculate the required RDS(ON) from the following formula:
V - VOUT
IN
Regarding the input capacitor, connecting a capacitor which
≥ 100μF between VIN and ground is recommended to
increase stability. With large value of capacitance could
result in better performance for both PSRR and line
transient response.
N−MOSFET RDS(ON) =
ILOAD
For example, the MOSFET operate up to 2A when the
input voltage is 1.5V and set the output voltage is 1.2V,
RON = (1.5V-1.2V) / 2A = 150mΩ, the MOSFET's
RON must be lower than 150mΩ. Philip PHD3055E
MOSFET with an RDS(ON) of 120mΩ(typ.) is a suitable
solution.
When driving external pass element, connecting a
capacitor ≥ 100μF between VOUT and ground is
recommended for stability. With larger capacitance can
reduce noise and improve load transient response and
PSRR.
The power dissipation is calculate as :
PD = (VIN − VOUT) x ILOAD
The thermal resistance from junction to ambient θ(JA) is :
(T − T )
Output Voltage Setting
J
A
θ
=
(JA)
P
D
The RT9024 develops a 0.8V reference voltage; especially
suitable for low voltage application.As shown in application
circuit, the output voltage could easy set the output
voltage by R1 & R2 divider resistor.
In this example, PD = (1.5V − 1.2V) x 2A = 0.6W. The
PHD3055E's θ(JA) is 75°C/W for itsD-PAK package, which
translates to a 45°C temperature rise above ambient. The
package provides exposed backsides that directly transfer
heat to the PCB board.
Power Good Function
The RT9024 has the power good function with delay. The
power good output is an open drain output. Connect a
100kΩ pull up resistor to VOUT to obtain an output voltage.
When the output voltage arrives 90% of normal value.
PGOODwill become active and be pulled high by external
circuits with typically 3ms delay.
PNP Transistor Selection
The RT9024 could driver the PNP transistor to sink output
current. PNP transistor selection criteria includeDC current
gain hFE, threshold voltage VEB, collector-emitter voltage
VEN, maximum continues collector current IC, package
thermal resistance θ(JA).
Chip Enable Operation
For example, the PNP transistor operates sink current up
to 0.5A when the input voltage is 1.5V and set the output
voltage is 1.2V. As show in Figure 3. A KSB772 PNP
transistor, the VEN = 1.2V, VBE = -1V, IC = 0.5A, IB = 0.5/
160 ≥ 3.125mA, when the DRI pin voltage is 0.2V could
sink 6.8mA(MAX) is a close match.
Pull the EN pin low to drive the device into shutdown mode.
During shutdown mode, the standby current drops to
5μA(MAX). The external capacitor and load current determine
the output voltage decay rate. Drive the EN pin high to
turn on the device again.
DS9024-01 March 2007
www.richtek.com
7
Preliminary
RT9024
DRI Sink Current vs. DRI Voltage
25
V
IN
20
15
10
5
PGOOD
R
C
IN
VCC
Q1
DRI
V
CC
Ccc
PGOOD
V
PGOOD
GND
EN
OUT
RT9024
Chip Enable
FB
C
R1
R2
OUT
Q2
TA = 25°C
0
0
0.5
1
1.5
2
2.5
3
Figure 3
DRI Voltage (V)
Figure 4
Layout Considerations
There are three critical layout considerations. One is the divider resistors should be located to RT9024 as possible to
avoid inducing any noise. The second is capacitors place. The CIN and COUT have to put at near the N-MOSFET for
improve performance. The third is the copper area for pass element. We have to consider when the pass element
operating under high power situation that could rise the junction temperature. In addition to the package thermal resistance
limit, we could add the copper area to improve the power dissipation. As show in Figure 5 and Figure 6.
V
IN
V
IN
PGOOD
C
IN
VCC
Q1
DRI
V
GND
CC
Ccc
R
PGOOD
PGOOD
GND
EN
V
OUT
PGOOD
FB
V
CC
RT9024
Chip Enable
FB
R1
R2
C
V
OUT
OUT
EN
GND
Figure 5
Figure 6
www.richtek.com
8
DS9024-01 March 2007
Preliminary
RT9024
Outline Dimension
H
D
L
C
A
B
b
A1
e
Dimensions In Millimeters
Dimensions In Inches
Symbol
Min
Max
Min
Max
A
A1
B
0.889
0.000
1.397
0.250
2.591
2.692
0.838
0.080
0.300
1.295
0.152
1.803
0.560
2.997
3.099
1.041
0.254
0.610
0.031
0.000
0.055
0.010
0.102
0.106
0.033
0.003
0.012
0.051
0.006
0.071
0.022
0.118
0.122
0.041
0.010
0.024
b
C
D
e
H
L
SOT-23-6 Surface Mount Package
Richtek Technology Corporation
Headquarter
Richtek Technology Corporation
Taipei Office (Marketing)
5F, No. 20, Taiyuen Street, Chupei City
Hsinchu, Taiwan, R.O.C.
8F, No. 137, Lane 235, Paochiao Road, Hsintien City
Taipei County, Taiwan, R.O.C.
Tel: (8863)5526789 Fax: (8863)5526611
Tel: (8862)89191466 Fax: (8862)89191465
Email: marketing@richtek.com
DS9024-01 March 2007
www.richtek.com
9
相关型号：
©2020 ICPDF网 联系我们和版权申明