RT9212GC [RICHTEK]
Dual 5V Synchronous Buck PWM DC-DC and Linear Power Controller; 5V双路同步降压PWM DC -DC和线性电源控制器
| 型号： | RT9212GC |
| 厂家： | 
RICHTEK TECHNOLOGY CORPORATION |
| 描述： | Dual 5V Synchronous Buck PWM DC-DC and Linear Power Controller |
| 文件： | 总14页 (文件大小：301K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Preliminary
RT9212
Dual 5V Synchronous Buck PWM DC-DC and Linear Power
Controller
General Description
Features
z Operating with Single 5V Supply Voltage
z Drives All Low Cost N-MOSFETs
z Voltage Mode PWM Control
The RT9212 is a 3-in-one power controller delivers high
efficiency and tight regulation from two voltage regulating
synchronous buck PWM DC-DC and one linear power
controllers.
z 300kHz Fixed Frequency Oscillator
z Fast Transient Response :
The RT9212 can control two independent output voltages
adjustment in range of 0.8V to 4.0V with 180 degrees
channel to channel phase operation to reduce input ripple.
In dual power supply application the RT9212 monitors the
output voltage of both Channel 1 and Channel 2. An
independent PGOOD (power good) signal is asserted for
each channel after the soft-start sequence has completed,
and the output voltage is within 15% of the set point. The
linear controller drives an external transistor to provide an
adjustable output voltage.
Full 0% to 100% Duty Ratio
z Internal Soft-Start
z Adaptive Non-Overlapping Gate Driver
z Over-Current Fault Monitor on VCC, No Current
Sense Resistor Required
z RoHS Compliant and 100% Lead (Pb)-Free
Applications
z Graph Card
z Motherboard, Desktop Servers
z IA Equipments
Built-in over-voltage protection prevents the output from
going above 137.5% of the set point by holding the lower
MOSFET on and the upper MOSFET off.Adjustable over-
current protection (OCP) monitors the voltage drop across
the RDS(ON) of the upper MOSFET for each synchronous
buck PWMDC-DC controller individually.
z Telecomm Equipments
z High PowerDC-DC Regulators
Pin Configurations
(TOP VIEW)
24
23
22
21
20
19
18
17
16
15
14
13
UGATE1
BOOT1
PHASE1
NC
FB1
COMP1
NC
PGND1
LGATE1
2
3
4
5
6
Ordering Information
RT9212
PVCC1
OCSET1/SD
OCSET2/SD
PGOOD
FB2
FBL
DRV
VCC
LGATE2
PGND2
Package Type
C : TSSOP-24
7
8
9
10
11
12
Operating Temperature Range
P : Pb Free with Commercial Standard
G : Green (Halogen Free with Commer-
cial Standard)
NC
GNDA
PHASE2
BOOT2
UGATE2
Note :
TSSOP-24
RichTek Pb-free and Green products are :
`RoHS compliant and compatible with the current require-
ments of IPC/JEDEC J-STD-020.
`Suitable for use in SnPb or Pb-free soldering processes.
`100% matte tin (Sn) plating.
DS9212-05 March 2007
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1
Preliminary
RT9212
Typical Application Circuit
V
V
IN
CC
5V
2.5V/3.3V/5V
( >V
& V
)
OUT2
V
OUT1
IN
2.5V/3.3V/5V
C3
C10
470uF
R9
10k
D1
1N4148
C1
C2
1uF
R1
3.48k
R2
3.48k
1nF
1nF
RT9212
C9
0.1uF
PHKD6N02LT
Q5
Q6
19
15
VCC
PGOOD
Q1
L1
1uH
RESET2
RESET1
C12 to C15
150uF (x 4
)
V
OUT1
1.8V
21
20
2
1
OCSET1/SD BOOT1
OCSET2/SD
UGATE1
Q2
3.3V
3
PHASE1
PVCC1
LGATE1
PGND1
16
17
DRV
FBL
22
23
V
C4
100uF
CC
5V
V
IN
24
6
2.5V/3.3V/5V
D2
COMP1
2SD1802
V
1N4148
OUT3
2.5V
11
12
10
14
C7
5.6nF
BOOT2
UGATE2
PHASE2
LGATE2
C6
100pF
C5
470uF
C11
0.1uF
PHKD6N02LT
R3
255
R5
6.34k
5
Q3
L2
FB1
C16 to C17
150uF (x 2)
1uH
V
OUT2
1.5V
13
18
PGND2
FB2
R6
1k
R4
120
GNDA
Q4
R10
105
9
C8
15nF
R7
1.25k
R8
100
R11
120
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2
DS9212-05 March 2007
Preliminary
RT9212
Functional Pin Description
UGATE1 (Pin 1)
BOOT2 (Pin 11)
Channel 1 upper gate driver output. Connect to gate of the
high-side powerN-MOSFET. This pin is monitored by the
adaptive shoot-through protection circuitry to determine
when the upper MOSFET has turned off.
Bootstrap supply pin for the upper gate driver. Connect the
bootstrap capacitor between BOOT2 pin and the PHASE2
pin. The bootstrap capacitor provides the charge to turn on
the upper MOSFET.
BOOT1 (Pin 2)
UGATE2 (Pin 12)
Bootstrap supply pin for the upper gate driver. Connect
the bootstrap capacitor between BOOT1 pin and the
PHASE1 pin. The bootstrap capacitor provides the charge
to turn on the upper MOSFET.
Channel 2 upper gate driver output. Connect to gate of the
high-side powerN-MOSFET. This pin is monitored by the
adaptive shoot-through protection circuitry to determine
when the upper MOSFET has turned off.
PHASE1 (Pin 3)
PGND2 (Pin 13)
Connect this pin to the source of the upper MOSFET and
the drain of the lower MOSFET. PHASE1 is used to
monitor the Voltage drop across the upper MOSFET of
the channel 1regulator for over-current protection.
Return pin for high currents flowing in low-side power
N-MOSFET. Ties the pin directly to the low-side MOSFET
source and ground plane with the lowest impedance.
LGATE2 (Pin 14)
NC (Pin 4, 7, 8)
Channel 2 lower gate drive output. Connect to gate of the
low-side power N-MOSFET. This pin is monitored by the
adaptive shoot-through protection circuitry to determine
when the lower MOSFET has turned off.
No connection. Don’ t connect any component to this pin.
FB1 (Pin 5)
Channel 1 feedback voltage. This pin is the inverting input
of the error amplifier. FB1 senses the channel 1 through
an external resistor divider network.
VCC (Pin 15)
Connect this pin to a well-decoupled 5V bias supply. It is
also the positive supply for the lower gate driver, LGATE2.
COMP1 (Pin 6)
DRV (Pin 16)
Channel 1 external compensation. This pin internally
connects to the output of the error amplifier and input of
the PWM comparator. Use a RC + C network at this pin
to compensate the feedback loop to provide optimum
transient response.
Connect this pin to the base of an external transistor. This
pin provides the drive for the linear regulator's pass
transistor.
FBL (Pin 17)
GNDA (Pin 9)
Linear regulator feedback voltage. This pin is the inverting
input of the error amplifier and protection monitor. Connect
this pin to the external resistor divider network of the linear
regulator.
Signal ground for the IC. All voltage levels are measured
with respect to this pin. Ties the pin directly to ground
plane with the lowest impedance.
PHASE2 (Pin 10)
FB2 (Pin 18)
Connect this pin to the source of the upper MOSFET and
the drain of the lower MOSFET. PHASE2 is used to
monitor the Voltage drop across the upper MOSFET of
the channel 2regulator for over-current protection.
Channel 2 feedback voltage. This pin is the inverting input
of the error amplifier. FB2 senses the channel 2 through an
external resistor divider network.
DS9212-05 March 2007
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3
Preliminary
RT9212
PGOOD (Pin 19)
PVCC1 (Pin 22)
PGOODis an open-drain output used to indicate that both
the channel 1 and channel 2 regulators are within normal
operating voltage ranges.
Connect this pin to a well-decoupled 5V supply. It is also
the positive supply for the lower gate driver, LGATE1.
LGATE1 (Pin 23)
OCSET2/SD (Pin 20), OCSET1/SD (Pin 21)
Channel 1 power gate drive output. Connect to gate of the
low-side powerN-Channel MOSFET. This pin is monitored
by the adaptive shoot-through protection circuitry to
determine when the lower MOSFET has turned off.
Connect a resistor (ROCSET) from this pin to the drain of
the upper MOSFET of the supply voltage sets the over-
current trip point. ROCSET, an internal 40μAcurrent source
, and the upper MOSFET on-resistance, (RDS(ON), set the
converter over-current trip point (IOCSET) according to the
following equation:
PGND1 (Pin 24)
Return pin for high currents flowing in low-side power
N-MOSFET. Ties the pin directly to the low-side MOSFET
source and ground plane with the lowest impedance.
40uA × ROCSET
IOCSET =
RDS(ON) of the upper MOSFET
An over-current trip cycles the soft-start function. Pulling
the pin to ground resets the device and all external
MOSFETs are turned off allowing the two output voltage
power rails to float.
Function Block Diagram
VCC
Thermal
Bias
SHDN
137.5%
0.8V
Ref.
+
Power
on
Reset
62.5%
OCSET1/SD
POR
OC
OV
40uA
OVP
&
UVP
-
0.8V
UV
FB1
Soft-
Start
1
Power
Good
BOOT1
PGOOD
COMP1
+
EA
PWM1
+
+
-
-
UGATE1
OC
Control
Logic
PHASE1
PVCC1
LGATE1
PGND1
OV
UV
Thermal
SHDN
300kHz
Oscillator
PGND2
PWM2
-
+
LGATE2
+
+
EA
FB2
-
Control
Logic
Zf
OC
VCC
FB2
PHASE2
OV
UV
180 deg
shift
Zc
Thermal
SHDN
Linear
UGATE2
BOOT2
Regulator
FBL
Soft-
Start
2
OV
UV
OCSET2/SD
+
-
DRV
OC
POR
40uA
GNDA
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4
DS9212-05 March 2007
Preliminary
Absolute Maximum Ratings (Note 1)
RT9212
z Supply Voltage, VCC ------------------------------------------------------------------------------------------------- 7V
z BOOT, VBOOT - VPHASE ----------------------------------------------------------------------------------------------- 7V
z Input, Output or I/O Voltage ---------------------------------------------------------------------------------------- GND-0.3V to 7V
z Package Thermal Resistance
TSSOP-24, θJA -------------------------------------------------------------------------------------------------------- 100°C/W
z Junction Temperature ------------------------------------------------------------------------------------------------ 150°C
z Lead Temperature (Soldering, 10 sec.)-------------------------------------------------------------------------- 260°C
z Storage Temperature Range --------------------------------------------------------------------------------------- − 65°C to 150°C
z ESD Susceptibility (Note 2)
HBM (Human Body Mode) ----------------------------------------------------------------------------------------- 2kV
MM (Machine Mode) ------------------------------------------------------------------------------------------------- 200V
Recommended Operating Conditions
(Note 3)
z Supply Voltage, VCC ------------------------------------------------------------------------------------------------- 5V 5 %
z Ambient Temperature Range--------------------------------------------------------------------------------------- 0°C to 70°C
z Junction Temperature Range--------------------------------------------------------------------------------------- 0°C to 125°C
Electrical Characteristics
(VCC = 5V, TA = 25°C, unless otherwise specified)
Parameter
Symbol
Test Conditions
Min Typ Max Units
V
CC
Supply Current
OCSET1/SD, OCSET2/SD = V
UGATE1 & 2, LGATE1 & 2 Open
CC;
Nominal Supply Current
--
--
5
3
--
--
mA
mA
I
I
CC
Shutdown Supply
(OCSET1/SD, OCSET2/SD) = 0V
CCSD
Power-On Reset
V
V
= 4.5V
= 4.5V
OCSET1/SD, OCSET2/SD
POR Threshold
3.7
--
4.1
0.5
4.5
--
V
V
VCCRTH
Rising
CC
Hysteresis
V
VCCHYS
OCSET1/SD, OCSET2/SD
Reference
Error Amp Reference Voltage
Tolerance
--
--
2
%
V
Δ
VEAR
Error Amp Reference
Oscillator
0.784 0.8 0.816
V
V
= 5V
VREF
CC
Free Running Frequency
Ramp Amplitude
275
--
300
1.9
325
--
kHz
f
= 5V
CC
OSC
ΔV
V
P-P
OSC
V1 Error Amplifier (External Compensation)
DC Gain
--
--
--
90
10
6
--
--
--
dB
Gain-Bandwidth Product
Slew Rate
GBW
SR
MHz
V/μs
COMP = 10pF
To be continued
DS9212-05 March 2007
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5
Preliminary
RT9212
Parameter
Symbol
Test Conditions
Min
--
Typ Max Units
V2 Error Amplifier (Internal Compensation)
DC Gain
35
--
--
dB
Linear Regulator
DRV Driver Source
IDS
--
100
mA
PWM Controller Gate Drivers
BOOT = 10V
Upper Gate Source (UGATE1 and 2)
--
7
--
R
UGATE
Ω
BOOT − V
= 1V
UGATE
Upper Gate Sink (UGATE1 and 2)
Lower Gate Source (LGATE1 and 2)
Lower Gate Sink (LGATE1 and 2)
Upper Gate Rising Time (UGATE1 and 2)
Upper Gate Falling Time (UGATE1 and 2)
Lower Gate Rising Time (LGATE1 and 2)
Lower Gate Falling Time (LGATE1 and 2)
Dead Time
--
--
--
--
--
--
--
--
5
4
--
--
R
R
R
V
V
V
= 1V
Ω
Ω
UGATE
UGATE
− V
= 1V
LGATE
CC
LGATE
2
--
= 1V
Ω
LGATE
LGATE
70
50
50
32
--
--
ns
ns
ns
ns
ns
T
T
T
T
C
C
C
C
= 3.3nF
= 3.3nF
= 3.3nF
= 3.3nF
R_UGATE
F_UGATE
R_LGATE
F_LGATE
Load
Load
Load
Load
--
--
--
TDT
100
Protection
FB1 & FB2 Over-Voltage Trip
FB1 & FB2 Under-Voltage Trip
OCSET1 & OCSET2 Current Source
OCP Blocking Time
FB1 & FB2 Rising
FB1 & FB2 Falling
125 137.5
--
ΔFBOVT
ΔFBUVT
%
%
--
34
--
62.5
40
75
46
I
V , = 4.5V
OCSET1/SD OCSET2/SD
μA
ns
OCSET
320
--
540
0.2
Logic-Low Voltage
OCSET/SD
VIL
VIH
Shutdown
Enable
--
V
Logic-High Voltage
2.0
--
--
4
--
--
Soft-Start Interval
ms
T
SS
Power Good
Upper Threshold
Lower Threshold
FB1 & FB2 Rising
FB1 & FB2 Rising
110
80
115
85
120
90
%
%
V
V
PG+
PG–
Note 1.Stresses listed as the above “Absolute Maximum Ratings” may cause permanent damage to the device. These are
for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for
extended periods may remain possibility to affect device reliability.
Note 2. Devices are ESD sensitive. Handling precaution recommended.
Note 3. The device is not guaranteed to function outside its operating conditions.
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6
DS9212-05 March 2007
Preliminary
Typical Operating Characteristics
RT9212
Power Good Rising
Power Good Falling
VCC
(5V/Div)
VCC
(5V/Div)
VOUT1
(2V/Div)
VOUT1
(2V/Div)
VOUT2
(2V/Div)
VOUT2
(2V/Div)
PGOOD
(5V/Div)
PGOOD
(5V/Div)
Time (5ms/Div)
Time (25ms/Div)
Power Off
Power On
I
= IOUT2 = 5A
I
= IOUT2 = 5A
OUT1
OUT1
VOUT1
(2V/Div)
VOUT1
(2/Div)
VOUT2
(2/Div)
VOUT2
(2V/Div)
UGATE1
(10/Div)
UGATE1
(10V/Div)
UGATE2
(5V/Div)
UGATE2
(5V/Div)
Time (500us/Div)
Time (5ms/Div)
UGATE Phase Shift
LGATE Phase Shift
LGATE1
(5V/Div)
UGATE1
(5V/Div)
LGATE2
(5V/Div)
UGATE2
(5V/Div)
Time (1us/Div)
Time (1us/Div)
DS9212-05 March 2007
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7
Preliminary
RT9212
Bootstrap
Bootstrap
UGATE1
(5V/Div)
UGATE2
(5V/Div)
LGATE1
(5V/Div)
LGATE2
(5V/Div)
Time (1us/Div)
Time (1us/Div)
VOUT2 Short
VOUT1 Short
VOUT2
(1V/Div)
VOUT1
(2V/Div)
LGATE2
(5V/Div)
UGATE1
(10V/Div)
UGATE2
(10V/Div)
LGATE1
(5V/Div)
Time (5ms/Div)
Time (5ms/Div)
VOUT1 Transient
VOUT2 Transient
VOUT1
(100mV/Div)
VOUT2
(10mV/Div)
IOUT2
(5A/Div)
IOUT1
(5A/Div)
VIN = 5V, VOUT = 3.3V, COUT = 3000μF
VIN = 5V, VOUT = 2.5V, COUT = 3000μF
Time (250us/Div)
Time (250us/Div)
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DS9212-05 March 2007
8
Preliminary
RT9212
VOUT3 Transient
POR (Start Up)
VIN = 5V, VOUT = 1.8V
VOUT3
(200mV/Div)
VCC
(5V/Div)
VOUT1
(2V/Div)
IOUT3
(2A/Div)
VOUT2
(2V/Div)
Time (2.5ms/Div)
Time (5ms/Div)
POR (Rising/Falling) vs. Temperature
Frequency vs. Temperature
4.25
4.2
315
310
305
300
295
290
285
Rising
4.15
4.1
Falling
4.05
4
3.95
3.9
-40
-10
20
50
80
110
140
-40
-20
0
20
40
60
80
100 120
Temperature
(°C)
Temperature
(°C)
Iocset & Temperature
Reference vs. Temperature
0.808
0.806
0.804
0.802
0.8
55
50
45
40
35
30
VOUT1
0.798
0.796
0.794
0.792
0.79
VOUT2
VOUT2
VOUT1
0.788
-40
-20
0
20
40
60
80
100 120
-40 -20
0
20
40
60
80 100 120 140
(°C)
Temperature
(°C)
Temperature
DS9212-05 March 2007
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9
Preliminary
RT9212
Applications Information
Inductor
The response time is the time required to slew the inductor
current from an initial current value to the transient current
level. The inductor limit input current slew rate during
the load transient. Minimizing the transient response time
can minimize the output capacitance required. The response
time is different for application of load and removal of load
to a transient. The following equations give the approximate
response time for application and removal of a transient
load :
The inductor is required to supply constant current to the
output load. The inductor is selected to meet the output
voltage ripple requirements and minimize the converter's
response time to the load transient.
A larger value of inductance reduces ripple current and
voltage. However, the larger value of inductance has a larger
physical size, lower output capacitor and slower transient
response time.
L× ΔIOUT
L × ΔIOUT
VIN − VOUT
A good rule for determining the inductance is to allow the
peak-to-peak ripple current in the inductor to be
approximately 30% of the maximum output current. The
inductance value can be calculated by the following
equation :
,
TFall =
TRise =
VOUT
Where
TRise is the response time to the application of load,
TFall is the response time to the removal of load,
(VIN − VOUT)× VOUT
L =
VIN ×FS × ΔIOUT
Δ
IOUT is the transient load current step.
Where
VIN is the input voltage,
Input Capacitor
The input capacitor is required to supply theAC current to
the Buck converter while maintaining theDC input voltage.
The capacitor should be chosen to provide acceptable ripple
on the input supply lines. Use a mix of input bypass
capacitors to control the voltage overshoot across the
MOSFETs. Use small ceramic capacitors for high frequency
decoupling and bulk capacitors to supply the current. Place
the small ceramic capacitors close to the MOSFETs and
between the drain of Q1/Q3 and the source of Q2/Q4.
VOUT is the output voltage,
FS is the switching frequency,
Δ
IOUT is the peak-to-peak inductor ripple current.
The inductance value determines the converter's ripple
current and the ripple voltage. The ripple current is
calculated by the following equations :
(VIN − VOUT)× VOUT
ΔI =
VIN ×Fs×L
The key specifications for input capacitor are the voltage
rating and the RMS current rating. For reliable operation,
select the bulk capacitor with voltage and current ratings
above the maximum input voltage and largest RMS current.
The capacitor voltage rating should be at least 1.25 times
greater than the maximum input voltage and voltage rating
of 1.5 times is a conservative guideline. The RMS current
rating for the input capacitor of a buck regulator should be
greater than approximately 0.5 the DC load current.
Increasing the value of inductance reduces the ripple current
and voltage. However, the large inductance values raise
the converter's response time to a load transient.
One of the parameters limiting the converter's response to
a load transient is the time required to change the inductor
current. Given a sufficiently fast control loop design, the
RT9212 will provide 0% to 100% duty cycle in response to
a load transient.
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DS9212-05 March 2007
Preliminary
RT9212
Output Capacitor
For the Buck converter the average inductor current is equal
to the output load current. The conduction loss is defined
as :
The output capacitor is required to maintain theDC output
voltage and supply the load transient current. The capacitor
must be selected and placed carefully to yield optimal
results and should be chosen to provide acceptable ripple
on the output voltage.
PCD (high side switch) = IO2 * RDS(ON) * D
PCD (low side switch) = IO2 * RDS(ON) * (1-D)
The switching loss is more difficult to calculate. The reason
is the effect of the parasitic components and switching
times during the switching procedures such as turn-on /
turn-off delays and rise and fall times. With a linear
approximation, the switching loss can be expressed as :
The key specification for output capacitor is its ESR. Low
ESR capacitors are preferred to keep the output voltage
ripple low. The bulk capacitor's ESR will determine the
output ripple voltage and the initial voltage drop after a
high slew-rate transient. For transient response, a
combination of low value, high frequency and bulk capacitors
placed close to the load will be required. High frequency
decoupling capacitors should be placed as close to the
power pins of the load as possible. In most cases, multiple
electrolytic capacitors of small case size perform better
than a single large case capacitor.
PSW = 0.5 * VDS(OFF) * IO * (TRise + TFall) * F
Where
VDS(OFF) is drain to source voltage at off time,
T
Rise
is rise time,
TFall is fall time,
F is switching frequency.
The capacitor value must be high enough to absorb the
inductor's ripple current. The output ripple is calculated as
The total power dissipation in the switching MOSFET can
be calculate as :
:
ΔVOUT = ΔIOUT ×ESR
PHigh Side Switch
=
Another concern is high ESR induced output voltage ripple
may trigger UV or OV protections will cause IC shutdown.
IO2 * RDS(ON) D + 0.5 * VDS(OFF)* IO* (TRise + TFall)* F
PLow Side Switch = IO2 * RDS(ON) * (1-D)
*
MOSFET
For input voltages of 3.3V and 5V, conduction losses often
The MOSFET should be selected to meet power transfer
requirements is based on maximum drain-source voltage
(VDS), gate-source drive voltage (VGS), maximum output
current, minimum on-resistance (RDS(ON)) and thermal
management.
dominate switching losses. Therefore, lowering the RDS(ON)
of the MOSFETs always improves efficiency.
Feedback Compensation
The RT9212 is a voltage mode controller; the control loop
is a single voltage feedback path including an error amplifier
and PWM comparator as Figure 1 shows. In order to achieve
fast transient response and accurate output regulation, a
adequate compensator design is necessary. The goal of
the compensation network is to provide adequate phase
margin (greater than 45 degrees) and the highest 0dB
crossing frequency. And to manipulate loop frequency
response that its gain crosses over 0dB at a slope of -
20dB/dec.
In high-current applications, the MOSFET power
dissipation, package selection and heatsink are the
dominant design factors. The losses can be divided into
conduction and switching losses.
Conduction losses are related to the on resistance of
MOSFET, and increase with the load current. Switching
losses occur on each ON/OFF transition. The conduction
losses are the largest component of power dissipation for
both the upper and the lower MOSFETs.
DS9212-05 March 2007
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11
Preliminary
RT9212
Vin
Compensation Frequency Equations
The compensation network consists of the error amplifier
and the impedance networks ZC and ZF as Figure 2 shows.
Lo
Vout
PWM
Co
Zf
C1
Zc
ESR
R1
VOUT
R2
C2
Zf
-
Zc
FB1
+
-
-
PWM
Comparator
+
EA
+
COMP1
Rf
VREF
RT9212
VREF
Compensator
VRAMP
Figure 2
FP1 = 0
FZ1 =
Figure 1
1
2π ×R2 × C2
Modulator Frequency Equations
1
The modulator transfer function is the small-signal transfer
function of VOUT/VE/A. This transfer function is dominated
by aDC gain and the output filter (LO and CO), with a double
pole frequency at FLC and a zero at FESR. The DC gain of
the modulator is the input voltage (VIN) divided by the peak-
FP1 =
2π ×R2(C1// C2)
Figure 3 shows theDC-DC converter's gain vs. frequency.
The compensation gain uses external impedance networks
ZC and ZF to provide a stable, high bandwidth loop.
to-peak oscillator voltage VRAMP
.
High crossover frequency is desirable for fast transient
response, but often jeopardize the system stability. In order
to cancel one of the LC filter poles, place the zero before
the LC filter resonant frequency. In the experience, place
the zero at 75% LC filter resonant frequency.Crossover
frequency should be higher than the ESR zero but less
than 1/5 of the switching frequency.
The first step is to calculate the complex conjugate poles
contributed by the LC output filter.
The output LC filter introduces a double pole,−40dB/decade
gain slope above its corner resonant frequency, and a total
phase lag of 180 degrees. The Resonant frequency of the
LC filter expressed as follows :
The second pole be place at half the switching frequency.
1
FP(LC) =
2π × LO ×CO
80
Loop Gain
60
The next step of compensation design is to calculate the
ESR zero. The ESR zero is contributed by the ESR
associated with the output capacitance. Note that this
requires that the output capacitor should have enough ESR
to satisfy stability requirements. The ESR zero of the
output capacitor expressed as follows :
40
Compensation
Gain
20
0
Modulator
Gain
-20
1
FZ(ESR) =
-40
2π × CO ×ESR
-60
10
100k
1M
100
1k
10k
Frequency (Hz)
Figure 3
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12
DS9212-05 March 2007
Preliminary
RT9212
Reference Voltage
2. There are two sets of critical components in a DC-DC
converter. The switching components are the most critical
because they switch large amounts of energy, and therefore
tend to generate large amounts of noise. The others are
the small signal components that connect to sensitive
nodes or supply critical bypass current and signal coupling.
Make all critical component ground connections with vias
toGNDplane.
Because one of the RT9212 regulators uses a low 35dB
gain error amplifier, shown in Figure 4. The voltage
regulation is dependent on VIN & VOUT setting.The FB
reference voltage of 0.8V is trimmed at VIN = 5V &
VOUT = 2.5V condition. In a fixed VIN = 5V application, the
FB reference voltage vs. VOUT voltage can be calculated
as Figure 5.
3. Use fewer, but larger output capacitors, keep the
capacitors clustered, and use multiple layer traces with
heavy copper to keep the parasitic resistance low. Place
the output capacitors as close to the load as possible.
R2
56K
R1
FB
+
-
-
EA
+
1K
+
PWM
-
4. The inductor, output capacitor and the MOSFET should
be as close to each other as possible. This helps to reduce
the EMI radiated.
REF
0.8V
RAMP
1.9V
Figure 4
5. Place the switching MOSFET as close to the input
capacitors as possible. The MOSFET gate traces to the
IC must be as short, straight, and wide as possible. Use
copper filled polygons on the top and bottom layers for the
PHASE nodes.
0.815
0.81
0.805
0.8
6. Place the CBOOT as close as possible to the BOOT and
PHASE pins.
0.795
0.79
7. The feedback part of the system should be kept away
from the inductor and other noise sources, and be placed
close to the IC. Connect to the GND pin with a single
trace, and connect this local GND trace to the output
capacitorGND.
0.785
0.78
0.775
1
1.5
2
2.5
3
3.5
4
4.5
5
VOUT (V)
8. Minimize the leakage current paths on the OCSET/SD
pin and locate the resistor as close to the OCSET/SD pin
as possible because the internal current source is only
40μA.
Figure 5
Layout Consideration
The layout is very important when designing high frequency
switching converters. Layout will affect noise pickup and
can cause a good design to perform with less than expected
results.
9. In multilayer PCB, use one layer as ground plane and
have a control circuit ground (analog ground), to which all
signals are referenced. The goal is to localize the high
current path to a separate loop that does not interfere with
the more sensitive analog control function. These two
grounds must be connected together on the PC board
layout at a single point.
1. Even though double-sided PCB is usually sufficient for
a good layout, four-layer PCB is the optimum approach to
reducing the noise. Use the two internal layers as the power
andGNDplanes, the top layer for power connections with
wide, copper filled areas, and the bottom layer for the noise
sensitive traces.
DS9212-05 March 2007
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13
Preliminary
RT9212
Outline Dimension
D
L
E
E1
e
A2
A
A1
b
Dimensions In Millimeters
Dimensions In Inches
Symbol
Min
Max
Min
Max
0.047
0.006
0.041
0.012
0.311
A
A1
A2
b
0.850
0.050
0.800
0.190
7.700
1.200
0.150
1.050
0.300
7.900
0.033
0.002
0.031
0.007
0.303
D
e
0.650
0.026
E
6.300
4.300
0.450
6.500
4.500
0.750
0.248
0.169
0.018
0.256
0.177
0.030
E1
L
24-Lead TSSOP Plastic Package
Richtek Technology Corporation
Headquarter
Richtek Technology Corporation
Taipei Office (Marketing)
5F, No. 20, Taiyuen Street, Chupei City
Hsinchu, Taiwan, R.O.C.
8F, No. 137, Lane 235, Paochiao Road, Hsintien City
Taipei County, Taiwan, R.O.C.
Tel: (8863)5526789 Fax: (8863)5526611
Tel: (8862)89191466 Fax: (8862)89191465
Email: marketing@richtek.com
www.richtek.com
14
DS9212-05 March 2007
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