RT9611AGQW_技术文档

®

RT9611A/B

Synchronous Rectified Buck MOSFET Drivers

General Description

Features

z Drive Two N-MOSFETs

The RT9611A/B is a high frequency, synchronous rectified,

single phase dual MOSFET driver designed to adapt from

normal MOSFET driving applications to high performance

CPU VR driving capabilities.

z Adaptive Shoot Through Protection

z Embedded Bootstrap Diode

z Support High Switching Frequency

z Fast Output Rise Time

The RT9611A/B can be utilized under both V_CC= 5V or

V_CC= 12V applications. The RT9611A/B also builds in an

internal power switch to replace external boot strap diode.

The RT9611A/B can support switching frequency efficiently

up to 500kHz. The RT9611A/B has the UGATE driving

circuit and the LGATE driving circuit for synchronous

rectified DC/DC converter applications. The driving rise/

fall time capability is designed within 30ns and the shoot

through protection mechanism is designed to prevent shoot

through of high side and low side power MOSFETs. The

RT9611A/B has PWM tri-state shut down and OD input

shut down functions which can force driver output into

high impedance.

z Tri-State Input for Bridge Shutdown

z Disable Control Input

z Small SOP-8, SOP-8 (Exposed Pad) and 8-Lead

WDFN Packages

z RoHS Compliant and Halogen Free

Applications

z Core Voltage Supplies forDesktop, Motherboard CPU

z High Frequency Low ProfileDC/DC Converters

z High Current Low VoltageDC/DC Converters

Ordering Information

RT9611A/B

The difference of the RT9611A and the RT9611B is the

propagation delay, t_UGATEpdh. The RT9611B has

comparatively large t_UGATEpdhthan RT9611B. Hence, the

RT9611A is usually recommended to be utilized in

performance oriented applications, such as high power

density CPU VR or GPU VR.

Package Type

S : SOP-8

SP : SOP-8 (Exposed Pad-Option1)

QW : WDFN-8EL 3x3 (W-Type)

Lead Plating System

G : Green (Halogen Free and Pb Free)

Z : ECO (Ecological Element with

Halogen Free and Pb free)

The RT9611A/B comes in a small footprint with 8-pin

packages. The choice of packages type includes SOP-8,

SOP-8 (Exposed Pad) and WDFN-8EL 3x3.

Long Dead Time

Short Dead Time

Note :

Richtek products are :

` RoHS compliant and compatible with the current require-

ments of IPC/JEDEC J-STD-020.

` Suitable for use in SnPb or Pb-free soldering processes.

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1

RT9611A/B

Pin Configurations

BOOT

(TOP VIEW)

8

7

6

5

8

7

6

5

UGATE

PHASE

GND

BOOT

PWM

OD

UGATE

PHASE

GND

2

3

4

PWM

2

3

4

GND

OD

9

VCC

LGATE

VCC

LGATE

SOP-8

SOP-8 (Exposed Pad)

1

2

3

4

8

7

6

5

UGATE

PHASE

GND

BOOT

PWM

GND

OD

VCC

9

LGATE

WDFN-8EL 3x3

Marking Information

RT9611xGS

RT9611xGSP

RT9611xGS : Product Number

RT9611xGSP : Product Number

x :Aor B

RT9611x

GSYMDNN

RT9611x

GSPYMDNN

x :Aor B

YMDNN : Date Code

RT9611xZSP

RT9611xZS

RT9611xZSP : Product Number

x :Aor B

RT9611xZS : Product Number

x :Aor B

RT9611x

ZSPYMDNN

RT9611x

ZSYMDNN

YMDNN : Date Code

RT9611AGQW

RT9611BGQW

02= : Product Code

YMDNN : Date Code

04= : Product Code

YMDNN : Date Code

02=YM

DNN

04=YM

DNN

RT9611AZQW

RT9611BZQW

02 : Product Code

YMDNN : Date Code

04 : Product Code

YMDNN : Date Code

02 YM

DNN

04 YM

DNN

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DS9611A/B-03 June 2012

RT9611A/B

Typical Application Circuit

ATX_12V

V

IN

C6

1000µF

x 3

C7

10µF

x 4

RT9611A/B

R2

1

R1

10

1

C2

1µF

BOOT

4

ATX_12V

VCC

R3

2.2

C1

8

7

1µF

L1

1µH

Q1

Q2

UGATE

PHASE

V

CORE

3

2

5V

PWM

OD

R5

2.2

R4

0

C4

C5

10µF

x 2

5

2200µF

PWM

LGATE

x 2

C3

GND

6

3.3nF

Timing Diagram

PWM

t

pdlLGATE

90%

LGATE

UGATE

t

pdlUGATE

1.5V

90%

1.5V

t

pdhLGATE

pdhUGATE

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RT9611A/B

Functional Pin Description

Pin No.

Pin Name

Pin Function

SOP-8 (Exposed Pad) /

SOP-8

WDFN-8EL 3x3

1

2

1

2

BOOT

PWM

Floating Bootstrap Supply Pin for Upper Gate Driver.

Input PWM Signal for Controlling the Driver.

Output Disable. When low, both UGATE and LGATE are

driven low and the normal operation is disabled.

3

4

5

3

4

5

OD

VCC

12V Supply Voltage.

Lower Gate Driver Output. Connected to gate of low side

power N-MOSFET.

Ground. The exposed pad must be soldered to a large

PCB and connected to GND for maximum power

dissipation.

LGATE

GND

6,

6

9 (Exposed Pad)

Connect this pin to the source of the high side MOSFET

and the drain of the low side MOSFET.

7

8

7

8

PHASE

UGATE

Upper Gate Driver Output. Connected this pin to gate of

high side power N-MOSFET.

Function Block Diagram

VCC

Internal

3.6V

Bootstrap

Control

POR

15k

BOOT

Input

Disable

PWM

Shoot-Through

Protection

UGATE

15k

12k

Turn Off

Detection

PHASE

12k

OD

VCC

Shoot Through

Protection

LGATE

12k

GND

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DS9611A/B-03 June 2012

RT9611A/B

Absolute Maximum Ratings (Note 1)

z Supply Voltage, VCC ----------------------------------------------------------------------------------−0.3V to 15V

z BOOT to PHASE ---------------------------------------------------------------------------------------−0.3V to 15V

z PHASE to GND

DC----------------------------------------------------------------------------------------------------------−5V to 15V

< 200ns ---------------------------------------------------------------------------------------------------−10V to 30V

z LGATE

DC----------------------------------------------------------------------------------------------------------(GND − 0.3V) to (V_CC+ 0.3V)

< 200ns ---------------------------------------------------------------------------------------------------−2V to (V_CC+ 0.3V)

z UGATE ----------------------------------------------------------------------------------------------------(V_PHASE− 0.3V) to (V_BOOT+ 0.3V)

< 200ns ---------------------------------------------------------------------------------------------------(V_PHASE− 2V) to (V_BOOT+ 0.3V)

z PWM Input Voltage ------------------------------------------------------------------------------------(GND − 0.3V) to 7V

z OD----------------------------------------------------------------------------------------------------------(GND − 0.3V) to 7V

z Power Dissipation, P_D@ T_A= 25°C

SOP-8 -----------------------------------------------------------------------------------------------------0.833W

SOP-8 (Exposed Pad) --------------------------------------------------------------------------------1.333W

WDFN-8EL 3x3 -----------------------------------------------------------------------------------------1.429W

z Package Thermal Resistance (Note 2)

SOP-8, θ_JA-----------------------------------------------------------------------------------------------120°C/W

SOP-8 (Exposed Pad), θ_JA---------------------------------------------------------------------------75°C/W

SOP-8 (Exposed Pad), θ_JC--------------------------------------------------------------------------15°C/W

WDFN-8EL 3x3, θ_JA------------------------------------------------------------------------------------70°C/W

WDFN-8EL 3x3, θ_JC-----------------------------------------------------------------------------------8.2°C/W

z Lead Temperature (Soldering, 10 sec.)------------------------------------------------------------260°C

z Junction Temperature ----------------------------------------------------------------------------------150°C

z Storage Temperature Range -------------------------------------------------------------------------−65°C to 150°C

z ESD Susceptibility (Note 3)

HBM (Human Body Model)---------------------------------------------------------------------------2kV

Recommended Operating Conditions (Note 4)

z Supply Voltage, VCC ----------------------------------------------------------------------------------12V ±10%

z Junction Temperature Range-------------------------------------------------------------------------−40°C to 125°C

z Ambient Temperature Range-------------------------------------------------------------------------−40°C to 85°C

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RT9611A/B

Electrical Characteristics

(V_CC= 12V, T_A= 25°C, unless otherwise specified)

Parameter

Symbol

V_CC

Test Conditions

V_BOOT= 12V, PWM = 0V

V_CCRising

Min

4.5

--

Typ

--

Max

13.5

--

Unit

V

Power Supply Voltage

Power Supply Current

Power On Reset

I_VCC

1.2

mA

POR Threshold

V_POR

3

4

4.4

--

V

Hysteresis

--

V_{CC_hys}

0.5

PWM Input

Maximum Input Current

PWM Floating Voltage

PWM Rising Threshold

PWM Falling Threshold

Output Disable Input

I_PWM

PWM = 0V or 5V

V_CC= 12V

--

1.6

2.8

--

300

1.8

--

2

μA

V

V_{PWM_fl}

V_{PWM_rth}

V_{PWM_fth}

--

V

--

0.8

V

V_{OD_rth}

V_{OD_hys}

OD Rising Threshold

OD Hysteresis

1

1.3

0.3

1.6

--

V

--

Timing

UGATE Rise Time

UGATE Fall Time

LGATE Rise Time

LGATE Fall Time

t_UGATEr

t_UGATEf

t_LGATEr

t_LGATEf

V_CC= 12V, 3nF load

--

25

12

24

10

22

60

22

20

8

--

ns

RT9611A

RT9611B

t_UGATEpdh

V_BOOT− V_PHASE= 12V

See Timing Diagram

Propagation Delay

t_UGATEpdl

ns

RT9611A/B t_LGATEpdh

t_LGATEpdl

See Timing Diagram

Output

V_BOOT− V_PHASE= 12V

V_UGATE− V_PHASE= 12V

UGATE Drive Source

I_UGATEsr

--

2

--

A

UGATE Drive Sink

LGATE Drive Source

LGATE Drive Sink

R_UGATEsk

I_LGATEsr

V_BOOT− V_PHASE= 12V

V_CC= 12V, V_LGATE= 2V

V_CC= 12V

--

1.4

2.2

1.1

--

Ω

A

R_LGATEsk

Ω

Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are

stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in

the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may

affect device reliability.

Note 2. θ_JAis measured at T_A= 25°C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. θ_JCis

measured at the exposed pad of the package.

Note 3. Devices are ESD sensitive. Handling precaution is recommended.

Note 4. The device is not guaranteed to function outside its operating conditions.

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DS9611A/B-03 June 2012

RT9611A/B

Typical Operating Characteristics

Drive Enable

Drive Disable

UGATE

(20V/Div)

UGATE

(20V/Div)

PHASE

(10V/Div)

PHASE

(10V/Div)

LGATE

(10V/Div)

LGATE

(10V/Div)

OD

(5V/Div)

OD

(5V/Div)

V_IN= 12V, No Load

Time (1μs/Div)

PWM Rising Edge

PWM Falling Edge

UGATE

(20V/Div)

UGATE

(20V/Div)

PHASE

(10V/Div)

LGATE

(10V/Div)

LGATE

(10V/Div)

PWM

(5V/Div)

PWM

(5V/Div)

V_IN= 12V, No Load

Time (20ns/Div)

Dead Time

UGATE

PHASE

LGATE

(5V/Div)

V_IN= 12V, PWM Rising, No Load

Time (20ns/Div)

V_IN= 12V, PWM Falling, No Load

Time (20ns/Div)

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RT9611A/B

Dead Time

UGATE

PHASE

LGATE

UGATE

PHASE

LGATE

(5V/Div)

V_IN= 12V, PWM Rising, Full Load

Time (20ns/Div)

V_IN= 12V, PWM Falling, Full Load

Time (20ns/Div)

Short Pulse

PHASE

UGATE

LGATE

(5V/Div)

V_IN= 12V, Start Up

Time (20ns/Div)

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DS9611A/B-03 June 2012

RT9611A/B

Application Information

propagation delay, t_UGATEpdh. The RT9611B has

comparatively large t_UGATEpdhto further prevent from shoot

through when high side power MOSFETs are going to be

turned on. The long propagation delay of the RT9611B

sacrifices efficiency for compromise of system safety.

Hence, the RT9611A is usually recommended to be

utilized in performance oriented applications, such as high

power density CPU VR or GPU VR.

The RT9611A/B is a High frequency, synchronous rectified,

single phase dual MOSFET driver containing Richtek's

advanced MOSFET driver technologies. The RT9611A/B

is designed to be able to adapt from normal MOSFET

driving applications to high performance CPU VR driving

capabilities. The RT9611A/B can be utilized under both

V_CC= 5V or V_CC= 12V applications which may happen in

different fields of electronics application circuits. In the

efficiency point of view, higher VCC equals higher driving

voltage of UG/LG which may result in higher switching

loss and lower conduction loss of power MOSFETs. The

choice of V_CC= 12V or V_CC= 5V can be a tradeoff to

optimize system efficiency.

Non-overlap Control

To prevent the overlap of the gate drives during the UGATE

pull low and the LGATE pull high, the non-overlap circuit

monitors the voltages at the PHASE node and high side

gate drive (UGATE-PHASE). When the PWM input signal

goes low, UGATE begins to pull low (after propagation

delay). Before LGATE can pull high, the non-overlap

protection circuit ensures that the monitored voltages have

gone below 1.1V. Once the monitored voltages fall below

1.1V, LGATE begins to turn high. For short pulse condition,

if the PHASE pin had not gone high after LGATE pulls

low, the LGATE has to wait for 200ns before pull high. By

waiting for the voltages of the PHASE pin and high side

gate drive to fall below 1.1V, the non-overlap protection

circuit ensures that UGATE is low before LGATE pulls

high.

The RT9611A/B are designed to drive both high side and

low sideN-MOSFET through external input PWM control

signal. It has power on protection function which held

UGATE and LGATE low before the VCC voltage rises to

higher than rising threshold voltage.After the initialization,

the PWM signal takes the control. The rising PWM signal

first forces the LGATE signal turns low then UGATE signal

is allowed to go high just after a non-overlapping time to

avoid shoot through current. The falling of PWM signal

first forces UGATE to go low. When UGATE and PHASE

signal reach a predetermined low level, LGATE signal is

allowed to turn high.

Also to prevent the overlap of the gate drives during LGATE

pull low and UGATE pull high, the non-overlap circuit

monitors the LGATE voltage. When LGATE go below 1.1V,

UGATE is allowed to go high.

The PWM signal is acted as “High” if the signal is above

the rising threshold and acted as “Low” if the signal is

below the falling threshold. Any signal level enters and

remains within the shutdown window is considered as “tri-

state” the output drivers are disabled and both MOSFET

gates are pulled and held low. If left the PWM signal floating,

the pin will be kept around 1.8V by the internal divider and

provide the PWM controller with a recognizable level. OD

pin will also turn off both high/low side MOSFETs when

tied to GND.

Driving Power MOSFETs

The DC input impedance of the power MOSFET is

extremely high. When V_gs1or V_gs2is at 12V or 5V, the

gate draws the current only for few nano-amperes. Thus

once the gate has been driven up to “ON” level, the

current could be negligible.

The RT9611A/B builds in an internal bootstrap power switch

to replace external bootstrap diode, and this can facilitate

PCB design and reduce total BOM cost of the system.

Hence, no external bootstrap diode is required in real

applications.

However, the capacitance at the gate to source terminal

should be considered. It requires relatively large currents

to drive the gate up and down 12V (or 5V) rapidly. It is

also required to switch drain current on and off with the

required speed. The required gate drive currents are

calculated as follows.

The difference of the RT9611A and the RT9611B is the

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RT9611A/B

D1

turned on. From Figure 1, the body diode “D₂” had been

L

d1

s1

turned on before high side MOSFETs turned on.

V

OUT

IN

dV

12

I

= C

gd1

(3)

Cgs1

gd1

Cgd1

dt

t

r1

Cgd2

Cgs2

d2

Igs1

Before the low side MOSFET is turned on, the C_gd2have

been charged to V_IN. Thus, as C_gd2reverses its polarity

and g₂is charged up to 12V, the required current is :

Igd1

Ig1

_Ig2Igd2

Igs2

g1

g2

D2

dV

dt

+

Vi 12

s2

I

= C

gd2

(4)

gd2

t

r2

GND

It is helpful to calculate these currents in a typical case.

Assume a synchronous rectified buck converter, input

voltage V_IN= 12V, V_g1= V_g2= 12V. The high side

MOSFET is PHB83N03LT whose C_iss= 1660pF,

C_rss= 380pF, and t_r= 14ns. The low side MOSFET is

PHB95N03LT whose C_iss= 2200pF, C_rss= 500pF and t_r=

30ns, from the equation (1) and (2) we can obtain :

V

g1

V

+12V

PHASE

t

V

g2

12V

-12

1660 x 10 x 12

(5)

(6)

I

=

= 1.428 (A)

= 0.88 (A)

gs1

-9

14 x 10

-12

2200 x 10 x 12

I

gs2

Figure1. Equivalent Circuit andAssociated Waveforms

-9

30 x 10

from equation. (3) and (4)

In Figure 1, the current I_g1and I_g2are required to move the

gate up to 12V. The operation consists of charging C_gd1

,

380 x 10^-12x 12

C_gd2, C_gs1and C_gs2. C_gs1and C_gs2are the capacitors from

gate to source of the high side and the low side power

MOSFETs, respectively. In general data sheets, the C_gs1

and C_gs2are referred as “C_iss” which are the input

capacitors. C_gd1and C_gd2are the capacitors from gate to

drain of the high side and the low side power MOSFETs,

respectively and referred to the data sheets as “C_rss” the

reverse transfer capacitance. For example, t_r1and t_r2are

the rising time of the high side and the low side power

I_gd1

=

= 0.326 (A)

(7)

(8)

14 x 10^-9

500 x 10^-12x 12+12

(

)

I_gd2

= 0.4 (A)

30 x 10^-9

the total current required from the gate driving source can

be calculated as following equations :

I_g1= I_gs1+ I_gd1= 1.428 + 0.326 = 1.754 (A)

(9)

(

)

I_g2= I_gs2+ I_gd2= 0.88 + 0.4 = 1.28 (A)

(10)

(

)

MOSFETs respectively, the required current I_gs1and I_gs2

,

By a similar calculation, we can also get the sink current

required from the turned off MOSFET.

are shown as below :

dV

C

x 12

gs1

g1

(1)

(2)

I

= C

=

gs1

dt

dV

t

r1

Select the Bootstrap Capacitor

C

x 12

g2

gs1

Figure 2 shows part of the bootstrap circuit of the RT9611A/

B. The V_CB(the voltage difference between BOOT and

PHASE on RT9611A/B) provides a voltage to the gate of

the high side power MOSFET. This supply needs to be

ensured that the MOSFET can be driven. For this, the

I

= C

=

gs2

gs1

dt

t

r2

Before driving the gate of the high side MOSFET up to

12V (or 5V), the low side MOSFET has to be off; and the

high side MOSFET is turned off before the low side is

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DS9611A/B-03 June 2012

RT9611A/B

capacitance C_Bhas to be selected properly. It is

determined by following constraints.

Figure 4 shows the power dissipation of the RT9611A/B

as a function of frequency and load capacitance. The value

of C_Uand C_Lare the same and the frequency is varied

from 100kHz to 1MHz.

V

IN

BOOT

+

C

B

Power Dissipation vs. Frequency

UGATE

PHASE

V

CB

1000

-

900

V

CC

C_U= C_L= 3nF

800

LGATE

GND

700

600

C_U= C_L= 2nF

500

400

300

Figure 2. Part of Bootstrap Circuit of RT9611A/B

C_U= C_L= 1nF

200

100

0

In practice, a low value capacitor C_Bwill lead to the over

charging that could damage the IC. Therefore, to minimize

the risk of overcharging and to reduce the ripple on V_CB,

the bootstrap capacitor should not be smaller than 0.1μF,

and the larger the better. In general design, using 1μF can

provide better performance.At least one low ESR capacitor

should be used to provide good local de-coupling. It is

recommended to adopt a ceramic or tantalum capacitor.

0

200

400

600

800

1000

Frequency (kHz)

Figure 4. Power Dissipation vs. Frequency

The operating junction temperature can be calculated from

the power dissipation curves (Figure 4). Assume

V_CC= 12V, operating frequency is 200kHz and

C_U= C_L= 1nF which emulate the input capacitances of

the high side and low side power MOSFETs. From Figure

4, the power dissipation is 100mΩ. Thus, for example,

with the SOP-8 package thermal resistance θ_JAis 120°C/

W. The operating junction temperature is calculated as :

Power Dissipation

To prevent driving the IC beyond the maximum

recommended operating junction temperature of 125°C,

it is necessary to calculate the power dissipation

appropriately. This dissipation is a function of switching

frequency and total gate charge of the selected MOSFET.

T_J= (120°C/W x 100mW) + 25°C = 37°C

where the ambient temperature is 25°C.

(11)

Figure 3 shows the power dissipation test circuit. C_Land

C_Uare the UGATE and LGATE load capacitors,

respectively. The bootstrap capacitor value is 1μF.

Thermal Considerations

C

BOOT

1µF

10

For recommended operating condition specifications of

the RT9611A/B, the maximum junction temperature is

125°C and T_Ais the ambient temperature. The junction to

ambient thermal resistance, θ_JA, is layout dependent. For

SOP-8 packages, the thermal resistance, θ_JA, is 120°C/

Won a standard JEDEC 51-7 four-layer thermal test board.

For SOP-8 (Exposed Pad) packages, the thermal

resistance, θ_JA, is 75°C/W on a standard JEDEC 51-7

four-layer thermal test board. For WDFN-8EL 3x3

packages, the thermal resistance, θ_JA, is 70°C/W on a

standard JEDEC 51-7 four-layer thermal test board. The

12V

BOOT

UGATE

2N7002

VCC

1µF

C

3nF

U

RT9611A/B

PHASE

OD

2N7002

5V

PWM

20

LGATE

C

3nF

L

GND

Figure 3. Test Circuit

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RT9611A/B

maximum power dissipation at T_A= 25°C can be calculated

Layout Consideration

by the following formulas :

Figure 6 shows the schematic circuit of a synchronous

buck converter to implement the RT9611A/B. The

converter operates from 5V to 12V of input Voltage.

P_D(MAX)= (125°C − 25°C) / (120°C/W) = 0.833W for

SOP-8 package

L1

12V

P_D(MAX)= (125°C − 25°C) / (75°C/W) = 1.333W for

SOP-8 (Exposed Pad) package

V

12V

IN

C2

1

C1

R1

C4

BOOT

4

2

VCC

P_D(MAX)= (125°C − 25°C) / (70°C/W) = 1.429W for

WDFN-8EL 3x3 package

CB

RT9611A/B

8

7

Q1

UGATE

PWM

5V

L2

The maximum power dissipation depends on the operating

ambient temperature for fixed T_J(MAX)and thermal

resistance, θ_JA. The derating curves in Figure 5 allow the

designer to see the effect of rising ambient temperature

on the maximum power dissipation.

V

CORE

PHASE

LGATE

3

6

PHB83N03LT

PHB95N03LT

OD

C3

GND

5

Q2

Figure 6. Synchronous Buck Converter Circuit

1.5

1.4

Four-Layer PCB

1.3

1.2

When layout the PCB, it should be very careful. The power

circuit section is the most critical one. If not configured

properly, it will generate a large amount of EMI. The

junction of Q1, Q2, L2 should be very close.

SOP-8 (Exposed Pad)

1.1

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0.0

SOP-8

WDFN-8EL 3x3

Next, the trace from UGATE, and LGATE should also be

short to decrease the noise of the driver output signals.

PHASE signals from the junction of the power MOSFET,

carrying the large gate drive current pulses, should be as

heavy as the gate drive trace. The bypass capacitor C4

should be connected to GND directly. Furthermore, the

bootstrap capacitors (C_B) should always be placed as close

to the pins of the IC as possible.

0

25

50

75

100

125

Ambient Temperature (°C)

Figure 5.Derating Curve of Maximum PowerDissipation

©

is a registered trademark of Richtek Technology Corporation.

www.richtek.com

12

DS9611A/B-03 June 2012

RT9611A/B

Outline Dimension

H

A

M

J

B

F

C

I

D

Dimensions In Millimeters

Dimensions In Inches

Symbol

Min

Max

Min

Max

A

B

C

D

F

H

I

4.801

3.810

1.346

0.330

1.194

0.170

0.050

5.791

0.400

5.004

3.988

1.753

0.508

1.346

0.254

6.200

1.270

0.189

0.150

0.053

0.013

0.047

0.007

0.002

0.228

0.016

0.197

0.157

0.069

0.020

0.053

0.010

0.244

0.050

J

M

8-Lead SOP Plastic Package

©

is a registered trademark of Richtek Technology Corporation.

DS9611A/B-03 June 2012

www.richtek.com

13

RT9611A/B

H

A

Y

M

EXPOSED THERMAL PAD

(Bottom of Package)

J

B

X

F

C

I

D

Dimensions In Millimeters Dimensions In Inches

Symbol

Min

Max

Min

Max

A

B

C

D

F

H

I

4.801

3.810

1.346

0.330

1.194

0.170

0.000

5.791

0.406

2.000

2.100

3.000

5.004

4.000

1.753

0.510

1.346

0.254

0.152

6.200

1.270

2.300

2.500

3.500

0.189

0.150

0.053

0.013

0.047

0.007

0.000

0.228

0.016

0.079

0.083

0.118

0.197

0.157

0.069

0.020

0.053

0.010

0.006

0.244

0.050

0.091

0.098

0.138

J

M

X

Y

X

Y

Option 1

Option 2

8-Lead SOP (Exposed Pad) Plastic Package

©

is a registered trademark of Richtek Technology Corporation.

www.richtek.com

14

DS9611A/B-03 June 2012

RT9611A/B

D2

D

L

E

E2

SEE DETAIL A

1

e

b

2

1

2

1

A

A3

DETAILA

Pin #1 ID and Tie Bar Mark Options

A1

Note : The configuration of the Pin #1 identifier is optional,

but must be located within the zone indicated.

Dimensions In Millimeters

Dimensions In Inches

Symbol

Min

Max

Min

Max

0.031

0.002

0.010

0.012

0.120

0.106

0.120

0.069

A

A1

A3

b

0.700

0.000

0.175

0.180

2.950

2.200

2.950

1.450

0.800

0.050

0.250

0.300

3.050

2.700

3.050

1.750

0.028

0.000

0.007

0.116

0.087

0.116

0.057

D

D2

E

E2

e

0.500

0.020

L

0.350

0.450

0.014

0.018

W-Type 8EL DFN 3x3 Package (0.5mm Lead Pitch)

Richtek Technology Corporation

5F, No. 20, Taiyuen Street, Chupei City

Hsinchu, Taiwan, R.O.C.

Tel: (8863)5526789

Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should

obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot

assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be

accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third

parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.

DS9611A/B-03 June 2012

www.richtek.com

15


型号：	RT9611AGQW
厂家：	RICHTEK TECHNOLOGY CORPORATION
描述：	Synchronous Rectified Buck MOSFET Drivers
文件：	总15页 (文件大小：228K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

RT9611AGQW [RICHTEK]

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