RTQ2536-QA [RICHTEK]
暂无描述;
| 型号： | RTQ2536-QA |
| 厂家： | 
RICHTEK TECHNOLOGY CORPORATION |
| 描述： | 暂无描述 双倍数据速率 |
| 文件： | 总11页 (文件大小：206K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
RTQ2536-QA
DDR Termination Regulator
General Description
Features
AEC-Q100 Grade 1 Qualified
VIN Input Voltage Range : 1V to 3.5V
VCNTL Input Voltage Range : 2.9V to 5.5V
Support Ceramic Capacitors
10mA Source/Sink Reference Output
Meets DDRI, DDRII JEDEC Spec
Supports DDRIII, DDRIII-L, DDRIV and DDRIV-L
Applications
The RTQ2536-QA is a sink/source tracking termination
regulator. It is specifically designed for low-cost and low-
external component count systems. The RTQ2536-QA
possesses a high speed operating amplifier that provides
fast load transient response and only requires a minimum
10μF (effective value) ceramic output capacitor. The
RTQ2536-QA supports remote sensing functions and all
features required to power the DDRI / DDRII / DDRIII /
DDRIII-L / DDRIV and DDRIV-L VTT bus termination
according to the JEDEC specification.
Soft-Start Function
UVLO and OCP Protection
Thermal Shutdown
The RTQ2536-QA is available in the thermal efficient
package, WDFN-10SL 3x3.
Applications
Automotive and Industrial Supplies
Ordering Information
RTQ2536
Notebook/Desktop/Server
-QA
Telecom/Datacom, GSM Base Station, LCD-TV/PDP-
TV, Copier/Printer, Set-Top Box
Grade
QA : AEC-Q100 Qualified and
Screened by High Temperature
Package Type
QW : WDFN-10SL 3x3 (W-Type)
Marking Information
KG= : Product Code
Lead Plating System
G : Green (Halogen Free and Pb Free)
YMDNN : Date Code
KG=YM
DNN
Note :
Richtek products are :
RoHS compliant and compatible with the current require-
ments of IPC/JEDEC J-STD-020.
Suitable for use in SnPb or Pb-free soldering processes.
Simplified Application Circuit
RTQ2536-QA
VCNTL
V
VIN
VCNTL
S5
IN
C4
C5
C3
VDDQSNS
S5
REFOUT
REFOUT
VOUT
V
OUT
C3
SENSE
PGND
S3
S3
GND
Copyright 2018 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
DSQ2536-QA-01 September 2018
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1
RTQ2536-QA
Pin Configuration
(TOP VIEW)
1
2
3
10
9
VDDQSNS
VIN
VCNTL
S5
GND
S3
8
7
6
VOUT
PGND
SENSE
4
5
11
REFOUT
WDFN-10SL 3x3
Functional Pin Description
Pin No.
Pin Name
Pin Function
1
2
3
4
VDDQSNS Reference input.
VIN
Power input of the regulator.
Power output of the regulator.
Power ground of the regulator.
VOUT
PGND
Voltage sense input for the regulator. Connect to positive terminal of the output
capacitor or the load.
5
SENSE
6
7
9
REFOUT
S3
Reference output. Connect to GND through a 0.1F ceramic capacitor.
S3 signal input.
S5 signal input.
S5
Control voltage input. Connect this pin to the 3.3V or 5V power supply. A
ceramic decoupling capacitor with a value 4.7F is required.
10
8
VCNTL
GND
Analog ground. Connect to negative terminal of the output capacitor.
Exposed pad. The exposed pad is internally unconnected and must be
soldered to a large PGND plane. Connect this PGND plane to other layers with
thermal vias to help dissipate heat from the device.
11 (Exposed Pad) PAD
Copyright 2018 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
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2
DSQ2536-QA-01 September 2018
RTQ2536-QA
Functional Block Diagram
REFOUT
VIN
S3
S5
OTP
+
OCP
-
VCNTL
UVLO
EN_VTT
VOUT
PGND
VDDQSNS
+
-
+
-
+
OCP
-
SENSE
GND
Operation
The RTQ2536-QAis a linear sink/sourceDDR termination
regulator with current capability up to 2A. The RTQ2536-
QAbuilds in a high-sideN-MOSFET which provides current
sourcing and a low-sideN-MOSFET which provides current
sinking. All the control circuits are supplied by the power
VCNTL. In normal operation, the error amplifier OP adjusts
the gate driving voltage of the power MOSFET to achieve
SENSE voltage well tracking the VDDQSNS/2 voltage.
Thermal Protection
Both the high-side and low-side power MOSFETs will be
turned off when the junction temperature is higher than
typically 160°C, and be released to normal operation when
junction temperature falls below 135°C typically.
Power State Control
The input pins S3 and S5 of the RTQ2536-QA, provide
simple control of the power state. Table 1 describes S3/
S5 terminal logic state and corresponding state of
REFOUT/VOUT outputs. VOUT is turn-off and discharged
to GND in state S3. When both S5 and S3 pins are LOW,
the power state is set to S4/S5. In S4/S5 state, all the
outputs are turn-off and discharged toGND.
Both the source and sink currents are detected by the
internal sensing resistor, and the OCP function will work
to limit the current to a designed value when overload
happens. Furthermore, the current will be folded back to
be one half if VOUT is out of the power good window.
Buffer
This function provides REFOUT output equal to
VDDQSNS/2 with 10mA source/sink current capability.
Control Logic
This block includes VCNTL UVLO, VDDQSNS UVLO and
Enable/Disable functions, and provides logic control to
the whole chip.
Table 1. S3 and S5 Control Table
STATE
S0
S3
HI
S5
HI
REFOUT
ON
VOUT
ON
S3
LO
LO
HI
ON
OFF (Discharge)
S4/S5
LO
OFF (Discharge) OFF (Discharge)
Copyright 2018 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
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RTQ2536-QA
Absolute Maximum Ratings (Note 1)
Supply Voltage, VIN, VCNTL ------------------------------------------------------------------------------------------- −0.3V to 6V
Input Voltage, S3, VDDQSNS, SENSE, S5 ------------------------------------------------------------------------ −0.3V to 6V
Output Voltage, VOUT, REFOUT -------------------------------------------------------------------------------------- −0.3V to 6V
Power Dissipation, PD @ TA = 25°C
WDFN-10SL 3x3 ----------------------------------------------------------------------------------------------------------- 4.09W
Package Thermal Resistance (Note 2)
WDFN-10SL 3x3, θJA ----------------------------------------------------------------------------------------------------- 30.5°C/W
WDFN-10SL 3x3, θJC ----------------------------------------------------------------------------------------------------- 7.5°C/W
Lead Temperature (Soldering, 10 sec.)------------------------------------------------------------------------------- 260°C
Junction Temperature ----------------------------------------------------------------------------------------------------- 150°C
Thermal Shutdown Temperature --------------------------------------------------------------------------------------- 160°C
Thermal Shutdown Hysteresis ----------------------------------------------------------------------------------------- 15°C
Storage Temperature Range -------------------------------------------------------------------------------------------- −65°C to 150°C
ESD Susceptibility (Note 3)
HBM (Human Body Model)---------------------------------------------------------------------------------------------- 2kV
Recommended Operating Conditions (Note 4)
Control Input Voltage, VCNTL ------------------------------------------------------------------------------------------ 2.9V to 5.5V
Supply Input Voltage, VIN ----------------------------------------------------------------------------------------------- 1V to 3.5V
Junction Temperature Range-------------------------------------------------------------------------------------------- −40°C to 125°C
Ambient Temperature Range-------------------------------------------------------------------------------------------- −40°C to 125°C
Electrical Characteristics
(VIN = VVDDQSNS = 1.5V, VCNTL = 3.3V, VSENSE = 0.75V, COUT = 10μF x 1, TJ = −40°C to 125°C, unless otherwise specified)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
Supply Current
VCNTL Supply Current IVCNTL
VS3 = VCNTL, VS5 = VCNTL, no load
--
--
--
--
--
0.5
65
0.75
80
mA
A
A
A
A
V
S3 = 0V, VS5 = 0V, no load
VCNTL Shutdown
Current
ISHDN_VCNTL
VS3 = 0V, VS5 = VCNTL, no load
VS3 = VCNTL, VS5 = VCNTL, no load
VS3 = 0V, VS5 = 0V, no load
200
1
350
35
VIN Supply Current
VIN Shutdown Current
Output
IVIN
ISHDN_VIN
0.1
10
V
IN = 1.5V, VVDDQSNS = 1.5V,
--
--
--
--
0.75
0.675
0.6
--
--
--
--
I
OUT = 0A
VIN = 1.35V, VVDDQSNS = 1.35V,
IOUT = 0A
VOUT Output Voltage
VOUT
V
VIN = 1.2V, VVDDQSNS = 1.2V,
I
OUT = 0A
VIN = 1.05V, VVDDQSNS = 1.05V,
OUT = 0A (Note 5)
0.525
I
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is a registered trademark of Richtek Technology Corporation.
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DSQ2536-QA-01 September 2018
RTQ2536-QA
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
I
OUT = ±2A, VIN = 1.5V,
30
--
30
VREFOUT = 0.75V
IOUT = ±2A, VIN = 1.35V,
30
30
30
--
--
--
30
30
30
VREFOUT = 0.675V
VOUT Output Voltage Offset VOUT_OS
mV
IOUT = ±2A, VIN = 1.2V,
VREFOUT = 0.6V
IOUT = ±2A, VIN = 1.05V,
VREFOUT = 0.525V
(Note 5)
VOUT Source Current Limit ILIM_VOUT_SR
VOUT in PGOOD window
VOUT in PGOOD window
2
2
--
--
--
--
A
A
VOUT Sink Current Limit
ILIM_VOUT_SK
RDISCHARGE
VOUT Discharge
Resistance
VVDDQSNS = 0V, VOUT = 0.3V,
VS3 = 0V
--
18
25
VDDQSNS and REFOUT
VDDQSNS Input Current
VDDQSNS Voltage Range
IVDDQSNS
VVDDQSNS
VVDDQSNS = 1.8V
20
30
--
40
A
0.5
1.8
V
10mA < IREFOUT < 10mA,
VVDDQSNS = 1.5V
15
13.5
12
--
--
--
--
15
13.5
12
10mA < IREFOUT < 10mA,
VVDDQSNS = 1.35V
REFOUT Voltage Tolerance
to VVDDQSNS
VTOL_REFOUT
mV
10mA < IREFOUT < 10mA,
VVDDQSNS = 1.2V
10mA < IREFOUT < 10mA,
10.5
10.5
VVDDQSNS = 1.05V (Note 5)
REFOUT Source Current
Limit
ILIM_REFOUT_SR
VREFOUT = 0V
10
10
40
40
--
--
mA
mA
REFOUT Sink Current Limit ILIM_REFOUT_SK
VREFOUT = VDDQSNS / 2 + 1V
UVLO/S3/S5
Rising
2.5
--
2.7
120
--
2.85
--
V
UVLO Threshold
VUVLO_VCNTL
Hysteresis
mV
Logic-High VIN_H
Logic-Low VIN_L
1.7
--
S3/S5 Input
Voltage
V
--
--
0.3
Copyright 2018 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
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RTQ2536-QA
Note 1. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation of the device at these or any other conditions beyond those
indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating
conditions may affect device reliability.
Note 2. θJA is measured under natural convection (still air) at TA = 25°C with the component mounted on a high effective-
thermal-conductivity four-layer test board on a JEDEC 51-7 thermal measurement standard. θJC is measured at the
exposed pad of the package.
Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
Note 5. Guarantee by design.
Copyright 2018 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
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DSQ2536-QA-01 September 2018
RTQ2536-QA
Typical Application Circuit
RTQ2536-QA
2
1
10
9
VCNTL
V
VIN
VCNTL
S5
IN
C1
10µF x 2
C4
4.7µF
VDDQSNS
S5
6
7
3
5
VOUT
REFOUT
C3
V
OUT
REFOUT
S3
C5
10µF x 2
SENSE
0.1µF
S3
4
PGND
GND
8
Copyright 2018 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
DSQ2536-QA-01 September 2018
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RTQ2536-QA
Typical Operating Characteristics
REFOUT Voltage vs. Temperature
Output Voltage vs. Temperature
1.0
0.9
0.8
0.7
0.6
0.5
1.0
0.9
0.8
0.7
0.6
VCNTL = 3.3V,
VCNTL = 3.3V,
VIN = VDDQSNS = 1.5V, VOUT = 0.75V
VIN = VDDQSNS = 1.5V, VOUT = 0.75V
0.5
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature (°C)
Temperature (°C)
VCNTL Supply Current vs. Temperature
VCNTL Shutdown Current vs. Temperature
500
480
460
440
420
400
380
360
340
320
300
350
300
250
200
150
100
50
VCNTL = 5V
VCNTL = 5V
VCNTL = 3.3V
VCNTL = 3.3V
VIN = VDDQSNS = 1.5V, VOUT = 0.75V
VIN = VDDQSNS = 1.5V, VOUT = 0.75V
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature (°C)
Temperature (°C)
UVLO vs. Temperature
Sourcing Current Limit vs. Temperature
3.0
2.9
2.8
2.7
2.6
2.5
2.4
2.3
2.2
2.1
2.0
4.0
3.5
3.0
2.5
2.0
1.5
1.0
Rising
Falling
VIN = VDDQSNS = 1.5V,
S3 = 2V, VOUT = 0.75V
VCNTL = 3.3V,
VIN = VDDQSNS = 1.5V, VOUT = 0.75V
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature (°C)
Temperature (°C)
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DSQ2536-QA-01 September 2018
RTQ2536-QA
Sinking Current Limit vs. Temperature
Power On from S3
4.0
3.5
3.0
2.5
2.0
1.5
1.0
S3
(2V/Div)
VOUT
(0.5V/Div)
IOUT
(1A/Div)
VREFOUT
(1V/Div)
VCNTL = 3.3V,
VIN = VDDQSNS = 1.5V, VOUT = 0.75V
VCNTL = 3.3V, VIN = VDDQSNS = 1.5V,
VOUT = 0.75V, IOUT = 1.5A, COUT = 10μF
-50
-25
0
25
50
75
100
125
Time (100μs/Div)
Temperature (°C)
0.75VOUT @ 1.5A Transient Response
Power Off from S3
S3
(2V/Div)
VOUT
(20mV/Div)
VOUT
(0.5V/Div)
IOUT
(1A/Div)
IOUT
(1A/Div)
VREFOUT
(1V/Div)
VCNTL = 3.3V, VIN = VDDQSNS = 1.5V,
VOUT = 0.75V, IOUT = 1.5A, COUT = 10μF
Source, VIN = 1.5V, COUT = 10μF
Time (500μs/Div)
Time (10μs/Div)
0.75VOUT @ 1.5A Transient Response
VOUT
(20mV/Div)
IOUT
(1A/Div)
Sink, VIN = 1.5V, COUT = 10μF
Time (500μs/Div)
Copyright 2018 Richtek Technology Corporation. All rights reserved.
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is a registered trademark of Richtek Technology Corporation.
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RTQ2536-QA
Application Information
The RTQ2536-QAis a 2Asink/source tracking termination
regulator. It is specifically designed for low-cost and low-
external component count system such as notebook PC
applications. The RTQ2536-QApossesses a high speed
operating amplifier that provides fast load transient response
and only requires two 10μF ceramic input capacitor and a
10μF ceramic output capacitors.
resistance, θJA, is highly package dependent. For a
WDFN-10SL 3x3 package, the thermal resistance, θJA, is
30.5°C/Won a standard JEDEC 51-7 high effective-thermal-
conductivity four-layer test board. The maximum power
dissipation at TA = 25°C can be calculated as below :
PD(MAX) = (125°C − 25°C) / (30.5°C/W) = 4.09W for a
WDFN-10SL 3x3 package.
The maximum power dissipation depends on the operating
ambient temperature for the fixed TJ(MAX) and the thermal
resistance, θJA. The derating curves in Figure 1 allows
the designer to see the effect of rising ambient temperature
on the maximum power dissipation.
Capacitor Selection
Good bypassing is recommended from VINtoGNDto help
improveAC performance.A10μF or greater input capacitor
located as close as possible to the IC is recommended.
The input capacitor must be located at a distance of less
than 0.5 inches from the VIN pin of the IC.
For stable operation, the total capacitance of the ceramic
capacitor at the VTT output terminal must be larger than
10μF (effective value). The RTQ2536-QA is designed
specifically to work with low ESR ceramic output capacitor
in space saving and performance consideration. Larger
output capacitance can reduce the noise and improve load
transient response, stability and PSRR. The output
capacitor should be located near the VTT output terminal
pin as close as possible.
5.0
Four-Layer PCB
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
Thermal Considerations
The junction temperature should never exceed the
absolute maximum junction temperature TJ(MAX), listed
under Absolute Maximum Ratings, to avoid permanent
damage to the device. The maximum allowable power
dissipation depends on the thermal resistance of the IC
package, the PCB layout, the rate of surrounding airflow,
and the difference between the junction and ambient
temperatures. The maximum power dissipation can be
calculated using the following formula :
0
25
50
75
100
125
150
Ambient Temperature (°C)
Figure 1. Derating Curve of Maximum PowerDissipation
PD(MAX) = (TJ(MAX) − TA) / θJA
where TJ(MAX) is the maximum junction temperature, TA is
the ambient temperature, and θJA is the junction-to-ambient
thermal resistance.
For continuous operation, the maximum operating junction
temperature indicated under Recommended Operating
Conditions is 125°C. The junction-to-ambient thermal
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is a registered trademark of Richtek Technology Corporation.
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DSQ2536-QA-01 September 2018
RTQ2536-QA
Outline Dimension
2
1
2
1
DETAILA
Pin #1 ID and Tie Bar Mark Options
Note : The configuration of the Pin #1 identifier is optional,
but must be located within the zone indicated.
Dimensions In Millimeters
Dimensions In Inches
Symbol
Min.
0.700
0.000
0.175
0.200
2.900
2.550
2.900
1.590
Max.
0.800
0.050
0.250
0.300
3.100
2.650
3.100
1.690
Min.
0.028
0.000
0.007
0.008
0.114
0.100
0.114
0.063
Max.
0.031
0.002
0.010
0.012
0.122
0.104
0.122
0.067
A
A1
A3
b
D
D2
E
E2
e
0.500
0.020
L
0.300
0.400
0.012
0.016
W-Type 10SL DFN 3x3 Package
Richtek Technology Corporation
14F, No. 8, Tai Yuen 1st Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: (8863)5526789
Richtek products are sold by description only. Customers should obtain the latest relevant information and data sheets before placing orders and should verify
that such information is current and complete. Richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek
product. Information furnished by Richtek is believed to be accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use;
nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent
or patent rights of Richtek or its subsidiaries.
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11
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