R1272S013A-E2-FE [RICOH]
Switching Controller;
| 型号： | R1272S013A-E2-FE |
| 厂家： | 
RICOH ELECTRONICS DEVICES DIVISION |
| 描述： | Switching Controller |
| 文件： | 总43页 (文件大小：1713K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
R1272S Series
34 V Input Synchronous Step-down DC / DC Controller
NO.EA-351-151001
OUTLINE
The R1272S is a step-down DC/DC controller which can generate an output voltage of 0.7 V to 5.3 V by driving
external high- / low-side NMOSs. By the adoption of a unique current mode PWM architecture without an
external current sense resistor, the R1272S can make up a stable DC/DC converter with high-efficiency even
if adding low Ron MOSFETs and a low DCR inductor externally. And, by the frequency characteristics
optimization with using external phase compensation capacitor, the R1272S can achieve a high-speed
response to variations of input voltage and load current. The user-settable oscillation frequency is adjustable
over a range of 250 kHz to 1 MHz1 by external resistors, and also can be synchronized to an external clock.
Output Voltage Control Methods have three operating modes: Forced PWM mode, PLL_PWM mode, and
PWM/VFM Auto-switching mode. These modes are selectable according to conditions of the MODE pin.
Especially, the PWM/VFM Auto-switching mode can improve efficiency under light load conditions.
When the input voltage drops down at cranking, to hold the output voltage level, the R1272S reduces the off-
duty by decrease the operation frequency below one-quarter so that the input-output difference voltage
becomes small.
Protection functions include a current limit function, an UVLO (Under Voltage Lock Out) function, an OVP (Over
Voltage Protection) function, a soft-start function, a low-inductor current shutdown function, and so on. Also, a
power good function provide the status of output with using a power good (PGOOD) pin.
For EMI reduction, SSCG (Spread-Spectrum Clock Generation) for diffused oscillation frequency at the PWM
operation is optionally available. The R1272S is available in HSOP-18 package.
FEATURES
● Operating Voltage (Maximum Rating) ······················· 4.0 V to 34 V (36 V)
● Operating Temperature Range ································ -40°C ≤ Ta ≤ 105°C
(Usable in high-temperature environment)
● Start-up Voltage ··················································· 4.5 V
● Output Voltage ················· ··································· 0.7 V to 5.3 V
● Feedback Voltage Tolerance ················· ················· 0.64 V ± 1%
● Consumption Current at No Load (at VFM mode) ········ Typ.15 µA
● Adjustable Oscillation Frequency1 ········ ··················· 250 kHz to 1 MHz
● Synchronizable Clock Frequency1···························· 250 kHz to 1 MHz
● Spreading Rate for SSCG ······································ Typ. ±3.6%
● Minimum On-Time ··· ············································ Typ.100 ns
● Minimum Off-Time ················································ Typ.120 ns (at regulation mode)
At dropout, actual minimum off-time is reduced.
● Adjustable Soft-start Time2 ····································· Min. 500 µs (with using an external capacitor)
● Pre-bias Start-up
● Anti-phase Clock Output
1
The adjustable oscillation frequency range becomes 250 kHz ≤ fOSC ≤ 600 kHz when 0.7 V ≤ VOUT < 1.35V.
2 Available the tracking function through the application of an external voltage.
1
R1272S
NO.EA-351-151001
● Thermal Shutdown Function ··································· Tj = 160ºC (Typ.)
● Under Voltage Lockout (UVLO) Function········· ·········· Typ. 3.3 V
● Output Over Voltage Detection ································ FB pin voltage (VFB) + 10%
● Over-current Protection·········································· Hiccup-mode / Latch mode
● Selectable Current Limit Threshold··························· 50 mV / 70 mV / 100 mV
● Power Good Output ·············································· NMOS Open-drain Output
● Package····························································· HSOP-18
APPLICATIONS
● Power source for digital home appliances such as digital TV, DVD players.
● Power source for office equipment such as printers and fax machines.
● Power source for 5V PSU or 2-cell or more Li-ion battery powered communication equipment, cameras,
video instruments such as VCRs, camcorders.
● Power source for high voltage battery-powered equipment.
SELECTION GUIDE
The function and setting for the ICs are selectable at the user’s request.
Product Name
Package
Quantity per Reel
Pb Free
Halogen Free
R1272SxxyA-E2-FE
HSOP-18
1,000
Yes
Yes
xx : Select the combination of processing and function.
xx
00
01
03
Over Current Protection
Non-latch type hiccup mode
Latch mode
SSCG
Disable
Disable
Enable
Latch mode
If required a version with SSCG function, please contact our sales offices.
y : Select the current limit threshold voltage.
Set Voltage for Current
Limit Threshold (Typ.)
y
1
2
3
50 mV
70 mV
100 mV
2
R1272S
NO.EA-351-151001
BLOCK DIAGRAMS
VOUT
VIN
Thermal Shutdown
VCC
0.6V
-
+
UVLO
OVP
INT Regulator
Int_Reg
OVP
Hiccup
/Latch
SHDN
EN
CE
-
+
1.2V
VCC
VCC Regulator
VCC
Mode
Select
MODE
PFC
Filter
SSCG_EN ＜Enable/ Disable＞
OVD
SHDN
BST
Mode
Freq
Detection
Freq_NG
CLK
RT
VCO
Set_Pulse
HGATE
LX
Mode
OFF_Pulse
Drive
Circuit
AVIN
VOUT
Mode
Rev
OFF_Pulse
Soft_Start
VFM Control
LGATE
Over Voltage Detection
Under Voltage Detection
OVD
FB
PGND
AGND
UVD
Reverse
Detection
Rev
Int_Reg
2μA
Mode
OVD
Set_Pulse
S
R
Q
SHDN
-
+
-
+
CSS/TRK
ILIM
Hiccup
/Latch
OVD
Limit Circuit
Hiccup/Latch
SHDN
OVP
Soft Start
Circuit
Soft_Start
Freq_NG
Peak Limit
Circuit
SENSE
Reference
COMP
VOUT
VCC
PGOOD
Slope
Soft_Start
CLK
SHDN
OVD
UVD
VIN VOUT
CLKOUT
R1272SxxxA
3
R1272S
NO.EA-351-151001
PIN DESCRIPTIONS
HSOP-18
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
VIN
VCC
BST
TOP VIEW
CSS
/TRK
AGND
CE
HGATE
LX
SENSE
VOUT
RT
LGATE
PGND
MODE
PGOOD
CLKOUT
PAD*
COMP
FB
HSOP-18 Pin Description
Pin No.
Pin Name
Description
1
2
3
4
5
6
7
VIN
CSS/TRK
AGND
CE
Power supply pin
Soft-start adjustment pin
Analog GND pin
Chip enable pin (Active ”H”)
Sense pin for inductor current
Output voltage feedback input pin
Oscillation adjustment pin
SENSE
VOUT
RT
Capacitor connecting pin for phase compensation of error-
amplifier
8
COMP
9
FB
CLKOUT
PGOOD
MODE
PGND
LGATE
LX
Feedback input pin to the error amplifier
Clock output pin
10
11
12
13
14
15
16
17
18
Power-good output pin
Mode-set input pin
Power GND pin
L-side FET control pin
Switchingpin
HGATE
BST
H-side FET control pin
Boostrap pin
VCC
VCC output pin
∗ The tab on the bottom of the package must be electrically connected to GND (substrate level) when mounted on the
board.
4
R1272S
NO.EA-351-151001
INTERNAL EQUIVALENT CIRCUIT FOR EACH PIN
VIN
VIN
Int_Reg
CE
Int_Reg
< VIN Pin >
< CE Pin >
VIN
VIN
VCC
VIN
VOUT
CSS/TRK
1kΩ
Int_Reg
< CSS/TRK Pin >
< VOUT Pin >
VCC
VIN
Int_Reg
Int_Reg Int_Reg
RT
SENSE
< SENSE Pin >
< RT Pin >
5
R1272S
NO.EA-351-151001
VCC
Int_Reg
COMP
FB
< COMP Pin >
VCC VCC
< FB Pin >
CLKOUT
PGOOD
< CLKOUT Pin >
< PGOOD Pin >
VCC
VCC
VCC
VCC
LGATE
MODE
PGND
PGND
PGND
PGND
< MODE Pin >
< LGATE Pin >
6
R1272S
NO.EA-351-151001
BST
BST
BST
BST
VIN
HGATE
HGATE
LX
LX
LX
LX
< LX Pin >
< HGATE Pin >
VCC
BST
< BST Pin >
< VCC Pin >
AGND
PGND
< AGND-PGND Pins >
7
R1272S
NO.EA-351-151001
ABSOLUTE MASIMUM RATINGS
Symbol
VIN
VCE
VCSS/VTRK
VOUT
Item
Rating
-0.3 to 36
-0.3 to 36
-0.3 to 3
Unit
V
V
VIN pin voltage
CE pin voltage
CSS/TRK pin voltage
VOUTpin voltage
SENSEpin voltage
RT pin voltage
V
-0.3 to 6
-0.3 to 6
-0.3 to 3
V
V
V
VSENSE
VRT
1
VCOMP
COMP pin voltage
FB pin voltage
-0.3 to 6
-0.3 to 3
V
V
VFB
VCC pin voltage
-0.3 to 6
V
VCC
Output current for VCC pin
BST pin voltage
HGATE pin voltage
LX pin voltage
LGATE pin voltage
MODE pin voltage
PGOOD pin voltage
CLKOUT pin voltage
Internally limited
LX-0.3 to LX+6
LX-0.3 to BST
-0.3 to 36
-0.3 to 6
mA
V
V
VBST
VHGATE
2
VLX
V
V
V
1
VLGATE
VMODE
-0.3 to 6
VPGOOD
VCLKOUT
-0.3 to 6
-0.3 to 6
V
V
1
Power Dissipation
(HSOP-18)
JEDEC STD.51-7 Test
Land Pattern
3
PD
2500
mW
Tj
Tstg
Junction Temperature
Storage Temperature Range
-
40 to 125
°C
°C
-55 to 125
ABSOLUTE MAXIMUM RATINGS
Electronic and mechanical stress momentarily exceeded absolute maximum ratings may cause the permanent
damages and may degrade the life time and safety for both device and system using the device in the field.
The functional operation at or over these absolute maximum ratings are not assured.
RECOMMENDED OPERATING CONDITIONS
Symbol
VIN
Item
Rating
4.0 to 34
−40 to 105
Unit
V
°C
Input Voltage
Operating Temperature Range
Ta
RECOMMENDED OPERATING RATINGS
All of electronic equipment should be designed that the mounted semiconductor devices operate within the
recommended operating ratings. The semiconductor devices cannot operate normally over the recommended
operating ratings, even if when they are used over such ratings by momentary electronic noise or surge. And the
semiconductor devices may receive serious damage when they continue to operate over the recommended
operating ratings.
1
2
3
The pin voltage must be prevented from exceeding VCC +0.3V.
The pin voltage must be prevented from exceeding VIN +0.3V.
Refer to POWER DISSIPATION for detailed information.
8
R1272S
NO.EA-351-151001
ELECTRICAL CHARACTERISTICS
VIN = 12 V, CE = VIN, unless otherwise specified.
The specifications surrounded by
are guaranteed by design engineering at -40°C ≤ Ta ≤ 105°C.
R1272SxxxA
(Ta = 25°C)
Symbol
VSTART
VOUT
Item
Start-up Voltage
Output Voltage Range
VCC Pin Voltage (VCC–AGND) VFB = 0.672 V
Conditions
Min.
Typ.
Max. Unit
4.5
5.3
5.3
20
V
V
0.7
4.9
VCC
5.1
3
V
ISTANDBY
Standby Current
VIN = 34 V, CE = 0 V
µA
VFB = 0.672 V,
MODE = 5 V,
VOUT = SENSE = LX = 5V
VFB = 0.672 V,
MODE = 0 V
VIN Consumption Current 1
at Switching Stop in PWM mode
IVIN1
1.0
15
1.3
mA
µA
VIN Consumption Current 2
at Switching Stop in VFM mode
IVIN2
75
VOUT = SENSE = LX = 5V
VUVLO2
VUVLO1
VCC Rising
4.0
3.3
4.2
V
V
UVLO Threshold Voltage
FB Voltage Accuracy
VCC Falling
3.1
0.6336
0.6272
225
Ta = 25°C
0.6464
0.6528
275
VFB
0.64
V
-40°C ≤ Ta ≤ 105°C
RT = 135 kΩ
RT = 32 kΩ
fOSC0
fOSC1
tOFF
Oscillation Frequency 0
Oscillation Frequency 1
Minimum OFF Time
Minimum ON Time
250
1000
120
kHz
900
1100 kHz
VIN = 5 V, VOUT = 5 V
190
120
ns
ns
tON
100
fosc×0.5
250
fosc×1.5 kHz
fSYNC
Synchronizing Frequency
fOSC as the reference
1000
tSS1
tSS2
ITSS
Soft-start Time 1
Soft-start Time 2
CSS / TRK = OPEN
CSS = 4.7 nF
0.4
0.75
2.0
ms
ms
µA
1.4
Charge Current for Soft-start Pin CSS / TRK = 0 V
1.8
2
2.2
CSS/TRK Pin Voltage at End of
Soft-start
Discharge Resistance for
CSS/TRK Pin
On-resistance of Pull-up
Transistor (HGATE Pin)
On-resistance of Pull-down
Transistor (HGATE Pin)
On-resistance of Pull-up
Transistor (LGATE Pin)
On-resistance of Pull-down
Transistor (LGATE Pin)
VFB
+0.03
VFB
+0.06
VSSEND
RDIS_CSS
V
kΩ
Ω
VIN = 4.5 V, CE = 0 V,
CSS / TRK = 3 V
(BST – LX) = 5 V,
IHGATE = -100 mA
(BST – LX) = 5 V,
IHGATE = 100 mA
(VCC – PGND) = 5 V,
ILGATE = -100 mA
(VCC – PGND) = 5 V,
ILGATE = 100 mA
2.0
3.0
2.5
1.5
4.0
1.5
5.0
5.0
3.5
7.0
3.5
RUPHGATE
RDOWNHGATE
RUPLGATE
Ω
Ω
RDOWNLGATE
Ω
9
R1272S
NO.EA-351-151001
VIN = 12 V, CE = VIN, unless otherwise specified.
The specifications surrounded by
are guaranteed by design engineering at -40°C ≤ Ta ≤ 105°C.
R1272SxxxA Continued
(Ta = 25°C)
Symbol
Item
Conditions
Min.
40
Typ.
50
Max. Unit
60
80
mV
mV
mV
mV
mV
mV
Current Limit Threshold Voltage
(SENSE – VOUT)
VILIMIT
60
70
90
100
-25
-35
-50
110
-15
-25
-40
-35
-45
-60
Reverse Current Sense Threshold
(SENSE – VOUT)
VIREVLIMIT
MODE = H / CLK
LX Shot to GND Detector Threshold
Voltage (VIN – LX)
LX Short to VCC Detector
Threshold Voltage (LX – PGND)
VLXSHORTL
VLXSHORTH
0.345
0.43
0.43
0.520
0.515
V
V
0.330
1.27
VCEH
VCEL
CE ”High” Input Voltage
CE ”Low” Input Voltage
CE ”High” Input Current
CE ”Low” Input Current
FB ”High” Input Current
FB ”Low” Input Current
MODE ”High” Input Voltage
MODE ”Low” Input Voltage
MODE ”High” Input Current
MODE ”Low” Input Current
V
V
1.14
2.45
1.00
0.10
0.10
ICEH
CE = 34 V
CE = 0 V
VFB = 3 V
VFB = 0 V
0.20
-1.00
-0.10
-0.10
1.33
0
0
0
0
µA
µA
µA
µA
V
ICEL
IFBH
IFBL
VMODEH
VMODEL
IMODEH
IMODEL
0.74
6.60
1.00
VCC
V
MODE = 6 V
MODE = 0 V
1.00
-1.00
4.7
0
0
µA
µA
V
VCLKOUTH CLKOUT Pin ”High” Output Voltage CLKOUT = Hi-z
VCLKOUTL CLKOUT Pin ”Low” Output Voltage CLKOUT = Hi-z
0
0.1
V
TTSD
TTSR
Ta Rising
Ta Falling
150
125
160
140
℃
℃
Thermal Shutdown Threshold
Temperature
VIN = 4.0 V,
VPGOODOFF PGOOD Pin ”OFF” Voltage
IPGOODOFF PGOOD Pin ”OFF” Current
0.26
0
0.54
0.10
V
PGOOD = 1 mA
VIN = 34 V, CE = 0 V,
PGOOD = 6 V
-0.10
µA
VFBOVD1
VFB Rising
V
V
V
V
FB×1.10 0.740
V
V
V
V
FB Pin OVD Threshold Voltage
VFBOVD2
VFB Falling
VFB Falling
VFB Rising
0.664
0.556
FB×1.07
VFBUVD1
FB×0.90
FB Pin UVD Threshold Voltage
VFBUVD2
FB×0.93 0.628
Trans Conductance Amplifier
gm (EA)
COMP = 1.5 V,
0.35
1
1.55 mS
All test items listed under Electrical Characteristics are done under the pulse load condition (Tj ≈ Ta = 25°C).
10
R1272S
NO.EA-351-151001
OPERATING DESCRIPTIONS
MODE Pin Function
The R1272S operating mode is switched among the forced PWM mode, PWM/VFM auto-switching mode and
PLL_PWM mode, by a voltage or a pulse applied to MODE pin. The forced PWM mode is selected when the
voltage of the MODE pin is more than 1.33 V, and the PWM works regardless of a load current. The PWM/VFM
auto-switching mode is selected when it is less than 0.74 V, and control is switched between a PWM mode
and a VFM mode depending on the load current.
See Forced PWM mode and VFM mode for details. And see Frequency Synchronization Function for the
operation on connecting an external clock.
Frequency Synchronization Function
The R1272S can synchronize to the external clock being inputted via the MODE pin, with using a PLL (Phase-
locked loop). The forced PWM mode is selected during synchronization. The external clock with a pulse-width
of 100 ns or more is required. The allowable range of oscillation frequency is 0.5 to 1.5 times of the set
frequency1, and the operating guaranteed frequency is in the 250 kHz to 1 MHz range2. The R1272S can
synchronize to the external clock even if the soft-start works. That is, the R1272S executes the soft-start and
the synchronization functions at a time if having started up while inputting an external clock to the MODE pin.
PGOOD (Power Good) Output Function
The power good function with using a NMOS open drain output pin can detect the following states of the
R1272S. The NMOS turns on and the PGOOD pin becomes “Low” when detecting them. After the R1272S
returns to their original state, the NMOS turns off and the PGOOD pin outputs “High” (PGOOD Input Voltage:
VUP).
・CE = “L” (Shut down)
・UVLO (Shut down)
・Thermal Shutdown
・Soft-start time
・at UVD Threshold Voltage Detection
・at OVD Threshold Voltage Detection
・at hiccup-type Protection (when hiccup mode is selected)
・at latch-type Protection (when latch mode is selected)
The PGOOD pin is designed to become 0.54 V or less in “Low” level as the flag when the current floating to
the PGOOD pin is 1 mA. The use of the PGOOD input voltage (VUP) of 5.5 V or less and the pull-up resistor
(RPG) of 10 kΩ to 100 kΩ are recommended. If not using the PGOOD pin, connect it to “Open” or “GND”.
1
See Oscillation Frequency Setting for details of the set frequency.
The adjustable oscillation frequency range becomes 250 kHz ≤ fOSC ≤ 600 kHz when 0.7 V ≤ VOUT < 1.35V.
2
11
R1272S
NO.EA-351-151001
R1272S
RPG
PGOOD
VUP
VPGOOD
“H” is detected under
abnormal condition.
PGOOD Output Pin Connecting Diagram
VIN
1.1V
CE
time
time
time
time
VFB
0.64V
PGOOD
120us
(Typ.)
Hi-z
Hi-z
Rising / Falling Sequence of Power Good Circuit
12
R1272S
NO.EA-351-151001
Under Voltage Detection (UVD)
The UVD function indirectly monitors the output voltage with using the FB pin. The PGOOD pin outputs “L”
when the UVD detector threshold is 90% (Typ.) of VFB and VFB is less than the UVD detector threshold for
more than 30 µs (Typ.). When VFB is over 93% (Typ.) of 0.64 V, the PGOOD pin outputs “H” after delay time
(Typ.120 µs.). And, the hiccup- / latch-type overcurrent protection works when detecting an overcurrent, an LX
power supply protection, or an over voltage protection during the UVD detection.
Over Voltage Detection (OVD)
The OVD function indirectly monitors the output voltage with using the FB pin. Switching stops even if the
internal circuit is active state, when detecting the over voltage of VFB. The PGOOD pin outputs “L” when the
OVD detector threshold is 110% (Typ.) of VFB and VFB is over the OVD detector threshold for more than 30 µs
(Typ.). When VFB is under 107% (Typ.) of VFB, which is the OVD released voltage, the PGOOD pin outputs “H”
after delay time (Typ.120 µs.). Then, switching is controlled by normal operation. The over voltage protection
works when an error is caused by a feedback resistor in peripheral circuits for the FB pin.
Over Voltage Protection (OVP)
The OVP function monitors the voltage of VOUT pin to reduce an over voltage, when an error is caused in
peripheral circuits for the FB pin. Switching stops even if the internal circuit is active state, when VOUT is over
the OVP detector threshold. When VOUT is under the OVP detector threshold, switching is controlled by normal
operation. If the UVD for FB pin occur during the OVP detect state, an error will occur and hiccup- / latch-type
protection will work. However, the operation under this function is not guaranteed because the OVP detector
threshold is set to the absolute maximum rating and more for the VOUT pin.
LX Power Supply (VIN Short) / GND (GND Short) Protection
In addition to normal current limit, the R1272S provides the LX power supply / GND short protection to monitor
the voltage between the FET’s drain and source. Since the current limit function is controlled with an external
inductor’s DCR or a sense resistance, the current limit function cannot work when a flow-through current is
generated on FET and when an overcurrent is generated by shorting the LX pin to VDD/GND. The detecting
current is determined by LX shot to VDD/GND detector threshold voltage (FET_ON-Resistance x Current,
Typ.0.43 V).
Hiccup-type / Latch-type Overcurrent Protection
The hiccup-type / latch-type overcurrent protection can work under the operating conditions that is the UVD
can function during the current limit or OVP and the LX GND short protection. The latch-type protection can
release the circuit by setting the CE pin to “L” or by reducing VIN to be less than the UVLO detector threshold,
when the output is latched off. The hiccup type protection stops switching releases the circuit after the
protection delay time (Typ. 3.5 ms). Since this protection is auto-release, the CE pin switching of “L” / “H” is
unnecessary. And, damage due to the overheating might not be caused because the term to release is long.
When the output is shorted to GND, switching of “ON” / “OFF” is repeated until the shorting is released.
13
R1272S
NO.EA-351-151001
Current Limit Function
The current limit function can be to limit the current by the peak current method to turn the high-side transistor
off that the potential differences is over the current limit threshold voltage. The threshold voltage is selectable
among 50 mV / 70 mV / 100 mV. And, the two following detection methods can be selected by external
components connected.
A. Detecting Method with RSENSE
The current limit value is detected with the voltage across the inductor that a sense resistance is connected in
series. By connecting a resistance with low level of variation, the current limit with high accuracy can achieve.
As a result, be caution that the power loss is caused from the current and RSENSE. The peak current in the
current limit inductor can be calculated by the following equation.
Peak current in Current limit inductor (A) = Current limit threshold voltage (mV) / RSENSE (Ω)
SENSE
VOUT
HS_FET
LS_FET
LX
COUT
RSENSE
Inductor
Figure A Detection with Sense Resistance
B. Detecting Method with DCR of Inductor
The current limit value is detected with the DCR of the inductor. The reduction of the loss is minimized since
the inductor is in no need of a resistance. But, the SENSE pin requires to connect a resistor and a capacitor
to each end of the inductor. Because a constant slope is caused depending on the inductance and the
capacitance. Factors causing the poor accuracy of current limit value include the variation in production of the
inductor’s DCR and the temperature characteristics. RS and CS can be calculated by the following equation.
Peak current in Current limit inductor (A) = Current limit threshold voltage (mV) / Inductor’s DCR (Ω)
CS = L / (DCR x RS)
SENSE
RS
CS
HS_FET
LS_FET
LX
VOUT
COUT
DCR
Inductor
Figure B Detecting with Inductor’s DCR
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R1272S
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Output Voltage Setting
The output voltage (VOUT) can be set by adjustable values of RTOP and RBOT. The value of VOUT can be
calculated by the following equation (1) :
VOUT = VFB × (RTOP + RBOT) / RBOT ······················································································· (1)
For example, when setting VOUT = 3.3 V and setting RBOT = 22 kΩ, RTOP can be calculated by substituting them
to the equation (1). As a result of the expanding equation (2), RTOP can be set to 91.4 kΩ.
To make 91.4 kΩ with using the E24 type resistors, the connecting use of 91 kΩ and 0.39 kΩ resistors in series
is required. If the tolerance level of the set output voltage is wide, using a resistor of 91 kΩ to RTOP can reduce
the number of components.
R
TOP = (3.3 V / 0.64 V - 1) × 22 kΩ
= 91.4 kΩ ·············································································································· (2)
Oscillation Frequency Setting
Connecting the oscillation frequency setting resistor (RRT) between the RT pin and GND can control the
oscillation frequency in the range of 250 kHz to 1 MHz1. For example, using the resistor of 66 kΩ can set the
frequency of about 500 kHz.
The Electrical Characteristics guarantees the oscillation frequency under the conditions stated below for fOSC0
(at RRT = 135 kΩ) and fOSC1 (at RRT = 55 kΩ).
1200
1000
800
600
400
200
0
30
50
70
90
110
130
150
RRT [kΩ]
RRT [kΩ] = 41993 x fOSC [kHz] ^ (-1.039)
R1272S001A Oscillation Frequency Setting Resistor (RRT) vs. Oscillation Frequency (fOSC
)
1
The adjustable oscillation frequency range becomes 250 kHz ≤ fOSC ≤ 600 kHz when 0.7 V ≤ VOUT < 1.35V.
15
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Soft-start Function
The soft-start time is a time between a rising edge (“H” level) of the CE pin and the timing when the output
voltage reaches the set output voltage. Connecting a capacitor (CSS) to the CSS / TRK pin can adjust the soft-
start time (tSS) – provided the internal soft-start time of 500 µs (Typ.) as a lower limit. The adjustable soft-start
time (tSS2) is 1.6 ms (Typ.) when connecting an external capacitor of 4.7 nF with the charging current of 2.0
μA (Typ.). If not required to adjust the soft-start time, set the CSS / TRK pin to “Open” to enable the internal
soft-start time (tSS1) of 500 µs (Typ.).
Each of soft-start time (tss1/ tss2) is guaranteed under the conditions described in the chapter of “Electrical
Characteristics”.
tSS
10ms
3.3ms
CSS [nF] = (tSS - tVO_S) / 0.64 × 2.0
1.6ms
tSS: Soft-start time (ms)
1.2ms
tVO_S: Time period from CE = “H” to VOUT’s rising
(Typ. 0.160 ms)
0.5ms
CSS
1nF
3.3nF4.7nF 10nF
33nF
Soft-start Time Adjustable Capacitor (CSS) vs. Soft-start Time (tSS)
tSS
CE
tVO_S
1.27V
time
VOUT
VSET
time
PGOOD
120us
(Typ.)
time
Soft-start Sequence
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Tracking Function
Applying an external tracking voltage to the CSS / TRK pin can control the soft-start sequence – provided that
the lowest internal soft-start time is limited to 500 µs (Typ.). Since VFB becomes nearly equal to VCSS/TRK at
tracking, the complex start timing and soft-start can be easily designed. The available voltage at tracking is
between 0 V and 0.64 V. If the tracking voltage is over 0.64 V, the internal reference voltage of 0.64 V is
enabled. Also, an arbitrary falling waveform can be generated by reducing VCSS/TRK to 0.64 V (Typ.) or less,
because the R1272S supports both of up- and down- tracking.
VOUT
0.64V
CSS/TRK
SS
Normal Operation
SS
Tracking Sequence
Min. ON-time
The min. ON time (Max. 120 ns), which is determined in the R1272S internal circuit, is a minimum time to turn
high-side FET on. The R1272S cannot generate a pulse width less than the min. ON time. Therefore, settings
of the output set voltage and the oscillator frequency are required so that the minimum step-down ratio
[VOUT/VIN x (1 / fOSC)] does not stay below 120ns. If staying below 120 ns, the pulse skipping will operate to
stabilize the output voltage. However, the ripple current and the output voltage ripple will be larger.
Min. OFF-time
By the adoption of bootstrap method, the high-side FET, which is used as the R1272S internal circuit for the
min. OFF time, is used a NMOS . The voltage sufficient to drive the high-side FET must be charged. Therefore,
the min. OFF time is determined from the required time to charge the voltage. By the adoption of the
frequency’s reduction method by one-quarter of a set value (Min.), if the input-output difference voltage
becomes small or load transients are caused, the OFF period can be caused once in four-cycle period of
normal cycle. As a result, the min. OFF time becomes 30 ns (Typ.) substantially, and the maximum duty cycle
can be improved.
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Through-type Current Protection
The HGATE pin voltage (VHGATE) and the LGATE pin voltage (VLGATE) are monitored to protect a through-type
current caused by an external FET. For example, if the HGATE pin changes from “High” to “Low” (that is, VHGATE
is less than 1 V), boosting of VLGATE can control not to turn high- / low- both side of the FET on, in order to
protect the through-type current. If the LGATE pin changes form “High” to “Low”, this protection will work
likewise.
Reverse Current Limit Function
The reverse current limit function works when the output voltage is pulled up more than the set output voltage
by shorting. When the current is over the threshold current to detect the reverse current, the LGATE pin
becomes to “L” to control the reverse current. As with the current limit value, the reverse current limit value is
determined by the voltage between the VOUT pin and the SENSE pin. The detector threshold is one half of
the current limit value.
SSCG (Spread Spectrum Clock Generator)
The SSCG function works for EMI reduction at the PWM mode. This function is enabled in the R1272S03xA.
This function make EMI waveforms decrease in amplitude to generate a ramp waveform within approximately
±3.6% (Typ.) of the oscillator frequency (fOSC). The modulation cycle is fOSC / 128. At the VFM mode, the SSCG
is disabled.
Bad Frequency (BADFREQ) Protection
If a current equivalent to 2 MHz (Typ.) or more or 125 kHz (Typ.) or less is applied to the RT pin when the
resistor of the RT pin is in open / short, the R1272S will stop switching to protect the IC and will cause the
internal state to transition to its state before the soft-start. The CLKOUT pin is fixed to “L” while the bad
frequency as above is detected. The R1272S will restart under the normal control from the state of soft-start
when recover after the abnormal condition.
BADFEQ
Detection
BADFEQ
Release
VFB
0.64V
time
time
time
CLKOUT
PGOOD
BADFREQ Detection / Release Sequence
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Operation of the Step-down Converter
A basic step-down DC/DC converter circuit is illustrated in the following figures. This DC/DC converter charges
energy in the inductor when the high-side transistor turns on, and discharges the energy from the inductor
when the high-side transistor turns off and controls with less energy loss, so that a lower output voltage than
the input voltage is obtained.
IL
ILMAX
ILMIN
i1
Hside Tr.
Lside Tr.
tOPEN
VIN
VOUT
L
i2
COUT
tON
tOFF
GND
t=1/ fOSC
Basic Circuit
Current Through Inductor
Step1. The high-side transistor turns on and current IL (= i1) flows, and energy is charged into COUT. At this
moment, IL increases from ILMIN (= 0) to reach ILMAX in proportion to the on-time period (ton) of the
high-side transistor turns on and current IL (= i1) flows, and energy is charged into COUT. At this
moment, IL increases from ILMIN (= 0) to reach ILMAX in proportion to the on-time period (tON) of the
high-side transistor.
Step2. When the high-side transistor turns off, the low-side transistor turns on in order to maintain IL at ILMAX
,
and current IL (= i2) flows.
Step3. When MODE = L (VFM/PWM Auto-switching mode),
IL (= i2) decreases gradually and reaches IL = ILMIN = 0 after a time period of tOPEN, and the low-side
transistor turns off. This case is called as discontinuous mode. The VFM mode is switched if go to
the discontinuous mode. If the output current is increased, a time period of tOFF runs out prior to reach
of IL = ILMIN = 0. The result is that the high-side transistor turns on and the low-side transistor turns off
in the next cycle. This case is called continuous mode.
When MODE = H (Forced PWM mode), MODE = External Clock (PLL_PWM mode),
Since the continuous mode works at all time, the low-side transistor turns on until going to the next
cycle. That is, the low-side transistor must keep “On” to meet IL = ILMIN < 0, when reaches IL = ILMIN
0 after a time period of tOPEN
=
.
In the PWM mode, the output voltage is maintained constant by controlling tON with the constant switching
frequency (fOSC).
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Forced PWM Mode and VFM Mode
The output voltage control methods are selectable between the PWM / VFM Auto-switching mode and the
forced PWM mode by using the MODE pin.
Forced PWM Mode
Forced PWM mode is selected when setting the MODE pin to “H”. This mode can reduce the output noise,
since the frequency is fixed during light load conditions. Thus, ILMIN becomes less than "0" when IOUT is less
than ∆IL/2. That is, the electric charge, which is charged to COUT, is discharged via FET for the durations –
when IL reaches “0” from ILMIN during the tON periods and when IL reaches ILMIN from “0” during tOFF periods.
VFM Mode
PWM / VFM Auto-switching mode is selected when setting the MODE pin to “L”. This mode can automatically
switch from PWM to VFM to achieve a high-efficiency during light load conditions. By the VFM mode
architecture, the high-side FET is turned on for tON x 1.54 (typ.) at the PWM mode under the same condition
as the VFM mode when the VFB pin voltage drops below the internal reference voltage (Typ.0.64 V). After the
On-time, the high-side FET is turned off and the low-side FET is turned on. When the inductor current of 0 A
is detected, the low-side FET is turned off and the switching operation is stopped (Both of hi- and low-side
FETs are OFF). The switching operation restarts when the VFB pin voltage becomes less than 0.64 V.
The On-time at the PWM mode is determined by a resistance, input and output voltages, which are connected
to the RT pin. Refer to “Calculation of VFM Ripple” for detailed description on the On-time at the VFM mode.
ILMAX
IL
ILMAX
IL
ΔIL
IOUT
0
0
ILMIN
ILMIN
t
t
tON
tOFF
T=1/fOSC
tON
tOFF
Forced PWM Mode
VFM Mode
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Calculation of VFM Ripple
Calculation example of output ripple voltage (VOUT_VFM) is described. VOUT_VFM can be calculated by the
following equation (1). And, the maximum value of inductor current (IL_VFM) can be calculated by the following
equation (2).
VOUT_VFM = RCOUT_ESR × (IL_VFM) + COEF_TON_VFM × (IL_VFM / 2) / fOSC / COUT_EFF ··································· (1)
IL_VFM = ((VIN -VOUT) / L) × COEF_TON_VFM × VOUT / VIN / fOSC·························································· (2)
VOUT_VFM : Output ripple
COUT_ESR : ESR of output capacitor
L_VFM : Maximum current of inductor
OEF_TON_VFM : Scaling factor of On-time - Typ.1.54X (Design value)
(VIN-VOUT) / L : Slope of inductor current
OEF_TON_VFM × VOUT / VIN / fOSC : On-time
R
I
C
C
IL (A)
Inductor Current (Max.)
IL_VFM
Slope
Slope
⊿IL=(VIN-VOUT)/L
⊿IL= VOUT/L
Average Area of
IL (A) x Time (s)
Time(s)
T2
T1
HGATE
LGATE
Inductor Current Waveform at VFM Mode
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Output voltage can be calculated by the following simple equation.
VOUT = I × T/C
I : Current, C : Capacitance, T : Time
Since I is represented by 1/2 x IL_VFM as the average current, the time of current passing at the VFM mode can
be expressed by the following equation.
T = COEF_TON_VFM / fOSC
And, the output ripple voltage (VOUT_VFM) is superimposed a voltage for ESR × I, and the equation (1) is
determined. But, ESR is so small that it may be ignored if ceramic capacitors are connected in parallel.
The amount of charge to the output capacitor can be calculated by the following equation (3).
(High-side FET’s On-time (T1) + Low-side FET’s On-time (T2)) × Average amount of current·········· (3)
Then, T1 and T2 can be calculated by the following equations, and the time of current passing can be
determined.
T1 = COEF_TON_VFM / fOSC × VOUT / VIN····· (On-time at VFM)
T2 = (VIN/VOUT-1) × T1 (0 = IL_VFM – VOUT/L × T2)
T = T1 + T2
= VIN /VOUT × T1
= COEF_TON_VFM / fOSC
And then, the amount of charge can be determine as the following equation (4).
T x IL_VFM /2 = COEF_TON_VFM / fOSC × IL_VFM /2 ·········································································· (4)
With using above-equations, the output ripple voltage (VOUT_VFM) can be calculated by the following equation
(5).
V = IT/C = COEF_TON_VFM / fOSC × IL_VFM / 2 / COUT_EFF ······························································· (5)
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APPLICATION INFORMAITON
Typical Application Circuit
2.2μF
0.22μF
VCC
VIN
CSS/TRC
AGND
CE
BST
HGATE
LX
40μF
VIN
4.5V to 34V
VOUT
3.3V
6.8mΩ
150μF
SENSE
LGATE
PGND
MODE
FLAG
2.2μH
R1272SxxxA
VOUT
RT
HS/LS-FET
NP35N04YLG
1kΩ
COMP
VFB
91.4kΩ
CLKOUT
24pF
13kΩ
3.3nF
2700pF47pF
22kΩ
66kΩ
R1272SxxxA Typical Application Circuit at 500 kHz
2.2μF
VCC
VIN
CSS/TRC
AGND
CE
0.22μF
BST
HGATE
LX
20μF
VIN
4.5V to 12V
VOUT
1.35V
5mΩ
200μF
SENSE
VOUT
RT
LGATE
PGND
MODE
FLAG
1.0μH
R1272SxxxA
HS/LS-FET
NVTFS5811NLTAG
1kΩ
COMP
VFB
24.3kΩ
CLKOUT
47pF
5.5kΩ
3.3nF
3.3nF 100pF
22kΩ
33kΩ
R1272SxxxA Typical Application Circuit at 1MHz
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Selection of External Components
External components and its value required for R1272S are described. Each value is reference value at initial.
Since inductor’s variations and output capacitor’s effective value may lead a drift of phase characteristics,
adjustment to a unity-gain and phase characteristics may be required by evaluation on the actual unit.
1. Determination of Requirements
Determine the frequency, the output capacitor, and the input voltage required. For reference values,
parameters listed in the following table will be used to explain each equation.
Parameter
Output Voltage (VOUT
Value
3.3 V
)
Output Current (IOUT
Input Voltage (VIN)
)
10 A
12 V
Input Voltage Range
Frequency (fOSC
ESR of Output Capacitor (RCOUT_ESR
8 V to 16 V
500 kHz
3 mΩ
)
)
2. Selection of Unity-gain frequency (fUNITY
)
The unity-gain frequency (fUNITY) is determined by the frequency that the loop gain becomes “1” (zero dB). It is
recommended to select within the range of one-sixth to one-tenth of the oscillator frequency (fOSC). Since the
f
UNITY determines the transient response, the higher the fUNITY, the faster response is achieved, but the phase
margin will be tight. Therefore, it is required that the fUNITY can secure the adequate stability. As for the reference,
the fUNITY is set to 70 kHz.
3. Selection of Inductor
After the input and the output voltages are determined, a ripple current (∆IL) for the inductor current is
determined by an inductance (L) and an oscillator frequency (fOSC). The ripple current (∆IL) can be calculated
by the following equation (1).
∆IL= (VOUT / L / fOSC) x (1-VOUT / VIN_MAX) ··················································································· (1)
VIN_MAX : Maximum input voltage
The core loss in the inductor and the ripple current of the output voltage become small when the ripple current
(∆IL) is small. But, a large inductance is required as shown by the equation (1). The inductance can be
calculated by the following equation (2) when a reference value of ∆IL assumes 30% of IOUT is appropriate
value.
L = (VOUT / ∆IL / fOSC) x (1-VOUT / VIN_MAX)··················································································· (2)
= (VOUT / (IOUT x 0.3) / fOSC) x (1-VOUT / VIN_MAX
)
24
R1272S
NO.EA-351-151001
The inductance can be calculated by substituting each parameter to the equation (2).
L = (3.3 V / 3 A / 500 kHz) x (1-3.3 V / 16 V)
= 1.75 µH
When selecting the inductor of 2.2µH as an approximate value of the above calculated value, ∆IL can be shown
as below.
∆IL = (3.3 V / 2.2 µH / 500 kHz) x (1-3.3 V / 16 V)
= 2.38 A
4. Setting of Output Capacitance
The output capacitance (COUT) must be set to meet the following conditions.
■ Calculation based on phase margin
To secure the adequate stability, it is recommended that the pole frequency (fP_OUT) is set to become equal or
below one-fourteenth of the unity-gain frequency. The pole frequency (fP_OUT) can be calculated by the following
equation (3).
f
P_OUT = 1/(2 x π x COUT_EFF x ((ROUT_MIN x 2 x π x fOSC x L) / (ROUT_MIN + 2 x π x fOSC x L) + RCOUT_ESR))
············(3)
COUT_EFF : Output capacitance (rms)
ROUT_MIN : Output resistance at maximum output current
ROUT_MIN = VOUT/ IOUT
= 3.3 V / 10 A
= 0.33 Ω
The following equation (4) can be expressed by substituting fP_OUT = fUNITY / 14 to the equation (3).
C
OUT_EFF = 14 / (2 ×π× fUNITY × ((ROUT_MIN × 2 ×π× fOSC × L) / (ROUT_MIN + 2 ×π× fOSC × L) + RCOUT_ESR))
············ (4)
Then, the output capacitance (rms) can be calculated by substituting each parameter to the equation (4).
C
OUT_EFF =14 / (2 ×π×70kHz×((0.33Ω × 2 ×π× 500 kHz × 2.2 µH) / (0.33Ω+ 2 ×π× 500kHz × 2.2µH)+3mΩ))
= 100.1 µF
It is recommended that the output capacitance is set to become equal or over the value (rms) calculated by
the equation (4).
The output capacitance (rms), which is derated depending on the DC voltage applied, can be calculated by
the following equation (5). Refer to “Capacitor Manufacture’s Datasheet” for details about derating.
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NO.EA-351-151001
COUT_EFF = COUT_SET × (VCO_AB - VOUT) / VCO_AB ··········································································· (5)
COUT_SET : Output capacitor’s spec
VCO_AB : Capacitor’s voltage rating
With using the equation (5), the effective value (rms) is calculated to become 100.1 µF or more. The output
voltage (COUT) can be shown as below when VCO_AB is 10 V.
C
OUT_SET > COUT_EFF / ((VCO_AB - VOUT) / VCO_AB)
COUT_SET > 100.1µF / ((10 - 3.3) / 10)
COUT > 149.4 µF
As the calculated result, COUT selects a capacitor of 150 µF (rms is 100.5 µF).
■ Calculation based on ripple at VFM mode
With using the calculated value of COUT, the amount of ripple at the VFM mode can be shown as the following
equations of (6) and (7).
IL_VFM = ((VIN_MAX-VOUT) / L) × COEF_TON_VFM × VOUT / VIN_MAX / fOSC ··················································· (6)
VOUT_VFM = RCOUT_ESR × (IL_VFM) + COEF_TON_VFM × (IL_VFM / 2) / fOSC / COUT_EFF ····································· (7)
IL_VFM : Maximum current of inductor
COEF_TON_VFM : On-time scaling (multiples of PWM_ON time)
VOUT_VFM : Maximum output ripple
COEF_TON_VFM can be calculated by 1.54 times (Typ.) as the design value. The ripple value can be calculated by
substituting each parameter to the equations of (6) and (7).
IL_VFM = ((16 V - 3.3 V ) / 2.2 µH) × 1.54 × 3.3 V / 16 V / 500 kHz
= 3.67 A
VOUT_VFM = 3 mΩ ×3.67 A + 1.54 × (3.67 A / 2) / 500 kHz / 100.5 µF
= 67.2 mV
VOUT_VFM must be set to become the target ripple value or less. If VOUT_VFM is over the target value, the output
capacitance must be calculated by the following equation (8).
C
OUT_EFF = 1.54 × (IL_VFM / 2) / fOSC / (VOUT_VFM - RCOUT_ESR × (IL_VFM)) ··············································· (8)
5. Designation of Phase Compensation
Since the current amplifier for the voltage feedback is output via the COMP pin, the phase compensation is
achieved with using external components. The phase compensation is able to secure stable operation with
using an external ceramic capacitor and the phase compensation circuit.
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R1272S
NO.EA-351-151001
VOUT
CSPD
RTOP
ERROR_AMP
VFB
COMP
-
+
RBOT
RC
VREF
0.64V
CC CC2
Connection Example for External Phase Compensation Circuit
■ Calculation of RC
The phase compensation resistance (RC) to set the calculated unity-gain frequency can be calculated by the
following equation (9).
RC = 2 ×π× fUNITY × VOUT × COUT_EFF / (gm_ea × VREF × gm_pwr) ························································ (9)
gm_ea : Error amplifier of gm
VREF : Reference voltage (0.64 V)
gm_pwr : power level of gm
gm_pwr × ∆VS = ∆IL
gm_ea / ∆VS = 0.05 × 10 ^ 6 × fOSC / VOUT
gm_ea × gm_pwr = 0.05 × 10 ^ 6 ×∆IL × fOSC / VOUT ·······································································(10)
∆VS : Output amplitude of the slope circuit
RC can be calculated by substituting the equation (10) to the equation (9).
RC = 2 ×π× fUNITY × VOUT × COUT_EFF / (VREF × 0.05 × 10 ^ 6 × ∆IL × fOSC / VOUT
)
= 2 ×π× 70 kHz × 3.3 V × 100.5 µF / (0.64 × 0.05 × 10 ^ 6 × 2.38A × 500 kHz / 3.3 V)
=12.63 ≒13 kΩ
■ Calculation of CC
CC must be calculated by the equation (11) so that the zero frequency of the error amplifier meets the highest
pole frequency (fP_OUT). Then, fP_OUT = 5.0 kHz is determined by calculation of the equation (3).
CC = 1 / (2 ×π× RC × fP_OUT) ································································································(11)
= 1/ (2 × 3.14 ×13 kΩ × 5.0 kHz)
= 2.45 ≒ 2.7 nF
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■ Calculation of CC2
C
C2 can be calculated by two different calculation methods to vary from the zero frequency (fZ_ESR) depending
on the ESR of a capacitor. Z_ESR can be calculated by the equation (12).
f
fZ_ESR = 1 / (2 ×π× RCOUT_ESR × COUT_EFF) ···············································································(12)
= 528 kHz
[When the zero frequency is lower than fOSC / 2]
CC2 sets the pole to fZ_ESR
.
CC2 = RCOUT_ESR × COUT_EFF / RC·····························································································(13)
[When the zero frequency is higher fOSC / 2]
C
C2 sets the pole to fOSC / 2 so as to be a noise filter for the COMP pin.
fOSC / 2 = 1 / (2 ×π× RC × CC2）
CC2 = 2 / (2 ×π× RC × fOSC)··································································································(14)
In the reference example, CC2 is used as the noise filter for the COMP pin because of being higher than fOSC/2.
CC2 = 49 ≒ 47 pF
■ Calculation of CSPD
C
SPD sets the zero frequency to meet the unity-gain frequency.
RTOP = RBOT × (VOUT / VREF -1)
CSPD = 1 / (2 ×π× fUNITY × RTOP)····························································································(15)
When RBOT = 22 kΩ,
RTOP = 22 k × (3.3 V / 0.64 V -1)
= 91.4 kΩ
CSPD = 1 / (2 ×π× 70 kHz × 91.4 kΩ)
= 24.8 ≒ 27 pF
28
R1272S
NO.EA-351-151001
Cautions in Selecting External Components
Inductor
● Choose an inductor that has small DC resistance, has sufficient allowable current and is hard to cause
magnetic saturation. The inductance value must be determined with consideration of load current under the
actual condition. If the inductance value of an inductor is extremely small, the peak current of LX may
increase along with the load current. As a result, the current limit circuit may start to operate when the peak
current of LX reaches to “LX limit current”.
Capacitor
● Choose a capacitor that has a sufficient margin to the drive voltage ratings with consideration of the DC
bias characteristics and the temperature characteristics.
● The combined use of a ceramic capacitor and an electrolyte capacitor is recommended though CIN is able
to connect a ceramic capacitor. Especially, choose the electrolyte capacitor with the lowest possible ESR
with consideration of the allowable ripple current rating (IRMS). IRMS can be calculated by the following
equation.
IRMS ≒ IOUT/ VIN x √{ VOUT x (VIN – VOUT) }
FET
● Gate – Source Voltage
When considering variations in production and margin, a FET with a withstand voltage of 10 V or more is
recommended despite the 5 V high and low driver.
● Gate Threshold Voltage
Choose a FET with the threshold voltage between 1.0 V (Min.) and 3.4 V (Max.) with consideration of
variations in production and margin.
● Drain Current
Choose a FET having a sufficient margin with consideration of peak current and limit current.
● Connection of Body Diode for Source Current
Choose a diode with the withstand current over the reverse limit current rating. The R1272S reverse current
value becomes one-half of the normal limit current value.
● On-resistance (RDS (on)) & All Gate Capacitance (Qg)
Choose a FET with the lowest possible characteristics because having an influence on efficiency. Generally,
a high-performance FET is rated that RDS x Qq (performance figure) is small.
● FET Losses
The FET total loss is calculated by the sum of the switching losses when the high side and the low side
FETs turning-on / off and the conduction losses by the FET’s on-resistance. If the total loss become larger
than expected, the external FET must be selected with consideration of the on-resistance, the switching
losses and the package’s power dissipation. The following figure shows the timing chart of the high side /
low side FETs at normal switching. The loss at each delay time can be calculated as follows.
29
R1272S
NO.EA-351-151001
VCC
VSP
HS-FET
VGS
VTH
VIN
LX
LS-FET VDS
(RONL × IOUT
)
VF (Body Diode)
VCC
LS-FET
VGS
VSP
VTH
time
t6
t1
t2
t3
t4
t5
t6
DCDC Converter Basic Switching Timing Chart
t1 (t5):
For the duration between the high side FET’s turn-on and the low side FET’s turn-off, the loss occurs to
supply a current from the body diode on the low side FET. Likewise, for the duration between the high side
FET’s turn-off and the low side FET’s turn-on, the loss occurs. The losses (PDEAD) for t1 and t5 can be
calculated by the following equation.
PDEAD = VF × IOUT × fOSC × (tDEAD1 + tDEAD5
)
VF: The forward voltage of a body-diode
t
DEAD1: The delay time from the instant when the gate-source voltage (VGS) falls below the threshold voltage
(VTH) on the low side FET to the instant when VGS exceeds VTH on the high side FET.
tDEAD5: The delay time from the instant when VGS falls below VTH on the high side FET to the instant when
VGS exceeds VTH on the low side FET.
t2 (t4):
Since the drain-source voltage (VDS) is equal to VIN when the high side FET turns on/off after delay time
(tDEAD1 / tDEAD5), the source current and the output current (IOUT) become equal. Therefore, a large loss
occurs. The losses (PSW) at turn-on / off can be calculated by the following equation.
PSW = 1/2 × VIN × IOUT × fOSC × (tRISE + tFALL)
30
R1272S
NO.EA-351-151001
tRISE: A duration between the gate voltage rising start time from the threshold voltage and the end of
stabilized voltage (VSP) on the high side FET.
tFALL: A duration between the start time of the gate voltage stabilizing and the falling time below the threshold
voltage on the high side FET.
For the stabilized duration, VGS of the high side FET remains constant roughly since the gate charge current
is used to charge CGD. And, the reverse recovery loss (PRR) occurs to recover the body diode of the low
side FET when the high side FET turns on. Refer to the FET datasheet for information about the electric
charge (Qrr) required for recovery.
PRR = VIN × Qrr × fOSC
And, the power (PGH, PGL) for electric charge of the FET’ gate and the power (POSSH, POSSL) for electric
charge of the FET’s output capacity occur. Each power can be calculated by following equations. Refer to
the FET datasheet for detailed values.
P
P
P
P
GH = QGH × VCC × fOSC
GL = QGL × VCC × fOSC
OSSH = 1/2 × COSSH × (VIN)2 × fOSC
OSSL = 1/2 × COSSL × (VIN)2 × fOSC
VCC: VCC pin voltage
QGH, QGL: Gate electric charge quantity for High- /Low- side FETs
C
OSSH, COSSL: Drain-gate capacity + Drain-source capacity for High- /Low- side FETs
t3 (t6):
For the duration of t3, the conduction loss of the high side FET (PHS(on)) occurs. For the duration of t6, the
conduction loss of the low side FET (PLS(on)) occurs. Each loss can be calculated by the following equation.
ON duty is closely analogous to VIN / VOUT
.
I
RMS = √ (((IOUT)2 + (IP-P)2 / 12))
P
P
HS (on) = (IRMS)2 × RONH × VOUT / VIN
LS (on) =(IRMS)2 × RONL × (1-VOUT / VIN)
IRMS: FET’s rms current
IP-P: FET’s peak current amplitude
R
ONH, RONL: On-resistance for High- /Low- side FETs
31
R1272S
NO.EA-351-151001
Since the conduction loss depends on the duty, the loss varies with step-down ratio. When the step-down
ratio is large and the ON duty is small, the loss of the low side FET becomes larger, and when the ratio is
small, the loss of the high side FET becomes larger. From above equations, each loss of the high side and
the low side FETs can be calculated by the following equations.
P
HS = PHS (on) + PSW + PRR + PGH + POSSH
LS = PLS (on) + PGL + POSSL + PDEAD
P
As is evident from these equations, the switching loss becomes predominant when the input voltage and
the frequency are high, and the conduction loss conversely becomes predominant when they are low.
32
R1272S
NO.EA-351-151001
TECHNICAL NOTES
The performance of power source circuits using this IC largely depends on peripheral circuits. When selecting
the peripheral components, please consider the conditions of use. Do not allow each component, PCB pattern
or the IC to exceed their respected rated values (voltage, current, and power) when designing the peripheral
circuits.
● External components must be connected as close as possible to the ICs and make wiring as short as
possible. Especially, the capacitor connected in between VIN pin and GND pin must be wiring the shortest.
If their impedance is high, internal voltage of the IC may shift by the switching current, and the operating
may be unstable. Make the power supply and GND lines sufficient.
●
●
●
●
Place a capacitor (COUT) to keep a distance between CIN and COUT in order to avoid the high-
frequency noise by input.
AGND and PGND for the controller must be wired to the GND line at the low impedance point of the same
layer with CIN and COUT
.
Place a capacitor (CBST) as close as possible to the LX pin and the BST pin. If controlling slew rate
for EMI, a land pattern to add a resistor (RBST) in series to CBST must be provided.
The tab on the bottom of the HSOP-18 package must be connected to GND when mounted on the
board. To improve thermal dissipation on the multilayer board, set via to release the heat to the other
layer in the connecting part of the tab on the bottom. Likewise, thermal dissipation for FET is required.
●
●
The NC pin must be set to “Open”.
The MODE pin requires the H / L voltages with the high stability when the forced PWM mode (MODE =
“H”) or the VFM mode (MODE = “L”) is enabled. If the voltage with the high stability cannot be applied,
connection to the VCC pin as “H” level or the AGND pin as “L” level is recommended. If connecting to the
PGND pin as noisy, a malfunction may occur. Avoid the use of the MODE pin being “Open”.
●
●
If VOUT is a minus potential, the setup cannot occur.
The power for the controller and for the high-side FET must be used on the same power supply, since the
internal slope compensation is applied as the power supply voltage of the high-side FET is equal to the
controller’s. If applying the other power supply voltage, the controller will become unstable owing to the
inappropriate slope compensation.
33
R1272S
NO.EA-351-151001
TYPICAL CHARACTERISTICS
Typical Characteristics are intended to be used as reference data, they are not guaranteed.
1) FB Voltage vs. Temperature
2) Oscillation Frequency vs. Temperature
250kHz (RT = 135 kΩ)
600 kHz (RT = 55 kΩ)
3) Soft-start time 1 vs. Temperature
Fixed soft-start time
(CSS = Open)
Adjustable soft-start time
(CSS = 4.7 nF)
34
R1272S
NO.EA-351-151001
4) Current limit threshold voltage vs. Temperature
Current limit threshold voltage
(R1272Sxx2x)
Overcurrent limit threshold voltage
(R1272Sxx2x)
5) LX GND/VIN short threshold voltage vs. Temperature
LX GND short threshold voltage
(VIN-LX)
LX VIN short threshold voltage
(LX-PGND)
6) Current consumption vs. Temperature
Current consumption (VFM)
(VIN = 12 V)
Current consumption (PWM)
(VIN = 12 V)
35
R1272S
NO.EA-351-151001
7) UVLO vs. Temperature
UVLO release voltage
UVLO threshold voltage
8) CE input voltage vs. Temperature
CE "H" input voltage
CE "L" input voltage
9) Output current vs. Efficiency
VOUT = 1.5 V
VOUT = 1.5 V
fOSC = 250 kHz / VIN = 8 V / 12 V / 16 V
fOSC = 500 kHz / VIN = 8 V / 12 V / 16 V
36
R1272S
NO.EA-351-151001
VOUT = 3.3 V
VOUT = 3.3 V
fOSC = 250 kHz, VIN = 8 V / 12 V / 16 V
fOSC = 500 kHz, VIN = 8 V / 12 V / 16 V
VOUT = 5.0 V
VOUT = 5.0 V
fOSC = 250 kHz / VIN = 8 V / 12 V / 16 V
fOSC = 500 kHz / VIN = 8 V / 12 V / 16 V
10) Load transient response
VIN = 12 V, VOUT = 3.3 V
VIN = 12 V, VOUT = 3.3 V
fOSC=500kHz, MODE=L VFM/PWM auto-switching fOSC=500 kHz, MODE=L VFM/PWM auto-switching
37
R1272S
NO.EA-351-151001
VIN = 12 V, VOUT = 3.3 V
Vin = 12V, VOUT = 3.3V
fOSC = 500 kHz, MODE = H Forced PWM
fOSC = 500 kHz, MODE = H Forced PWM
11) Output voltage vs. Output current
VOUT = 3.3V
VOUT = 3.3 V
fOSC = 250 kHz, VIN = 12 V
fOSC = 500 kHz, VIN = 12 V
12) Input transient response
VOUT = 3.3 V
VOUT = 3.3 V
fOSC=500kHz, MODE=L VFM/PWM auto-switching fOSC=500kHz, MODE=L VFM/PWM auto-switching
IOUT = 0.1 A VFM mode IOUT = 0.1 A VFM mode
38
R1272S
NO.EA-351-151001
VOUT = 3.3 V
VOUT = 3.3 V
fOSC=500kHz, MODE=H VFM/PWM auto-switching fOSC=500kHz, MODE=H VFM/PWM auto-switching
IOUT = 5 A PWM mode
IOUT = 5 A PWM mode
13) Input voltage vs. Output voltage
VOUT = 3.3 V
VOUT = 3.3 V
fOSC=500kHz, MODE= L VFM/PWM auto-switching fOSC=500kHz, MODE=H Forced PWM
14) Up-down tracking
15) Load dump
VOUT = 3.3 V
VIN = 12 V、VOUT = 3.3 V
fOSC = 500 kHz, MODE = H Forced PWM
fOSC = 500 kHz, MODE = H Forced PWM
39
R1272S
NO.EA-351-151001
16) Line regulation
VOUT = 5.0 V
fOSC = 500 kHz, MODE = H Forced PWM
Line regulation UVLO release expanding
VOUT = 5.0 V
Line regulation UVLO detection expanding
VOUT = 5.0 V
fOSC = 500 kHz, MODE = H Forced PWM
fOSC = 500 kHz, MODE = H Forced PWM
40
POWER DISSIPATION
HSOP-18
Ver. A
Power Dissipation (PD) depends on conditions of mounting on board. This specification is based on the
measurement at the condition below:
Measurement Conditions
JEDEC STD.51-7 Test Land Pattern
Environment
Board Material
Mounting on Board (Wind velocity=0m/s)
Glass cloth epoxy plastic (4 layers)
76.2 mm x 114.3 mm x 1.6 mm
Board Dimensions
Top side, Back side (60 mm square) : Approx.10%
2nd, 3rd Layer (74.2 mm square): Approx. 100%
φ 0.85 mm x 44 pcs
Copper Ratio
Through-holes
Measurement Result
(Ta = 25°C, Tjmax = 125°C)
JEDEC STD.51-7 Test Land Pattern
2500 mW
Power Dissipation
θja =(125-25°C)/2.5W = 40°C/W
θjc = 9°C/W
Thermal Resistance
76.2
60
3500
3000
2500
2500
JEDEC STD.51-7
TEST Land Pattern
2000
1500
1000
500
0
105
0
25
50
75
100
125
Ambient Temperature (°C)
IC Mount Area (Unit: mm)
Measurement Board Pattern
Power Dissipation (mW) vs. Temperature (°C)
i
PACKAGE DIMENSIONS
HSOP-18
Ver. A
2.90±0.05
(0.30)
18
10
＊
1
9
0.50
0.20±0.1
0.60TYP
M
0.12
5.20±0.3
DETAIL
A
0.40±0.2
0.10 S
S
DETAIL
A
(Unit : mm)
∗) The tab on the bottom of the package enhances thermal
performance and is electrically connected to GND
(substrate level). It is recommended that the tab be
connected to the ground plane on the board, or otherwise
be left floating.
HSOP-18 Package Dimensions
i
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discontinuation of production without notice for reasons such as improvement. Therefore, before
deciding to use the products, please refer to Ricoh sales representatives for the latest information
thereon.
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4.The technical information described in this document shows typical characteristics of and example
application circuits for the products. The release of such information is not to be construed as a
warranty of or a grant of license under Ricoh's or any third party's intellectual property rights or any
other rights.
5.The products listed in this document are intended and designed for use as general electronic
components in standard applications (office equipment, telecommunication equipment, measuring
instruments, consumer electronic products, amusement equipment etc.). Those customers intending to
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the products or the technical information.
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Ricoh has been providing RoHS compliant products since April 1, 2006 and Halogen-free products since
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April 1, 2012.
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