74AC11373DBR [ROCHESTER]
AC SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO24, PLASTIC, SSOP-24;
| 型号： | 74AC11373DBR |
| 厂家： | 
Rochester Electronics |
| 描述： | AC SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO24, PLASTIC, SSOP-24 驱动 光电二极管 输出元件 逻辑集成电路 |
| 文件： | 总12页 (文件大小：935K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74AC11373
OCTAL TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCAS213A − MAY 1987 − REVISED APRIL 1996
DB, DW, OR NT PACKAGE
(TOP VIEW)
D
D
D
D
D
Eight Latches in a Single Package
3-State Bus-Driving True Outputs
Full Parallel Access for Loading
Buffered Control Inputs
1Q
2Q
3Q
OE
1D
2D
3D
4D
VCC
1
24
23
22
21
20
19
2
3
Flow-Through Architecture Optimizes
PCB Layout
4Q
4
GND
GND
GND
GND
5Q
5
D
D
D
D
Center-Pin V and GND Configurations
CC
6
Minimize High-Speed Switching Noise
7
18 VCC
EPICt (Enhanced-Performance Implanted
CMOS) 1-mm Process
8
17
16
15
14
13
5D
6D
7D
8D
LE
9
500-mA Typical Latch-Up Immunity at
125°C
Package Options Include Plastic
Small-Outline (DW) and Shrink
Small-Outline (DB) Packages, and Standard
Plastic 300-mil DIPs (NT)
10
11
12
6Q
7Q
8Q
description
This 8-bit latch features 3-state outputs designed specifically for driving highly-capacitive or relatively
low-impedance loads. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus
drivers, and working registers.
The eight latches of the 74AC11373 are transparent D-type latches. While the latch-enable (LE) input is high,
the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up
at the D inputs.
OE can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a
high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly.
The high-impedance third state and increased drive provide the capability to drive bus lines in a bus-organized
system without need for interface or pullup components.
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered
while the outputs are off.
The 74AC11373 is characterized for operation from −40°C to 85°C.
FUNCTION TABLE
(each latch)
INPUTS
OUTPUT
Q
OE
L
LE
H
H
L
D
H
L
H
L
L
L
X
X
Q
0
H
X
Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
Copyright © 1996, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
74AC11373
OCTAL TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCAS213A − MAY 1987 − REVISED APRIL 1996
logic symbol†
24
OE
EN
C1
13
LE
23
1D
22
1
2
1D
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
2D
21
3
3D
20
4
4D
17
9
5D
16
10
11
12
6D
15
7D
14
8D
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
24
OE
13
LE
C1
1
23
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
1D
2D
3D
4D
5D
6D
7D
8D
1D
C1
1D
2
3
22
21
20
17
16
15
14
C1
1D
C1
1D
4
C1
1D
9
C1
1D
10
11
12
C1
1D
C1
1D
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
74AC11373
OCTAL TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCAS213A − MAY 1987 − REVISED APRIL 1996
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V + 0.5 V
I
CC
Output voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V + 0.5 V
O
CC
Input clamp current, I (V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
IK
I
I
CC
Output clamp current, I (V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
OK
O
O
CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
O
O
CC
Continuous current through V or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 mA
CC
Maximum power dissipation at T = 55°C (in still air) (see Note 2): DB package . . . . . . . . . . . . . . . . . . 0.65 W
A
DW package . . . . . . . . . . . . . . . . . . 1.7 W
NT package . . . . . . . . . . . . . . . . . . . 1.3 W
Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150_C and a board trace length of 750 mils,
except for the NT package, which has a trace length of zero.
recommended operating conditions
MIN NOM
MAX
UNIT
V
Supply voltage
3
2.1
5
5.5
V
CC
IH
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 3 V
= 4.5 V
= 5.5 V
= 3 V
3.15
3.85
V
High-level input voltage
V
V
0.9
1.35
1.65
= 4.5 V
= 5.5 V
V
IL
Low-level input voltage
V
V
Input voltage
0
0
V
V
V
I
CC
Output voltage
V
CC
O
V
V
V
V
V
V
= 3 V
−4
CC
CC
CC
CC
CC
CC
= 4.5 V
= 5.5 V
= 3 V
−24
−24
12
24
24
5
I
High-level output current
Low-level output current
mA
mA
OH
= 4.5 V
= 5.5 V
I
OL
OE
Data, LE
0
0
Dt/Dv
Input transition rise or fall rate
Operating free-air temperature
ns/V
10
85
T
−40
°C
A
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
74AC11373
OCTAL TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCAS213A − MAY 1987 − REVISED APRIL 1996
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T = 25°C
A
PARAMETER
TEST CONDITIONS
V
MIN
MAX
UNIT
CC
MIN
2.9
TYP
MAX
3 V
2.9
4.4
4.5 V
5.5 V
3 V
4.4
I
= −50 mA
OH
5.4
5.4
I
I
I
= −4 mA
= −24 mA
= −75 mA
2.58
3.94
4.94
2.48
3.8
OH
OH
OH
V
OH
V
4.5 V
5.5 V
5.5 V
3 V
4.8
{
3.85
0.1
0.1
0.1
0.1
0.1
0.44
0.44
0.44
1.65
5
4.5 V
5.5 V
3 V
I
OL
= 50 mA
0.1
I
OL
I
OL
I
OL
= 12 mA
= 24 mA
0.36
0.36
0.36
V
OL
V
4.5 V
5.5 V
5.5 V
5.5 V
5.5 V
5.5 V
5 V
{
= 75 mA
I
I
I
V
= V or GND
0.5
0.1
8
mA
mA
mA
pF
pF
OZ
O
CC
V = V or GND
1
I
I
CC
V = V or GND,
I = 0
O
80
CC
I
CC
C
C
V = V or GND
4
i
I
CC
V
= V or GND
5 V
10
o
O
CC
†
Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
timing requirements over recommended operating free-air temperature range,
VCC = 3.3 V 0.3 V (unless otherwise noted) (see Figure 1)
T = 25°C
A
MIN
MAX
UNIT
MIN
5.5
4
MAX
t
w
t
su
t
h
Pulse duration, LE high
Setup time, data before LE↓
Hold time, data after LE↓
5.5
4
ns
ns
ns
2
2
timing requirements over recommended operating free-air temperature range,
VCC = 5 V 0.5 V (unless otherwise noted) (see Figure 1)
T = 25°C
A
MIN
MAX
UNIT
MIN
4
MAX
t
w
t
su
t
h
Pulse duration, LE high
Setup time, data before LE↓
Hold time, data after LE↓
4
3.5
2
ns
ns
ns
3.5
2
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
74AC11373
OCTAL TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCAS213A − MAY 1987 − REVISED APRIL 1996
switching characteristics over recommended operating free-air temperature range,
CC = 3.3 V 0.3 V (unless otherwise noted) (see Figure 1)
V
T
A
= 25°C
TYP
9
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
MIN
MAX
UNIT
ns
MIN
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
MAX
13.1
10.6
14.5
12.8
13.1
11.6
12
t
t
t
t
t
t
t
t
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
14.8
11.7
16.3
14.2
14.7
13.1
12.7
10.8
PLH
PHL
PLH
PHL
PZH
PZL
PHZ
PLZ
D
Q
8
10
LE
OE
OE
Any Q
Any Q
Any Q
ns
9.5
9
ns
8.5
9.5
7.5
ns
10.2
switching characteristics over recommended operating free-air temperature range,
VCC = 5 V 0.5 V (unless otherwise noted) (see Figure 1)
T
A
= 25°C
TYP
6
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
MIN
MAX
UNIT
ns
MIN
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
MAX
8.9
7.6
10
t
t
t
t
t
t
t
t
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
10.3
8.4
PLH
PHL
PLH
PHL
PZH
PZL
PHZ
PLZ
D
Q
5.5
6.5
6.5
6.5
6
11.3
10.2
10.8
9.7
LE
OE
OE
Any Q
Any Q
Any Q
ns
9.1
9.5
8.6
10.6
8.2
ns
8.5
6
11.1
8.7
ns
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER
TEST CONDITIONS
f = 1 MHz
TYP
47
UNIT
Outputs enabled
Outputs disabled
C
Power dissipation capacitance per latch
C = 50 pF,
pF
pd
L
36
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
74AC11373
OCTAL TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCAS213A − MAY 1987 − REVISED APRIL 1996
PARAMETER MEASUREMENT INFORMATION
2 × V
CC
S1
500 Ω
Open
GND
From Output
Under Test
TEST
/t
S1
t
t
Open
PLH PHL
t
C = 50 pF
L
/t
2 × V
500 Ω
PLZ PZL
CC
(see Note A)
/t
GND
PHZ PZH
LOAD CIRCUIT
V
CC
Timing Input
(see Note B)
50%
0 V
t
w
t
h
t
V
CC
su
V
CC
Input
50%
50%
50%
50%
Data Input
0 V
0 V
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
Output
Control
(low-level
enabling)
V
V
CC
CC
Input
50%
50%
50%
50%
0 V
0 V
t
PZL
t
t
PHL
PLH
t
PLZ
Output
Waveform 1
V
OH
[ V
CC
In-Phase
Output
50% V
50% V
CC
50% V
50% V
CC
CC
20% V
CC
S1 at 2 × V
CC
V
OL
V
OL
(see Note B)
t
PHZ
t
PLH
t
PHL
t
PZH
Output
Waveform 2
S1 at GND
V
OH
V
OH
Out-of-Phase
Output
80% V
CC
50% V
50% V
CC
CC
CC
[ 0 V
V
OL
(see Note B)
VOLTAGE WAVEFORMS
NOTES: A. C includes probe and jig capacitance.
VOLTAGE WAVEFORMS
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t = 3 ns, t = 3 ns.
O
r
f
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
7-Jun-2010
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
Samples Not Available
Samples Not Available
Samples Not Available
Samples Not Available
Samples Not Available
74AC11373DBLE
74AC11373DBR
74AC11373DW
74AC11373DWR
74AC11373NT
OBSOLETE
OBSOLETE
OBSOLETE
OBSOLETE
OBSOLETE
SSOP
SSOP
SOIC
SOIC
PDIP
DB
DB
DW
DW
NT
24
24
24
24
24
TBD
TBD
TBD
TBD
TBD
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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相关型号：
74AC11373NT
Bus Driver, AC Series, 1-Func, 8-Bit, True Output, CMOS, PDIP24, 0.300 INCH, PLASTIC, DIP-24
ROCHESTER
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