AD9721BR [ROCHESTER]
PARALLEL, WORD INPUT LOADING, 0.0045us SETTLING TIME, 10-BIT DAC, PDSO28, PLASTIC, SOIC-28;
| 型号： | AD9721BR |
| 厂家： | 
Rochester Electronics |
| 描述： | PARALLEL, WORD INPUT LOADING, 0.0045us SETTLING TIME, 10-BIT DAC, PDSO28, PLASTIC, SOIC-28 输入元件 光电二极管 转换器 |
| 文件： | 总9页 (文件大小：851K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
10-Bit, 400 MSPS
D/A Converters
a
AD9720/AD9721
FEATURES
lated bipolar process. T he AD9720 is ECL compatible, and will
update up to 400 MSPS; the AD9721 is T T L compatible and
will update up to 100 MSPS.
400 MSPS (ECL)/ 100 MSPS (TTL) Update Rate
Low Glitch Im pulse: 1.5 pV-s
Fast Settling: 4.5 ns to 1/ 2 LSB
Low Pow er: 1.1 W
On-Board Quadrature Logic for DDS Applications
Differential Clock (ECL)
Designed for direct digital synthesis (DDS), waveform recon-
struction, and high resolution video applications, both devices
feature low glitch impulse of 1.5 pV-s and fast settling times of
4.5 ns to 1/2 LSB.
APPLICATIONS
Both converters are characterized for dynamic performance, and
have excellent harmonic suppression and spectral purity in
waveform generation applications.
Direct Digital Synthesis
Arbitrary Waveform Synthesis
Waveform Reconstruction
High Speed Im aging
T he units are available in 28-pin DIPs, LCCs and SOICs.
Industrial temperature range devices are packaged in plastic for
operation from –25°C to +25°C; extended temperature range
devices for operation from –55°C to +125°C are in hermetic
ceramic packages. Contact the factory for information about the
availability of MIL-ST D-883 devices.
GENERAL D ESCRIP TIO N
T he AD9720 and AD9721 D/A converters are 10-bit, high
speed digital-to-analog converters constructed in an oxide iso-
FUNCTIO NAL BLO CK D IAGRAM
ANALOG
RETURN
D
D
1
I
OUT
2
10
TTL
OR
I
OUT
ECL
DRIVE
LOGIC
D
10
INVERT
CLOCK
CLOCK
REFERENCE
IN
+
0.1µF
CONTROL
AMP
CONTROL
AMP OUT
INTERNAL
VOLTAGE
–
REFERENCE
R
SET
REFERENCE
OUT
CONTROL
AMP IN
DIGITAL
–V
DIGITAL
+V
ANALOG
–V
S
S
S
BYP.
BYP.
BYP.
–5.2V
+5V
–5.2V
REV. A
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.
Tel: 617/ 329-4700 Fax: 617/ 326-8703
AD9720/AD9721–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (R–V = –5.2 V; +V = +5 V (AD9721 only); Reference Voltage = –1.25 V;
S
S
SET = 1,960 ⍀, unless otherwise noted)
Test
AD 9720BN/BR
AD 9720TE/TQ
AD 9721BN/BR
AD 9721TE/TQ
Min Typ Max Units
P aram eter (Conditions)
Tem p Level Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
RESOLUT ION
10
10
10
10
Bits
DC ACCURACY
Differential Nonlinearity
+25°C
Full
+25°C
Full
I
VI
I
0.25
0.5
0 75
1.0
1.0
0.6
0.7
1.0
1.5
1.5
2.0
0.25
0.5
0.75
1.0
1.0
0.6
0.7
1.0
1.5
1.5
2.0
LSB
LSB
LSB
LSB
Integral Nonlinearity
(“Best Fit” Straight Line)
VI
1.5
1.5
INIT IAL OFFSET ERROR
Zero-Scale Offset Error
+25°C
Full
+25°C
Full
I
VI
I
VI
V
16
20
2
60
75
15
15
16
20
2
60
75
15
15
16
20
2
60
75
15
15
16
20
2
60
75
15
15
µA
µA
%
%
µA/°C
Full-Scale Gain Error1
Offset Drift Coefficient
+25°C
0.04
0.04
0.04
0.04
REFERENCE/CONT ROL AMP
Internal Reference Voltage
+25°C
Full
Full
Full
+25°C
+25°C
I
–1.15 –1.25 –1.35 –1.15 –1.25
–1.35 –1.15 –1.25 –1.35 –1.15 –1.25 –1.35
V
V
µV/°C
VI
V
IV
V
V
–1.15
–1.35 –1.15
–1.35 –1.15
–1.35 –1.15
–1.35
Internal Reference Voltage Drift
Internal Reference Output Current
Amplifier Input Impedance
Amplifier Bandwidth
100
100
100
100
–50
+500 –50
+500
–50
+500 –50
+500 µA
kΩ
50
1
50
1
50
1
50
1
MHz
REFERENCE INPUT 2
Reference Input Impedance
+25°C
+25°C
V
V
4.6
75
4.6
75
4.6
75
4.6
75
kΩ
MHz
Reference Multiplying Bandwidth3
OUT PUT PERFORMANCE
Full-Scale Output Current2, 4
Output Compliance Range
Output Resistance
+25°C
+25°C IV
V
20.48
20.48
20.48
20.48
mA
V
Ω
pF
MSPS
ns
–1.5
+3
–1.5
+3
–1.5
+3
–1.5
+3
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
V
V
V
V
V
V
V
V
V
210
6
400
4.5
4.0
1.5
1,000
675
470
210
6
400
4.5
4.0
1.5
1,000
675
470
210
6
100
4.5
4.5
1.5
1,000
675
470
210
6
100
4.5
4.5
1.5
1,000
675
470
Output Capacitance
Output Update Rate
Voltage Settling T ime (1/2 LSB)5
6
Propagation Delay (tPD
)
ns
Glitch Impulse7
pV-s
V/µs
ps
Output Slew Rate8
Output Rise T ime8
Output Fall T ime8
ps
DIGIT AL INPUT S
Logic “1” Voltage
Logic “0” Voltage
Logic “1” Current
Logic “0” Current
Input Capacitance
Input Setup T ime (tS)9
Full
Full
Full
Full
VI
VI
VI
VI
V
–1.0
–0.9
2.0
2.0
V
V
–1.5
50
2
–1.6
50
2
0.8
400
700
0.8
400
700
µA
µA
pF
ns
ns
ns
ns
ns
ns
+25°C
3
0.4
3
0.4
3
0.5
3
0.5
+25°C IV
Full IV
+25°C IV
Full IV
+25°C IV
+25°C IV
1.0
1.2
1.6
2.8
1.1
1.4
1.0
1.2
1.6
2.8
1.1
1.4
1.0
1.2
2.0
2.3
1.0
1.1
1.0
1.2
2.0
2.3
1.0
1.1
10
Input Hold T ime (tH
)
1.2
1.2
1.25
1.25
Clock Pulse Width (Low)
Clock Pulse Width (High)
0.85
0.85
0.85
0.85
0.85
0.85
0.85
0.85
DYNAMIC PERFORMANCE
Spurious-Free Dynamic Range (SFDR)11
2.02 MHz; 100 MSPS; 2 MHz Span
25.01 MHz; 100 MSPS; 2 MHz Span
10.02 MHz; 250 MSPS; 5 MHz Span
62.54 MHz; 250 MSPS; 5 MHz Span
70 MHz; 220 MSPS; 10 MHz Span
+25°C
+25°C
+25°C
+25°C
+25°C
V
V
V
V
V
75
66
70
55
70
75
66
70
55
70
75
66
N/A
N/A
N/A
75
66
N/A
N/A
N/A
dBc
dBc
dBc
dBc
dBc
POWER SUPPLY12
Negative Supply Current (–5.2 V)13
+25°C
Full
+25°C
Full
I
VI
I
VI
V
V
210
280
290
210
280
290
218
14
290
300
30
218 290
300
mA
mA
mA
mA
W
Positive Supply Current (+5.0 V)
Nominal Power Dissipation
N/A
N/A
1.1
N/A
N/A
1.1
14
30
30
30
+25°C
1.2
50
1.2
50
Power Supply Rejection Ratio (PSRR)14 +25°C
50
50
µA/V
–2–
REV. A
AD9720/AD9721
NOT ES
11Measured as error in ratio of full-scale current to current through R SET (640 µA nominal); ratio is nominally 32. DAC load is virtual ground.
12Full-scale current variations among devices are higher when driving REFERENCE IN directly.
13Frequency at which a 3 dB change in output of DAC is observed, R L = 50 Ω; 100 mV modulation at midscale.
14Based on IFS = 32 (CONT ROL AMP IN/RSET) when using internal control amplifier. DAC load is virtual ground.
15Measured as voltage settling at midscale transition to ±0.1%; RL = 50 Ω.
16Measured from 50% point of rising edge of CLOCK signal to 1/2 LSB change in output signal.
17Peak glitch impulse is measured as the largest area under a single positive or negative transient.
18Measured with RL = 50 Ω and DAC operating in latched mode.
19Data must remain stable for specified time prior to rising edge of CLOCK.
10Data must remain stable for specified time after rising edge of CLOCK.
11SFDR is defined as the difference in signal energy between the fundamental and worst case spurious frequencies in the output spectrum window, which is centered at
the fundamental frequency and covers the indicated span.
12Supply voltages should remain stable within ±5% for normal operation.
13190 mA typ on Digital –VS, 30 mA typ on Analog –VS.
14Measured at ±5% of +VS (AD9721 only) and –VS (AD9720 or AD9721) using external reference.
Specifications subject to change without notice.
ABSO LUTE MAXIMUM RATINGS1
EXP LANATIO N O F TEST LEVELS
Positive Supply Voltage (+VS) (AD9721 Only) . . . . . . . . +6 V
T est Level
Negative Supply Voltage (–VS)
I
– 100% production tested.
(AD9720 and AD9721) . . . . . . . . . . . . . . . . . . . . . . . . –7 V
Digital Input Voltages (D1–D10, CLOCK, CLOCK)
AD9720 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to –VS
AD9721 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to +VS
Internal Reference Output Current . . . . . . . . . . . . . . . 500 µA
Control Amplifier Input Voltage Range . . . . . . . . . 0 V to –4 V
Control Amplifier Output Current . . . . . . . . . . . . . . . ±2.5 mA
Reference Input Voltage Range (VREF) . . . . . . . . . . . 0 V to –VS
Analog Output Current . . . . . . . . . . . . . . . . . . . . . . . . 30 mA
Operating T emperature Range
II – 100% production tested at +25°C, and sample tested at
specified temperatures.
III – Sample tested only.
IV – Parameter is guaranteed by design and characterization
testing.
V
– Parameter is a typical value only.
VI – All devices are 100% tested at +25°C. 100% production
tested at temperature extremes for extended temperature
devices; sample tested at temperature extremes for com-
mercial/industrial devices.
AD9720/AD9721BN/BR . . . . . . . . . . . . . . –25°C to +85°C
AD9720/AD9721T E/T Q . . . . . . . . . . . . . –55°C to +125°C
Maximum Junction T emperature2
AD9720/AD9721BN/BR . . . . . . . . . . . . . . . . . . . . +150°C
AD9720/AD9721T E/T Q . . . . . . . . . . . . . . . . . . . . +175°C
Lead T emperature (Soldering, 10 sec) . . . . . . . . . . . . +300°C
Storage T emperature Range . . . . . . . . . . . . –65°C to +150°C
D IE LAYO UT AND MECH ANICAL INFO RMATIO N
Die Dimensions . . . . . . . . . . . . . . . 199 ϫ 165 ϫ 15 (±2) mils
Pad Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ϫ 4 mils
Metalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Aluminum
Backing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . None
Substrate Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –VS
Passivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Nitride
NOT ES
1Absolute maximum ratings are limiting values to be applied individually, and
beyond which the serviceability of the circuit may be impaired. Functional
operability is not necessarily implied. Exposure to absolute maximum rating
conditions for an extended period of time may affect device reliability.
2T ypical thermal impedances:
28-pin plastic DIP: θJA = 37°C/W, θJC = 10°C/W;
28-pin LCC:
28-pin SOIC:
Cerdip:
θJA = 41°C/W, θJC = 13°C/W;
θJA = 46°C/W, θJC = 10°C/W;
θJA = 35°C/W, θJC = 10°C/W.
Soldered to board; no air flow.
O RD ERING GUID E
Tem perature
Range
P ackage
D escription
P ackage
O ption
Model
AD9720BN
AD9720BR
AD9720T E
AD9720T Q
–25°C to +85°C
–25°C to +85°C
–55°C to +125°C
–55°C to +125°C
28-Pin Plastic DIP
28-Pin SOIC
28-Pin LCC
N-28
R-28
E-28A
Q-28
28-Pin Cerdip
AD9721BN
AD9721BR
AD9721T E
AD9721T Q
–25°C to +85°C
–25°C to +85°C
–55°C to +125°C
–55°C to +125°C
28-Pin Plastic DIP
28-Pin SOIC
28-Pin LCC
N-28
R-28
E-28A
Q-28
28-Pin Cerdip
REV. A
–3–
AD9720/AD9721
P IN D ESCRIP TIO NS
D IP
P in # Nam e
Function
1
D1 (MSB)
D2–D9
Most Significant Bit (MSB) of digital input word.
2-9
Eight of 10 digital input bits. Digital inputs are 10K ECL compatible for AD9720; T T L compatible
for AD9721. See coding table elsewhere.
10
D10 (LSB)
Least Significant Bit (LSB) of digital input word.
Input Coding vs. Current O utput
IOUT
Input Code D1–D10 IOUT (mA)
(mA)
1111111111
0000000000
–20.48
0
0
–20.48
11
CLOCK
Edge-triggered latch enable signal for on-board registers. 10K ECL compatible for AD9720. T T L
compatible for AD9721. Register loads data on rising edge of CLOCK signal; must be driven in con-
junction with CLOCK.
12
13
CLOCK/NC
Complementary edge-triggered latch enable signal for on-board registers. 10K ECL compatible for
AD9720; not connected (NC) for AD9721.
INVERT
Normally connected to logic LOW; inverters are transparent in this mode. Logic High inverts the 9
LSBs (D2–D10) when the MSB is LOW. No internal pull-down resistor.
14
15
16
17
DIGIT AL –VS/+VS
GROUND
One of three digital supply pins; nominally –5.2 V for AD9720; +5 V for AD9721.
Converter ground return.
DIGIT AL –VS
RSET
One of three negative digital supply pins; nominally –5.2 V.
Connection for external resistance reference; nominally 1,960 Ω. Full-scale current out = 32 ϫ
(CONT ROL AMP IN/RSET) when using internal amplifier. DAC load is virtual ground.
18
19
GROUND
Converter ground return.
ANALOG RET URN
Analog current return. T his point and the reference side of the DAC load resistors should be con-
nected to the same potential (nominally ground).
20
IOUT
Analog current output; full-scale output occurs with digital inputs at all “1.” With external load resis-
tor, output voltage IOUT ϫ (RLOAD || RINT ERNAL). RINT ERNAL is nominally 210 Ω.
21
22
23
IOUT
Complementary analog current output; zero-scale output occurs with digital inputs at all “1.”
Negative analog supply; nominally –5.2 V.
ANALOG –VS
REFERENCE IN
Normally connected to CONT ROL AMP OUT (Pin 24). Direct line to DAC current source network.
Voltage changes (noise) at this point have a direct effect on the full-scale output current of DAC.
Full-scale current output = 32 ϫ (CONT ROL AMP IN/RSET ) when using internal amplifier. DAC
load is virtual ground.
24
CONT ROL AMP OUT Normally connected to REFERENCE INPUT (Pin 23). Output of internal control amplifier, which
provides a reference for the current switch network.
25
26
27
28
REFERENCE OUT
CONT ROL AMP IN
DIGIT AL –VS
Normally connected to CONT ROL AMP IN (Pin 26). Internal voltage reference, nominally –1.25 V.
Normally connected to REFERENCE OUT (Pin 25) if not connected to external reference.
One of three negative digital supply pins; nominally –5.2 V.
GROUND
Converter ground return.
P IN CO NFIGURATIO NS
D IP & SO IC P ackages
LCC P ackage
D
(MSB)
1
2
3
4
5
6
GROUND
28
27
26
25
1
DIGITAL –V
D
2
S
D
3
CONTROL AMP IN
REFERENCE OUT
4
3
2
1
28 27 26
D
4
5
D
D
25 REFERENCE OUT
AD9720/
AD9721
5
D
5
24 CONTROL AMP OUT
24
23
22
21
20
6
7
8
9
CONTROL AMP OUT
REFERENCE IN
6
D
6
23
22
21
20
19
18
17
REFERENCE IN
AD9720/AD9721
LCC
D
7
8
9
DIP
ANALOG –V
S
D
7
7
8
9
D
D
ANALOG –V
S
TOP VIEW
(Not to Scale)
D
8
I
OUT
TOP VIEW
(Not to Scale)
I
OUT
D
9
I
OUT
10
11
D
(LSB)
I
10
OUT
ANALOG RETURN
GROUND
D
(LSB) 10
10
ANALOG RETURN
CLOCK
19
CLOCK 11
12 13 14 15 16 17 18
R
12
CLOCK (NC)
SET
INVERT 13
DIGITAL –V (+V
14
16 DIGITAL –V
S
)
S
15
GROUND
S
REV. A
–4–
AD9720/AD9721
CLOCK
CLOCK
CLOCK
CLOCK
ERROR
BAND
tS tH
OUTPUT
ERROR
DATA INPUTS
CODE 1
VALID DATA
CODE 2
VALID DATA
D
– D
10
1
tPD
tST
CODE 2
tS
–
–
INPUT SETUP TIME
INPUT HOLD TIME
tPD
OUTPUT
CODE 1
tH
tST
–
OUTPUT SETTLING TIME
–
OUTPUT PROPAGATION DELAY
tPD
AD9720/AD9721 Tim ing Diagram
TH EO RY AND AP P LICATIO NS
When using the internal reference, REFERENCE OUT (Pin
25) should be connected to CONT ROL AMP IN (Pin 26).
CONT ROL AMP OUT (Pin 24) should be connected to REF-
ERENCE IN (Pin 23). A 0.1 µF ceramic capacitor from Pin 23
to ANALOG –VS (Pin 22) improves settling by decoupling
switching noise from the current sink base line. A reference
current cell provides feedback to the control amp by sinking
current through RSET (Pin 17).
T he AD9720/AD9721 high speed digital-to-analog converters
utilize Most Significant Bit (MSB) decoding and segmentation
techniques to reduce glitch impulse and maintain 10-bit linear-
ity without trimming.
As shown in the functional block diagram, the design is based
on four main subsections: the Decoder/Driver circuits, the Edge
T riggered Data Register, the Switch Network, and the Control
Amplifier. An internal bandgap reference is also included to al-
low operation with a minimum of external components. T he
block labeled “Inverters” is transparent in normal operation, but
can be used to minimize the external components requirements
in DDS applications using the AD9950, a 300 MSPS phase ac-
cumulator (see AD9950 data sheet).
Full-scale output current is determined by CONT ROL AMP IN
and RSET according to the equation:
IOUT (FS) = (CONTROL AMP IN/RSET) ϫ 32
T he internal reference is nominally –1.25 V with a tolerance of
±8% and typical drift over temperature of 100 ppm/°C. If
greater accuracy or better temperature stability is required, an
external reference can be utilized. T he AD589 reference features
±10 ppm/°C drift over temperatures from 0°C to +70°C.
D igital Inputs/Tim ing
T he AD9720 employs single-ended ECL-compatible inputs for
data inputs D1–D10 and the differential clock signals CLOCK
and CLOCK. T he internal ECL midpoint reference is designed
to match 10K ECL device thresholds. On the AD9721, a T T L
translator is added at each input and the clock becomes single
ended; with these exceptions, the AD9720 and AD9721 are
identical. (NOT E: Pin 14 is +VS on AD9721; –VS on AD9720.)
T wo modes of multiplying operation are possible with the
AD9720/AD9721. Signals with bandwidths up to 1 MHz and
input swings from –0.6 V to –1.2 V can be applied to the CON-
T ROL AMP input as shown in Figure 1. Because the control
amplifier is internally compensated, the 0.1 µF capacitor dis-
cussed above can be reduced to maximize the multiplying band-
width. However, it should be noted that settling time for
changes to the digital inputs will be degraded.
In the Decoder/Driver section, the four MSBs (D1–D4) are de-
coded to 15 “thermometer code” lines. An equalizing delay is
included for the six Least Significant Bits (LSBs) and the clock
signals. T his delay minimizes data skew and data setup and hold
times at the register inputs.
AD9720/AD9721
R
SET
T he on-board register is rising-edge-triggered and should be
used to synchronize data to the current switches by applying a
pulse with proper data set-up and hold times as shown in the
timing diagram.
R
17
26
SET
CONTROL
AMP IN
–0.6V TO –1.2V
400 kHz MAX
Although the AD9720/AD9721 chip is designed to provide iso-
lation from digital inputs to the outputs, some coupling of digi-
tal transitions is inevitable, especially with T T L or CMOS
inputs applied to the AD9721. Digital feedthrough can be re-
duced by forming a low-pass filter using a resistor in series with
the capacitance of each digital input; this rolls off the slew rate
of the digital inputs.
R
T
CONTROL
AMP OUT
24
23
REFERENCE
IN
Refer ences
0.1µF
ANALOG – V
As shown in the functional block diagram, the internal band-gap
reference, control amplifier, and reference input are pinned out
for maximum user flexibility when setting the reference.
S
Figure 1. Low Frequency Multiplying Circuit
REV. A
–5–
AD9720/AD9721
10k
T he REFERENCE IN pin can also be driven directly for wider
bandwidth multiplying operation. T he analog signal for this
mode of operation must have a signal swing in the range of
–3.3 V to –4.25 V. T his can be implemented by capacitively
coupling into REFERENCE IN a signal with a dc bias of –3.3 V
(IOUT ~ 22.5 mA) to –4.25 V (IOUT ~ 3 mA), as shown in Figure
2, or by driving REFERENCE IN with a low impedance op
amp whose signal swing is limited to the stated range.
+
10k
1/2
–
AD708
–
200
1/2
AD708
R
1
+
100
IOS
R
2
25
26
400
RFB
REF CONTROL
OUT
AMP IN
IOUT
IFS
25
AD9720/AD9721
20
21
–
VOUT
RFF
AD9617
+
AD9720/
AD9721
25
RL
±2.048 V
REFERENCE
IN
IOUT
23
–3.8V
—
Figure 3. I/V Conversion Using Current Feedback Am p
–V
S
–V
S
D D S Applications
T he performance characteristics of the AD9720/AD9721 make
it ideally suited for direct digital synthesis (DDS) and other
waveform generation applications. Since the aliased distortion of
the DAC collects around the fundamental when generating fre-
quencies which are nearly integer fractions of the clock rate,
these are often considered worst case conditions.
Figure 2. Wideband Multiplying Circuit
O utputs
T he Switch Network provides complementary current outputs
IOUT
IOUT and
statistical current source matching which provides 10-bit linear-
IOUT
. T he design of the AD9720/AD9721 is based on
Please contact the factory for information concerning the avail-
ability of an evaluation board or for additional characterization
data.
ity without trim. Current is steered to either IOUT or
in
proportion to the digital input code. T he sum of the two cur-
rents is always equal to the full-scale output current minus one
LSB.
SETTLING TIME ≈ 4.5ns
NET GLITCH = 1.34pV-s
PEAK GLITCH = 1.36pV-s
T he current output can be converted to a voltage by resistive
IOUT
loading as shown in the block diagram. Both IOUT and
should be loaded equally for best overall performance. T he volt-
age which is developed is the product of the output current and
the value of the load resistor.
An operational amplifier can also be used to perform the I to V
conversion of the DAC output. Figure 3 shows an example of a
circuit which uses the AD9617, a high speed, current feedback
amplifier. T he resistor values in Figure 3 provide a 4.096 V
swing, centered at ground, at the output of the AD9617
amplifier.
AD9720
100 MHz
I
OUT
LPF
50Ω
TEST CIRCUIT
5 ns/DIVISION
Figure 4. AD9720 Glitch Im pulse
REV. A
–6–
AD9720/AD9721
0
–10
–20
–30
–40
–50
–60
–70
–80
0
–10
–20
–30
–40
–50
–60
–70
–80
0
–10
–20
–30
–40
–50
–60
–70
–80
AD9720 UPDATED
AT 220 MSPS
AD9720 UPDATED
AT 250 MSPS
AD9720 UPDATED
AT 250 MSPS
dB
dB
dB
66
68
70
72
74
60
61
62
63
64
65
8
9
10
11
12
MHz
MHz
MHz
Figure 5. Typical Output Spectrum
Figure 7. Typical Output Spectrum
Figure 6. Typical Output Spectrum
0
0
0
AD9720 UPDATED
–10
AD9720 UPDATED
–10
AD9720 UPDATED
–10
AT 100 MSPS
AT 250 MSPS
AT 100 MSPS
–20
–20
–20
–30
–30
–30
–40
–50
–60
–70
–80
–40
–50
–60
–70
–80
dB
dB
–40
–50
–60
–70
–80
dB
1.2
1.6
2.0
MHz
2.4
2.8
81
82
83
MHz
84
85
24.2
24.6
25.0
MHz
25.4
25.8
Figure 8. Typical Output Spectrum
Figure 10. Typical Output Spectrum
Figure 9. Typical Output Spectrum
EXTERNAL
+5V
POWER
TTL CLOCK
REFERENCE
GENERATOR
CLOCK
CIRCUIT
POWER
SUPPLY
INTERFACE
SUPPLY
–5.2V
AD9713B
STANDARD PRINTER CABLE
AD9955
100MHz
CMOS DDS
OR
AD9721
DAC
INTERFACE
LOGIC
50Ω
CABLE
AD9955 DDS EVALUATION BOARD
SOFTWARE
PROVIDED
IBM-COMPATIBLE PC
SPECTRUM ANALYZER
Figure 11. Direct Digital Synthesis System Diagram
REV. A
–7–
AD9720/AD9721
O UTLINE D IMENSIO NS
D imensions shown in inches and (mm).
28-P in P lastic D IP (Suffix N)
28-P in SO IC (Suffix R)
28
1
15
14
28
15
0.550 (13.97)
0.530 (13.46)
0.300 (7.60)
0.292 (7.40)
0.419 (10.65)
0.319 (10.00)
0.625 (15.8)
1.565 (39.70)
1.380 (35.10)
0.060 (1.52)
0.015 (0.38)
0.600 (15.24)
1
14
0.250 (6.35)
MAX
0.140
(3.56)
MIN
0.712 (18.08)
0.700 (17.78)
0.015 (0.381)
0.008 (0.204)
0.104 (2.65)
0.093 (2.35)
0.70 (1.77)
MAX
0.022 (0.558) 0.100 (2.54)
BSC
0.014 (0.356)
0.04 (1.02)
0.050 (1.27) BSC
0.019 (0.49)
0.014 (0.35)
0.013 (0.32)
0.009 (0.23)
0.012 (0.3)
0.004 (0.1)
0.024 (0.61)
28-P in Leadless Chip Car r ier (Suffix E)
28-P in Cer dip (Suffix Q )
0.100 (2.54) 1
0.064 (1.63)
1.490 (37.84) MAX
0.055 (1.40)
0.045 (1.14)
1.91
0.75
REF
15
28
0.610 (15.49)
0.500 (12.70)
1
14
0.620 (15.74)
0.590 (14.93)
0.028 (0.71)
0.022 (0.56)
GLASS SEALANT
28
0.22
(5.59)
MAX
NO. 1 PIN INDEX
0.050 ± (1.27)
0.018 (0.45)
0.008 (0.20)
0.005 ± (0.13)
15
0
BOTTOM VIEW
0.110 (2.79)
0.026 (0.660)
0.07 (1.78)
0.03 (0.76)
0.125
(3.175)
MIN
0.014 (0.356) 0.098 (2.45)
0.040 x 45°
(1.02 x 45°)
REF 3 PLCS
0.020 x 45°
(0.51 x 45°) REF
0.458 (11.63) 2
0.442 (11.23)
NOTES
1. THIS DIMENSION CONTROLS THE OVERALL PACKAGE THICKNESS.
2. APPLIES TO ALL FOUR SIDES.
3. ALL TERMINALS ARE GOLD PLATED.
REV. A
–8–
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