CAT1163J-45 [ROCHESTER]

SPECIALTY MICROPROCESSOR CIRCUIT, PDSO8, SOIC-8;


型号：	CAT1163J-45
厂家：	Rochester Electronics
描述：	SPECIALTY MICROPROCESSOR CIRCUIT, PDSO8, SOIC-8 光电二极管
文件：	总13页 (文件大小：751K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CAT1163 (16K)

Supervisory Circuit with I²C Serial CMOS EEPROM, Precision Reset Controller and Watchdog Timer

FEATURES

■ Active high or low reset

— Precision power supply voltage monitor

— 5V, 3.3V and 3V systems

■ Watchdog timer input (WDI)

■ 400kHz I²C bus compatible

■ 2.7V to 6.0V operation

— Five threshold voltage options

■ 1,000,000 Program/Erase cycles

■ Manual reset

■ Low power CMOS technology

■ 16-Byte page write buffer

■ Built-in inadvertent write protection

— V_CClock out

■ 100 Year data retention

■ 8-pin DIP or 8-pin SOIC

■ Commercial and industrial temperature ranges

— Write protect pin, WP

DESCRIPTION

supply voltages are out of tolerance reset signals become

active, preventing the system microcontroller, ASIC or

peripherals from operating. Reset signals become inactive

typically 200 ms after the supply voltage exceeds the reset

threshold level. With both active high and low reset signals,

interface to microcontrollers and other ICs is simple. In

addition, a reset pin can be used as debounced input for

push-button manual reset capability.

The CAT1163 is a complete memory and supervisory

solution for microcontroller-based systems. A serial

EEPROM memory (16K) with hardware memory write

protection, a system power supervisor with brown out

protectionandawatchdogtimerareintegratedtogether

inlowpowerCMOStechnology. Memoryinterfaceisvia

an I²C bus.

The CAT1163 memory features a 16-byte page. In addition,

hardware data protection is provided by a write protect pin

WP and by a V_CCsense circuit that prevents writes to

memory whenever V_CCfalls below the reset threshold or

until V_CCreaches the reset threshold during power up.

The 1.6-second watchdog circuit returns a system to a

known good state if a software or hardware glitch halts

or“hangs”thesystem.TheCAT1163watchdogmonitors

the WDI input pin.

The power supply monitor and reset circuit protects

memory and system controllers during power up/down

and against brownout conditions. Five reset threshold

voltages support 5V, 3.3V and 3V systems. If power

Available packages include an 8-pin DIP and a surface

mount, 8-pin SO package.

BLOCK DIAGRAM

PIN CONFIGURATION

EXTERNAL LOAD

SENSE AMPS

SHIFT REGISTERS

OUT

WDI

ACK

RESET

CAT1163

WORD ADDRESS

BUFFERS

COLUMN

DECODERS

GND

SCL

SDA

GND

START/STOP

LOGIC

SDA

EEPROM

XDEC

Reset Threshold Voltage Options

CONTROL

LOGIC

Part Dash Minimum Maximum

Number Threshold Threshold

DATA IN STORAGE

-45

-42

-30

-28

-25

4.50

4.25

3.00

2.85

2.55

4.75

4.50

3.15

3.00

2.70

HIGH VOLTAGE/

TIMING CONTROL

RESET Controller

STATE COUNTERS

SCL

Precision

SLAVE

ADDRESS

COMPARATORS

WATCHDOG

Vcc Monitor

WDI RESET RESET

Doc No. 3003, Rev. C

Characteristics subject to change without notice

CAT1163

PIN FUNCTIONS

ABSOLUTE MAXIMUM RATINGS

Pin No. Pin Name Function

Temperature Under Bias ................. –55°C to +125°C

Storage Temperature....................... –65°C to +150°C

WDI

Watchdog Timer Input

Active Low Reset I/O

RESET

Voltage on any Pin with

Respect to Ground⁽¹⁾............ –2.0V to +V_CC+2.0V

GND

SDA

Write Protect

Ground

_CCwith Respect to Ground ............... –2.0V to +7.0V

Serial Data/Address

Clock Input

Package Power Dissipation

Capability (T_A= 25°C) ................................... 1.0W

SCL

Lead Soldering Temperature (10 secs) ............ 300°C

Output Short Circuit Current⁽²⁾........................ 100 mA

RESET

V_CC

Active High Reset I/O

Power Supply

Stresses above those listed under “Absolute Maximum

Ratings” may cause permanent damage to the device.

These are stress ratings only, and functional operation

of the device at these or any other conditions outside of

those listed in the operational sections of this specifica-

tion is not implied. Exposure to any absolute maximum

rating for extended periods may affect device perfor-

mance and reliability.

RELIABILITY CHARACTERISTICS

Symbol

Parameter

Reference Test Method

Min

Max

Units

(3)

N_END

Endurance

MIL-STD-883, Test Method 1033 1,000,000

Cycles/Byte

Years

(3)

T_DR

Data Retention

ESD Susceptibility

Latch-Up

MIL-STD-883, Test Method 1008

MIL-STD-883, Test Method 3015

JEDEC Standard 17

100

2000

100

(3)

V_ZAP

Volts

(3)(4)

I_LTH

DC OPERATING CHARACTERISTICS

= +2.7V to +6.0V, unless otherwise specified.

Symbol

I_CC

Parameter

Test Conditions

Min

Typ

Max

Units

Power Supply Current

Standby Current

f_SCL= 100 kHz

I_SB

V_CC= 3.3V

V_CC= 5

µA

I_LI

Input Leakage Current

Output Leakage Current

Input Low Voltage

V_IN= G_NDor V_CC

µA

I_LO

V_IL

V_IH

V_OL1

-1

V_CCx 0.3

V_CC+ 0.5

0.4

Input High Voltage

V_CCx 0.7

Output Low Voltage (SDA) I_OL= 3 mA, V_CC= 3.0V

Note:

(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC

voltage on output pins is V +0.5V, which may overshoot to V +2.0V for periods of less than 20 ns.

(2) Output shorted for no more than one second. No more than one output shorted at a time.

(3) This parameter is tested initially and after a design or process change that affects the parameter.

(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to V +1V.

Doc. No. 3003, Rev. C

CAT1163

CAPACITANCE

T = 25˚C, f = 1.0 MHz, V

= 5V

Symbol Test

Max

Units

Conditions

V_I/O= 0V

V_IN= 0V

(1)

C_I/O

Input/Output Capacitance (SDA)

Input Capacitance (SCL)

(1)

C_IN

AC CHARACTERISTICS

V_CC=2.7V to 6.0V unless otherwise specified.

Output Load is 1 TTL Gate and 100pF.

_CC= 2.7V - 6V

V_CC= 4.5V - 5.5V

SYMBOL PARAMETER

Min

Max

100

200

Min

Max

400

200

Units

kHz

F_SCL

T_I⁽¹⁾

Clock Frequency

Noise Suppresion Time

Constant at SCL, SDA Inputs

SLC Low to SDA Data Out

and ACK Out

t_AA

3.5

µs

(1)

t_BUF

Time the Bus Must be Free Before

a New Transmission Can Start

4.7

1.2

t_HD:STA

t_LOW

Start Condition Hold Time

Clock Low Period

0.6

1.2

0.6

µs

4.7

t_HIGH

Clock High Period

t_SU:STA

Start Condition Setup Time

(for a Repeated Start Condition)

4.7

t_HD:DAT

t_SU:DAT

Data in Hold Time

µs

Data in Setup Time

(1)

t_R

SDA and SCL Rise Time

SDA and SCL Fall Time

Stop Condition Setup Time

Data Out Hold Time

0.3

(1)

t_F

300

t_SU:STO

t_DH

0.6

100

(1)(2)

POWER-UP TIMING

Symbol Parameter

Max

Units

t_PUR

t_PUW

Power-up to Read Operation

Power-up to Write Operation

WRITE CYCLE LIMITS

Symbol Parameter

Min

Typ

Max

Units

t_WR

Write Cycle Time

The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the

write cycle, the bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave address.

NOTE:

(1) This parameter is tested initially and after a design or process change that affects the parameter.

(2)

and t

are the delays required from the time V is stable until the specific operation can be initiated.

PUR

PUW

Doc No. 3003, Rev. C

CAT1163

RESET CIRCUIT CHARACTERISTICS

Symbol

t_GLITCH

V_RT

Parameter

Min

Typ

Max

Units

Glitch Reject Pulse Width

Reset Threshold Hystersis

Reset Output Low Voltage (I_OLRS=1mA)

100

V_OLRS

V_OHRS

0.4

Reset Output High Voltage

Reset Threshold (VCC=5V)

(CAT1163-45)

V_CC-0.75

4.50

4.75

Reset Threshold (VCC=5V)

(CAT1163-42)

4.25

3.00

2.85

2.55

130

4.50

3.15

3.00

2.70

270

Reset Threshold (VCC=3.3V)

(CAT1163-30)

V_TH

Reset Threshold (VCC=3.3V)

(CAT1163-28)

Reset Threshold (VCC=3V)

(CAT1163-25)

t_PURST

t_WD

Power-Up Reset Timeout

Watchdog Period

sec

µs

1.6

t_RPD

V_THto RESET Output Delay

RESET Output Valid

V_RVALID

Doc. No. 3003, Rev. C

CAT1163

RESEToutputs.Duringpower-up,theRESEToutputsremain

active until V_CCreaches the V_THthreshold and will continue

driving the outputs for approximately 200ms (t_PURST) after

reachingV_TH.Afterthet_PURSTtimeoutinterval,thedevicewill

cease to drive the reset outputs. At this point the reset

outputs will be pulled up or down by their respective pull up/

down resistors. During power-down, the RESET outputs will

be active when V_CCfalls below V_TH. The RESET outputs will

be valid so long as V_CCis >1.0V (V_RVALID).

PIN DESCRIPTIONS

WDI: WATCHDOG INPUT

If there is no transition on the WDI for more than 1.6

seconds, the watchdog timer times out.

WP:

WRITE PROTECT

If the pin is tied to V_CCthe entire memory array

becomes Write Protected (READ only). When the pin

is tied to GND or left floating normal read/write

operations are allowed to the device.

TheRESETpinsareI/Os;therefore,theCAT1163canactas

a signal conditioning circuit for an externally applied reset.

Theinputsareedgetriggered;thatis, theRESETinputinthe

CAT1163 will initiate a reset timeout after detecting a low to

high transition and the RESET input in the CAT1163 will

initiate a reset timeout after detecting a high to low transition.

RESET/RESET: RESET I/O

These are open drain pins and can be used as reset

trigger inputs. By forcing a reset condition on the pins

the device will initiate and maintain a reset condition.

The RESET pin must be connected through a pull-

down resistor and the RESET pin must be connected

through a pull-up resistor.

Watchdog Timer

TheWatchdogTimerprovidesanindependentprotectionfor

microcontrollers. During a system failure, the CAT1163 will

respond with a reset signal after a time-out interval of 1.6

seconds for a lack of activity. The CAT1163 is designed with

a WDI input pin for the Watchdog Timer function. If the

microcontroller does not toggle the WDI input pin within 1.6

seconds, the Watchdog Timer times out. This will generate

a reset condition on reset outputs. The Watchdog Timer is

cleared by any transition on WDI.

SDA: SERIAL DATA ADDRESS

The bidirectional serial data/address pin is used to

transfer all data into and out of the device. The SDA

pin is an open drain output and can be wire-ORed

with other open drain or open collector outputs.

SCL: SERIAL CLOCK

Serial clock input.

As long as the reset signal is asserted, the Watchdog Timer

will not count and will stay cleared.

DEVICE OPERATION

Reset Controller Description

The CAT1163 precision RESET controller ensures

correct system operation during brownout and power

up/down conditions. It is configured with open drain

Figure 1. RESET Output Timing

GLITCH

RVALID

RPD

PURST

RESET

RPD

RESET

Doc No. 3003, Rev. C

CAT1163

Hardware Data Protection

Any attempt to access the internal EEPROM is not

recognized and an ACK will not be sent on the SDA line

when RESET or RESET is active.

The CAT1163 is designed with the following hardware

data protection features to provide a high degree of data

integrity.

Reset Threshold Voltage

TheCAT1163isofferedwithfiveresetthresholdvoltage

ranges. They are 4.50-4.75V, 4.25-4.50V, 3.00-3.15V,

2.85-3.00V and 2.55-2.70V.

(1) The CAT1163 features a WP pin. When the WP pin

is tied high the entire memory array becomes write

protected (read only).

(2) The V_CCsense provides write protection when V_CC

fallsbelowtheresetthresholdvalue(VTH).TheV_CClock

out inhibits writes to the serial EEPROM whenever V_CC

falls below (power down) VTH or until V_CCreaches the

reset threshold (power up) V_TH

Figure 2. Bus Timing

HIGH

LOW

SCL

HD:DAT

SU:STA

HD:STA

SU:DAT

SU:STO

SDA IN

BUF

SDA OUT

Figure 3. Write Cycle Timing

SCL

SDA

8TH BIT

BYTE n

ACK

STOP

CONDITION

START

CONDITION

ADDRESS

Figure 4. Start/Stop Timing

SDA

SCL

START BIT

STOP BIT

Doc. No. 3003, Rev. C

CAT1163

STOP Condition

FUNCTIONAL DESCRIPTION

The CAT1163 supports the I²C Bus data transmission

protocol.ThisInter-IntegratedCircuitBusprotocoldefines

any device that sends data to the bus to be a transmitter

and any device receiving data to be a receiver. The

transfer is controlled by the Master device which

generates the serial clock and all START and STOP

conditions for bus access. Both the Master device and

Slavedevicecanoperateaseithertransmitterorreceiver,

but the Master device controls which mode is activated.

A LOW to HIGH transition of SDA when SCL is HIGH

determinestheSTOPcondition.Alloperationsmustend

with a STOP condition.

DEVICE ADDRESSING

The Master begins a transmission by sending a START

condition.TheMastersendstheaddressoftheparticular

slave device it is requesting. The four most significant

bits of the 8-bit slave address are fixed as 1010.

I²C Bus Protocol

Thenextthreebits(Figure6)definememoryaddressing.

For the CAT1163 the three bits define higher order bits.

The features of the I²C bus protocol are defined as

follows:

The last bit of the slave address specifies whether a

ReadorWriteoperationistobeperformed.Whenthisbit

is set to 1, a Read operation is selected, and when set

to 0, a Write operation is selected.

(1) Data transfer may be initiated only when the bus is

not busy.

(2) During a data transfer, the data line must remain

stable whenever the clock line is high. Any changes in

thedatalinewhiletheclocklineishighwillbeinterpreted

as a START or STOP condition.

After the Master sends a START condition and the slave

address byte, the CAT1163 monitors the bus and

responds with an acknowledge (on the SDA line) when

its address matches the transmitted slave address. The

CAT1163 then performs a Read or Write operation

depending on the R/W bit.

START Condition

The START Condition precedes all commands to the

device, and is defined as a HIGH to LOW transition of

SDA when SCL is HIGH. The CAT1163 monitors the

SDA and SCL lines and will not respond until this

condition is met.

Figure 5. Acknowledge Timing

SCL FROM

MASTER

DATA OUTPUT

FROM TRANSMITTER

DATA OUTPUT

FROM RECEIVER

START

ACKNOWLEDGE

Figure 6. Slave Address Bits

CAT1163

24C163

a10 a9

a8 R/W

‘X’ corresponds to Don’t Care Bits (can be zero or a one).

** a8, a9 and a10 correspond to the address of the memory array address word.

Doc No. 3003, Rev. C

CAT1163

ACKNOWLEDGE

acknowledgefromtheSlave,theMasterdevicetransmits

thedatatobewrittenintotheaddressedmemorylocation.

The CAT1163 acknowledges once more and the Master

generates the STOP condition. At this time, the device

begins an internal programming cycle to non-volatile

memory. While the cycle is in progress, the device will not

respond to any request from the Master device.

After a successful data transfer, each receiving device

is required to generate an acknowledge. The

acknowledging device pulls down the SDA line during

the ninth clock cycle, signaling that it received the 8 bits

of data.

The CAT1163 responds with an acknowledge after

receivingaSTARTconditionanditsslaveaddress.Ifthe

device has been selected along with a write operation,

it responds with an acknowledge after receiving each 8-

bit byte.

Page Write

The CAT1163 writes up to 16 bytes of data in a single

write cycle, using the Page Write operation. The page

write operation is initiated in the same manner as the byte

write operation, however instead of terminating after the

initial byte is transmitted, the Master is allowed to send up

to 15 additional bytes. After each byte has been

transmitted, the CAT1163 will respond with an

acknowledge and internally increment the lower order

addressbitsbyone.Thehighorderbitsremainunchanged.

When the CAT1163 begins a READ mode it transmits 8

bits of data, releases the SDA line and monitors the line

for an acknowledge. Once it receives this acknowledge,

the CAT1163 will continue to transmit data. If no

acknowledgeissentbytheMaster,thedeviceterminates

data transmission and waits for a STOP condition.

WRITE OPERATIONS

IftheMastertransmitsmorethan16bytesbeforesending

the STOP condition, the address counter ‘wraps around,’

and previously transmitted data will be overwritten.

Byte Write

In the Byte Write mode, the Master device sends the

START condition and the slave address information

(with the R/W bit set to zero) to the Slave device. After

the Slave generates an acknowledge, the Master sends

a 8-bit address that is to be written into the address

pointers of the CAT1163. After receiving another

When all 16 bytes are received, and the STOP condition

has been sent by the Master, the internal programming

cycle begins. At this point, all received data is written to

the CAT1163 in a single write cycle.

Figure 7. Byte Write Timing

BUS ACTIVITY:

MASTER

SLAVE

ADDRESS

BYTE

ADDRESS

DATA

SDA LINE

Figure 8. Page Write Timing

BUS ACTIVITY:

MASTER

SLAVE

ADDRESS

BYTE

ADDRESS (n)

DATA n

DATA n+1

DATA n+15

SDA LINE

Doc. No. 3003, Rev. C

CAT1163

Acknowledge Polling

protected and becomes read only. The CAT1163 will

accept both slave and byte addresses, but the memory

locationaccessedisprotectedfromprogrammingbythe

device’s failure to send an acknowledge after the first

byte of data is received.

Disabling of the inputs can be used to take advantage of

the typical write cycle time. Once the stop condition is

issued to indicate the end of the host’s write opration the

CAT1163 initiates the internal write cycle. ACK polling

can be initiated immediately. This involves issuing the

start condition followed by the slave address for a write

operation. If the CAT1163 is still busy with the write

operation, no ACK will be returned. If a write operation

hascompleted, anACKwillbereturnedandthehostcan

then proceed with the next read or write operation.

Read Operations

The READ operation for the CAT1163 is initiated in the

same manner as the write operation with one exception,

thatR/Wbitissettoone.ThreedifferentREADoperations

are possible: Immediate/Current Address READ,

Selective/Random READ and Sequential READ.

WRITE PROTECTION

The Write Protection feature allows the user to protect

against inadvertent memory array programming. If the

WP pin is tied to V_CC, the entire memory array is

Figure 9. Immediate Address Read Timing

BUS ACTIVITY:

MASTER

SLAVE

ADDRESS

SDA LINE

DATA

SCL

SDA

8TH BIT

DATA OUT

NO ACK

STOP

Doc No. 3003, Rev. C

CAT1163

Immediate/Current Address Read

The data being transmitted from CAT1163 is outputted

sequentially with data from address N followed by data

fromaddressN+1.TheREADoperationaddresscounter

increments all of the CAT1163 address bits so that the

entire memory array can be read during one operation.

If more than E (where E=2047 for the CAT1163) bytes

arereadout,thecounterwill‘wraparound’andcontinue

to clock out data bytes.

The CAT1163’s address counter contains the address

of the last byte accessed, incremented by one. In other

words, if the last READ or WRITE access was to

addressN,theREADimmediatelyfollowingwouldaccess

data from address N+1. If N=E (where E=2047 for the

CAT1163)thenthecounterwill‘wraparound’toaddress

0 and continue to clock out data. After the CAT1163

receives its slave address information (with the R/W bit

set to one), it issues an acknowledge, then transmits the

8-bit byte requested. The master device does not send

an acknowledge, but will generate a STOP condition.

Manual Reset Operation

The CAT116x RESET or RESET pin can also be used

as a manual reset input.

Selective/RandomRead

Only the “active” edge of the manual reset input is

internallysensed.ThepositiveedgeissensedifRESET

is used as a manual reset input and the negative edge

is sensed if RESET is used as a manual reset input.

Selective/Random READ operations allow the Master

device to select at random any memory location for a

READ operation. The Master device first performs a

‘dummy’writeoperationbysendingtheSTARTcondition,

slave address and byte addresses of the location it

wishes to read. After the CAT1163 acknowledges, the

MasterdevicesendstheSTARTconditionandtheslave

address again, this time with the R/W bit set to one. The

CAT1163thenrespondswithitsacknowledgeandsends

teh 8-bit byte requested. The master device does not

sendanacknowledgebutwillgenerateaSTOPcondition.

An internal counter starts a 200 ms count. During this

time, the complementary reset output will be kept in the

active state. If the manual reset input is forced active for

more than 200 ms, the complementary reset output will

switch back to the non active state after the 200 ms

expired, regardless for how long the manual reset input

is forced active.

The embedded EEPROM is disabled as long as a reset

conditionismaintainedonanyRESETpin.Iftheexternal

forcedRESET/RESET islongerthaninternalcontrolled

time-out period, tPURST, the memory will not respond

with an acknowledge for any access as long as the

manual reset input is active.

Sequential Read

The Sequential READ operation can be initiated by

either the Immediate Address READ or Selective READ

operations. AftertheCAT1163sendstheinital8-bitbyte

requested,theMasterwillrespondswithanacknowledge

whichtellsthedeviceitrequiresmoredata.TheCAT1163

willcontinuetooutputan8-bitbyteforeachacknowledge,

thus sending the STOP condition.

Figure 10. Selective Read Timing

BUS ACTIVITY:

MASTER

SLAVE

ADDRESS

BYTE

ADDRESS (n)

SLAVE

ADDRESS

SDA LINE

DATA n

Doc. No. 3003, Rev. C

CAT1163

Figure 11. Sequential Read Timing

BUS ACTIVITY:

MASTER

SLAVE

ADDRESS

DATA n

DATA n+1

DATA n+2

DATA n+x

SDA LINE

Ordering Information

Prefix

Device #

Suffix

-30

1163

CAT

TE13

Optional

Company ID

Temperature Range

Blank = Commercial (0˚ to 70˚C)

I = Industrial (-40˚ to 85˚C)

Product

Number

1163: 16K

Tape & Reel

TE13: 2000/Reel

ResetThreshold

Voltage

45: 4.5-4.75V

42: 4.25-4.5V

30: 3.0-3.15V

28: 2.85-3.0V

25: 2.55-2.7V

Package

P: PDIP

J: SOIC (JEDEC)

Note:

(1) The device used in the above example is a CAT1163JI-30TE13 (16K I C Memory, SOIC, Industrial Temperature, 3.0-3.15V Reset

Threshold Voltage, Tape and Reel)

Doc No. 3003, Rev. C

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Trademarks and registered trademarks of Catalyst Semiconductor include each of the following:

DPP ™

AE²™

Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents

issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000.

CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS

PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE

RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING

OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.

Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or

other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a

situation where personal injury or death may occur.

Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets

labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale.

Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate

typical semiconductor applications and may not be complete.

Catalyst Semiconductor, Inc.

Corporate Headquarters

1250 Borregas Avenue

Sunnyvale, CA 94089

Phone: 408.542.1000

Fax: 408.542.1200

Publication #: 3003

Revison:

Issue date:

Type:

03/29/02

Final

www.catalyst-semiconductor.com

CAT1163J-45 [ROCHESTER]

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