CY7C1020BN-15ZXC [ROCHESTER]
32KX16 STANDARD SRAM, 15ns, PDSO44, LEAD FREE, TSOP2-44;
| 型号： | CY7C1020BN-15ZXC |
| 厂家： | 
Rochester Electronics |
| 描述： | 32KX16 STANDARD SRAM, 15ns, PDSO44, LEAD FREE, TSOP2-44 静态存储器 光电二极管 内存集成电路 |
| 文件： | 总9页 (文件大小：1059K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1020BN
32K x 16 Static RAM
Features
Functional Description
• High speed
The CY7C1020BN is a high-performance CMOS static RAM
organized as 32,768 words by 16 bits. This device has an
automatic power-down feature that significantly reduces
power consumption when deselected.
— tAA = 12, 15 ns
• CMOS for optimum speed/power
• Low active power
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O1 through I/O8), is
written into the location specified on the address pins (A0
through A15). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O9 through I/O16) is written into the location
specified on the address pins (A0 through A15).
— 825 mW (max.)
• Low CMOS standby power (L version only)
— 2.75 mW (max.)
• Automatic power-down when deselected
• Independent control of upper and lower bits
• Available in 44-pin TSOP II and 400-mil SOJ
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O1 to I/O8. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O9 to I/O16. See
the truth table at the back of this data sheet for a complete
description of read and write modes.
The input/output pins (I/O1 through I/O16) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a write operation (CE
LOW, and WE LOW).
The CY7C1020BN is available in standard 44-pin TSOP Type
II and 400-mil-wide SOJ packages.
Logic Block Diagram
Pin Configuration
SOJ / TSOP II
DATA IN DRIVERS
Top View
44
1
NC
A
5
43
42
41
40
39
38
A
A
2
3
4
5
6
3
6
A
A
2
7
A7
A6
A5
A4
A3
A2
OE
A
1
BHE
BLE
I/O
I/O
I/O
A
0
32K x 16
CE
I/O1–I/O8
RAM Array
I/O
7
1
16
37
36
35
34
33
I/O
I/O
8
2
3
15
14
13
I/O9–I/O16
9
A1
A0
10
11
12
13
I/O
V
SS
I/O
4
CC
V
SS
V
V
CC
32
31
30
29
28
27
I/O
I/O
I/O
5
6
7
8
12
11
I/O
I/O
I/O
14
15
16
I/O
I/O
10
9
COLUMN DECODER
WE 17
NC
18
A
A
8
15
BHE
19
26
25
A
A
14
9
WE
CE
OE
A
13
20
21
22
A
11
10
A
A
12
24
23
NC
NC
BLE
Cypress Semiconductor Corporation
Document #: 001-06443 Rev. **
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised February 1, 2006
CY7C1020BN
Selection Guide
7C1020BN-12
7C1020BN-15
Maximum Access Time (ns)
12
140
3
15
130
3
Maximum Operating Current (mA)
Maximum CMOS Standby Current (mA)
L
0.5
0.5
Current into Outputs (LOW)......................................... 20 mA
Maximum Ratings
Static Discharge Voltage............................................>2001V
(per MIL-STD-883, Method 3015)
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Latch-Up Current.....................................................>200 mA
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Operating Range
Ambient
Supply Voltage on VCC to Relative GND[1] .... –0.5V to +7.0V
Range
Commercial
Industrial
Temperature[2]
0×C to +70×C
VCC
DC Voltage Applied to Outputs
5V ± 10%
5V ± 10%
in High Z State[1] ......................................–0.5V to VCC+0.5V
–40×C to +85×C
DC Input Voltage[1]...................................–0.5V to VCC+0.5V
Electrical Characteristics Over the Operating Range
7C1020BN-12 7C1020BN-15
Test
Parameter
VOH
VOL
VIH
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage[1]
Input Load Current
Conditions
VCC = Min., IOH = –4.0 mA
VCC = Min., IOL = 8.0 mA
Min.
Max.
Min. Max. Unit
2.4
2.4
V
V
0.4
6.0
0.4
6.0
2.2
–0.5
–1
2.2
–0.5
–1
V
VIL
0.8
0.8
V
IIX
GND < VI < VCC
+1
+1
µA
µA
mA
mA
IOZ
Output Leakage Current
GND < VI < VCC, Output Disabled
Output Short Circuit Current[3] VCC = Max., VOUT = GND
–1
+1
–1
+1
IOS
–300
140
–300
130
ICC
VCC Operating Supply Current VCC = Max.,IOUT = 0 mA, f = fMAX = 1/tRC
ISB1
Automatic CE Power-Down
Current—TTL Inputs
Max. VCC, CE > VIH
VIN > VIH or VIN < VIL, f = fMAX
20
20
mA
ISB2
3
3
mA
mA
Automatic CE Power-Down
Current—CMOS Inputs
Max. VCC, CE > VCC – 0.3V,
VIN > VCC – 0.3V, or VIN < 0.3V,
L
0.5
0.5
f = 0
Capacitance[4]
Parameter
Description
Test Conditions
TA = 25°C, f = 1 MHz,
CC = 5.0V
Max.
Unit
CIN
Input Capacitance
8
pF
V
COUT
Output Capacitance
8
pF
Notes:
1. V (min.) = –2.0V for pulse durations of less than 20 ns.
IL
2. T is the case temperature.
A
3. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
4. Tested initially and after any design or process changes that may affect these parameters.
Document #: 001-06443 Rev. **
Page 2 of 8
CY7C1020BN
AC Test Loads and Waveforms
R 481Ω
R 481Ω
ALL INPUT PULSES
5V
5V
OUTPUT
3.0V
90%
10%
90%
10%
OUTPUT
R2
255Ω
R2
255Ω
GND
30 pF
5 pF
INCLUDING
JIG AND
SCOPE
INCLUDING
JIG AND
SCOPE
Rise Time: 1 V/ns
Fall Time: 1 V/ns
1.73V
(b)
(a)
167
OUTPUT
Equivalent to:
THÉVENIN
EQUIVALENT
30 pF
Switching Characteristics[5] Over the Operating Range
7C1020BN-12
7C1020BN-15
Parameter
Read Cycle
tRC
Description
Min.
Max.
Min.
Max.
Unit
Read Cycle Time
12
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z[6]
OE HIGH to High Z[6, 7]
CE LOW to Low Z[6]
CE HIGH to High Z[6, 7]
CE LOW to Power-Up
CE HIGH to Power-Down
Byte Enable to Data Valid
Byte Enable to Low Z
Byte Disable to High Z
12
15
tOHA
3
3
tACE
12
6
15
7
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
0
3
0
0
3
0
6
6
7
7
tPD
12
6
15
7
tDBE
tLZBE
tHZBE
Write Cycle[8]
tWC
0
0
6
7
Write Cycle Time
12
9
15
10
10
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSCE
CE LOW to Write End
tAW
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
8
tHA
0
tSA
0
0
tPWE
8
10
8
tSD
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z[6]
6
tHD
0
0
tLZWE
tHZWE
3
3
WE LOW to High Z[6, 7]
6
7
tBW
Byte Enable to End of Write
8
9
Notes:
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
/I and 30-pF load capacitance.
OL OH
6. At any given temperature and voltage condition, t
is less than t
, t
is less than t
, and t
is less than t
for any given device.
HZCE
LZCE HZOE
LZOE
HZWE
LZWE
7. t
, t
, t
, and t
are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state
HZOE HZBE HZCE
HZWE
voltage.
8. The internal write time of the memory is defined by the overlap of CE LOW, WE LOW and BHE / BLE LOW. CE, WE and BHE / BLE must be LOW to initiate
a write, and the transition of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal
that terminates the write.
Document #: 001-06443 Rev. **
Page 3 of 8
CY7C1020BN
Switching Waveforms
Read Cycle No. 1[9, 10]
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 (OE Controlled)[10, 11]
ADDRESS
CE
t
RC
t
ACE
OE
t
HZOE
t
DOE
BHE, BLE
t
LZOE
t
HZCE
t
DBE
t
LZBE
t
HZBE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
VCC
SUPPLY
CURRENT
DATA VALID
t
LZCE
t
PD
I
CC
t
PU
50%
50%
I
SB
Notes:
9. Device is continuously selected. OE, CE, BHE and/or BHE = V .
IL
10. WE is HIGH for read cycle.
11. Address valid prior to or coincident with CE transition LOW.
Document #: 001-06443 Rev. **
Page 4 of 8
CY7C1020BN
Switching Waveforms (continued)
Write Cycle No. 1 (CE Controlled)[12, 13]
t
WC
ADDRESS
t
SA
t
SCE
CE
t
AW
t
HA
t
PWE
WE
t
BW
BHE, BLE
t
t
SD
HD
DATA I/O
Write Cycle No. 2 (BLE or BHE Controlled)
t
WC
ADDRESS
t
SA
t
BW
BHE, BLE
t
AW
t
HA
t
PWE
WE
CE
t
SCE
t
t
SD
HD
DATA I/O
Notes:
12. Data I/O is high impedance if OE or BHE and/or BLE= V
.
IH
13. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
Document #: 001-06443 Rev. **
Page 5 of 8
CY7C1020BN
Switching Waveforms (continued)
Write Cycle No. 3 (WE Controlled, OE LOW)
t
WC
ADDRESS
CE
t
SCE
t
AW
t
HA
t
SA
t
PWE
WE
t
BW
BHE, BLE
t
HZWE
t
t
SD
HD
DATA I/O
t
LZWE
Truth Table
CE OE WE BLE BHE
I/O1–I/O8
High Z
I/O9–I/O16
Mode
Power
H
L
X
L
X
H
X
L
X
L
High Z
Data Out
High Z
Data Out
Data In
High Z
Data In
High Z
High Z
Power-Down
Read – All bits
Standby (ISB)
Data Out
Data Out
High Z
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
)
)
)
)
)
)
)
)
L
H
L
Read – Lower bits only
Read – Upper bits only
Write – All bits
H
L
L
X
L
L
Data In
Data In
High Z
L
H
L
Write – Lower bits only
Write – Upper bits only
H
X
H
L
L
H
X
H
X
X
H
High Z
Selected, Outputs Disabled
Selected, Outputs Disabled
High Z
Ordering Information
Speed
Package
Diagram
Operating
Range
(ns)
Ordering Code
CY7C1020BN-12VC
Package Type
12
51-85082
51-85082
51-85087
51-85087
51-85087
51-85087
44-Lead (400-Mil) Molded SOJ
44-Lead (400-Mil) Molded SOJ (Pb-free)
44-pin TSOP Type II
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
CY7C1020BN-12VXC
CY7C1020BN-12ZC
CY7C1020BN-12ZXC
CY7C1020BN-15ZC
CY7C1020BN-15ZXC
44-pin TSOP Type II (Pb-free)
44-pin TSOP Type II
15
44-pin TSOP Type II (Pb-free)
Please contact local sales representative regarding availability of these parts.
Document #: 001-06443 Rev. **
Page 6 of 8
CY7C1020BN
Package Diagrams
44-Lead (400-Mil) Molded SOJ (51-85082)
51-85082-*B
44-Pin TSOP II (51-85087)
51-85087-*A
All product and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 001-06443 Rev. **
Page 7 of 8
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY7C1020BN
Document History Page
Document Title: CY7C1020BN 32K x 16 Static RAM
Document #: 001-06443
Issue
Orig. of
Change
REV.
**
ECN NO. Date
Description of Change
426812
See ECN
NXR
New Data Sheet
Document #: 001-06443 Rev. **
Page 8 of 8
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