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CY7C1041CV33-12ZCT [ROCHESTER]

Standard SRAM, 256KX16, 12ns, CMOS, PDSO44, TSOP2-44;
CY7C1041CV33-12ZCT
型号： CY7C1041CV33-12ZCT
厂家： Rochester Electronics    Rochester Electronics
描述：

Standard SRAM, 256KX16, 12ns, CMOS, PDSO44, TSOP2-44

静态存储器 光电二极管
文件： 总13页 (文件大小：1264K)
中文：  中文翻译
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CY7C1041CV33  
4-Mbit (256K x 16) Static RAM  
Features  
Functional Description[1]  
• Pin equivalent to CY7C1041BV33  
• Temperature Ranges  
The CY7C1041CV33 is a high-performance CMOS Static  
RAM organized as 262,144 words by 16 bits.  
Writing to the device is accomplished by taking Chip Enable  
(CE) and Write Enable (WE) inputs LOW. If Byte LOW Enable  
(BLE) is LOW, then data from I/O pins (I/O0–I/O7), is written  
into the location specified on the address pins (A0–A17). If Byte  
HIGH Enable (BHE) is LOW, then data from I/O pins  
(I/O8–I/O15) is written into the location specified on the  
address pins (A0–A17).  
— Commercial: 0°C to 70°C  
— Industrial: –40°C to 85°C  
— Automotive-A: –40°C to 85°C  
— Automotive-E: –40°C to 125°C  
• High speed  
— tAA = 10 ns  
Reading from the device is accomplished by taking Chip  
Enable (CE) and Output Enable (OE) LOW while forcing the  
Write Enable (WE) HIGH. If Byte LOW Enable (BLE) is LOW,  
then data from the memory location specified by the address  
pins will appear on I/O0 – I/O7. If Byte HIGH Enable (BHE) is  
LOW, then data from memory will appear on I/O8 to I/O15. See  
the truth table at the back of this data sheet for a complete  
description of Read and Write modes.  
• Low active power  
— 324 mW (max.)  
• 2.0V data retention  
• Automatic power-down when deselected  
• TTL-compatible inputs and outputs  
• Easy memory expansion with CE and OE features  
The input/output pins (I/O0–I/O15  
)
are placed in  
a
high-impedance state when the device is deselected (CE  
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE  
are disabled (BHE, BLE HIGH), or during a Write operation  
(CE LOW, and WE LOW).  
• Available in Pb-free and non Pb-free 44-pin 400-mil-  
SOJ, 44-pin TSOP II and 48-ball FBGA packages  
The CY7C1041CV33 is available in a standard 44-pin  
400-mil-wide body width SOJ and 44-pin TSOP II package  
with center power and ground (revolutionary) pinout, as well  
as a 48-ball fine-pitch ball grid array (FBGA) package.  
Logic Block Diagram  
Pin Configuration  
SOJ/  
TSOP II  
Top View  
INPUT BUFFER  
44  
43  
42  
41  
40  
39  
38  
1
2
3
4
5
6
A
A
17  
0
A
A
16  
A
0
1
A
A
15  
A
1
2
A
2
A
OE  
BHE  
BLE  
3
I/O –I/O  
256K × 16  
0
7
A
A
3
4
ARRAY  
A
4
CE  
I/O –I/O  
A
I/O  
I/O  
5
7
8
15  
0
15  
A
6
37  
36  
35  
34  
33  
32  
I/O  
I/O  
8
I/O  
I/O  
1
2
14  
13  
12  
A
7
9
A
8
10  
11  
12  
13  
I/O  
V
SS  
I/O  
3
CC  
V
SS  
V
V
CC  
I/O  
I/O  
I/O  
4
5
6
7
11  
10  
COLUMN  
DECODER  
31  
30  
29  
28  
I/O  
I/O  
I/O  
14  
15  
16  
I/O  
9
8
I/O  
WE 17  
NC  
18  
27  
26  
25  
A
14  
A
5
BHE  
WE  
CE  
OE  
BLE  
19  
A
A
6
13  
A
20  
21  
22  
A
7
12  
A
11  
A
24  
23  
8
9
A
A
10  
Notes:  
1. For guidelines on SRAM system design, please refer to the “System Design Guidelines” Cypress application note, available on the internet at www.cypress.com.  
Cypress Semiconductor Corporation  
Document #: 38-05134 Rev. *H  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised September 1, 2006  
CY7C1041CV33  
Selection Guide  
-10  
10  
-12  
12  
85  
95  
-15  
15  
80  
90  
-20  
20  
75  
85  
85  
90  
10  
Unit  
ns  
Maximum Access Time  
Maximum Operating Current  
Commercial  
Industrial  
90  
mA  
mA  
mA  
mA  
mA  
100  
100  
Automotive-A  
Automotive-E  
Maximum CMOS Standby Current  
Commercial/  
Industrial  
10  
10  
10  
10  
Automotive-A  
Automotive-E  
mA  
mA  
15  
Pin Configurations  
48-ball FBGA  
(Top View)  
1
4
3
2
5
6
A
A
2
A
NC  
OE  
BLE  
0
A
B
C
1
I/O  
A
A
BHE  
CE  
I/O  
I/O  
0
4
3
8
I/O  
A
A
6
I/O  
I/O  
2
5
1
10  
9
I/O  
A
I/O  
V
V
A
CC  
D
E
F
11  
SS  
7
3
17  
A
V
CC  
NC  
V
I/O  
I/O  
12  
SS  
16  
4
I/O  
A
A
I/O  
13  
I/O  
I/O  
14  
14  
15  
5
6
A
A
I/O  
15  
G
H
I/O  
NC  
WE  
13  
12  
7
A
A
A
A
NC  
NC  
10  
9
11  
8
Document #: 38-05134 Rev. *H  
Page 2 of 12  
CY7C1041CV33  
Pin Definitions  
44-SOJ,  
44-TSOP  
48-ball FBGA  
Pin Number  
Pin Name  
Pin Number  
I/O Type  
Description  
A0–A17  
1–5, 18–27,  
42–44  
A3, A4, A5, B3,  
B4, C3, C4, D4,  
H2, H3, H4, H5,  
G3, G4, F3, F4,  
E4, D3  
Input  
Address Inputs used to select one of the address  
locations.  
I/O0–I/O15  
7–10,13–16, B1, C1, C2, D2, Input/Output Bidirectional Data I/O lines. Used as input or output lines  
29–32, 35–38 E2, F2, F1, G1,  
B6, C6, C5, D5,  
depending on operation  
E5, F5, F6, G6  
NC  
28  
17  
A6, E3, G2, H1, No Connect No Connects. This pin is not connected to the die  
H6  
WE  
G5  
Input/Control Write Enable Input, active LOW. When selected LOW, a  
WRITE is conducted. When selected HIGH, a READ is  
conducted.  
CE  
BHE, BLE  
OE  
6
B5  
B2, A1  
A2  
Input/Control Chip Enable Input, active LOW. When LOW, selects the chip.  
When HIGH, deselects the chip.  
40, 39  
41  
Input/Control Byte Write Select Inputs, active LOW. BHE controls  
I/O15–I/O8, BLE controls I/O7–I/O0  
Input/Control Output Enable, active LOW. Controls the direction of the I/O  
pins. When LOW, the I/O pins are allowed to behave as  
outputs. When deasserted HIGH, I/O pins are tri-stated, and  
act as input data pins.  
VSS  
VCC  
12, 34  
11, 33  
D1, E6  
D6, E1  
Ground  
Ground for the device. Should be connected to ground of the  
system.  
Power Supply Power Supply inputs to the device.  
Document #: 38-05134 Rev. *H  
Page 3 of 12  
CY7C1041CV33  
Maximum Ratings  
(Above which the useful life may be impaired. For user guide-  
lines, not tested.)  
Static Discharge Voltage............. ...............................>2001V  
(per MIL-STD-883, Method 3015)  
Latch-up Current...................................................... >200 mA  
Storage Temperature .................................–65°C to +150°C  
Ambient Temperature with  
Power Applied.............................................–55°C to +125°C  
Operating Range  
Ambient  
Supply Voltage on VCC to Relative GND[2] .... –0.5V to +4.6V  
Range  
Commercial  
Industrial  
Temperature  
VCC  
DC Voltage Applied to Outputs  
0°C to +70°C  
3.3V ± 0.3V  
in High-Z State[2] ....................................–0.5V to VCC + 0.5V  
–40°C to +85°C  
–40°C to +85°C  
–40°C to +125°C  
DC Input Voltage[2].................................–0.5V to VCC + 0.5V  
Automotive-A  
Automotive-E  
Current into Outputs (LOW).........................................20 mA  
DC Electrical Characteristics Over the Operating Range  
-10  
-12  
-15  
-20  
Parameter  
VOH  
Description  
Test Conditions  
Min. Max. Min. Max. Min. Max. Min. Max. Unit  
Output HIGH Voltage VCC = Min., IOH = –4.0 mA  
Output LOW Voltage VCC = Min., IOL = 8.0 mA  
Input HIGH Voltage  
2.4  
2.4  
2.4  
2.4  
V
V
V
VOL  
0.4  
0.4  
0.4  
0.4  
VIH  
2.0 VCC  
+ 0.3  
2.0  
VCC  
2.0  
VCC  
2.0  
VCC  
+ 0.3  
+ 0.3  
+ 0.3  
[2]  
VIL  
Input LOW Voltage  
–0.3 0.8 –0.3  
0.8 –0.3 0.8 –0.3 0.8  
V
IIX  
Input Leakage  
Current  
GND < VI < VCC  
Com’l/Ind’l –1  
+1  
+1  
–1  
+1  
+1  
–1  
+1  
+1  
–1  
–1  
+1  
+1  
µA  
Auto-A  
Auto-E  
–1  
µA  
–20 +20  
µA  
IOZ  
Output Leakage  
Current  
GND <VOUT<VCC, Com’l/Ind’l –1  
Output Disabled  
+1  
+1  
–1  
–1  
–1  
–1  
+1  
+1  
µA  
Auto-A  
Auto-E  
Com’l  
–1  
µA  
–20 +20  
µA  
ICC  
VCC Operating  
Supply Current  
VCC = Max.,  
f = fMAX = 1/tRC  
90  
85  
95  
80  
90  
75  
85  
85  
90  
40  
40  
45  
10  
10  
15  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
Ind’l  
100  
100  
Auto-A  
Auto-E  
Com’l/Ind’l  
Auto-A  
ISB1  
Automatic CE  
Power-down Current CE > VIH  
—TTL Inputs  
Max. VCC  
,
40  
40  
40  
10  
40  
10  
VIN > VIH or  
VIN < VIL, f = fMAX Auto-E  
ISB2  
Automatic CE  
Power-down Current CE > VCC – 0.3V,  
—CMOS Inputs IN > VCC – 0.3V,  
Max. VCC  
,
Com’l/Ind’l  
Auto-A  
10  
10  
V
or VIN < 0.3V, f = 0 Auto-E  
Capacitance[3]  
Parameter  
Description  
Test Conditions  
TA = 25°C, f = 1 MHz, VCC = 3.3V  
Max.  
Unit  
pF  
CIN  
Input Capacitance  
I/O Capacitance  
8
8
COUT  
pF  
Notes:  
2. V (min.) = –2.0V and V (max) = V + 0.5V for pulse durations of less than 20 ns.  
IL  
IH  
CC  
3. Tested initially and after any design or process changes that may affect these parameters.  
Document #: 38-05134 Rev. *H  
Page 4 of 12  
CY7C1041CV33  
Thermal Resistance[3]  
Parameter  
ΘJA  
Description  
Test Conditions  
TSOP-II  
42.96  
FBGA  
38.15  
9.15  
SOJ  
Unit  
Thermal Resistance (Junction to Ambient) Test conditions follow standard  
25.99 °C/W  
test methods and procedures for  
measuring thermal impedance,  
per EIA / JESD51.  
ΘJC  
Thermal Resistance (Junction to Case)  
10.75  
18.8  
°C/W  
AC Test Loads and Waveforms[4]  
10-ns Devices  
12-, 15-, 20-ns Devices  
R 317Ω  
Z = 50Ω  
3.3V  
OUTPUT  
OUTPUT  
30 pF  
50Ω  
30 pF*  
R2  
351Ω  
* CAPACITIVE LOAD CONSISTS  
OF ALL COMPONENTS OF THE  
TEST ENVIRONMENT  
1.5V  
(b)  
(a)  
High-Z Characteristics  
R 317Ω  
ALL INPUT PULSES  
3.0V  
3.3V  
OUTPUT  
5 pF  
90%  
90%  
10%  
10%  
GND  
R2  
351Ω  
(d)  
(c)  
Fall Time: 1 V/ns  
Rise Time: 1 V/ns  
AC Switching Characteristics[5] Over the Operating Range  
-10  
-12  
-15  
-20  
Parameter  
Description  
Min.  
Max.  
Min.  
Max.  
Min.  
Max.  
Min.  
Max.  
Unit  
Read Cycle  
[6]  
tpower  
VCC(typical) to the first access  
Read Cycle Time  
100  
10  
100  
12  
100  
15  
100  
20  
µs  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tRC  
tAA  
Address to Data Valid  
Data Hold from Address Change  
CE LOW to Data Valid  
OE LOW to Data Valid  
OE LOW to Low-Z  
OE HIGH to High-Z[7, 8]  
CE LOW to Low-Z[8]  
CE HIGH to High-Z[7, 8]  
CE LOW to Power-Up  
CE HIGH to Power-Down  
Byte Enable to Data Valid  
Byte Enable to Low-Z  
Byte Disable to High-Z  
10  
12  
15  
20  
tOHA  
tACE  
tDOE  
tLZOE  
tHZOE  
tLZCE  
tHZCE  
tPU  
3
3
3
3
10  
5
12  
6
15  
7
20  
8
0
3
0
0
3
0
0
3
0
0
3
0
5
5
6
6
7
7
8
8
tPD  
10  
5
12  
6
15  
7
20  
8
tDBE  
tLZBE  
0
0
0
0
tHZBE  
6
6
7
8
Notes:  
4. AC characteristics (except High-Z) for 10-ns parts are tested using the load conditions shown in Figure (a). All other speeds are tested using the Thevenin load  
shown in Figure (b). High-Z characteristics are tested for all speeds using the test load shown in Figure (d).  
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V.  
6. t  
7. t  
gives the minimum amount of time that the power supply should be at typical V values until the first memory access can be performed.  
POWER  
CC  
, t  
, and t  
are specified with a load capacitance of 5 pF as in part (d) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage  
HZWE  
HZOE HZCE  
8. At any given temperature and voltage condition, t  
is less than t  
, t  
is less than t  
, and t  
is less than t  
for any given device.  
HZCE  
LZCE HZOE  
LZOE  
HZWE  
LZWE  
9. The internal Write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a Write, and the transition of  
either of these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the  
Write.  
Document #: 38-05134 Rev. *H  
Page 5 of 12  
CY7C1041CV33  
AC Switching Characteristics[5] Over the Operating Range (continued)  
-10 -12  
-15  
-20  
Parameter  
Description  
Min.  
Max.  
Min.  
Max.  
Min.  
Max.  
Min.  
Max.  
Unit  
Write Cycle[9, 10]  
tWC  
tSCE  
tAW  
Write Cycle Time  
10  
7
12  
8
15  
10  
10  
0
20  
10  
10  
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
CE LOW to Write End  
Address Set-Up to Write End  
Address Hold from Write End  
Address Set-Up to Write Start  
WE Pulse Width  
7
8
tHA  
0
0
tSA  
0
0
0
0
tPWE  
tSD  
7
8
10  
7
10  
8
Data Set-Up to Write End  
Data Hold from Write End  
WE HIGH to Low-Z[7]  
5
6
tHD  
0
0
0
0
tLZWE  
tHZWE  
tBW  
3
3
3
3
WE LOW to High-Z[7, 8]  
5
6
7
8
Byte Enable to End of Write  
7
8
10  
10  
Switching Waveforms  
Read Cycle No. 1[11, 12]  
t
RC  
ADDRESS  
t
AA  
t
OHA  
DATA OUT  
PREVIOUS DATA VALID  
DATA VALID  
Read Cycle No. 2 (OE Controlled)[12, 13]  
ADDRESS  
t
RC  
CE  
t
ACE  
OE  
t
HZOE  
t
DOE  
BHE, BLE  
t
LZOE  
t
HZCE  
t
DBE  
t
LZBE  
t
HZBE  
HIGH  
IMPEDANCE  
HIGH IMPEDANCE  
DATA OUT  
VCC  
SUPPLY  
CURRENT  
DATA VALID  
t
LZCE  
t
PD  
I
CC
t
PU  
50%  
50%  
I
SB  
Notes:  
10. The minimum Write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of t  
and t  
.
HZWE  
SD  
11. Device is continuously selected. OE, CE, BHE and/or BHE = V .  
IL  
12. WE is HIGH for Read cycle.  
13. Address valid prior to or coincident with CE transition LOW.  
Document #: 38-05134 Rev. *H  
Page 6 of 12  
CY7C1041CV33  
Switching Waveforms (continued)  
Write Cycle No. 1 (CE Controlled)[14, 15]  
t
WC  
ADDRESS  
t
SA  
t
SCE  
CE  
t
AW  
t
HA  
t
PWE  
WE  
t
BW  
BHE, BLE  
t
t
SD  
HD  
DATA I/O  
Write Cycle No. 2 (BLE or BHE Controlled)  
t
WC  
ADDRESS  
t
SA  
t
BW  
BHE, BLE  
t
AW  
t
HA  
t
PWE  
WE  
CE  
t
SCE  
t
t
HD  
SD  
DATA I/O  
Notes:  
14. Data I/O is high-impedance if OE or BHE and/or BLE = V  
.
IH  
15. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.  
Document #: 38-05134 Rev. *H  
Page 7 of 12  
CY7C1041CV33  
Switching Waveforms (continued)  
Write Cycle No. 2 (WE Controlled, OE LOW)  
t
WC  
ADDRESS  
CE  
t
SCE  
t
AW  
t
HA  
t
SA  
t
PWE  
WE  
t
BW  
BHE, BLE  
t
HZWE  
t
t
SD  
HD  
DATA I/O  
t
LZWE  
Truth Table  
CE  
H
L
OE WE BLE  
BHE  
X
I/O0–I/O7  
High-Z  
I/O8–I/O15  
Mode  
Power  
X
L
X
H
H
H
L
X
L
High-Z  
Data Out  
High-Z  
Power-down  
Read All Bits  
Standby (ISB)  
L
Data Out  
Data Out  
High-Z  
Active (ICC  
Active (ICC  
Active (ICC  
Active (ICC  
Active (ICC  
Active (ICC  
Active (ICC  
)
)
)
)
)
)
)
L
L
L
H
L
Read Lower Bits Only  
Read Upper Bits Only  
Write All Bits  
L
L
H
L
Data Out  
Data In  
High-Z  
Data In  
High-Z  
L
X
X
X
H
L
Data In  
Data In  
High-Z  
L
L
L
H
L
Write Lower Bits Only  
Write Upper Bits Only  
Selected, Outputs Disabled  
L
L
H
X
L
H
X
High-Z  
Document #: 38-05134 Rev. *H  
Page 8 of 12  
CY7C1041CV33  
Ordering Information  
Speed  
Package  
Diagram  
Operating  
Range  
(ns)  
Ordering Code  
Package Type  
48-ball Fine Pitch BGA  
10  
CY7C1041CV33-10BAC  
CY7C1041CV33-10BAXC  
CY7C1041CV33-10VC  
CY7C1041CV33-10VXC  
CY7C1041CV33-10ZC  
CY7C1041CV33-10ZXC  
CY7C1041CV33-10BAI  
CY7C1041CV33-10BAXI  
CY7C1041CV33-10ZI  
CY7C1041CV33-10ZXI  
CY7C1041CV33-10ZSXA  
CY7C1041CV33-10BAXA  
CY7C1041CV33-12VC  
CY7C1041CV33-12VXC  
CY7C1041CV33-12ZC  
CY7C1041CV33-12ZXC  
CY7C1041CV33-12VXI  
CY7C1041CV33-12ZI  
CY7C1041CV33-12ZXI  
CY7C1041CV33-15VC  
CY7C1041CV33-15VXC  
CY7C1041CV33-15ZC  
CY7C1041CV33-15ZXC  
CY7C1041CV33-15VI  
CY7C1041CV33-15VXI  
CY7C1041CV33-15ZI  
CY7C1041CV33-15ZXI  
CY7C1041CV33-20ZC  
CY7C1041CV33-20ZXC  
CY7C1041CV33-20ZSXA  
CY7C1041CV33-20VE  
CY7C1041CV33-20VXE  
CY7C1041CV33-20ZE  
CY7C1041CV33-20ZSXE  
51-85106  
51-85082  
51-85087  
51-85106  
51-85087  
Commercial  
48-ball Fine Pitch BGA (Pb-Free)  
44-lead (400-mil) Molded SOJ  
44-lead (400-mil) Molded SOJ (Pb-Free)  
44-pin TSOP II  
44-pin TSOP II (Pb-Free)  
48-ball Fine Pitch BGA  
Industrial  
48-ball Fine Pitch BGA (Pb-Free)  
44-pin TSOP II  
44-pin TSOP II (Pb-Free)  
44-pin TSOP II (Pb-Free)  
48-ball Fine Pitch BGA (Pb-Free)  
44-lead (400-mil) Molded SOJ  
44-lead (400-mil) Molded SOJ (Pb-Free)  
44-pin TSOP II  
Automotive-A  
Commercial  
51-85106  
51-85082  
12  
51-85087  
44-pin TSOP II (Pb-Free)  
44-lead (400-mil) Molded SOJ (Pb-Free)  
44-pin TSOP II  
51-85082  
51-85087  
Industrial  
44-pin TSOP II (Pb-Free)  
44-lead (400-mil) Molded SOJ  
44-lead (400-mil) Molded SOJ (Pb-Free)  
44-pin TSOP II  
15  
51-85082  
51-85087  
51-85082  
51-85087  
51-85087  
Commercial  
44-pin TSOP II (Pb-Free)  
44-lead (400-mil) Molded SOJ  
44-lead (400-mil) Molded SOJ (Pb-Free)  
44-pin TSOP II  
Industrial  
44-pin TSOP II (Pb-Free)  
44-pin TSOP II  
20  
Commercial  
44-pin TSOP II (Pb-Free)  
44-pin TSOP II (Pb-Free)  
44-lead (400-mil) Molded SOJ  
44-lead (400-mil) Molded SOJ (Pb-Free)  
44-pin TSOP II  
Automotive-A  
Automotive-E  
51-85082  
51-85087  
44-pin TSOP II (Pb-Free)  
Please contact your local Cypress sales representative for availability of these parts  
Document #: 38-05134 Rev. *H  
Page 9 of 12  
CY7C1041CV33  
Package Diagrams  
48-Ball (7.00 mm x 8.5 mm x 1.2 mm) FBGA (51-85106)  
BOTTOM VIEW  
TOP VIEW  
A1 CORNER  
Ø0.05 M C  
Ø0.25 M C A B  
Ø0.30 0.05ꢀ(48X  
A1 CORNER  
1
2
3
(
5
6
6
5
(
3
2
1
A
A
B
C
D
E
B
C
D
E
F
F
G
G
H
H
1.475  
A
A
0.75  
B
7.00 0.10  
3.75  
B
7.00 0.10  
0.15ꢀ(8X  
51-85106-*E  
SEATING PLANE  
C
Document #: 38-05134 Rev. *H  
Page 10 of 12  
CY7C1041CV33  
Package Diagrams (continued)  
44-lead (400-mil) Molded SOJ (51-85082)  
51-85082-*B  
44-pin TSOP II (51-85087)  
51-85087-*A  
All products and company names mentioned in this document may be the trademarks of their respective holders.  
Document #: 38-05134 Rev. *H  
Page 11 of 12  
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use  
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be  
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its  
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress  
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
CY7C1041CV33  
Document History Page  
Document Title: CY7C1041CV33 4-Mbit (256K x 16) Static RAM  
Document Number: 38-05134  
Orig. of  
REV.  
**  
ECN NO. Issue Date Change  
Description of Change  
109513  
112440  
112859  
12/13/01  
12/20/01  
03/25/02  
HGK  
BSS  
DFP  
New Data Sheet  
*A  
Updated 51-85106 from revision *A to *C  
*B  
Added CY7C1042CV33 in BGA package  
Removed 1042 BGA option pin ACC Final Data Sheet  
Add applications foot note to data sheet  
Added 20-ns speed bin  
*C  
*D  
*E  
116477  
119797  
262949  
09/16/02  
10/21/02  
See ECN  
CEA  
DFP  
RKF  
1) Added Lead (Pb)-Free parts in the Ordering info (Page #9)  
2) Added Automotive Specs to Datasheet  
*F  
361795  
435387  
See ECN  
See ECN  
SYT  
NXR  
Added Pb-Free offerings in the Ordering Information  
*G  
Removed -8 Speed bin from Product offering.  
Corrected typo in description for BHE/BLE in pin definitions table on Page# 3  
corrected ther Pin name from OE2 to OE.  
Included the Maximum Ratings for Static Discharge Voltage and Latch up  
Current.  
Changed the description of IIX current from Input Load Current to  
Input Leakage Current  
Added note# 4 on page# 4  
Updated the Ordering Information table  
*H  
499153  
See ECN  
NXR  
Added Automotive-A Operating Range  
Changed tpower value from 1 µs to 100 µs  
Updated Ordering Information table  
Document #: 38-05134 Rev. *H  
Page 12 of 12  

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