CY7C1370DV25-167BZI [ROCHESTER]
512KX36 ZBT SRAM, 3.4ns, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, MO-216, FBGA-165;
| 型号： | CY7C1370DV25-167BZI |
| 厂家： | 
Rochester Electronics |
| 描述： | 512KX36 ZBT SRAM, 3.4ns, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, MO-216, FBGA-165 静态存储器 内存集成电路 |
| 文件： | 总30页 (文件大小：1595K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1370DV25
CY7C1372DV25
18-Mbit (512 K × 36/1 M × 18)
Pipelined SRAM with NoBL™ Architecture
18-Mbit (512
K × 36/1 M × 18) Pipelined SRAM with NoBL™ Architecture
Features
Functional Description
The CY7C1370DV25 and CY7C1372DV25 are 2.5 V, 512 K × 36
■ Pin-compatible and functionally equivalent to ZBT™
and 1-Mbit × 18 synchronous pipelined burst SRAMs with No
Bus Latency™ (NoBL logic, respectively. They are designed
to support unlimited true back-to-back read/write operations with
no wait states. The CY7C1370DV25 and CY7C1372DV25 are
equipped with the advanced NoBL logic required to enable
consecutive read/write operations with data being transferred on
every clock cycle. This feature dramatically improves the
throughput of data in systems that require frequent write/read
transitions. The CY7C1370DV25 and CY7C1372DV25 are
pin-compatible and functionally equivalent to ZBT devices.
■ Supports 250-MHz bus operations with zero wait states
❐ Available speed grades are 250, 200 and 167 MHz
■ Internally self-timed output buffer control to eliminate the need
to use asynchronous OE
■ Fully registered (inputs and outputs) for pipelined operation
■ Byte write capability
■ Single 2.5 V core power supply (VDD
)
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. All data outputs pass through output
registers controlled by the rising edge of the clock. The clock
input is qualified by the clock enable (CEN) signal, which when
deasserted suspends operation and extends the previous clock
cycle.
■ 2.5 V I/O power supply (VDDQ
)
■ Fast clock-to-output times
❐ 2.6 ns (for 250-MHz device)
■ Clock enable (CEN) pin to suspend operation
■ Synchronous self-timed writes
Write operations are controlled by the byte write selects
(BWa–BWd for CY7C1370DV25 and BWa–BWb for
CY7C1372DV25) and a write enable (WE) input. All writes are
conducted with on-chip synchronous self-timed write circuitry.
■ Available in JEDEC-standard Pb-free 100-pin TQFP, Pb-free
and non-Pb-free 119-ball BGA and 165-ball FBGA packages
■ IEEE 1149.1 JTAG-Compatible Boundary Scan
■ Burst capability—linear or interleaved burst order
■ “ZZ” sleep mode option and stop clock option
Three synchronous chip enables (CE1, CE2, CE3) and an
asynchronous output enable (OE) provide for easy bank
selection and output three-state control. In order to avoid bus
contention, the output drivers are synchronously three-stated
during the data portion of a write sequence.
Logic Block Diagram - CY7C1370DV25 (512 K × 36)
ADDRESS
REGISTER 0
A0, A1, A
A1
A0
A1'
A0'
D1
D0
Q1
Q0
BURST
LOGIC
MODE
C
ADV/LD
C
CLK
CEN
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
REGISTER 2
O
U
T
P
O
U
T
P
S
E
N
S
D
A
T
U
T
U
T
ADV/LD
A
E
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
R
E
G
I
MEMORY
ARRAY
B
U
F
S
T
E
E
R
I
DQs
DQP
DQP
DQP
DQP
WRITE
DRIVERS
BW
BW
a
a
b
c
d
A
M
P
b
BW
BW
c
S
T
E
R
S
F
d
E
R
S
S
WE
E
E
N
G
INPUT
REGISTER 1
INPUT
REGISTER 0
E
E
OE
READ LOGIC
CE1
CE2
CE3
SLEEP
CONTROL
ZZ
Cypress Semiconductor Corporation
Document Number: 38-05558 Rev. *F
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised September 21, 2010
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CY7C1370DV25
CY7C1372DV25
Logic Block Diagram - CY7C1372DV25 (1 M × 18)
ADDRESS
REGISTER 0
A0, A1, A
A1
A0
A1'
A0'
D1
D0
Q1
Q0
BURST
LOGIC
MODE
C
ADV/LD
C
CLK
CEN
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
REGISTER 2
O
U
T
P
O
U
T
P
S
E
N
S
D
A
T
U
T
U
T
ADV/LD
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
A
R
E
G
I
MEMORY
ARRAY
E
B
DQs
U
WRITE
DRIVERS
BW
BW
a
S
T
E
E
R
I
A
M
P
F
F
E
R
S
DQP
DQP
a
b
S
T
E
R
S
b
S
N
G
WE
E
E
INPUT
REGISTER 1
INPUT
REGISTER 0
E
E
OE
READ LOGIC
CE1
CE2
CE3
Sleep
Control
ZZ
Document Number: 38-05558 Rev. *F
Page 2 of 29
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CY7C1370DV25
CY7C1372DV25
Contents
Selection Guide ................................................................4
Pin Configurations ...........................................................4
Pin Definitions ..................................................................7
Introduction .......................................................................8
Functional Overview ....................................................8
Sleep Mode .................................................................9
Interleaved Burst Address Table
Scan Register Sizes .......................................................15
Identification Register Definitions ................................15
Identification Codes .......................................................16
119-ball BGA Boundary Scan Order .............................16
165-ball FBGA Boundary Scan Order ...........................17
Maximum Ratings ...........................................................18
Operating Range .............................................................18
Electrical Characteristics ...............................................18
Capacitance ....................................................................19
Thermal Resistance ........................................................19
Switching Waveforms ....................................................21
Read/Write/Timing .....................................................21
NOP,STALL and DESELECT Cycles ........................22
ZZ Mode Timing ........................................................22
Ordering Information ......................................................23
Ordering Code Definitions .........................................23
Package Diagrams ..........................................................24
Acronyms ........................................................................27
Document Conventions .................................................27
Units of Measure .......................................................27
Document History Page .................................................28
Sales, Solutions, and Legal Information ......................29
Worldwide Sales and Design Support .......................29
Products ....................................................................29
PSoC Solutions .........................................................29
(MODE = Floating or VDD) ...............................................9
Linear Burst Address Table (MODE = GND) ..................9
ZZ Mode Electrical Characteristics .................................9
Truth Table ......................................................................10
Partial Write Cycle Description .....................................10
IEEE 1149.1 Serial Boundary Scan (JTAG) ..................11
Disabling the JTAG Feature ......................................11
TAP Controller State Diagram ......................................11
Test Access Port (TAP) .............................................11
TAP Controller Block Diagram ......................................12
PERFORMING A TAP RESET ..................................12
TAP REGISTERS ......................................................12
TAP Instruction Set ...................................................12
TAP Timing ......................................................................13
TAP AC Switching Characteristics ...............................14
2.5 V TAP AC Test Conditions .......................................15
2.5 V TAP AC Output Load Equivalent .........................15
TAP DC Electrical Characteristics And
Operating Conditions .....................................................15
Document Number: 38-05558 Rev. *F
Page 3 of 29
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CY7C1370DV25
CY7C1372DV25
Selection Guide
250 MHz
2.6
200 MHz
3.0
167 MHz
3.4
Unit
ns
Maximum access time
Maximum operating current
Maximum CMOS standby current
350
300
275
mA
mA
70
70
70
Pin Configurations
100-pin TQFP Pinout
DQPc
DQc
DQc
1
2
3
4
5
6
7
8
NC
NC
NC
DDQ
1
2
3
4
5
6
7
8
A
NC
NC
78
DQPb
DQb
DQb
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
80
79
V
V
DDQ
V
V
V
NC
DQPa
DQa
DQa
DDQ
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DDQ
SS
V
V
V
SS
SS
SS
DQc
DQc
NC
NC
DQb
DQb
DQb
DQb
DQb
DQc
DQc
9
DQb
9
V
V
SS
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
SS
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
SS
SS
V
V
DDQ
DDQ
V
V
DQa
DQa
V
NC
V
ZZ
DDQ
DDQ
DQc
DQc
NC
DQb
DQb
DQb
DQb
NC
V
SS
CY7C1370DV25
(512K × 36)
SS
V
V
DD
NC
DD
CY7C1372DV25
(1M × 18)
NC
NC
V
DD
DD
V
V
SS
SS
ZZ
DQa
DQa
DQd
DQb
DQa
DQa
DQd
DQb
DDQ
V
V
DDQ
V
V
V
DQa
DQa
NC
NC
V
V
DDQ
DDQ
V
V
SS
V
SS
SS
SS
DQd
DQd
DQd
DQd
DQa
DQa
DQb
DQb
DQa DQPb
DQa
NC
V
SS
V
V
SS
SS
SS
V
V
DDQ
DDQ
V
DDQ
DDQ
DQd
DQd
DQPd
DQa
DQa
DQPa
NC
NC
NC
NC
NC
NC
Document Number: 38-05558 Rev. *F
Page 4 of 29
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CY7C1370DV25
CY7C1372DV25
Pin Configurations (continued)
119-ball BGA
Pinout
CY7C1370DV25 (512 K × 36)
1
2
3
4
5
6
7
VDDQ
A
A
A
A
A
VDDQ
A
NC/576M
NC/1G
DQc
CE2
A
A
A
ADV/LD
VDD
A
A
CE3
A
NC
NC
B
C
D
DQPc
VSS
NC
VSS
DQPb
DQb
DQc
VDDQ
DQc
DQc
DQc
DQc
DQc
VDD
VSS
VSS
CE1
VSS
VSS
DQb
DQb
DQb
DQb
VDD
DQb
VDDQ
DQb
DQb
VDDQ
DQa
DQa
VDDQ
DQa
DQa
E
F
OE
A
G
H
J
BWc
VSS
NC
BWb
VSS
NC
DQc
WE
VDD
VDDQ
DQd
DQd
VDDQ
DQd
DQd
DQd
DQd
DQd
DQd
DQPd
VSS
BWd
VSS
CLK
NC
VSS
BWa
VSS
VSS
VSS
DQa
DQa
DQa
DQa
DQPa
K
L
M
N
P
CEN
A1
VSS
VSS
MODE
A
A0
NC/144M
NC
A
VDD
A
A
NC/288M
ZZ
R
T
NC
A
NC/72M
TMS
NC/36M
NC
VDDQ
TDI
TCK
TDO
VDDQ
U
CY7C1372DV25 (1 M x 18)
1
2
3
4
5
6
7
VDDQ
A
A
A
A
A
VDDQ
A
B
C
D
E
F
NC/576M
NC/1G
DQb
CE2
A
A
A
NC
NC
CE3
A
ADV/LD
VDD
A
A
NC
DQb
NC
VSS
VSS
VSS
NC
VSS
VSS
VSS
DQPa
NC
NC
NC
DQa
VDDQ
CE1
VDDQ
DQa
OE
A
NC
DQb
VDDQ
DQb
NC
VDD
NC
VSS
NC
NC
DQa
VDD
DQa
NC
VDDQ
G
H
J
BWb
VSS
NC
WE
VDD
NC
DQb
DQb
NC
VSS
NC
CLK
NC
VSS
NC
DQa
NC
DQa
NC
A
DQa
NC
K
L
BWa
VSS
VDDQ
DQb
DQb
NC
VSS
VSS
VSS
MODE
A
VDDQ
NC
M
N
P
R
T
CEN
A1
VSS
VSS
NC
A
NC
DQPb
A
A0
DQa
NC/144M
NC/72M
VDDQ
VDD
NC/36M
TCK
NC/288M
ZZ
A
A
TMS
TDI
TDO
NC
VDDQ
U
Document Number: 38-05558 Rev. *F
Page 5 of 29
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CY7C1370DV25
CY7C1372DV25
Pin Configurations (continued)
165-ball FBGA Pinout
CY7C1370DV25 (512 K × 36)
1
2
A
3
4
5
6
7
8
9
A
10
A
11
NC
NC/576M
NC/1G
DQPc
ADV/LD
A
B
C
D
CE1
BWc
BWd
VSS
VDD
BWb
BWa
VSS
VSS
CE3
CLK
VSS
VSS
CEN
WE
A
CE2
VDDQ
VDDQ
OE
VSS
VDD
A
A
NC
NC
DQc
VSS
VSS
VDDQ
VDDQ
NC
DQb
DQPb
DQb
DQc
DQc
DQc
DQc
NC
DQc
DQc
DQc
NC
VDDQ
VDDQ
VDDQ
NC
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
NC
DQb
DQb
DQb
NC
DQb
DQb
DQb
ZZ
E
F
G
H
J
DQd
DQd
DQd
DQd
DQd
DQd
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DQa
DQa
DQa
DQa
DQa
DQa
K
L
DQd
DQd
NC
VDDQ
VDDQ
A
VDD
VSS
A
VSS
NC
VSS
NC
A1
VSS
NC
VDD
VSS
A
VDDQ
VDDQ
A
DQa
NC
A
DQa
DQPa
M
N
P
DQPd
NC/144M NC/72M
MODE NC/36M
TDI
TDO
NC/288M
A
A
TMS
A0
TCK
A
A
A
A
R
CY7C1372DV25 (1 M × 18)
1
NC/576M
NC/1G
NC
2
A
3
4
5
NC
6
CE3
7
8
9
A
10
A
11
A
A
B
C
D
CE1
BWb
NC
CEN
ADV/LD
A
CE2
VDDQ
VDDQ
BWa
VSS
VSS
CLK
VSS
VSS
A
A
NC
WE
VSS
VSS
OE
VSS
VDD
NC
DQb
VSS
VDD
VDDQ
VDDQ
NC
NC
DQPa
DQa
NC
NC
NC
DQb
DQb
DQb
NC
VDDQ
VDDQ
VDDQ
NC
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
NC
NC
NC
DQa
DQa
DQa
ZZ
E
F
NC
NC
G
H
J
NC
NC
DQb
DQb
DQb
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DQa
DQa
DQa
NC
NC
NC
K
L
NC
NC
DQb
NC
NC
VDDQ
VDDQ
A
VDD
VSS
A
VSS
NC
VSS
NC
A1
VSS
NC
VDD
VSS
A
VDDQ
VDDQ
A
DQa
NC
A
NC
NC
M
N
P
DQPb
NC/144M NC/72M
MODE NC/36M
TDI
TDO
NC/288M
A
A
TMS
A0
TCK
A
A
A
A
R
Document Number: 38-05558 Rev. *F
Page 6 of 29
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CY7C1370DV25
CY7C1372DV25
Pin Definitions
Pin Name
I/O Type
Input-
synchronous the CLK.
Pin Description
A0
A1
A
Address inputs used to select one of the address locations. Sampled at the rising edge of
BWa
BWb
BWc
BWd
Input-
Byte write select inputs, active LOW. Qualified with WE to conduct writes to the SRAM.
synchronous Sampled on the rising edge of CLK. BWa controls DQa and DQPa, BWb controls DQb and DQPb,
BWc controls DQc and DQPc, BWd controls DQd and DQPd.
WE
Input-
Write enable input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This
synchronous signal must be asserted LOW to initiate a write sequence.
ADV/LD
Input- Advance/load input used to advance the on-chip address counter or load a new address.
synchronous When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a
new address can be loaded into the device for an access. After being deselected, ADV/LD should
be driven LOW in order to load a new address.
CLK
CE1
CE2
CE3
OE
Input-
clock
Clock input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN.
CLK is only recognized if CEN is active LOW.
Input-
Chip enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
synchronous CE2 and CE3 to select/deselect the device.
Input-
Chip enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction
synchronous with CE1 and CE3 to select/deselect the device.
Input-
Chip enable 3 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
synchronous CE1 and CE2 to select/deselect the device.
Input-
Output enable, active LOW. Combined with the synchronous logic block inside the device to
asynchronous control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs.
When deasserted HIGH, I/O pins are three-stated, and act as input data pins. OE is masked
during the data portion of a write sequence, during the first clock when emerging from a
deselected state and when the device has been deselected.
CEN
DQS
Input-
Clock enable input, active LOW. When asserted LOW the clock signal is recognized by the
synchronous SRAM. When deasserted HIGH the clock signal is masked. Since deasserting CEN does not
deselect the device, CEN can be used to extend the previous cycle when required.
I/O-
Bidirectional data I/O lines. As inputs, they feed into an on-chip data register that is triggered
synchronous by the rising edge of CLK. As outputs, they deliver the data contained in the memory location
specified by A[17:0] during the previous clock rise of the read cycle. The direction of the pins is
controlled by OE and the internal control logic. When OE is asserted LOW, the pins can behave
as outputs. When HIGH, DQa–DQd are placed in a three-state condition. The outputs are
automatically three-stated during the data portion of a write sequence, during the first clock when
emerging from a deselected state, and when the device is deselected, regardless of the state of
OE.
DQPX
MODE
TDO
TDI
I/O-
Bidirectional data parity I/O lines. Functionally, these signals are identical to DQs. During write
synchronous sequences, DQPa is controlled by BWa, DQPb is controlled by BWb, DQPc is controlled by BWc,
and DQPd is controlled by BWd.
Input strap pin Mode input. Selects the burst order of the device. Tied HIGH selects the interleaved burst order.
Pulled LOW selects the linear burst order. MODE should not change states during operation.
When left floating MODE will default HIGH, to an interleaved burst order.
JTAG serial Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK.
output
synchronous
JTAG serial Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK.
input
synchronous
TMS
TCK
Test mode This pin controls the Test access port state machine. Sampled on the rising edge of TCK.
select
synchronous
JTAG-clock Clock input to the JTAG circuitry.
Document Number: 38-05558 Rev. *F
Page 7 of 29
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CY7C1370DV25
CY7C1372DV25
Pin Definitions (continued)
Pin Name
VDD
I/O Type
Pin Description
Power supply Power supply inputs to the core of the device.
VDDQ
I/O power Power supply for the I/O circuitry.
supply
VSS
NC
Ground
Ground for the device. Should be connected to ground of the system.
No connects. This pin is not connected to the die.
–
–
NC/(36M,72M,
144M, 288M,
576M, 1G)
These pins are not connected. They will be used for expansion to the 36M, 72M, 144M, 288M,
576M, and 1G densities.
ZZ
Input-
ZZ “Sleep” Input. This active HIGH input places the device in a non-time critical “sleep”
asynchronous condition with data integrity preserved. For normal operation, this pin has to be LOW or left
floating. ZZ pin has an internal pull-down.
control logic. OE must be driven LOW in order for the device to
drive out the requested data. During the second clock, a
Introduction
subsequent operation (read/write/deselect) can be initiated.
Deselecting the device is also pipelined. Therefore, when the
SRAM is deselected at clock rise by one of the chip enable
signals, its output will three-state following the next clock rise.
Functional Overview
The
CY7C1370DV25
and
CY7C1372DV25
are
synchronous-pipelined Burst NoBL SRAMs designed
specifically to eliminate wait states during write/read transitions.
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. The clock signal is qualified with the
clock enable input signal (CEN). If CEN is HIGH, the clock signal
is not recognized and all internal states are maintained. All
synchronous operations are qualified with CEN. All data outputs
pass through output registers controlled by the rising edge of the
clock. Maximum access delay from the clock rise (tCO) is 2.6 ns
(250-MHz device).
Burst Read Accesses
The CY7C1370DV25 and CY7C1372DV25 have an on-chip
burst counter that allows the user the ability to supply a single
address and conduct up to four reads without reasserting the
address inputs. ADV/LD must be driven LOW in order to load a
new address into the SRAM, as described in the Single Read
Accesses section above. The sequence of the burst counter is
determined by the MODE input signal. A LOW input on MODE
selects a linear burst mode, a HIGH selects an interleaved burst
sequence. Both burst counters use A0 and A1 in the burst
sequence, and will wrap around when incremented sufficiently.
A HIGH input on ADV/LD will increment the internal burst counter
regardless of the state of chip enables inputs or WE. WE is
latched at the beginning of a burst cycle. Therefore, the type of
access (read or write) is maintained throughout the burst
sequence.
Accesses can be initiated by asserting all three chip enables
(CE1, CE2, CE3) active at the rising edge of the clock. If clock
enable (CEN) is active LOW and ADV/LD is asserted LOW, the
address presented to the device will be latched. The access can
either be a read or write operation, depending on the status of
the write enable (WE). BWX can be used to conduct byte write
operations.
Write operations are qualified by the write enable (WE). All writes
are simplified with on-chip synchronous self-timed write circuitry.
Single Write Accesses
Three synchronous chip enables (CE1, CE2, CE3) and an
asynchronous output enable (OE) simplify depth expansion. All
operations (reads, writes, and deselects) are pipelined. ADV/LD
should be driven LOW once the device has been deselected in
order to load a new address for the next operation.
Write access are initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are all asserted active, and (3) the write signal WE is
asserted LOW. The address presented is loaded into the
address register. The write signals are latched into the control
logic block.
Single Read Accesses
On the subsequent clock rise the data lines are automatically
three-stated regardless of the state of the OE input signal. This
allows the external logic to present the data on DQ and DQP
(DQa,b,c,d/DQPa,b,c,d for CY7C1370DV25 and DQa,b/DQPa,b for
CY7C1372DV25). In addition, the address for the subsequent
access (read/write/deselect) is latched into the address register
(provided the appropriate control signals are asserted).
A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are all asserted active, (3) the write enable input signal
WE is deasserted HIGH, and (4) ADV/LD is asserted LOW. The
address presented to the address inputs is latched into the
address register and presented to the memory core and control
logic. The control logic determines that a read access is in
progress and allows the requested data to propagate to the input
of the output register. At the rising edge of the next clock the
requested data is allowed to propagate through the output
register and onto the data bus within 2.6 ns (250-MHz device)
provided OE is active LOW. After the first clock of the read
access the output buffers are controlled by OE and the internal
On the next clock rise the data presented to DQ and DQP
(DQa,b,c,d/DQPa,b,c,d for CY7C1370DV25 & DQa,b/DQPa,b for
CY7C1372DV25) (or a subset for byte write operations, see
Write Cycle Description table for details) inputs is latched into the
device and the write is complete.
Document Number: 38-05558 Rev. *F
Page 8 of 29
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CY7C1370DV25
CY7C1372DV25
The data written during the write operation is controlled by BW
(BWa,b,c,d for CY7C1370DV25 and BWa,b for CY7C1372DV25)
signals. The CY7C1370DV25/CY7C1372DV25 provides byte
write capability that is described in the Write Cycle Description
table. Asserting the write enable input (WE) with the selected
byte write select (BW) input will selectively write to only the
desired bytes. Bytes not selected during a byte write operation
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation “sleep” mode. Two clock
cycles are required to enter into or exit from this “sleep” mode.
While in this mode, data integrity is guaranteed. Accesses
pending when entering the “sleep” mode are not considered valid
nor is the completion of the operation guaranteed. The device
must be deselected prior to entering the “sleep” mode. CE1, CE2,
and CE3, must remain inactive for the duration of tZZREC after the
ZZ input returns LOW.
will remain unaltered.
A
synchronous self-timed write
mechanism has been provided to simplify the write operations.
Byte write capability has been included in order to greatly simplify
read/modify/write sequences, which can be reduced to simple
byte write operations.
Interleaved Burst Address Table
(MODE = Floating or V )
Because the CY7C1370DV25 and CY7C1372DV25 are
common I/O devices, data should not be driven into the device
while the outputs are active. The output enable (OE) can be
deasserted HIGH before presenting data to the DQ and DQP
(DQa,b,c,d/DQPa,b,c,d for CY7C1370DV25 and DQa,b/DQPa,b for
CY7C1372DV25) inputs. Doing so will three-state the output
DD
First
Address
Second
Third
Fourth
Address
Address
Address
A1, A0
00
A1, A0
01
A1, A0
10
A1, A0
11
drivers. As
a
safety precaution, DQ and DQP
(DQa,b,c,d/DQPa,b,c,d for CY7C1370DV25 and DQa,b/DQPa,b for
CY7C1372DV25) are automatically three-stated during the data
portion of a write cycle, regardless of the state of OE.
01
00
11
10
10
11
00
01
11
10
01
00
Burst Write Accesses
The CY7C1370DV25/CY7C1372DV25 has an on-chip burst
counter that allows the user the ability to supply a single address
and conduct up to four write operations without reasserting the
address inputs. ADV/LD must be driven LOW in order to load the
initial address, as described in the Single Write Accesses section
above. When ADV/LD is driven HIGH on the subsequent clock
rise, the chip enables (CE1, CE2, and CE3) and WE inputs are
ignored and the burst counter is incremented. The correct BW
(BWa,b,c,d for CY7C1370DV25 and BWa,b for CY7C1372DV25)
inputs must be driven in each cycle of the burst write in order to
write the correct bytes of data.
Linear Burst Address Table (MODE = GND)
First
Address
Second
Address
Third
Address
Fourth
Address
A1, A0
00
A1, A0
01
A1, A0
10
A1, A0
11
01
10
11
00
10
11
00
01
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
IDDZZ
Description
Sleep mode standby current
Device operation to ZZ
ZZ recovery time
Test Conditions
Min
Max
Unit
mA
ns
ZZ VDD 0.2 V
–
80
2tCYC
–
tZZS
ZZ VDD 0.2 V
–
2tCYC
–
tZZREC
tZZI
ZZ 0.2 V
ns
ZZ active to sleep current
ZZ Inactive to exit sleep current
This parameter is sampled
This parameter is sampled
2tCYC
–
ns
tRZZI
0
ns
Document Number: 38-05558 Rev. *F
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CY7C1370DV25
CY7C1372DV25
Truth Table[1, 2, 3, 4, 5, 6, 7]
Address
Used
Operation
CE
ZZ
ADV/LD WE BWx
OE
CEN CLK
DQ
Deselect cycle
None
H
X
L
L
L
L
L
L
L
L
L
L
L
L
H
L
H
L
X
X
H
X
H
X
L
X
X
X
X
X
X
L
X
L
L
L
L
L
L
L
L
L
L
H
X
L–H
L–H
L–H
L–H
L–H
L–H
L–H
L–H
L–H
L–H
L–H
X
Tri-state
Tri-state
Data out (Q)
Data out (Q)
Tri-state
Tri-state
Data in (D)
Data in (D)
Tri-state
Tri-state
–
Continue deselect cycle
Read cycle (begin burst)
Read cycle (continue burst)
NOP/dummy read (begin burst)
Dummy read (continue burst)
Write cycle (begin burst)
Write cycle (continue burst)
NOP/write abort (begin burst)
Write abort (continue burst)
Ignore clock edge (stall)
Sleep mode
None
X
L
External
Next
X
L
H
L
L
External
Next
H
H
X
X
X
X
X
X
X
L
H
L
External
Next
X
L
H
L
X
L
L
None
H
H
X
X
Next
X
X
X
H
X
X
X
X
X
Current
None
Tri-state
[1, 2, 3, 8]
Partial Write Cycle Description
Function (CY7C1370DV25)
Read
WE
BWd
X
H
H
H
H
H
H
H
H
L
BWc
X
H
H
H
H
L
BWb
BWa
X
H
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
H
H
L
Write – No bytes written
Write byte a – (DQa and DQPa)
Write byte b – (DQb and DQPb)
Write bytes b, a
H
L
L
Write byte c – (DQc and DQPc)
Write bytes c, a
H
H
L
H
L
L
Write bytes c, b
L
H
L
Write bytes c, b, a
L
L
Write byte d – (DQd and DQPd)
Write bytes d, a
H
H
H
H
L
H
H
L
H
L
L
Write bytes d, b
L
H
L
Write bytes d, b, a
L
L
Write bytes d, c
L
H
H
L
H
L
Write bytes d, c, a
L
L
Write bytes d, c, b
L
L
H
L
Write all bytes
L
L
L
Notes
1. X = “Don't Care”, H = Logic HIGH, L = Logic LOW, CE stands for all chip enables active. BWx = L signifies at least one Byte Write Select is active, BW = Valid
x
signifies that the desired byte write selects are asserted, see Write Cycle Description table for details.
2. Write is defined by WE and BW . See Write Cycle Description table for details.
X
3. When a write cycle is detected, all I/Os are tri-stated, even during byte writes.
4. The DQ and DQP pins are controlled by the current cycle and the OE signal.
5. CEN = H inserts wait states.
6. Device will power-up deselected and the I/Os in a tri-state condition, regardless of OE.
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles.During a read cycle DQ and DQP = Three-state when
s
X
OE is inactive or when the device is deselected, and DQ = data when OE is active.
s
8. Table only lists a partial listing of the byte write combinations. Any Combination of BW is valid. Appropriate write will be done based on which byte write is active.
X
Document Number: 38-05558 Rev. *F
Page 10 of 29
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CY7C1370DV25
CY7C1372DV25
Function (CY7C1372DV25)
WE
H
L
BWb
BWa
x
Read
x
H
H
L
Write – No bytes Written
Write byte a – (DQa and DQPa)
Write byte b – (DQb and DQPb)
Write both bytes
H
L
L
L
H
L
L
L
Test Access Port (TAP)
IEEE 1149.1 Serial Boundary Scan (JTAG)
Test Clock (TCK)
The CY7C1370DV25/CY7C1372DV25 incorporates a serial
boundary scan test access port (TAP).This part is fully compliant
with 1149.1. The TAP operates using JEDEC-standard 3.3 V or
2.5 V I/O logic levels.
The test clock is used only with the TAP controller. All inputs are
captured on the rising edge of TCK. All outputs are driven from
the falling edge of TCK.
The CY7C1370DV25/CY7C1372DV25 contains
controller, instruction register, boundary scan register, bypass
register, and ID register.
a
TAP
Test Mode Select (TMS)
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to leave
this ball unconnected if the TAP is not used. The ball is pulled up
internally, resulting in a logic HIGH level.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are
internally pulled up and may be unconnected. They may
alternately be connected to VDD through a pull-up resistor. TDO
should be left unconnected. Upon power-up, the device will
come up in a reset state which will not interfere with the operation
of the device.
Test Data-In (TDI)
The TDI ball is used to serially input information into the registers
and can be connected to the input of any of the registers. The
register between TDI and TDO is chosen by the instruction that
is loaded into the TAP instruction register. For information on
loading the instruction register, see TAP Controller State
Diagram. TDI is internally pulled up and can be unconnected if
the TAP is unused in an application. TDI is connected to the most
significant bit (MSB) of any register. (See TAP Controller Block
Diagram on page 12.)
TAP Controller State Diagram
TEST-LOGIC
1
RESET
0
Test Data-Out (TDO)
1
1
1
RUN-TEST/
IDLE
SELECT
DR-SCAN
SELECT
IR-SCAN
0
The TDO output ball is used to serially clock data-out from the
registers. The output is active depending upon the current state
of the TAP state machine. The output changes on the falling edge
of TCK. TDO is connected to the least significant bit (LSB) of any
register. (See TAP Controller State Diagram.)
0
0
1
1
CAPTURE-DR
CAPTURE-IR
0
0
SHIFT-DR
0
SHIFT-IR
0
1
1
1
1
EXIT1-DR
EXIT1-IR
0
0
PAUSE-DR
0
PAUSE-IR
0
1
1
0
0
EXIT2-DR
1
EXIT2-IR
1
UPDATE-DR
UPDATE-IR
1
0
1
0
The 0/1 next to each state represents the value of TMS at the
rising edge of TCK.
Document Number: 38-05558 Rev. *F
Page 11 of 29
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CY7C1370DV25
CY7C1372DV25
The boundary scan register is loaded with the contents of the
RAM I/O ring when the TAP controller is in the Capture-DR state
and is then placed between the TDI and TDO balls when the
controller is moved to the Shift-DR state. The EXTEST,
SAMPLE/PRELOAD and SAMPLE Z instructions can be used to
capture the contents of the I/O ring.
TAP Controller Block Diagram
0
Bypass Register
2
1
0
0
0
Selection
Circuitry
The Boundary Scan Order tables show the order in which the bits
are connected. Each bit corresponds to one of the bumps on the
SRAM package. The MSB of the register is connected to TDI and
the LSB is connected to TDO.
Instruction Register
31 30 29
Identification Register
S
election
TDI
TDO
Circuitr
y
.
.
. 2 1
x
.
.
.
.
. 2 1
Identification (ID) Register
Boundary Scan Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired into
the SRAM and can be shifted out when the TAP controller is in
the Shift-DR state. The ID register has a vendor code and other
information described in the Identification Register Definitions
table.
TCK
TMS
TAP CONTROLLER
TAP Instruction Set
Performing a TAP Reset
Overview
A RESET is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This RESET does not affect the operation of the
SRAM and may be performed while the SRAM is operating.
Eight different instructions are possible with the three bit
instruction register. All combinations are listed in the Instruction
Codes table. Three of these instructions are listed as
RESERVED and should not be used. The other five instructions
are described in detail below.
At power-up, the TAP is reset internally to ensure that TDO
comes up in a high Z state.
Instructions are loaded into the TAP controller during the Shift-IR
state when the instruction register is placed between TDI and
TDO. During this state, instructions are shifted through the
instruction register through the TDI and TDO balls. To execute
the instruction once it is shifted in, the TAP controller needs to be
moved into the Update-IR state.
TAP Registers
Registers are connected between the TDI and TDO balls and
allow data to be scanned into and out of the SRAM test circuitry.
Only one register can be selected at a time through the
instruction register. Data is serially loaded into the TDI ball on the
rising edge of TCK. Data is output on the TDO ball on the falling
edge of TCK.
EXTEST
The EXTEST instruction enables the preloaded data to be driven
out through the system output pins. This instruction also selects
the boundary scan register to be connected for serial access
between the TDI and TDO in the shift-DR controller state.
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the TDI
and TDO balls as shown in the TAP Controller Block Diagram.
Upon power-up, the instruction register is loaded with the
IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as described
in the previous section.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO balls and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state.
When the TAP controller is in the Capture-IR state, the two least
significant bits are loaded with a binary “01” pattern to allow for
fault isolation of the board-level serial test data path.
The IDCODE instruction is loaded into the instruction register
upon power-up or whenever the TAP controller is given a test
logic reset state.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between the
TDI and TDO balls. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW (VSS
when the BYPASS instruction is executed.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register to
be connected between the TDI and TDO balls when the TAP
controller is in a Shift-DR state. It also places all SRAM outputs
into a high Z state.
)
Boundary Scan Register
SAMPLE/PRELOAD
The boundary scan register is connected to all the input and
bidirectional balls on the SRAM.
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the
Document Number: 38-05558 Rev. *F
Page 12 of 29
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CY7C1370DV25
CY7C1372DV25
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is
captured in the boundary scan register.
BYPASS
When the BYPASS instruction is loaded in the instruction register
and the TAP is placed in a Shift-DR state, the bypass register is
placed between the TDI and TDO balls. The advantage of the
BYPASS instruction is that it shortens the boundary scan path
when multiple devices are connected together on a board.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 20 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because there
is a large difference in the clock frequencies, it is possible that
during the Capture-DR state, an input or output will undergo a
transition. The TAP may then try to capture a signal while in
transition (metastable state). This will not harm the device, but
there is no guarantee as to the value that will be captured.
Repeatable results may not be possible.
EXTEST Output Bus Tri-State
IEEE Standard 1149.1 mandates that the TAP controller be able
to put the output bus into a tri-state mode.
The boundary scan register has a special bit located at bit #85
(for 119-BGA package) or bit #89 (for 165-fBGA package). When
this scan cell, called the “extest output bus tri-state,” is latched
into the preload register during the “Update-DR” state in the TAP
controller, it will directly control the state of the output (Q-bus)
pins, when the EXTEST is entered as the current instruction.
When HIGH, it will enable the output buffers to drive the output
bus. When LOW, this bit will place the output bus into a high Z
condition.
To guarantee that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller’s capture set-up plus
hold times (tCS and tCH). The SRAM clock input might not be
captured correctly if there is no way in a design to stop (or slow)
the clock during a SAMPLE/PRELOAD instruction. If this is an
issue, it is still possible to capture all other signals and simply
ignore the value of the CK and CK captured in the boundary scan
register.
This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that cell,
during the “Shift-DR” state. During “Update-DR,” the value
loaded into that shift-register cell will latch into the preload
register. When the EXTEST instruction is entered, this bit will
directly control the output Q-bus pins. Note that this bit is preset
HIGH to enable the output when the device is powered-up, and
also when the TAP controller is in the “Test-Logic-Reset” state.
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the boundary
scan register between the TDI and TDO pins.
PRELOAD allows an initial data pattern to be placed at the
latched parallel outputs of the boundary scan register cells prior
to the selection of another boundary scan test operation.
The shifting of data for the SAMPLE and PRELOAD phases can
occur concurrently when required—that is, while data captured
is shifted out, the preloaded data can be shifted in.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
TAP Timing
1
2
3
4
5
6
Test Clock
(TCK)
t
t
t
TH
CYC
TL
t
t
t
t
TMSS
TDIS
TMSH
Test Mode Select
(TMS)
TDIH
Test Data-In
(TDI)
t
TDOV
t
TDOX
Test Data-Out
(TDO)
DON’T CARE
UNDEFINED
Document Number: 38-05558 Rev. *F
Page 13 of 29
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CY7C1370DV25
CY7C1372DV25
TAP AC Switching Characteristics
Over the Operating Range[9, 10]
Parameter
Clock
tTCYC
tTF
Description
Min
Max
Unit
TCK clock cycle time
TCK clock frequency
TCK clock HIGH time
TCK clock LOW time
50
–
–
20
–
ns
MHz
ns
tTH
20
20
tTL
–
ns
Output Times
tTDOV TCK clock LOW to TDO valid
tTDOX TCK clock LOW to TDO invalid
Set-up Times
tTMSS TMS set-up to TCK clock rise
tTDIS
–
0
10
–
ns
ns
5
5
5
–
–
–
ns
ns
ns
TDI set-up to TCK clock rise
Capture set-up to TCK rise
tCS
Hold Times
tTMSH
tTDIH
TMS hold after TCK clock rise
TDI hold after clock rise
5
5
5
–
–
–
ns
ns
ns
tCH
Capture hold after clock rise
Notes
9.
t
and t refer to the set-up and hold time requirements of latching data from the boundary scan register.
CS CH
10. Test conditions are specified using the load in TAP AC test Conditions. t /t = 1 ns.
R
F
Document Number: 38-05558 Rev. *F
Page 14 of 29
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CY7C1370DV25
CY7C1372DV25
2.5 V TAP AC Test Conditions
2.5 V TAP AC Output Load Equivalent
1.25V
Input pulse levels................................................VSS to 2.5 V
Input rise and fall time .....................................................1 ns
Input timing reference levels........................................ 1.25 V
Output reference levels ............................................... 1.25 V
Test load termination supply voltage ........................... 1.25 V
50
TDO
ZO= 50
20pF
TAP DC Electrical Characteristics And Operating Conditions
(0 °C < TA < +70 °C; VDD = 2.5 V ± 0.125 V unless otherwise noted)[11]
Parameter
VOH1
Description
Test Conditions
Min
2.0
2.1
–
Max
–
Unit
V
Output HIGH voltage IOH = –1.0 mA, VDDQ = 2.5 V
Output HIGH voltage IOH = –100 µA, VDDQ = 2.5 V
Output LOW voltage IOL = 8.0 mA, VDDQ = 2.5 V
VOH2
VOL1
VOL2
VIH
–
V
0.4
0.2
V
Output LOW voltage IOL = 100 µA
Input HIGH voltage
VDDQ = 2.5 V
–
V
VDDQ = 2.5 V
VDDQ = 2.5 V
1.7
–0.3
–5
VDD + 0.3
V
VIL
Input LOW voltage
0.7
5
V
IX
Input load current
GND < VIN < VDDQ
µA
Scan Register Sizes
Bit Size (x18)
Register Name
Bit Size (x36)
Instruction
3
3
Bypass
1
1
ID
32
85
89
32
85
89
Boundary scan order (119-ball BGA package)
Boundary scan order (165-ball FBGA package)
Identification Register Definitions
Instruction Field
Revision number (31:29)
Cypress device ID (28:12)
Cypress JEDEC ID (11:1)
CY7C1372DV25
CY7C1370DV25
Description
Reserved for version number.
000
000
01011001000100101
00000110100
01011001000010101 Reserved for future use.
00000110100
Allows unique identification of
SRAM vendor.
ID register presence (0)
1
1
Indicate the presence of an ID
register.
Note
11.All voltages referenced to V (GND).
SS
Document Number: 38-05558 Rev. *F
Page 15 of 29
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CY7C1370DV25
CY7C1372DV25
Identification Codes
Instruction
EXTEST
Code
Description
000
001
010
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM outputs to high Z state.
IDCODE
Loads the ID register with the vendor ID code and places the register between TDI and
TDO. This operation does not affect SRAM operations.
SAMPLE Z
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a high Z state.
RESERVED
011
100
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Does not affect SRAM operation.
RESERVED
RESERVED
BYPASS
101
110
111
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operations.
119-ball BGA Boundary Scan Order [12, 13]
Bit #
1
Ball ID
Bit #
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
Ball ID
F6
Bit #
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
Ball ID
G4
A4
G3
C3
B2
B3
A3
C2
A2
B1
C1
D2
E1
F2
Bit #
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
Ball ID
L1
H4
T4
T5
T6
R5
L5
2
E7
D7
H7
G6
E6
D6
C7
B7
C6
A6
C5
B5
G5
B6
D4
B4
F4
M2
N1
3
4
P1
5
K1
6
L2
7
R6
U6
R7
T7
P6
N7
M6
L7
N2
P2
8
9
R3
10
11
12
13
14
15
16
17
18
19
20
21
22
T1
R1
T2
L3
R2
K6
P7
N6
L6
G1
H2
D1
E2
G2
H1
J3
T3
L4
N4
P4
K7
J5
M4
A5
K4
E4
Internal
H6
G7
2K
Notes
12. Balls which are NC (No Connect) are pre-set LOW.
13. Bit# 85 is pre-set HIGH.
Document Number: 38-05558 Rev. *F
Page 16 of 29
[+] Feedback
CY7C1370DV25
CY7C1372DV25
165-ball FBGA Boundary Scan Order [14, 15]
Bit #
1
Ball ID
N6
Bit #
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
Ball ID
D10
C11
A11
B11
A10
B10
A9
Bit #
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
Ball ID
G1
D2
E2
2
N7
3
N10
P11
P8
4
F2
5
G2
H1
H3
J1
6
R8
7
R9
8
P9
B9
9
P10
R10
R11
H11
N11
M11
L11
K11
J11
M10
L10
K10
J10
H9
C10
A8
K1
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
L1
B8
M1
J2
A7
B7
K2
B6
L2
A6
M2
N1
N2
P1
B5
A5
A4
B4
R1
R2
P3
B3
A3
A2
R3
P2
H10
G11
F11
E11
D11
G10
F10
E10
B2
C2
R4
P4
B1
A1
N5
P6
C1
D1
R6
Internal
E1
F1
Notes
14. Balls which are NC (No Connect) are pre-set LOW.
15. Bit# 89 is pre-set HIGH.
Document Number: 38-05558 Rev. *F
Page 17 of 29
[+] Feedback
CY7C1370DV25
CY7C1372DV25
DC input voltage.................................. –0.5 V to VDD + 0.5 V
Current into outputs (LOW) ......................................... 20 mA
Maximum Ratings
(Above which the useful life may be impaired. For user
guidelines, not tested.)
Static discharge voltage.......................................... > 2001 V
(per MIL-STD-883, method 3015)
Storage temperature ................................ –65 °C to +150 °C
Latch-up current .................................................... > 200 mA
Ambient temperature with
power applied ........................................... –55 °C to +125 °C
Operating Range
Supply voltage on VDD relative to GND........–0.5 V to +3.6 V
Supply voltage on VDDQ relative to GND....... –0.5 V to +VDD
DC to outputs in tri-state....................–0.5 V to VDDQ + 0.5 V
Ambient
VDD/VDDQ
Range
Temperature
Commercial
Industrial
0 °C to +70 °C
2.5 V ± 5%
–40 °C to +85 °C
Electrical Characteristics
Over the Operating Range[16, 17]
Parameter
VDD
Description
Power supply voltage
I/O supply voltage
Output HIGH voltage
Output LOW voltage
Input HIGH voltage[18] for 2.5 V I/O
Input LOW voltage[18] for 2.5 V I/O
Test Conditions
Min
Max
Unit
V
2.375
2.375
2.0
2.625
VDDQ
VOH
VOL
VIH
VIL
for 2.5 V I/O
VDD
V
for 2.5 V I/O, IOH = 1.0 mA
–
V
for 2.5 V I/O, IOL= 1.0 mA
–
0.4
V
1.7
VDD + 0.3 V
V
–0.3
–5
0.7
5
V
IX
Input leakage current
except ZZ and MODE
GND VI VDDQ
A
Input current of MODE Input = VSS
Input = VDD
–30
–
–
A
A
5
Input current of ZZ
Input = VSS
Input = VDD
–5
–
–
A
30
A
IOZ
IDD
Output leakage current GND VI VDD, output disabled
–5
–
5
A
VDD operating supply
VDD = Max, IOUT = 0 mA,
f = fMAX = 1/tCYC
4.0-ns cycle, 250 MHz
5.0-ns cycle, 200 MHz
6.0-ns cycle, 167 MHz
4.0-ns cycle, 250 MHz
5.0-ns cycle, 200 MHz
6.0-ns cycle, 167 MHz
All speed grades
350
300
275
160
150
140
70
mA
mA
mA
mA
mA
mA
mA
–
–
ISB1
Automatic CE
power-down
current—TTL inputs
Max. VDD, device deselected,
VIN VIH or VIN VIL,
f = fMAX = 1/tCYC
–
–
–
ISB2
Automatic CE
power-down
current—CMOS inputs f = 0
Max. VDD, device deselected,
VIN 0.3 V or VIN > VDDQ 0.3 V,
–
ISB3
Automatic CE
power-down
current—CMOS Inputs f = fMAX = 1/tCYC
Max. VDD, device deselected,
VIN 0.3V or VIN > VDDQ 0.3 V,
4.0-ns cycle, 250 MHz
5.0-ns cycle, 200 MHz
6.0-ns cycle, 167 MHz
All speed grades
–
–
–
–
135
130
125
80
mA
mA
mA
mA
ISB4
Automatic CE
power-down
current—TTL Inputs
Max. VDD, device deselected,
VIN VIH or VIN VIL, f = 0
Notes
16. Overshoot: V (AC) < V +1.5 V (Pulse width less than t
/2), undershoot: V (AC) > –2 V (Pulse width less than t
/2).
CYC
IH
DD
CYC
IL
17. T
: Assumes a linear ramp from 0V to V (min) within 200 ms. During this time V < V and V
< V
.
Power-up
DD
IH
DD
DDQ
DD
18. Tested initially and after any design or process change that may affect these parameters.
Document Number: 38-05558 Rev. *F
Page 18 of 29
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CY7C1370DV25
CY7C1372DV25
Capacitance[19]
100 TQFP
Package
119 BGA
Package
165 FBGA
Unit
Parameter
Description
Test Conditions
Package
CIN
Input capacitance
TA = 25 C, f = 1 MHz,
5
5
5
8
8
8
9
9
9
pF
pF
pF
V
DD = 2.5 V,
DDQ = 2.5 V
CCLK
CI/O
Clock input capacitance
Input/output capacitance
V
Thermal Resistance[19]
100 TQFP
Package
119 BGA
Package
165 FBGA
Package
Parameter
Description
Test Conditions
Unit
JA
Thermal resistance
(junction to ambient)
Test conditions follow standard
test methods and procedures
for measuring thermal
28.66
23.8
20.7
C/W
JC
Thermal resistance
(junction to case)
4.08
6.2
4.0
C/W
impedance, per EIA/JESD51.
AC Test Loads and Waveforms
2.5 V I/O Test Load
R = 1667
2.5 V
OUTPUT
ALL INPUT PULSES
90%
VDDQ
GND
OUTPUT
R = 50
90%
10%
Z = 50
0
10%
L
5 pF
R = 1538
1 ns
1 ns
V = 1.25 V
T
INCLUDING
JIG AND
SCOPE
(c)
(a)
(b)
Note
19. Tested initially and after any design or process change that may affect these parameters.
Document Number: 38-05558 Rev. *F
Page 19 of 29
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CY7C1370DV25
CY7C1372DV25
Switching Characteristics
[20, 21]
Over the Operating Range
–250
–200
–167
Unit
Parameter
Description
Min
Max
Min
Max
Min
Max
[22]
tPower
Clock
tCYC
VCC (typical) to the first access read or write
1
–
1
–
1
–
ms
Clock cycle time
Maximum operating frequency
Clock HIGH
4.0
–
–
250
–
5
–
200
–
6
–
167
–
ns
MHz
ns
FMAX
tCH
–
–
1.7
1.7
2.0
2.0
2.2
2.2
tCL
Clock LOW
–
–
–
ns
Output Times
tCO
Data output valid after CLK rise
OE LOW to output valid
–
–
2.6
2.6
–
–
–
3.0
3.0
–
–
–
3.4
3.4
–
ns
ns
ns
ns
ns
ns
ns
tEOV
tDOH
Data output hold after CLK rise
Clock to high Z[23, 24, 25]
Clock to low Z[23, 24, 25]
OE HIGH to output high Z[23, 24, 25]
OE LOW to output low Z[23, 24, 25]
1.0
–
1.3
–
1.3
–
tCHZ
2.6
–
3.0
–
3.4
–
tCLZ
1.0
–
1.3
–
1.3
–
tEOHZ
tEOLZ
Set-up Times
tAS
2.6
–
3.0
–
3.4
–
0
0
0
Address set-up before CLK rise
Data input set-up before CLK rise
CEN set-up before CLK rise
WE, BWx set-up before CLK rise
ADV/LD set-up before CLK rise
Chip select set-up
1.2
1.2
1.2
1.2
1.2
1.2
–
–
–
–
–
–
1.4
1.4
1.4
1.4
1.4
1.4
–
–
–
–
–
–
1.5
1.5
1.5
1.5
1.5
1.5
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
tDS
tCENS
tWES
tALS
tCES
Hold Times
tAH
Address hold after CLK rise
Data input hold after CLK rise
CEN hold after CLK rise
0.3
0.3
0.3
0.3
0.3
0.3
–
–
–
–
–
–
0.4
0.4
0.4
0.4
0.4
0.4
–
–
–
–
–
–
0.5
0.5
0.5
0.5
0.5
0.5
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
tDH
tCENH
tWEH
WE, BWx hold after CLK rise
ADV/LD hold after CLK rise
Chip select hold after CLK rise
tALH
tCEH
Notes
20. Timing reference 1.25 V when V
= 2.5 V.
DDQ
21. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
22. This part has a voltage regulator internally; t
is the time power needs to be supplied above V minimum initially, before a read or write operation can be
Power
DD
initiated.
23. t
, t
, t
, and t
are specified with AC test conditions shown in (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
EOHZ
CHZ CLZ EOLZ
24. At any given voltage and temperature, t
is less than t
and t
is less than t
to eliminate bus contention between SRAMs when sharing the same
EOHZ
EOLZ
CHZ
CLZ
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve high Z prior to low Z under the same system conditions.
25. This parameter is sampled and not 100% tested.
Document Number: 38-05558 Rev. *F
Page 20 of 29
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CY7C1370DV25
CY7C1372DV25
Switching Waveforms
Read/Write/Timing[26, 27, 28]
1
2
3
4
5
6
7
8
9
10
t
CYC
t
CLK
t
t
t
CENS CENH
CL
CH
CEN
t
t
CES
CEH
CE
ADV/LD
WE
BW
x
A1
A2
A4
CO
A3
A5
A6
A7
ADDRESS
t
t
t
t
DS
DH
t
t
t
DOH
OEV
CLZ
CHZ
t
t
AS
AH
Data
D(A1)
D(A2)
D(A2+1)
Q(A3)
Q(A4)
Q(A4+1)
D(A5)
Q(A6)
In-Out (DQ)
t
OEHZ
t
DOH
t
OELZ
OE
WRITE
D(A1)
WRITE
D(A2)
BURST
WRITE
READ
Q(A3)
READ
Q(A4)
BURST
READ
WRITE
D(A5)
READ
Q(A6)
WRITE
D(A7)
DESELECT
D(A2+1)
Q(A4+1)
DON’T CARE
UNDEFINED
Notes
26. For this waveform ZZ is tied LOW.
27. When CE is LOW, CE is LOW, CE is HIGH and CE is LOW. When CE is HIGH, CE is HIGH or CE is LOW or CE is HIGH.
1
2
3
1
2
3
28. Order of the Burst sequence is determined by the status of the MODE (0 = Linear, 1 = Interleaved). Burst operations are optional.
Document Number: 38-05558 Rev. *F
Page 21 of 29
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CY7C1370DV25
CY7C1372DV25
Switching Waveforms (continued)
NOP,STALL and DESELECT Cycles[29, 30, 31]
1
2
3
4
5
6
7
8
9
10
CLK
CEN
CE
ADV/LD
WE
BWx
A1
A2
A3
A4
A5
ADDRESS
t
CHZ
D(A4)
D(A1)
Q(A2)
Q(A3)
Q(A5)
Data
In-Out (DQ)
WRITE
D(A1)
READ
Q(A2)
STALL
READ
Q(A3)
WRITE
D(A4)
STALL
NOP
READ
Q(A5)
DESELECT
CONTINUE
DESELECT
DON’T CARE
UNDEFINED
ZZ Mode Timing[32, 33]
CLK
t
t
ZZ
ZZREC
ZZ
t
ZZI
I
SUPPLY
I
DDZZ
t
RZZI
ALL INPUTS
(except ZZ)
DESELECT or READ Only
Outputs (Q)
High-Z
DON’T CARE
Notes
29. For this waveform ZZ is tied LOW.
30. When CE is LOW, CE is LOW, CE is HIGH and CE is LOW. When CE is HIGH, CE is HIGH or CE is LOW or CE is HIGH.
1
2
3
1
2
3
31. The Ignore Clock Edge or Stall cycle (Clock 3) illustrated CEN being used to create a pause. A write is not performed during this cycle
32. Device must be deselected when entering ZZ mode. See cycle description table for all possible signal conditions to deselect the device.
33. I/Os are in high Z when exiting ZZ sleep mode.
Document Number: 38-05558 Rev. *F
Page 22 of 29
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CY7C1370DV25
CY7C1372DV25
Ordering Information
Cypress offers other versions of this type of product in different configurations and features. The following table contains only
the list of parts that are currently available.
For a complete listing of all options, visit the Cypress website at www.cypress.com and refer to the product summary page at
http://www.cypress.com/products, or contact your local sales representative.
Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives and distributors. To find the
office closest to you, visit us at http://www.cypress.com/go/datasheet/offices.
Speed
(MHz)
Package
Diagram
Operating
Range
Part and Package Type
Ordering Code
167
CY7C1370DV25-167AXC
CY7C1372DV25-167AXC
CY7C1370DV25-167BZC
CY7C1370DV25-167AXI
CY7C1370DV25-167BZI
CY7C1370DV25-200BZC
CY7C1370DV25-250AXC
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-free
Commercial
51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-free
51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)
51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-free
Industrial
200
250
Commercial
Commercial
Ordering Code Definitions
CY7C 137X V25 - XXX XX
D
X
Temperature Range: X = C or I (C = Commercial; I = Industrial)
Package Type: XX = AX or BZ
AX = 100-pin TQFP (Pb-free)
BZ = 165-ball FPBGA
Speed Grade: XXX = 167 MHz / 200 MHz / 250 MHz
2.5 Volt
Process Technology 90nm
137X
1370 = PL, 512 Kb x 36 (18 Mb)
1372 = PL, 1 Mb x 18 (18 Mb)
CY7C = Cypress SRAMs
Document Number: 38-05558 Rev. *F
Page 23 of 29
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CY7C1370DV25
CY7C1372DV25
Package Diagrams
100-pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm), 51-85050
51-85050 *C
Document Number: 38-05558 Rev. *F
Page 24 of 29
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CY7C1370DV25
CY7C1372DV25
Package Diagrams (continued)
119-ball BGA (14 x 22 x 2.4 mm), 51-85115
51-85115 *C
Document Number: 38-05558 Rev. *F
Page 25 of 29
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CY7C1370DV25
CY7C1372DV25
Package Diagrams (continued)
165-ball FPBGA (13 x 15 x 1.4 mm), 51-85180
51-85180 *C
Document Number: 38-05558 Rev. *F
Page 26 of 29
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CY7C1370DV25
CY7C1372DV25
Acronyms
Document Conventions
Units of Measure
Acronym
CE
Description
chip enable
clock enable
Symbol
ns
Unit of Measure
CEN
FPBGA
JTAG
NoBL
OE
nano seconds
Volts
fine-pitch ball grid array
Joint Test Action Group
No Bus Latency
output enable
V
µA
mA
ms
MHz
pF
W
micro Amperes
milli Amperes
milli seconds
Mega Hertz
pico Farad
Watts
SEL
single event latch-up
test clock
TCK
TDI
test data input
TMS
TDO
TQFP
WE
test mode select
test data output
thin quad flat pack
write enable
°C
degree Celcius
Document Number: 38-05558 Rev. *F
Page 27 of 29
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CY7C1370DV25
CY7C1372DV25
Document History Page
Document Title: CY7C1370DV25/CY7C1372DV25 18-Mbit (512 K × 36/1 M × 18)
Pipelined SRAM with NoBL™ Architecture
Document Number: 38-05558
Orig. of
Change
REV.
ECN No. Issue Date
Description of Change
**
254509
288531
See ECN
See ECN
RKF
New data sheet
*A
SYT
Edited description under “IEEE 1149.1 Serial Boundary Scan (JTAG)” for
non-compliance with 1149.1
Removed 225 Mhz Speed Bin
Added lead-free information for 100-Pin TQFP, 119 BGA and 165 FBGA
package
Added comment of ‘Lead-free BG packages availability’ below the Ordering
Information
*B
326078
See ECN
PCI
Address expansion pins/balls in the pinouts for all packages are modified as
per JEDEC standard
Added description on EXTEST Output Bus Tri-State
Changed description on the Tap Instruction Set Overview and Extest
Changed JA and JC for TQFP Package from 31 and 6 C/W to 28.66 and
4.08 C/W respectively
Changed JA and JC for BGA Packagefrom 45 and 7 C/W to 23.8 and 6.2
C/W respectively
Changed JA and JC for FBGA Package from 46 and 3 C/W to 20.7 and
4.0 C/W respectively
Modified VOL, VOH test conditions
Removed comment of ‘Lead-free BG packages availability’ below the
Ordering Information
Updated Ordering Information Table
*C
418125
See ECN
NXR
Converted from Preliminary to Final
Changed address of Cypress Semiconductor Corporation on Page# 1 from
“3901 North First Street” to “198 Champion Court”
Changed the description of IX from Input Load Current to Input Leakage
Current on page# 18
Changed the IX current values of MODE on page # 18 from –5 A and 30 A
to –30 A and 5 A
Changed the IX current values of ZZ on page # 18 from –30 A and 5 A
to –5 A and 30 A
Changed VIH < VDD to VIH < VDDon page # 18
Updated Ordering Information Table
*D
475677
See ECN
VKN
Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND.
Changed tTH, tTL from 25 ns to 20 ns and tTDOV from 5 ns to 10 ns in TAP
AC Switching Characteristics table.
Updated the Ordering Information table.
*E
*F
2897278 03/22/2010
3031731 09/16/2010
NJY
NJY
Removed obsolete part numbers from Ordering Information table and
updated package diagrams.
Updated Ordering Information and added Ordering Code Definitions
Added Acronyms and Units of Measure
Minor edits and updated in new template
Document Number: 38-05558 Rev. *F
Page 28 of 29
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CY7C1370DV25
CY7C1372DV25
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
Automotive
cypress.com/go/automotive
cypress.com/go/clocks
cypress.com/go/interface
cypress.com/go/powerpsoc
cypress.com/go/plc
PSoC Solutions
Clocks & Buffers
Interface
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© Cypress Semiconductor Corporation, 2006-2010. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-05558 Rev. *F
Revised September 21, 2010
Page 29 of 29
NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. ZBT is a trademark of Integrated Device Technology, Inc.
All products and company names mentioned in this document may be the trademarks of their respective holders.
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