CY7C182-25VC [ROCHESTER]
Cache SRAM, 8KX9, 25ns, CMOS, PDSO28, 0.300 INCH, PLASTIC, SOJ-28;
| 型号： | CY7C182-25VC |
| 厂家： | 
Rochester Electronics |
| 描述： | Cache SRAM, 8KX9, 25ns, CMOS, PDSO28, 0.300 INCH, PLASTIC, SOJ-28 静态存储器 光电二极管 内存集成电路 |
| 文件： | 总8页 (文件大小：835K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
182
CY7C182
8Kx9 Static RAM
The CY7C182, which is oriented toward cache memory appli-
cations, features fully static operation requiring no external
clocks or timing strobes. The automatic power-down feature
reduces the power consumption by more than 70% when the
circuit is deselected. Easy memory expansion is provided by
an active-LOW Chip Enable (CE1), an active HIGH Chip En-
able (CE2), an active-LOW Output Enable (OE), and three-
state drivers.
Features
• High speed
— tAA = 25 ns
• x9 organization is ideal for cache memory applications
• CMOS for optimum speed/power
• Low active power
— 770 mW
An active-LOW Write Enable signal (WE) controls the writ-
ing/reading operation of the memory. When CE1 and WE in-
puts are both LOW, data on the nine data input/output pins
(I/O0 through I/O8) is written into the memory location ad-
dressed by the address present on the address pins (A0
through A12). Reading the device is accomplished by selecting
the device and enabling the outputs, (CE1 and OE active LOW
and CE2 active HIGH), while (WE) remains inactive or HIGH.
Under these conditions, the contents of the location addressed
by the information on address pins is present on the nine data
input/output pins.
• Low standby power
— 195 mW
• TTL-compatible inputs and outputs
• Automatic power-down when deselected
• Easy memory expansion with CE1, CE2, OE options
Functional Description
The CY7C182 is a high-speed CMOS static RAM organized
as 8,192 by 9 bits and it is manufactured using Cypress’s high-
performance CMOS technology. Access times as fast as 25 ns
are available with maximum power consumption of only 770
mW.
The input/output pins remain in a high-impedance state unless
the chip is selected, outputs are enabled, and write enable
(WE) is HIGH.
A die coat is used to insure alpha immunity.
Logic Block Diagram
PinConfiguration
DIP/SOJ
Top View
A
A
A
A
A
A
V
CC
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
4
5
6
7
8
9
WE
CE
2
I/O
0
3
2
A
3
INPUT BUFFER
4
I/O
1
A
2
5
A
1
6
I/O
2
A
1
A
A
A
OE
7
10
11
12
A
2
A
0
8
I/O
3
A
3
CE
I/O
9
1
A
4
256 x 32 x 9
ARRAY
I/O
I/O
I/O
I/O
10
11
12
13
14
0
1
2
3
8
7
6
5
4
A
5
I/O
4
I/O
I/O
I/O
I/O
A
6
A
7
I/O
5
A
8
GND
I/O
6
C182–2
POWER
DOWN
CE
I/O
7
1
COLUMN
DECODER
CE
2
WE
I/O
8
OE
C182–1
Selection Guide
7C182-25
7C182-35
7C182-45
Maximum Access Time (ns)
25
140
35
35
140
35
45
140
35
Maximum Operating Current (mA)
Maximum Standby Current (mA)
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-05031 Rev. **
Revised August 24, 2001
CY7C182
Output Current into Outputs (LOW)............................. 20 mA
Maximum Ratings
Static Discharge Voltage .......................................... >2001V
(per MIL-STD-883, Method 3015.2)
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Latch-Up Current.................................................... >200 mA
Storage Temperature .....................................−65°C to +150°C
Ambient Temperature with
Power Applied..................................................−55°C to +125°C
Supply Voltage to Ground Potential[1]..............−0.5V to +7.0V
Operating Range
Ambient
Temperature
Range
VCC
DC Voltage Applied to Outputs
Commercial
0°C to + 70°C
5V ± 10%
in High Z State[1] .................................................−0.5V to +7.0V
DC Input Voltage[1]..............................................−0.5V to +7.0V
Electrical Characteristics Over the Operating Range
7C182-25, 35, 45
Parameter
VOH
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage[1]
Input Load Current
Test Conditions
Min.
Max.
Unit
VCC Min., IOH = −4.0 mA.
VCC Min., IOL = 8.0 mA
2.4
V
V
VOL
VIH
VIL
IIX
0.4
VCC
0.8
2.2
−0.5
−10
V
V
GND < VIN < VCC
,
+10
µA
GND < VOUT < VCC
,
Output Disabled
IOZ
IOS
Output Leakage Current
VCC = Max., VOUT = GND
VCC = Max., VOUT = GND
−10
+10
µA
Output Short Circuit
Current[2]
−300
mA
ICC
VCC Operating Circuit
Current
VCC Max., Output Current = 0 mA,
f = Max., VIN = VCC or GND
140
35
mA
mA
mA
Automatic Power-Down
Current — TTL Inputs
Max VCC, CE1 > VIH, CE2 < VIL,
VIN > VIH or VIN < VIL, f = fMAX
Automatic Power-Down
Current — CMOS Inputs
Max VCC, CE1 > VCC − 0.3V, CE2 < 0.3V,
VIN > VCC − 0.3V or VIN < 0.3V, f = 0
20
Capacitance[3]
Parameter
Description
Output Capacitance
Input Capacitance
Test Conditions
Max.
10
Unit
pF
COUT
TA = 25°C, f = 1 MHz,
VCC = 5.0V
CIN
10
pF
Note:
1. VIL (min.) = −3.0V for pulse durations of less than 20 ns.
2. Duration of the short circuit should not exceed 30 seconds. Not more than one output should be shorted at one time.
3. Tested initially and after any design or process changes that may affect these parameters.
AC Test Loads and Waveforms
R1 481Ω
R1 481Ω
5V
5V
ALL INPUT PULSES
OUTPUT
OUTPUT
3.0V
GND
90%
90%
10%
10%
R2
255Ω
R2
30pF
5 pF
255Ω
< 5 ns
< 5 ns
INCLUDING
JIG AND
SCOPE
INCLUDING
JIG AND
SCOPE
C182–3
C182–4
(a)
(b)
Equivalentto:
THÉVENIN EQUIVALENT
167Ω
OUTPUT
1.73V
Document #: 38-05031 Rev. **
Page 2 of 7
CY7C182
Switching Characteristics Over the Operating Range
7C182-25
Min. Max.
7C182-35
Min. Max.
7C182-45
Min. Max.
Parameter
Description
Unit
READ CYCLE[4]
tRC
Read Cycle Time
25
3
35
3
45
3
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address to Data Valid
Data Hold from Address Change
CE1 Access Time
25
35
45
tOHA
tACE1
tACE2
tLZCE1
tLZCE2
tHZCE1
tHZCE2
tPU
25
25
35
35
45
45
CE2 Access Time
CE1 LOW to Low Z
5
5
5
5
5
5
CE2 HIGH to Low Z
CE1 HIGH to High Z[5]
CE2 LOW to High Z[5]
CE1 LOW to Power-Up
CE1 HIGH to Power-Down
OE Access Time
18
18
20
20
25
25
0
3
0
3
0
3
ns
ns
ns
ns
ns
tPD
20
18
20
20
25
20
tDOE
tLZOE
tHZOE
WRITE CYCLE[6]
tWC
OE LOW to Low Z
OE HIGH to High Z[5]
18
20
25
Write Cycle Time
25
0
35
0
45
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSA
Address Set-Up Time
Address Valid to End of Write
Data Set-Up Time
tAW
20
15
20
20
20
0
30
20
30
30
25
0
40
25
40
40
30
0
tSD
tSCE1
tSCE2
tPWE
CE1 LOW to Write End
CE2 HIGH to Write End
WE Pulse Width
tHA
Address Hold from End of Write
Data Hold Time
Write HIGH to Low Z[7]
Write LOW to High Z[5, 7, 8]
tHD
0
0
0
tLZWE
3
3
3
tHZWE
13
15
20
Notes:
4. WE is HIGH for read cycle.
5. HZCE and tHZWE are specified with CL = 5 pF. Transition is measured ± 500 mV from steady-state voltage.
t
6. The internal write time of the memory is defined by the overlap of CE1 LOW, CE2 HIGH, and WE LOW. All three signals must be asserted to initiate a write
and any signal can terminate a write by being deasserted. The data input set-up and hold timing should be referenced to the rising edge of the signal that
terminates the write.
7. At any given temperature and voltage condition, tLZWE is less than tHZWE for any given device. These parameters are sampled and not 100% tested.
8. Address valid prior to or coincident with CE transition LOW and CE2 transition HIGH.
Document #: 38-05031 Rev. **
Page 3 of 7
CY7C182
Switching Waveforms
[4, 9]
Read Cycle No. 1
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
C182–5
[4, 10]
Read Cycle No. 2
t
RC
CE
1
t
t
ACE1
ACE2
CE
2
OE
t
HZOE
t
DOE
t
HZCE
t
LZOE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
DATA VALID
t
LZCE
t
PD
t
PU
ICC
V
CC
SUPPLY
CURRENT
50%
50%
ISB
C182–6
[6]
Write Cycle No.1 (WE Controlled)
t
WC
ADDRESS
t
t
SCE1
SCE2
CS
1
CS
2
t
t
HA
AW
t
SA
t
PWE
WE
t
t
HD
SD
DATA IN
DATA I/O
DATA VALID
t
t
LZWE
HZWE
HIGH IMPEDANCE
DATA UNDEFINED
C182–7
Notes:
9. Device is continuously selected. OE, CE1 = VIL. CE2 = VIH.
10. If CE1 goes HIGH and CE2 goes LOW simultaneously with WE HIGH, the output remains in a high-impedance state.
Document #: 38-05031 Rev. **
Page 4 of 7
CY7C182
Switching Waveforms (continued)
Write Cycle No.2(CE Controlled)[6, 10]
t
WC
ADDRESS
CE
1
t
SCE1
t
SA
t
SCE2
CE
2
t
t
HA
AW
t
PWE
WE
t
t
HD
SD
DATA IN
DATA VALID
t
HZWE
HIGH IMPEDANCE
DATA I/O
DATA UNDEFINED
C182–8
Truth Table
CE1
H
CE2
OE
X
WE
X
Data In
Data Out
Mode
Deselect/Power-Down
Read
X
H
H
H
L
Z
Z
Z
Valid
Z
L
L
H
L
X
L
Valid
Z
Write
L
H
X
H
Z
Output Disable
Deselect
X
X
Z
Z
Ordering Information
Speed
(ns)
Package
Name
Operating
Range
Ordering Code
Package Type
25
CY7C182−25PC
CY7C182−25VC
CY7C182−35PC
CY7C182−35VC
CY7C182−45PC
CY7C182−45VC
P21
V21
P21
V21
P21
V21
28-Lead (300-Mil) Molded DIP
28-Lead Molded SOJ
Commercial
Commercial
Commercial
35
45
28-Lead (300-Mil) Molded DIP
28-Lead Molded SOJ
28-Lead (300-Mil) Molded DIP
28-Lead Molded SOJ
Document #: 38-05031 Rev. **
Page 5 of 7
CY7C182
Package Diagrams
28-Lead (300-Mil) Molded DIP P21
51-85014-B
28-Lead (300-Mil) Molded SOJ V21
51-85031-B
Document #: 38-05031 Rev. **
Page 6 of 7
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C182
Document Title: CY7C182 8K x 9 Static RAM
Document Number: 38-05031
Issue
ECN NO. Date
Orig. of
Change
REV.
Description of Change
**
106825
09/15/01
SZV
Change from Spec number: 38-00110 to 38-05031
Document #: 38-05031 Rev. **
Page 7 of 7
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