CY7C245A-15WC [ROCHESTER]
2KX8 UVPROM, 10ns, CDIP24, 0.300 INCH, SLIM, WINDOWED, CERDIP-24;
| 型号： | CY7C245A-15WC |
| 厂家： | 
Rochester Electronics |
| 描述： | 2KX8 UVPROM, 10ns, CDIP24, 0.300 INCH, SLIM, WINDOWED, CERDIP-24 可编程只读存储器 电动程控只读存储器 CD 输出元件 内存集成电路 |
| 文件： | 总14页 (文件大小：1116K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
45A
CY7C245A
2K x 8 Reprogrammable Registered PROM
Functional Description
Features
• Windowed for reprogrammability
• CMOS for optimum speed/power
The CY7C245A is a high-performance, 2K x 8, electrically pro-
grammable, read only memory packaged in a slim 300-mil
plastic or hermetic DIP. The ceramic package may be
equipped with an erasure window; when exposed to UV light
the PROM is erased and can then be reprogrammed. The
memory cells utilize proven EPROM floating-gate technology
and byte-wide intelligent programming algorithms.
• High speed
— 15-ns address set-up
— 10-ns clock to output
• Low power
The CY7C245A replaces bipolar devices and offers the advan-
tages of lower power, reprogrammability, superior perfor-
mance and high programming yield. The EPROM cell requires
only 12.5V for the supervoltage, and low current requirements
allow gang programming. The EPROM cells allow each mem-
ory location to be tested 100%, because each location is writ-
ten into, erased, and repeatedly exercised prior to encapsula-
tion. Each PROM is also tested for AC performance to
guarantee that after customer programming the product will
meet AC specification limits.
— 330 mW (commercial) for -25 ns
— 660 mW (military)
• Programmable synchronous or asynchronous output
enable
• On-chip edge-triggered registers
• Programmable asynchronous register (INIT)
• EPROM technology, 100% programmable
• Slim, 300-mil, 24-pin plastic or hermetic DIP
• 5V ±10% VCC, commercial and military
• TTL-compatible I/O
The CY7C245A has an asynchronous initialize function (INIT).
This function acts as a 2049th 8-bit word loaded into the on-chip
register. It is user programmable with any desired word, or may be
used as a PRESET or CLEAR function on the outputs. INIT is trig-
gered by a low level, not an edge.
• Direct replacement for bipolar PROMs
• Capable of withstanding greater than 2001V static dis-
charge
PinConfigurations
Logic Block Diagram
DIP
Top View
INIT
1
24
23
22
21
A
A
6
V
CC
7
2
3
A
8
O
7
A
0
A
A
5
9
4
A
4
A
1
A
10
O
6
5
6
A
20
19
18
17
16
3
INIT
E/E
S
A
2
PROGRAMMABLE
ARRAY
ROW
A
MULTIPLEXER
2
A
3
ADDRESS
O
5
A
1
7
8
9
CP
O
7
O
6
A
4
8-BIT
A
0
EDGE-
A
O
4
5
O
0
TRIGGERED
REGISTER
ADDRESS
DECODER
O
10
11
12
O
5
1
A
6
15
14
13
O
O
4
2
O
3
A
7
GND
O
3
A
8
O
2
LCC/PLCC (Opaque only)
Top View
A
9
COLUMN
ADDRESS
O
1
A
10
4 3 2 1 282726
A
10
O
0
25
24
23
22
21
20
19
A
5
CP
4
A
INIT
3
PROGRAMMABLE
MULTIPLEXER
6
A
2
7
E/E
S
E/E
D
C
Q
S
A
1
8
CP
NC
A
0
9
CP
NC
O
7
10
11
O
0
O
6
131415161718
12
Selection Guide
7C245A-25
7C245A-35
7C245A-45
7C245A-15
7C245A-18 7C245AL-25 7C245AL-35 7C245AL-45
Minimum Address Set-Up Time (ns)
Maximum Clock to Output (ns)
15
10
18
12
25
12
35
15
45
25
Maximum Operating Standard Commercial
120
120
120
90
90
90
Current (mA)
Military
120
60
120
60
120
60
L
Commercial
Cypress Semiconductor Corporation
Document #: 38-04007 Rev. **
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Revised March 4, 2002
CY7C245A
DC Program Voltage (Pins 7, 18, 20)........................... 13.0V
UV Erasure................................................... 7258 Wsec/cm2
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Static Discharge Voltage ........................................... >2001V
(per MIL-STD-883, Method 3015)
Storage Temperature .....................................−65°C to +150°C
Latch-Up Current..................................................... >200 mA
Ambient Temperature with
Power Applied..................................................−55°C to +125°C
Operating Range
Supply Voltage to Ground Potential
(Pin 24 to Pin 12).................................................−0.5V to +7.0V
Ambient
Range
Commercial
Industrial[1]
Military[2]
Temperature
VCC
DC Voltage Applied to Outputs
in High Z State.....................................................−0.5V to +7.0V
0°C to +70°C
5V ±10%
5V ±10%
5V ±10%
−40°C to +85°C
−55°C to +125°C
DC Input Voltage .................................................−3.0V to +7.0V
Electrical Characteristics Over the Operating Range[3,4]
7C245A-25 7C245AL-25
7C245A-35 7C245AL-35
7C245A-15 7C245A-18 7C245A-45 7C245AL-45
Parameter
Description
Test Conditions
Min. Max. Min. Max. Min. Max. Min. Max. Unit
VOH
Output HIGH Voltage VCC = Min., IOH = −4.0 mA
2.4
2.4
2.4
2.4
2.0
−10
V
VIN = VIH or VIL
VOL
VIH
VIL
Output LOW Voltage VCC = Min., IOL = 16 mA
VIN = VIH or VIL
0.4
2.0 VCC 2.0 VCC 2.0
0.8 0.8
0.4
0.4
VCC
0.8
0.4
VCC
0.8
V
Input HIGH Level
Guaranteed Input Logical
HIGH Voltage for All Inputs
V
Input LOW Level
Guaranteed Input Logical
LOW Voltage for All Inputs
V
IIX
Input Leakage Current GND < VIN < VCC
−10 +10 −10 +10 −10 +10
+10
µA
VCD
Input Clamp Diode
Voltage
Note 4
IOZ
IOS
ICC
Output Leakage
Current
GND < VO < VCC
Output Disabled[5]
−10 +10 −10 +10 −10 +10
−20 −90 −20 −90 −20 −90
−10
−20
+10
−90
60
µA
mA
mA
Output Short
Circuit Current
VCC = Max.,
VOUT =0.0V[6]
Power Supply Current VCC = Max.,
IOUT=0 mA
Com’l
120
120
120
13
90
120
13
Mil
VPP
IPP
Programming Supply
Voltage
12
13
50
12
12
12
13
50
V
mA
V
Programming Supply
Current
50
50
VIHP
VILP
Input HIGH
Programming Voltage
3.0
3.0
3.0
3.0
Input LOW
0.4
0.4
0.4
0.4
V
Programming Voltage
]
Capacitance[4]
Parameter
CIN
Description
Input Capacitance
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
VCC = 5.0V
Max.
Unit
pF
10
10
COUT
pF
Note:
1. Contact a Cypress representative for industrial temperature range specifications.
2. TA is the “instant on” case temperature.
3. See the last page of this specification for Group A subgroup testing information.
4. See the “Introduction to CMOS PROMs” section of the Cypress Data Book for general information on testing.
5. For devices using the synchronous enable, the device must be clocked after applying these voltages to perform this measurement.
6. For test purposes, not more than one output at a time should be shorted. Short circuit test duration should not exceed 30 seconds.
Document #: 38-04007 Rev. **
Page 2 of 13
CY7C245A
AC Test Loads and Waveforms[3, 4]
R1 250Ω
R1 250Ω
5V
5V
ALL INPUT PULSES
3.0V
GND
OUTPUT
OUTPUT
90%
10%
90%
10%
R2
167Ω
R2
167Ω
50 pF
5 pF
≤
5 ns
5 ns
≤
INCLUDING
JIG AND
SCOPE
INCLUDING
JIG AND
SCOPE
(a) Normal Load
(b) HighZ Load
Equivalent to: THÉVENIN EQUIVALENT
100Ω
OUTPUT
2.0V
Switching Characteristics Over Operating Range[3, 4]
7C245A-25
7C245A-35
7C245A-15 7C245A-18 7C245A-35 7C245AL-25 7C245AL-35
Parameter
tSA
Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
Address Set-Up to Clock HIGH
Address Hold from Clock HIGH
Clock HIGH to Valid Output
Clock Pulse Width
15
0
18
0
25
0
35
0
45
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tHA
tCO
10
15
12
20
12
20
15
20
25
35
tPWC
tSES
tHES
tDI
10
10
5
12
10
5
15
12
5
20
15
5
20
15
5
ES Set-Up to Clock HIGH
ES Hold from Clock HIGH
Delay from INIT to Valid Output
INIT Recovery to Clock HIGH
INIT Pulse Width
tRI
10
10
12
12
15
15
20
20
20
25
tPWI
tCOS
tHZC
Valid Output from Clock HIGH[7]
15
15
15
15
15
15
20
20
30
30
Inactive Output from Clock
HIGH[7]
tDOE
Valid Output from E LOW[8]
Inactive Output from E HIGH[8]
12
15
15
15
15
15
20
20
30
30
ns
ns
tHZE
Notes:
7. Applies only when the synchronous (ES) function is used.
8. Applies only when the asynchronous (E) function is used.
LOWtotheenableinput. Thestoreddataisaccessedandloaded into
the master flip-flops of the data register during the address set-up
time. At the next LOW-to-HIGH transition of the clock (CP), data is
transferred to the slave flip-flops, which drive the output buffers, and
the accessed data will appear at the outputs (O0 - O7).
Operating Modes
The CY7C245A is a CMOS electrically programmable read
only memory organized as 2048 words x 8 bits and is a
pin-for-pin replacement for bipolar TTL fusible link PROMs.
The CY7C245A incorporates a D-type, master-slave register
on chip, reducing the cost and size of pipelined micropro-
grammed systems and applications where accessed PROM
data is stored temporarily in a register. Additional flexibility is
provided with a programmable synchronous (ES) or asynchro-
nous (E) output enable and asynchronous initialization (INIT).
If the asynchronous enable (E) is being used, the outputs may be
disabledat anytime by switching the enabletoa logic HIGH, and may
be returnedto the active state byswitchingthe enable toa logic LOW.
If the synchronous enable (ES) is being used, the outputs will go
to theOFFor high-impedancestateupon the nextpositive clock edge
after the synchronous enable input is switched to a HIGH level. If the
synchronous enable pin is switched to a logic LOW, the subsequent
positive clock edge will return the output to the active state. Following
apositiveclockedge, theaddressandsynchronousenableinputsare
free to change since no change in the output will occur until the next
LOW-to-HIGH transition of the clock. This unique feature allows the
CY7C245A decoders and sense amplifiers to access the next
location while previously addressed data remains stable on
the outputs.
Upon power-up the state of the outputs will depend on the
programmed state of the enable function (ES or E). If the syn-
chronous enable (ES) has been programmed, the register will be in
the set condition causing the outputs (O0 - O7) to be in the OFF or
high-impedance state. If the asynchronous enable (E) is being used,
the outputs will come up in the OFF or high-impedance state only if
the enable (E) input is at a HIGH logic level. Data is read by applying
the memory location to the address inputs (A0 - A10) and a logic
Document #: 38-04007 Rev. **
Page 3 of 13
CY7C245A
word to be loaded into the on-chip register. Each bit is programmable
and the initialize function can be used to load any desired combina-
tion of 1s and 0s into the register. In the unprogrammed state, activat-
ing INIT will generate a register CLEAR (all outputs LOW). If all the
bits of the initialize word are programmed, activating INIT performs a
register PRESET (all outputs HIGH).
Operating Modes (Continued)
System timing is simplified in that the on-chip edge triggered
register allows the PROM clock to be derived directly from the
system clock without introducing race conditions. The on-chip
register timing requirements are similar to those of discrete
registers available in the market.
Applying a LOW to the INITinput causes an immediate load of the
programmed initialize word into the master and slave flip-flops of the
register, independent of all other inputs, including the clock (CP). The
initialize data will appear at the device outputs after the outputs are
enabled by bringing the asynchronous enable (E) LOW.
The CY7C245A has an asynchronous initialize input (INIT).The
initialize function is useful during power-up and time-out sequences
and can facilitate implementation of other sophisticated functions
such as a built-in “jump start” address. When activated, the initialize
control input causes the contents of a user-programmed 2049th 8-bit
Switching Waveforms[4]
t
t
SA
t
HA
HA
A − A
0
10
t
t
t
t
HES
SES
HES
SES
E
S
t
t
HES
SES
t
t
t
PWC
PWC
PWC
CP
t
t
t
PWC
PWC
PWC
O
− O
0
7
t
t
t
CO
HZC
COS
t
CO
t
t
HZE
DOE
E
t
RI
t
DI
INIT
C245A-7
t
PWI
at the end of this section. Programming algorithms can be ob-
tained from any Cypress representative.
Erasure Characteristics
Wavelengths of light less than 4000 Angstroms begin to erase
the 7C245A. For this reason, an opaque label should be
placed over the window if the PROM is exposed to sunlight or
fluorescent lighting for extended periods of time.
Bit Map Data
Programmer Address
RAM Data
Contents
Data
Decimal
Hex
The recommended dose for erasure is ultraviolet light with a
wavelength of 2537 Angstroms for a minimum dose (UV inten-
sity multiplied by exposure time) of 25 Wsec/cm2. For an ultra-
violet lamp with a 12 mW/cm2 power rating the exposure time would
be approximately 35 minutes. The 7C245A needs to be within 1 inch
of the lamp during erasure. Permanent damage may result if the
PROM is exposed to high-intensity UV light for an extended period of
time. 7258 Wsec/cm2 is the recommended maximum dosage.
0
0
.
.
.
.
.
.
.
.
.
2047
2048
2049
7FF
800
801
Data
Init Byte
Control Byte
Programming Information
Control Byte
Programming support is available from Cypress as well as
from a number of third-party software vendors. For detailed
programming information, including a listing of software pack-
ages, please see the PROM Programming Information located
00 ............Asynchronous output enable (default state)
01 .....................................Synchronous output enable
Document #: 38-04007 Rev. **
Page 4 of 13
CY7C245A
Table 1. Mode Selection
Pin Function[9]
Read or Output Disable
Other
A10–A4
A10–A4
A10–A4
A10–A4
A10–A4
A10–A4
A10–A4
A10–A4
A10–A4
A10–A4
A10–A4
A10–A4
A3
A3
A3
A2 - A1
A2 - A1
A2 - A1
A2 - A1
A2 - A1
A2 - A1
A2 - A1
A2 - A1
A2 - A1
A2 - A1
A2 - A1
A2 - A1
A0
A0
A0
CP
PGM
VIL/VIH
X
E, ES
VFY
VIL
INIT
O7–O0
D7–D0
O7–O0
High Z
Init. Byte
D7–D0
O7–O0
High Z
D7–D0
High Z
D7–D0
Zeros
Mode
Read
VPP
VIH
Output Disable
Initialize
A3
A0
VIH
VIH
A3
A0
X
VIL
VIL
Program
A3
A0
VILP
VIHP
VIHP
VILP
VILP
VILP
VIHP
VIHP
VILP
VIHP
VIHP
VIHP
VIHP
VILP
VPP
VPP
VPP
VPP
VPP
VPP
VPP
Program Verify
Program Inhibit
Intelligent Program
A3
A0
A3
A0
A3
A0
Program Synchronous Enable
Program Initialization Byte
Blank Check Zeros
VIHP
VILP
A3
VPP
VPP
A0
Note:
9. X = “don’t care” but not to exceed VCC +5%.
DIP
Top View
LCC/PLCC (Opaque Only)
Top View
24
A
7
V
CC
1
3
2 1 2827
A
4
26
25
24
23 VFY
22
21
23
22
21
6
A
8
A
9
2
3
A
V
A
4
10
PP
5
6
7
8
9
10
11
A
5
A
3
A
2
A
4
A
10
4
A
20
19
18
17
16
V
PP
3
5
A
PGM
NC
D
7
D
1
A
2
A
VFY
6
0
NC
20
19
A
1
PGM
7
8
D
0
6
A
0
D
7
1314151617 18
12
D
0
D
1
D
2
D
6
D
5
D
4
D
3
9
15
14
13
10
11
12
GND
Figure 1. Programming Pinouts
Document #: 38-04007 Rev. **
Page 5 of 13
CY7C245A
Typical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
CLOCK TO OUTPUT TIME
vs. V
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
CC
1.6
1.4
1.2
1.0
1.6
1.2
1.4
1.2
1.0
1.1
1.0
0.9
0.8
T =25°C
A
0.8
0.6
0.8
0.6
f = f
MAX
T =25°C
A
−55
25
125
4.0
4.5
5.0
5.5
6.0
4.0
4.5
5.0
5.5
6.0
AMBIENT TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
CLOCK TO OUTPUT TIME
vs. TEMPERATURE
NORMALIZED SET-UP TIME
vs. SUPPLYVOLTAGE
NORMALIZED SET-UP TIME
vs. TEMPERATURE
1.6
1.2
1.0
1.6
1.4
1.2
1.0
0.8
1.4
1.2
1.0
0.8
0.8
0.6
0.4
T =25°C
A
0.6
−55
0.6
−55
25
125
4.0
4.5
5.0
5.5
6.0
25
125
AMBIENT TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
AMBIENT TEMPERATURE (°C)
NORMALIZED SUPPLY CURRENT
vs. CLOCK PERIOD
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
175
150
1.02
1.00
0.98
30.0
25.0
20.0
15.0
V
CC
=5.5V
T =25°C
A
125
100
75
0.96
0.94
0.92
V
=5.0V
CC
10.0
5.0
50
T =25°C
A
T =25°C
A
25
0
0.90
0.88
V
CC
=4.5V
0.0
0.0
1.0
2.0
3.0
4.0
0
25
50
75
100
0
200 400
600 800 1000
CLOCK PERIOD (ns)
CAPACITANCE (pF)
OUTPUT VOLTAGE (V)
C245A-10
Document #: 38-04007 Rev. **
Page 6 of 13
CY7C245A
Ordering Information[10]
Speed (ns)
ICC
(mA)
Ordering
Code
Package
Type
Operating
Range
tSA
tCO
Package Type
15
10
120 CY7C245A-15JC
CY7C245A-15PC
J64
P13
W14
J64
28-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) Molded DIP
24-Lead (300-Mil) Windowed CerDIP
28-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) Molded DIP
24-Lead (300-Mil) Windowed CerDIP
24-Lead (300-Mil) CerDIP
Commercial
Commercial
Military
CY7C245A-15WC
120 CY7C245A-18JC
CY7C245A-18PC
18
12
P13
W14
D14
L64
Q64
T73
W14
P13
W14
J64
CY7C245A-18WC
CY7C245A-18DMB
CY7C245A-18LMB
CY7C245A-18QMB
CY7C245A-18TMB
CY7C245A-18WMB
28-Square Leadless Chip Carrier
28-Pin Windowed Leadless Chip Carrier
24-Lead Windowed Cerpack
24-Lead (300-Mil) Windowed CerDIP
24-Lead (300-Mil) Molded DIP
24-Lead (300-Mil) Windowed CerDIP
28-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) Molded DIP
24-Lead Molded SOIC
25
15
60
90
CY7C245AL-25PC
CY7C245AL-25WC
CY7C245A-25JC
CY7C245A-25PC
CY7C245A-25SC
CY7C245A-25WC
Commercial
P13
S13
W14
D14
L64
Q64
T73
W14
P13
W14
J64
24-Lead (300-Mil) Windowed CerDIP
24-Lead (300-Mil) CerDIP
120 CY7C245A-25DMB
CY7C245A-25LMB
CY7C245A-25QMB
CY7C245A-25TMB
CY7C245A-25WMB
Military
28-Square Leadless Chip Carrier
28-Pin Windowed Leadless Chip Carrier
24-Lead Windowed Cerpack
24-Lead (300-Mil) Windowed CerDIP
24-Lead (300-Mil) Molded DIP
24-Lead (300-Mil) Windowed CerDIP
28-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) Molded DIP
24-Lead Molded SOIC
35
20
60
CY7C245AL-35PC
CY7C245AL-35WC
CY7C245A-35JC
CY7C245A-35PC
CY7C245A-35SC
CY7C245A-35WC
Commercial
90
P13
S13
W14
D14
L64
Q64
T73
W14
J64
24-Lead (300-Mil) Windowed CerDIP
24-Lead (300-Mil) CerDIP
120 CY7C245A-35DMB
CY7C245A-35LMB
CY7C245A-35QMB
CY7C245A-35TMB
CY7C245A-35WMB
Military
28-Square Leadless Chip Carrier
28-Pin Windowed Leadless Chip Carrier
24-Lead Windowed Cerpack
24-Lead (300-Mil) Windowed CerDIP
28-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) Molded DIP
28-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) Molded DIP
24-Lead Molded SOIC
45
25
60
CY7C245A-45JC
CY7C245A-45PC
CY7C245A-45JC
CY7C245A-45PC
CY7C245A-45SC
CY7C245A-45WC
Commercial
P13
J64
90
P13
S13
W14
D14
L64
Q64
T73
W14
24-Lead (300-Mil) Windowed CerDIP
24-Lead (300-Mil) CerDIP
120 CY7C245A-45DMB
CY7C245A-45LMB
CY7C245A-45QMB
CY7C245A-45TMB
CY7C245A-45WMB
Military
28-Square Leadless Chip Carrier
28-Pin Windowed Leadless Chip Carrier
24-Lead Windowed Cerpack
24-Lead (300-Mil) Windowed CerDIP
Note:
10. Most of these products are available in industrial temperature range. Contact a Cypress representative for specifications and product availability.
Document #: 38-04007 Rev. **
Page 7 of 13
CY7C245A
MILITARY SPECIFICATIONS
Group A Subgroup Testing
SMD Cross Reference
SMD
Number
Cypress
Number
Suffix
DC Characteristics
5962-88735
01KX
01LX
013X
02KX
02LX
023X
03KX
03LX
033X
04KX
04LX
043X
01KX
01LX
013X
02KX
02LX
023X
01LX
01KX
013X
02LX
02KX
023X
03LX
03KX
033X
CY7C245A-45KMB
Parameter
VOH
VOL
Subgroups
1, 2, 3
5962-88735
5962-88735
5962-88735
5962-88735
5962-88735
5962-88735
5962-88735
5962-88735
5962-88735
5962-88735
5962-88735
5962-87529
5962-87529
5962-87529
5962-87529
5962-87529
5962-87529
5962-89815
5962-89815
5962-89815
5962-89815
5962-89815
5962-89815
5962-89815
5962-89815
5962-89815
CY7C245A-45DMB
CY7C245A-45LMB
CY7C245A-35KMB
CY7C245A-35DMB
CY7C245A-35LMB
CY7C245A-35KMB
CY7C245A-35DMB
CY7C245A-25LMB
CY7C245A-25KMB
CY7C245A-25DMB
CY7C245A-25LMB
CY7C245A-45TMB
CY7C245A-45WMB
CY7C245A-45QMB
CY7C245A-35TMB
CY7C245A-35WMB
CY7C245A-35QMB
CY7C245A-35WMB
CY7C245A-35TMB
CY7C245A-35QMB
CY7C245A-25WMB
CY7C245A-25TMB
CY7C245A-25QMB
CY7C245A-18WMB
CY7C245A-18TMB
CY7C245A-18QMB
1, 2, 3
VIH
1, 2, 3
VIL
1, 2, 3
IIX
1, 2, 3
IOZ
1, 2, 3
ICC
1, 2, 3
Switching Characteristics
Parameter
Subgroups
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
tSA
tHA
tCO
Document #: 38-04007 Rev. **
Page 8 of 13
CY7C245A
Package Diagrams
24-Lead (300-Mil) CerDIP D14
MIL-STD-1835 D- 9 Config.A
51-80031
28-Lead Plastic Leaded Chip Carrier J64
51-85001-A
Document #: 38-04007 Rev. **
Page 9 of 13
CY7C245A
Package Diagrams (continued)
28-Square Leadless Chip Carrier L64
MIL-STD-1835 C-4
51-80051
24-Lead (300-Mil) Molded DIP P13/P13A
51-85013-A
Document #: 38-04007 Rev. **
Page 10 of 13
CY7C245A
Package Diagrams (continued)
28-Pin Windowed Leadless Chip Carrier Q64
MIL–STD–1835 C–4
51-80102
24-Lead (300-Mil) Molded SOIC S13
51-85025-A
Document #: 38-04007 Rev. **
Page 11 of 13
CY7C245A
Package Diagrams (continued)
24-Lead (300-Mil) Windowed CerDIP W14
MIL-STD-1835 D-9 Config. A
51-80086
Document #: 38-04007 Rev. **
Page 12 of 13
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C245A
Document Title: CY7C245A 2K x 8 Reprogrammable Registered PROM
Document Number: 38-04007
Issue
Date
Orig. of
Change
REV.
ECN NO.
Description of Change
**
113863
3/6/02
DSG
Change from Spec number: 38-00074 to 38-04007
Document #: 38-04007 Rev. **
Page 13 of 13
相关型号：
©2020 ICPDF网 联系我们和版权申明