CY7C64713-56PVXC [ROCHESTER]
8-BIT, EEPROM, 48 MHz, MICROCONTROLLER, PDSO56, LEAD FREE, SSOP-56;
| 型号： | CY7C64713-56PVXC |
| 厂家： | 
Rochester Electronics |
| 描述： | 8-BIT, EEPROM, 48 MHz, MICROCONTROLLER, PDSO56, LEAD FREE, SSOP-56 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 时钟 微控制器 光电二极管 外围集成电路 |
| 文件： | 总75页 (文件大小：2423K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C64713
EZ-USB FX1™ USB Microcontroller
Full Speed USB Peripheral Controller
EZ-USB FX1™ USB Microcontroller Full Speed USB Peripheral Controller
❐ Up to 48 MHz clock rate
Features
❐ Four clocks for each instruction cycle
■ Single chip integrated USB transceiver, SIE, and enhanced
8051 microprocessor
❐ Two USARTS
❐ Three counters or timers
❐ Expanded interrupt system
❐ Two data pointers
■ Fit, form, andfunctionupgradabletotheFX2LP(CY7C68013A)
❐ Pin compatible
❐ Object code compatible
■ 3.3 V operation with 5 V tolerant inputs
■ Smart SIE
❐ Functionally compatible (FX1 functionality is a subset of the
FX2LP)
■ Draws no more than 65 mA in any mode, making the FX1
suitable for bus powered applications
■ Vectored USB interrupts
■ Separate data buffers for the setup and DATA portions of a
CONTROL transfer
■ Software: 8051 runs from internal RAM, which is:
❐ Downloaded using USB
■ Integrated I2C controller, running at 100 or 400 KHz
■ 48 MHz, 24 MHz, or 12 MHz 8051 operation
■ Four integrated FIFOs
❐ Loaded from EEPROM
❐ External memory device (128 pin configuration only)
■ 16 KB of on-chip code/data RAM
❐ Brings glue and FIFOs inside for lower system cost
❐ Automatic conversion to and from 16-bit buses
❐ Master or slave operation
■ Four programmable BULK/INTERRUPT/ISOCHRONOUS
endpoints
❐ Buffering options: double, triple, and quad
❐ FIFOs can use externally supplied clock or asynchronous
strobes
■ Additional programmable (BULK/INTERRUPT) 64-byte
endpoint
❐ Easy interface to ASIC and DSP ICs
■ Vectored for FIFO and GPIF Interrupts
■ Up to 40 general purpose IOs (GPIO)
■ Four package options:
❐ 128-pin TQFP
■ 8- or 16-bit external data interface
■ Smart media standard ECC generation
■ GPIF
❐ Allows direct connection to most parallel interfaces; 8- and
16-bit
❐ Programmable waveform descriptors and configuration
❐ 100-pin TQFP
registers to define waveforms
❐ 56-pin SSOP
❐ Supports multiple ready (RDY) inputs and Control (CTL)
outputs
❐ 56-pin QFN Pb-free
■ Integrated, industry standard 8051 with enhanced features:
Errata: For information on silicon errata, see “Errata” on page 71. Details include trigger conditions, devices affected, and proposed workaround.
Cypress Semiconductor Corporation
Document Number: 38-08039 Rev. *K
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised July 22, 2013
CY7C64713
Logic Block Diagram
High performance micro
using standard tools
with lower-power options
24 MHz
Ext. XTAL
FX1
I2C
Master
/0.5
/1.0
/2.0
8051 Core
x20
VCC
1.5k
12/24/48 MHz,
four clocks/cycle
PLL
Abundant I/O
including two USARTS
Additional IOs (24)
connected for
enumeration
General
ADDR (9)
programmable I/F
to ASIC/DSP or bus
standards such as
D+
D–
GPIF
USB
CY
16 KB
RAM
RDY (6)
CTL (6)
ATAPI, EPP, etc.
ECC
Smart
XCVR
USB
Engine
Integrated
full speed XCVR
Up to 96 MBytes
burst rate
4 kB
FIFO
8/16
Enhanced USB core
Simplifies 8051 code
‘Soft Configuration’
Easy firmware changes
FIFO and endpoint memory
(master or slave operation)
Document Number: 38-08039 Rev. *K
Page 2 of 74
CY7C64713
Contents
Functional Description .....................................................4
Applications ......................................................................4
Functional Overview ........................................................4
USB Signaling Speed ..................................................4
8051 Microprocessor ...................................................4
I2C Bus ........................................................................5
Buses ..........................................................................5
USB Boot Methods ......................................................5
ReNumeration™ ..........................................................6
Bus-powered Applications ...........................................6
Interrupt System ..........................................................6
Reset and Wakeup ......................................................8
Program/Data RAM .....................................................9
Endpoint RAM ...........................................................11
External FIFO Interface .............................................11
GPIF ..........................................................................12
ECC Generation ........................................................13
USB Uploads and Downloads ...................................13
Autopointer Access ...................................................13
I2C Controller .............................................................13
Compatible with Previous Generation
EZ-USB FX2 .....................................................................14
Pin Assignments ............................................................14
CY7C64713 Pin Definitions ............................................20
Register Summary ..........................................................28
Absolute Maximum Ratings ..........................................47
Operating Conditions .....................................................47
DC Characteristics .........................................................47
USB Transceiver .......................................................47
AC Electrical Characteristics ........................................48
USB Transceiver .......................................................48
PORTC Strobe Feature Timings ...............................51
GPIF Synchronous Signals .......................................52
Slave FIFO Synchronous Read .................................53
Slave FIFO Asynchronous Read ...............................54
Slave FIFO Synchronous Write .................................55
Slave FIFO Asynchronous Write ...............................56
Slave FIFO Synchronous Packet End Strobe ...........56
Slave FIFO Asynchronous Packet End Strobe .........58
Slave FIFO Output Enable ........................................58
Slave FIFO Address to Flags/Data ............................58
Slave FIFO Synchronous Address ............................59
Slave FIFO Asynchronous Address ..........................59
Sequence Diagram ....................................................60
Ordering Information ......................................................64
Ordering Code Definitions .........................................64
Package Diagrams ..........................................................65
Quad Flat Package No Leads (QFN) Package
Design Notes ...................................................................68
Acronyms ........................................................................70
Document Conventions .................................................70
Units of Measure .......................................................70
Errata ...............................................................................71
Part Numbers Affected ..............................................71
EZ-USB FX1 Qualification Status ..............................71
EZ-USB FX1 Errata Summary ..................................71
Document History Page .................................................72
Sales, Solutions, and Legal Information ......................74
Worldwide Sales and Design Support .......................74
Products ....................................................................74
PSoC® Solutions ......................................................74
Cypress Developer Community .................................74
Technical Support .....................................................74
Document Number: 38-08039 Rev. *K
Page 3 of 74
CY7C64713
FX1 does not support the low speed signaling mode of 1.5 Mbps
or the high speed mode of 480 Mbps.
Functional Description
EZ-USB FX1 (CY7C64713) is a full speed, highly integrated,
USB microcontroller. By integrating the USB transceiver, Serial
Interface Engine (SIE), enhanced 8051 microcontroller, and a
programmable peripheral interface in a single chip, Cypress has
created a very cost effective solution that provides superior
time-to-market advantages.
8051 Microprocessor
The 8051 microprocessor embedded in the FX1 family has
256 bytes of register RAM, an expanded interrupt system, three
timer/counters, and two USARTs.
8051 Clock Frequency
The EZ-USB FX1 is more economical, because it incorporates
the USB transceiver and provides a smaller footprint solution
than the USB SIE or external transceiver implementations. With
EZ-USB FX1, the Cypress Smart SIE handles most of the USB
protocol in hardware, freeing the embedded microcontroller for
application specific functions and decreasing the development
time to ensure USB compatibility.
FX1 has an on-chip oscillator circuit that uses an external
24 MHz (±100 ppm) crystal with the following characteristics:
■ Parallel resonant
■ Fundamental mode
■ 500 W drive level
The General Programmable Interface (GPIF) and Master/Slave
Endpoint FIFO (8 or 16-bit data bus) provide an easy and
glueless interface to popular interfaces such as ATA, UTOPIA,
EPP, PCMCIA, and most DSP/processors.
■ 12 pF (5% tolerance) load capacitors.
An on-chip PLL multiplies the 24 MHz oscillator up to 480 MHz,
as required by the transceiver/PHY, and the internal counters
divide it down for use as the 8051 clock. The default 8051 clock
frequency is 12 MHz. The clock frequency of the 8051 is
dynamically changed by the 8051 through the CPUCS register.
Four Pb-free packages are defined for the family: 56-pin SSOP,
56-pin QFN, 100-pin TQFP, and 128-pin TQFP.
Applications
The CLKOUT pin, which is three-stated and inverted using the
internal control bits, outputs the 50% duty cycle 8051 clock at the
selected 8051 clock frequency which is 48, 24, or 12 MHz.
■ DSL modems
■ ATA interface
USARTS
■ Memory card readers
■ Legacy conversion devices
■ Home PNA
FX1 contains two standard 8051 USARTs, addressed by Special
Function Register (SFR) bits. The USART interface pins are
available on separate I/O pins, and are not multiplexed with port
pins.
■ Wireless LAN
UART0 and UART1 can operate using an internal clock at
230 KBaud with no more than 1% baud rate error. 230 KBaud
operation is achieved by an internally derived clock source that
generates overflow pulses at the appropriate time. The internal
clock adjusts for the 8051 clock rate (48, 24, 12 MHz) such that
it always presents the correct frequency for 230-KBaud
operation.[1]
■ MP3 players
■ Networking
The Reference Designs section of the cypress website provides
additional tools for typical USB applications. Each reference
design comes complete with firmware source and object code,
schematics,
http://www.cypress.com for more information.
and
documentation.
Please
visit
Special Function Registers
Certain 8051 SFR addresses are populated to provide fast
access to critical FX1 functions. These SFR additions are shown
in Table 1 on page 5. Bold type indicates non-standard,
enhanced 8051 registers. The two SFR rows that end with ‘0’ and
‘8’ contain bit addressable registers. The four I/O ports A–D use
the SFR addresses used in the standard 8051 for ports 0–3,
which are not implemented in the FX1. Because of the faster and
more efficient SFR addressing, the FX1 I/O ports are not
addressable in the external RAM space (using the MOVX
instruction).
Functional Overview
USB Signaling Speed
FX1 operates at one of the three rates defined in the USB
Specification Revision 2.0, dated April 27, 2000:
Full speed, with a signaling bit rate of 12 Mbps.
Note
1. 115-KBaud operation is also possible by programming the 8051 SMOD0 or SMOD1 bits to a ‘1’ for UART0 and UART1, respectively.
Document Number: 38-08039 Rev. *K
Page 4 of 74
CY7C64713
Figure 1. Crystal Configuration
24 MHz
C1
C2
12 pF
12 pF
12-pF capacitor values assumes
a trace capacitance of 3 pF per
side on a four layer FR4 PCA
20 × PLL
Table 1. Special Function Registers
x
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
8x
IOA
9x
IOB
Ax
Bx
Cx
Dx
Ex
Fx
IOC
IOD
IOE
SCON1
SBUF1
PSW
ACC
B
SP
EXIF
INT2CLR
INT4CLR
DPL0
DPH0
DPL1
DPH1
DPS
MPAGE
OEA
OEB
OEC
OED
OEE
PCON
TCON
TMOD
TL0
SCON0
SBUF0
IE
IP
T2CON
EICON
EIE
EIP
AUTOPTRH1
AUTOPTRL1
reserved
EP2468STAT
EP01STAT
GPIFTRIG
RCAP2L
RCAP2H
TL2
TL1
EP24FIFOFLGS
EP68FIFOFLGS
TH0
TH1
AUTOPTRH2
AUTOPTRL2
reserved
GPIFSGLDATH
GPIFSGLDATLX
TH2
CKCON
AUTOPTRSETUP GPIFSGLDATLNOX
2
in place of the internally stored values (0xC0). Alternatively, it
boot-loads the EEPROM contents into an internal RAM (0xC2).
If no EEPROM is detected, FX1 enumerates using internally
stored descriptors. The default ID values for FX1 are
VID/PID/DID (0x04B4, 0x6473, 0xAxxx where xxx=Chip
revision).[2]
I C Bus
FX1 supports the I2C bus as a master only at 100/400 KHz. SCL
and SDA pins have open drain outputs and hysteresis inputs.
These signals must be pulled up to 3.3 V, even if no I2C device
is connected.
Buses
Table 2. Default ID Values for FX1
Default VID/PID/DID
All packages: 8 or 16-bit ‘FIFO’ bidirectional data bus,
multiplexed on I/O ports B and D. 128-pin package: adds 16-bit
output only 8051 address bus, 8-bit bidirectional data bus.
Vendor ID 0x04B4 Cypress Semiconductor
Product ID 0x6473 EZ-USB FX1
USB Boot Methods
During the power up sequence, internal logic checks the I2C port
for the connection of an EEPROM whose first byte is either 0xC0
or 0xC2. If found, it uses the VID/PID/DID values in the EEPROM
Device
release
0xAnnn Depends on chip revision (nnn = chip
revision where first silicon = 001)
Notes
2
2. The I C bus SCL and SDA pins must be pulled up, even if an EEPROM is not connected. Otherwise this detection method does not work properly.
Document Number: 38-08039 Rev. *K
Page 5 of 74
CY7C64713
USB-Interrupt Autovectors
ReNumeration™
The main USB interrupt is shared by 27 interrupt sources. The
FX1 provides a second level of interrupt vectoring, called
Autovectoring, to save code and processing time that is normally
required to identify the individual USB interrupt source. When a
USB interrupt is asserted, the FX1 pushes the program counter
on to its stack and then jumps to address 0x0043, where it
expects to find a “jump” instruction to the USB Interrupt service
routine.
Because the FX1’s configuration is soft, one chip can take on the
identities of multiple distinct USB devices.
When first plugged into the USB, the FX1 enumerates
automatically and downloads firmware and the USB descriptor
tables over the USB cable. Next, the FX1 enumerates again, this
time as a device defined by the downloaded information. This
patented two step process, called ReNumeration, happens
instantly when the device is plugged in, with no indication that
the initial download step has occurred.
The FX1 jump instruction is encoded as shown in Table 3.
If Autovectoring is enabled (AV2EN = 1 in the INTSETUP
register), the FX1 substitutes its INT2VEC byte. Therefore, if the
high byte (“page”) of a jump table address is preloaded at
location 0x0044, the automatically inserted INT2VEC byte at
0x0045 directs the jump to the correct address out of the 27
addresses within the page.
Two control bits in the USBCS (USB Control and Status) register
control the ReNumeration process: DISCON and RENUM. To
simulate a USB disconnect, the firmware sets DISCON to 1. To
reconnect, the firmware clears DISCON to 0.
Before reconnecting, the firmware sets or clears the RENUM bit
to indicate if the firmware or the Default USB Device handles
device requests over endpoint zero:
FIFO/GPIF Interrupt (INT4)
Just as the USB Interrupt is shared among 27 individual
USB-interrupt sources, the FIFO/GPIF interrupt is shared among
14 individual FIFO/GPIF sources. The FIFO/GPIF Interrupt, such
as the USB Interrupt, can employ autovectoring. Table 4 on page
7 shows the priority and INT4VEC values for the 14 FIFO/GPIF
interrupt sources.
■ RENUM = 0, the Default USB Device handles device requests
■ RENUM = 1, the firmware handles device requests
Bus-powered Applications
The FX1 fully supports bus powered designs by enumerating
with less than 100 mA as required by the USB specification.
FIFO/GPIF Interrupt (INT4)
Interrupt System
Just as the USB Interrupt is shared among 27 individual
USB-interrupt sources, the FIFO/GPIF interrupt is shared among
14 individual FIFO/GPIF sources. The FIFO/GPIF Interrupt, such
as the USB Interrupt, can employ autovectoring.
Table 4 on page 7 shows the priority and INT4VEC values for the
14 FIFO/GPIF interrupt sources.
INT2 Interrupt Request and Enable Registers
FX1 implements an autovector feature for INT2 and INT4. There
are 27 INT2 (USB) vectors, and 14 INT4 (FIFO/GPIF) vectors.
See EZ-USB Technical Reference Manual (TRM) for more
details.
Table 3. INT2 USB Interrupts
USB INTERRUPT TABLE FOR INT2
Source
Priority
INT2VEC Value
Notes
1
2
00
04
08
0C
10
14
18
1C
20
24
28
2C
30
34
38
3C
40
SUDAV
SOF
Setup Data Available
Start of Frame
3
SUTOK
Setup Token Received
USB Suspend request
Bus reset
4
SUSPEND
5
USB RESET
6
Reserved
7
EP0ACK
FX1 ACK’d the CONTROL Handshake
Reserved
8
9
EP0-IN
EP0-OUT
EP1-IN
EP1-OUT
EP2
EP0-IN ready to be loaded with data
EP0-OUT has USB data
10
11
12
13
14
15
16
17
EP1-IN ready to be loaded with data
EP1-OUT has USB data
IN: buffer available. OUT: buffer has data
IN: buffer available. OUT: buffer has data
IN: buffer available. OUT: buffer has data
IN: buffer available. OUT: buffer has data
IN-Bulk-NAK (any IN endpoint)
EP4
EP6
EP8
IBN
Document Number: 38-08039 Rev. *K
Page 6 of 74
CY7C64713
Table 3. INT2 USB Interrupts (continued)
USB INTERRUPT TABLE FOR INT2
Source
Priority
18
INT2VEC Value
Notes
44
48
4C
50
54
58
5C
60
64
68
6C
70
74
78
7C
Reserved
19
EP0PING
EP1PING
EP2PING
EP4PING
EP6PING
EP8PING
ERRLIMIT
EP0 OUT was Pinged and it NAK’d
EP1 OUT was Pinged and it NAK’d
EP2 OUT was Pinged and it NAK’d
EP4 OUT was Pinged and it NAK’d
EP6 OUT was Pinged and it NAK’d
EP8 OUT was Pinged and it NAK’d
Bus errors exceeded the programmed limit
20
21
22
23
24
25
26
27
Reserved
28
Reserved
29
EP2ISOERR
EP4ISOERR
EP6ISOERR
EP8ISOERR
ISO EP2 OUT PID sequence error
ISO EP4 OUT PID sequence error
ISO EP6 OUT PID sequence error
ISO EP8 OUT PID sequence error
30
31
32
Table 4. Individual FIFO/GPIF Interrupt Sources
Priority
INT4VEC Value
Source
Notes
Endpoint 2 Programmable Flag
Endpoint 4 Programmable Flag
Endpoint 6 Programmable Flag
Endpoint 8 Programmable Flag
Endpoint 2 Empty Flag [3]
Endpoint 4 Empty Flag
1
2
80
84
88
8C
90
94
98
9C
A0
A4
A8
AC
B0
B4
EP2PF
EP4PF
EP6PF
EP8PF
EP2EF
EP4EF
EP6EF
EP8EF
EP2FF
EP4FF
EP6FF
EP8FF
3
4
5
6
7
Endpoint 6 Empty Flag
8
Endpoint 8 Empty Flag
9
Endpoint 2 Full Flag
10
11
12
13
14
Endpoint 4 Full Flag
Endpoint 6 Full Flag
Endpoint 8 Full Flag
GPIFDONE
GPIFWF
GPIF Operation Complete
GPIF Waveform
If Autovectoring is enabled (AV4EN = 1 in the INTSETUP
register), the FX1 substitutes its INT4VEC byte. Therefore, if the
high byte (“page”) of a jump-table address is preloaded at
location 0x0054, the automatically inserted INT4VEC byte at
0x0055 directs the jump to the correct address out of the 14
addresses within the page. When the ISR occurs, the FX1
pushes the program counter onto its stack and then jumps to
address 0x0053, where it expects to find a “jump” instruction to
the ISR Interrupt service routine.
Note
3. Errata: In Slave FIFO Asynchronous Word Wide mode, if a single word data is transferred from the USB host to EP2, configured as OUT Endpoint (EP) in the first
transaction, then the Empty flag behaves incorrectly. This does not happen if the data size is more than one word in the first transaction. For more information, see
the “Errata” on page 71.
Document Number: 38-08039 Rev. *K
Page 7 of 74
CY7C64713
during operation. A power on reset is defined as the time a reset
is asserted when power is being applied to the circuit. A powered
reset is defined to be when the FX1 has been previously
powered on and operating and the RESET# pin is asserted.
Reset and Wakeup
Reset Pin
The input pin, RESET#, resets the FX1 when asserted. This pin
has hysteresis and is active LOW. When a crystal is used with
the CY7C64713, the reset period must allow for the stabilization
of the crystal and the PLL. This reset period must be
approximately 5 ms after VCC has reached 3.0 Volts. If the
crystal input pin is driven by a clock signal the internal PLL
stabilizes in 200 s after VCC has reached 3.0 V[4]. Figure 2 on
page 8 shows a power on reset condition and a reset applied
Cypress provides an application note which describes and
recommends power on reset implementation and is found on the
Cypress web site. While the application note discusses the FX2,
the information provided applies also to the FX1. For more
information on reset implementation for the FX2 family of
products visit http://www.cypress.com.
Figure 2. Reset Timing Plots
RESET#
RESET#
VIL
VIL
3.3 V
3.0 V
3.3 V
VCC
VCC
0 V
0 V
TRESET
TRESET
Power on Reset
Powered Reset
wakeup interrupt. This applies irrespective of whether the FX1 is
connected to the USB or not.
Table 5. Reset Timing Values
The FX1 exits the power down (USB suspend) state using one
of the following methods:
Condition
TRESET
Power On Reset with crystal
5 ms
■ USB bus activity (if D+/D– lines are left floating, noise on these
lines may indicate activity to the FX1 and initiate a wakeup).
Power On Reset with external 200 s + Clock stability time
clock
■ External logic asserts the WAKEUP pin.
■ External logic asserts the PA3/WU2 pin.
Powered Reset
200 s
Wakeup Pins
The second wakeup pin, WU2, can also be configured as a
general purpose I/O pin. This allows a simple external R-C
network to be used as a periodic wakeup source. Note that
WAKEUP is by default active LOW.
The 8051 puts itself and the rest of the chip into a power down
mode by setting PCON.0 = 1. This stops the oscillator and PLL.
When WAKEUP is asserted by external logic, the oscillator
restarts, after the PLL stabilizes, and then the 8051 receives a
Note
4. If the external clock is powered at the same time as the CY7C64713 and has a stabilization wait period. It must be added to the 200 s.
Document Number: 38-08039 Rev. *K
Page 8 of 74
CY7C64713
external RAM or ROM is added, the external read and write
strobes are suppressed for memory spaces that exist inside the
chip. This allows the user to connect a 64 KByte memory without
requiring the address decodes to keep clear of internal memory
spaces.
Program/Data RAM
Size
The FX1 has 16 KBytes of internal program/data RAM, where
PSEN#/RD# signals are internally ORed to allow the 8051 to
access it as both program and data memory. No USB control
registers appear in this space.
Only the internal 16 KBytes and scratch pad 0.5 KBytes RAM
spaces have the following access:
Two memory maps are shown in the following diagrams:
■ Figure 3 on page 9 Internal Code Memory, EA = 0
■ Figure 4 on page 10 External Code Memory, EA = 1.
■ USB download
■ USB upload
■ Setup data pointer
■ I2C interface boot load
Internal Code Memory, EA = 0
This mode implements the internal 16 KByte block of RAM
(starting at 0) as combined code and data memory. When the
Figure 3. Internal Code Memory, EA = 0.
Inside FX1
Outside FX1
FFFF
7.5 KBytes
USB regs and
4K FIFO buffers
(OK to populate
data memory
here—RD#/WR#
strobes are not
active)
(RD#,WR#)
E200
E1FF
0.5 KBytes RAM
Data (RD#,WR#)*
E000
48 KBytes
External
Code
Memory
(PSEN#)
40 KBytes
External
Data
Memory
(RD#,WR#)
3FFF
(Ok to populate
data memory
here—RD#/WR#
strobes are not
active)
(OK to populate
program
memory here—
PSEN# strobe
is not active)
16 KBytes RAM
Code and Data
(PSEN#,RD#,WR#)*
0000
Data
2
Code
*SUDPTR, USB upload/download, I C interface boot access
Document Number: 38-08039 Rev. *K
Page 9 of 74
CY7C64713
External Code Memory, EA = 1
The bottom 16 KBytes of program memory is external, and therefore the bottom 16 KBytes of internal RAM is accessible only as data
memory.
Figure 4. External Code Memory, EA = 1
Inside FX1
Outside FX1
FFFF
7.5 KBytes
(OK to populate
USB regs and
4K FIFO buffers
(RD#,WR#)
data memory
here—RD#/WR#
strobes are not
active)
E200
E1FF
0.5 KBytes RAM
Data (RD#,WR#)*
E000
40 KBytes
External
Data
Memory
(RD#,WR#)
64 KBytes
External
Code
Memory
(PSEN#)
3FFF
(Ok to populate
data memory
here—RD#/WR#
strobes are not
active)
16 KBytes
RAM
Data
(RD#,WR#)*
0000
Data
2
Code
*SUDPTR, USB upload/download, I C interface boot access
Document Number: 38-08039 Rev. *K
Page 10 of 74
CY7C64713
Figure 5. Register Addresses
FFFF
4 KBytes EP2-EP8
buffers
(8 x 512)
Not all Space is available
for all transfer types
F000
EFFF
2 KBytes RESERVED
E800
E7FF
E7C0
64 Bytes EP1IN
E7BF
E780
64 Bytes EP1OUT
E77F
E740
64 Bytes EP0 IN/OUT
E73F
64 Bytes RESERVED
E700
E6FF
8051 Addressable Registers
(512)
E500
E4FF
Reserved (128)
E480
E47F
128 bytes GPIF Waveforms
E400
E3FF
E200
Reserved (512)
E1FF
512 bytes
8051 xdata RAM
E000
Endpoint RAM
Table 6. Default Alternate Settings
Size
Alternate
Setting
0
1
2
3
■ 3 × 64 bytes
(Endpoints 0 and 1)
ep0
64 64
64
64
■ 8 × 512 bytes (Endpoints 2, 4, 6, 8)
ep1out
ep1in
ep2
0
0
0
0
0
0
64 bulk
64 bulk
64 int
64 int
64 int
64 int
Organization
■ EP0—Bidirectional endpoint zero, 64 byte buffer
■ EP1IN, EP1OUT—64 byte buffers, bulk or interrupt
64 bulk out (2×) 64 int out (2×) 64 iso out (2×)
64 bulk out (2×) 64 bulk out (2×) 64 bulk out (2×)
64 bulk in (2×) 64 int in (2×) 64 iso in (2×)
64 bulk in (2×) 64 bulk in (2×) 64 bulk in (2×)
ep4
ep6
■ EP2, 4, 6, 8—Eight 512-byte buffers, bulk, interrupt, or
isochronous, of which only the transfer size is available. EP4
and EP8 are double buffered, while EP2 and 6 are either
double, triple, or quad buffered. Regardless of the physical size
of the buffer, each endpoint buffer accommodates only one full
speed packet. For bulk endpoints, the maximum number of
bytes it can accommodate is 64, even though the physical
buffer size is 512 or 1024. For an ISOCHRONOUS endpoint
the maximum number of bytes it can accommodate is 1023.
For endpoint configuration options, see Figure 6 on page 12.
ep8
External FIFO Interface
Architecture
The FX1 slave FIFO architecture has eight 512-byte blocks in the
endpoint RAM that directly serve as FIFO memories, and are
controlled by FIFO control signals (such as IFCLK, SLCS#,
SLRD, SLWR, SLOE, PKTEND, and flags). The usable size of
these buffers depend on the USB transfer mode as described in
the section Organization.
Setup Data Buffer
A separate 8-byte buffer at 0xE6B8-0xE6BF holds the Setup
data from a CONTROL transfer.
In operation, some of the eight RAM blocks fill or empty from the
SIE, while the others are connected to the I/O transfer logic. The
transfer logic takes two forms: the GPIF for internally generated
control signals or the slave FIFO interface for externally
controlled transfers.
Default Alternate Settings
In the following table, ‘0’ means “not implemented”, and ‘2×’
means “double buffered”.
Document Number: 38-08039 Rev. *K
Page 11 of 74
CY7C64713
Figure 6. Endpoint Configuration
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
EP0 IN&OUT
EP1 IN
EP1 OUT
EP2
64
EP2
EP2
EP2 EP2
EP2 EP2
EP2
64
EP2
EP2
64
EP2
EP2
64
64
64
64
64
64
64
1023
1023
1023
1023
64
64
64
64
64
1023
EP4
64
EP4 EP4
64
64
64
64
64
64
64
64
EP6
1023
1023
1023
1023
1023
64
64
64
64
EP6
64
EP6
64
EP6
EP6 EP6
EP6
EP6
EP6 EP6
64
64
1023
1023
64
64
64
64
64
64
1023
1023
1023
64
64
64
64
EP8
64
EP8
64
EP8
64
EP8
64
EP8
64
1023
64
64
64
64
64
64
1023
1023
1023
64
64
64
64
64
10
11
12
9
4
5
8
1
2
3
6
7
Master/Slave Control Signals
as strobes, rather than a clock qualifier as in the synchronous
mode. The signals SLRD, SLWR, SLOE, and PKTEND are gated
by the signal SLCS#.
The FX1 endpoint FIFOS are implemented as eight physically
distinct 256 × 16 RAM blocks. The 8051/SIE can switch any of
the RAM blocks between two domains: the USB (SIE) domain
and the 8051-I/O Unit domain. This switching is done
instantaneously, giving essentially zero transfer time between
“USB FIFOS” and “Slave FIFOS”. While they are physically the
same memory, no bytes are actually transferred between
buffers.
GPIF and FIFO Clock Rates
An 8051 register bit selects one of two frequencies for the
internally supplied interface clock: 30 MHz and 48 MHz.
Alternatively, an externally supplied clock of 5 to 48 MHz feeding
the IFCLK pin is used as the interface clock. IFCLK is configured
to function as an output clock when the GPIF and FIFOs are
internally clocked. An output enable bit in the IFCONFIG register
turns this clock output off, if desired. Another bit within the
IFCONFIG register inverts the IFCLK signal whether internally or
externally sourced.
At any time, some RAM blocks fill or empty with USB data under
SIE control, while other RAM blocks are available to the 8051
and the I/O control unit. The RAM blocks operate as a single-port
in the USB domain, and dual port in the 8051-I/O domain. The
blocks are configured as single, double, triple, or quad buffered.
GPIF
The I/O control unit implements either an internal master (M for
master) or external master (S for Slave) interface.
The GPIF is a flexible 8 or 16-bit parallel interface driven by a
user programmable finite state machine. It allows the
CY7C64713 to perform local bus mastering, and can implement
a wide variety of protocols such as ATA interface, printer parallel
port, and Utopia.
In Master (M) mode, the GPIF internally controls FIFOADR[1..0]
to select a FIFO. The RDY pins (two in the 56-pin package, six
in the 100-pin and 128-pin packages) are used as flag inputs
from an external FIFO or other logic if desired. The GPIF is run
from either an internally derived clock or an externally supplied
clock (IFCLK), at a rate that transfers data up to 96 Megabytes/s
(48 MHz IFCLK with 16-bit interface).
The GPIF has six programmable control outputs (CTL), nine
address outputs (GPIFADRx), and six general purpose Ready
inputs (RDY). The data bus width is 8 or 16 bits. Each GPIF
vector defines the state of the control outputs, and determines
what state a Ready input (or multiple inputs) must be before
proceeding. The GPIF vector is programmed to advance a FIFO
to the next data value, advance an address, and so on. A
sequence of the GPIF vectors create a single waveform that
executes to perform the data move between the FX1 and the
external device.
In Slave (S) mode, the FX1 accepts either an internally derived
clock or an externally supplied clock (IFCLK with a maximum
frequency of 48 MHz) and SLCS#, SLRD, SLWR, SLOE,
PKTEND signals from external logic. When using an external
IFCLK, the external clock must be present before switching to
the external clock with the IFCLKSRC bit. Each endpoint can
individually be selected for byte or word operation by an internal
configuration bit, and a Slave FIFO Output Enable signal SLOE
enables data of the selected width. External logic must ensure
that the output enable signal is inactive when writing data to a
slave FIFO. The slave interface can also operate
asynchronously, where the SLRD and SLWR signals act directly
Six Control OUT Signals
The 100-pin and 128-pin packages bring out all six Control
Output pins (CTL0–CTL5). The 8051 programs the GPIF unit to
define the CTL waveforms. The 56-pin package brings out three
Document Number: 38-08039 Rev. *K
Page 12 of 74
CY7C64713
of these signals: CTL0–CTL2. CTLx waveform edges are
programmed to make transitions as fast as once per clock
(20.8 ns using a 48 MHz clock).
Write any value to ECCRESET, then pass data across the GPIF
or Slave FIFO interface. The ECC for the first 512 bytes of data
is calculated and stored in ECC1; ECC2 is not used. After the
ECC is calculated, the value in ECC1 does not change until the
ECCRESET is written again, even if more data is subsequently
passed across the interface
Six Ready IN Signals
The 100-pin and 128-pin packages bring out all six Ready inputs
(RDY0–RDY5). The 8051 programs the GPIF unit to test the
RDY pins for GPIF branching. The 56 pin package brings out two
of these signals, RDY0–1.
USB Uploads and Downloads
The core has the ability to directly edit the data contents of the
internal 16 KByte RAM and of the internal 512 byte scratch pad
RAM via a vendor specific command. This capability is normally
used when ‘soft’ downloading user code and is available only to
and from the internal RAM, only when the 8051 is held in reset.
The available RAM spaces are 16 KBytes from 0x0000–0x3FFF
(code/data) and 512 bytes from 0xE000–0xE1FF (scratch pad
data RAM).[5]
Nine GPIF Address OUT Signals
Nine GPIF address lines are available in the 100-pin and 128-pin
packages: GPIFADR[8..0]. The GPIF address lines allow
indexing through up to a 512 byte block of RAM. If more address
lines are needed, I/O port pins are used.
Long Transfer Mode
Autopointer Access
In Master mode, the 8051 appropriately sets the GPIF
transaction count registers (GPIFTCB3, GPIFTCB2, GPIFTCB1,
or GPIFTCB0) for unattended transfers of up to 232 transactions.
The GPIF automatically throttles data flow to prevent under or
overflow until the full number of requested transactions are
complete. The GPIF decrements the value in these registers to
represent the current status of the transaction.
FX1 provides two identical autopointers. They are similar to the
internal 8051 data pointers, but with an additional feature: they
can optionally increment after every memory access. This
capability is available to and from both internal and external
RAM. The autopointers are available in external FX1 registers,
under the control of a mode bit (AUTOPTRSETUP.0). Using the
external FX1 autopointer access (at 0xE67B–0xE67C) allows
the autopointer to access all RAM, internal and external, to the
part. Also, the autopointers can point to any FX1 register or
endpoint buffer space. When autopointer access to external
memory is enabled, the location 0xE67B and 0xE67C in XDATA
and the code space cannot be used.
ECC Generation
The EZ-USB FX1 can calculate ECCs (Error Correcting Codes)
on data that pass across its GPIF or Slave FIFO interfaces.
There are two ECC configurations: Two ECCs, each calculated
over 256 bytes (SmartMedia™ Standard); and one ECC
calculated over 512 bytes.
2
I C Controller
The ECC can correct any one-bit error or detect any two-bit error.
FX1 has one I2C port that is driven by two internal controllers:
one that automatically operates at boot time to load VID/PID/DID
and configuration information; and another that the 8051, once
running, uses to control external I2C devices. The I2C port
operates in master mode only.
Note To use the ECC logic, the GPIF or Slave FIFO interface
must be configured for byte-wide operation.
ECC Implementation
The two ECC configurations are selected by the ECCM bit:
I2C Port Pins
0.0.0.1 ECCM = 0
The I2C pins SCL and SDA must have external 2.2 k pull up
resistors even if no EEPROM is connected to the FX1. External
EEPROM device address pins must be configured properly. See
Table 7 for configuring the device address pins.
Two 3-byte ECCs, each calculated over a 256-byte block of data.
This configuration conforms to the SmartMedia Standard.
Write any value to ECCRESET, then pass data across the GPIF
or Slave FIFO interface. The ECC for the first 256 bytes of data
is calculated and stored in ECC1. The ECC for the next 256 bytes
is stored in ECC2. After the second ECC is calculated, the values
in the ECCx registers do not change until the ECCRESET is
written again, even if more data is subsequently passed across
the interface.
Table 7. Strap Boot EEPROM Address Lines to These Values
Bytes
16
Example EEPROM
24LC00[6]
24LC01
A2
N/A
A1
N/A
A0
N/A
128
256
4K
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
24LC02
0.0.0.2 ECCM = 1
24LC32
One 3-byte ECC calculated over a 512-byte block of data.
8K
24LC64
16K
24LC128
Notes
5. After the data is downloaded from the host, a ‘loader’ executes from the internal RAM to transfer downloaded data to the external memory.
6. This EEPROM has no address pins.
Document Number: 38-08039 Rev. *K
Page 13 of 74
CY7C64713
I2C Interface Boot Load Access
plus a combination diagram showing which of the full set of
signals are available in the 128, 100, and 56-pin packages.
At power on reset the I2C interface boot loader loads the
VID/PID/DID configuration bytes and up to 16 KBytes of
program/data. The available RAM spaces are 16 KBytes from
0x0000–0x3FFF and 512 bytes from 0xE000–0xE1FF. The 8051
is in reset. I2C interface boot loads only occur after power on
reset.
The signals on the left edge of the 56-pin package in Figure 7 on
page 15 are common to all versions in the FX1 family. Three
modes are available in all package versions: Port, GPIF master,
and Slave FIFO. These modes define the signals on the right
edge of the diagram. The 8051 selects the interface mode using
the IFCONFIG[1:0] register bits. Port mode is the power on
default configuration.
I2C Interface General Purpose Access
The 8051 can control peripherals connected to the I2C bus using
the I2CTL and I2DAT registers. FX1 provides I2C master control
only, because it is never an I2C slave.
The 100-pin package adds functionality to the 56-pin package by
adding these pins:
■ PORTC or alternate GPIFADR[7:0] address signals
Compatible with Previous Generation EZ-USB FX2
■ PORTE or alternate GPIFADR[8] address signal and seven
The EZ-USB FX1 is fit, form, and function upgradable to the
EZ-USB FX2LP. This makes for an easy transition for designers
wanting to upgrade their systems from full speed to high speed
designs. The pinout and package selection are identical, and all
firmware developed for the FX1 function in the FX2LP with
proper addition of high speed descriptors and speed switching
code.
additional 8051 signals
■ Three GPIF Control signals
■ Four GPIF Ready signals
■ Nine 8051 signals (two USARTs, three timer inputs, INT4,and
INT5#)
■ BKPT, RD#, WR#.
Pin Assignments
The 128-pin package adds the 8051 address and data buses
plus control signals. Note that two of the required signals, RD#
and WR#, are present in the 100-pin version. In the 100-pin and
128-pin versions, an 8051 control bit is set to pulse the RD# and
WR# pins when the 8051 reads from and writes to the PORTC.
Figure 7 on page 15 identifies all signals for the three package
types. The following pages illustrate the individual pin diagrams,
Document Number: 38-08039 Rev. *K
Page 14 of 74
CY7C64713
Figure 7. Signals
GPIF Master
Port
Slave FIFO
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
FD[15]
FD[15]
FD[14]
FD[13]
FD[12]
FD[11]
FD[10]
FD[9]
FD[8]
FD[7]
FD[6]
FD[5]
FD[4]
FD[3]
FD[2]
FD[1]
FD[0]
FD[14]
FD[13]
FD[12]
FD[11]
FD[10]
FD[9]
FD[8]
FD[7]
FD[6]
FD[5]
FD[4]
FD[3]
FD[2]
FD[1]
FD[0]
XTALIN
XTALOUT
RESET#
WAKEUP#
SCL
SDA
56
SLRD
SLWR
RDY0
RDY1
FLAGA
FLAGB
FLAGC
CTL0
CTL1
CTL2
INT0#/PA0
INT1#/PA1
PA2
WU2/PA3
PA4
INT0#/ PA0
INT1#/ PA1
SLOE
INT0#/PA0
INT1#/PA1
PA2
WU2/PA3
PA4
PA5
PA6
IFCLK
CLKOUT
WU2/PA3
FIFOADR0
FIFOADR1
PKTEND
DPLUS
DMINUS
PA5
PA6
PA7
PA7/FLAGD/SLCS#
PA7
CTL3
CTL4
CTL5
RDY2
RDY3
RDY4
RDY5
100
BKPT
PORTC7/GPIFADR7
PORTC6/GPIFADR6
PORTC5/GPIFADR5
PORTC4/GPIFADR4
PORTC3/GPIFADR3
PORTC2/GPIFADR2
PORTC1/GPIFADR1
PORTC0/GPIFADR0
RxD0
TxD0
RxD1
TxD1
INT4
INT5#
T2
PE7/GPIFADR8
PE6/T2EX
PE5/INT6
PE4/RxD1OUT
PE3/RxD0OUT
PE2/T2OUT
PE1/T1OUT
PE0/T0OUT
T1
T0
RD#
WR#
CS#
OE#
PSEN#
D7
D6
D5
D4
D3
D2
D1
D0
A15
A14
A13
A12
A11
A10
A9
128
A8
A7
A6
A5
A4
A3
EA
A2
A1
A0
Document Number: 38-08039 Rev. *K
Page 15 of 74
CY7C64713
Figure 8. CY7C64713 128-pin TQFP Pin Assignment
1
102
CLKOUT
VCC
GND
PD0/FD8
*WAKEUP
VCC
RESET#
2
101
3
100
4
99
RDY0/*SLRD
RDY1/*SLWR
RDY2
RDY3
RDY4
RDY5
AVCC
XTALOUT
XTALIN
AGND
NC
5
98
CTL5
6
97
A3
A2
A1
A0
7
96
8
95
9
94
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
93
GND
92
PA7/*FLAGD/SLCS#
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
PA6/*PKTEND
PA5/FIFOADR1
PA4/FIFOADR0
D7
NC
NC
D6
D5
AVCC
DPLUS
DMINUS
AGND
A11
A12
A13
A14
A15
VCC
GND
INT4
T0
T1
T2
CY7C64713
128-pin TQFP
PA3/*WU2
PA2/*SLOE
PA1/INT1#
PA0/INT0#
VCC
GND
PC7/GPIFADR7
PC6/GPIFADR6
PC5/GPIFADR5
PC4/GPIFADR4
PC3/GPIFADR3
PC2/GPIFADR2
PC1/GPIFADR1
PC0/GPIFADR0
CTL2/*FLAGC
CTL1/*FLAGB
CTL0/*FLAGA
VCC
*IFCLK
RESERVED
BKPT
EA
SCL
SDA
CTL4
CTL3
GND
OE#
* indicates programmable polarity
Document Number: 38-08039 Rev. *K
Page 16 of 74
CY7C64713
Figure 9. CY7C64713 100-pin TQFP Pin Assignment
1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
VCC
GND
PD0/FD8
*WAKEUP
VCC
RESET#
CTL5
2
3
RDY0/*SLRD
RDY1/*SLWR
RDY2
RDY3
RDY4
RDY5
AVCC
XTALOUT
XTALIN
AGND
NC
4
5
6
GND
7
PA7/*FLAGD/SLCS#
PA6/*PKTEND
PA5/FIFOADR1
PA4/FIFOADR0
PA3/*WU2
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
PA2/*SLOE
PA1/INT1#
PA0/INT0#
NC
NC
CY7C64713
100-pin TQFP
VCC
GND
AVCC
DPLUS
DMINUS
AGND
VCC
GND
INT4
T0
T1
PC7/GPIFADR7
PC6/GPIFADR6
PC5/GPIFADR5
PC4/GPIFADR4
PC3/GPIFADR3
PC2/GPIFADR2
PC1/GPIFADR1
PC0/GPIFADR0
CTL2/*FLAGC
CTL1/*FLAGB
CTL0/*FLAGA
VCC
T2
*IFCLK
RESERVED
BKPT
SCL
CTL4
CTL3
SDA
* indicates programmable polarity
Document Number: 38-08039 Rev. *K
Page 17 of 74
CY7C64713
Figure 10. CY7C64713 56-pin SSOP Pin Assignment
CY7C64713
56-pin SSOP
1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
PD5/FD13
PD6/FD14
PD7/FD15
GND
CLKOUT
VCC
PD4/FD12
PD3/FD11
PD2/FD10
PD1/FD9
PD0/FD8
*WAKEUP
VCC
2
3
4
5
6
7
GND
8
RDY0/*SLRD
RDY1/*SLWR
AVCC
XTALOUT
XTALIN
AGND
RESET#
9
GND
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
PA7/*FLAGD/SLCS#
PA6/PKTEND
PA5/FIFOADR1
PA4/FIFOADR0
PA3/*WU2
PA2/*SLOE
PA1/INT1#
PA0/INT0#
VCC
AVCC
DPLUS
DMINUS
AGND
VCC
GND
*IFCLK
RESERVED
SCL
SDA
VCC
CTL2/*FLAGC
CTL1/*FLAGB
CTL0/*FLAGA
GND
VCC
GND
PB7/FD7
PB6/FD6
PB5/FD5
PB4/FD4
PB0/FD0
PB1/FD1
PB2/FD2
PB3/FD3
* indicates programmable polarity
Document Number: 38-08039 Rev. *K
Page 18 of 74
CY7C64713
Figure 11. CY7C64713 56-pin QFN Pin Assignment
RESET#
RDY0/*SLRD
RDY1/*SLWR
AVCC
1
2
42
41
40
39
38
37
36
35
34
33
32
31
30
29
GND
PA7/*FLAGD/SLCS#
PA6/*PKTEND
PA5/FIFOADR1
PA4/FIFOADR0
PA3/*WU2
3
XTALOUT
XTALIN
AGND
4
5
6
CY7C64713
56-pin QFN
AVCC
7
PA2/*SLOE
PA1/INT1#
DPLUS
8
DMINUS
AGND
9
PA0/INT0#
10
11
12
13
14
VCC
VCC
CTL2/*FLAGC
CTL1/*FLAGB
CTL0/*FLAGA
GND
*IFCLK
RESERVED
* indicates programmable polarity
Document Number: 38-08039 Rev. *K
Page 19 of 74
CY7C64713
CY7C64713 Pin Definitions
The FX1 Pin Definitions for CY7C64713 follow.[7]
Table 8. FX1 Pin Definitions
128-pin 100-pin 56-pin 56-pin
Name
Type Default
Description
TQFP TQFP SSOP
QFN
10
17
13
20
9
10
14
13
17
3
AVCC
AVCC
AGND
AGND
Power
Power
N/A
N/A
N/A
N/A
Analog VCC. Connect this pin to 3.3 V power source. This
signal provides power to the analog section of the chip.
16
12
19
7
6
Analog VCC. Connect this pin to 3.3 V power source. This
signal provides power to the analog section of the chip.
Ground
Ground
Analog Ground. Connect to ground with as short a path as
possible.
10
Analog Ground. Connect to ground with as short a path as
possible.
19
18
18
17
16
15
9
8
DMINUS
DPLUS
A0
I/O/Z
I/O/Z
Z
Z
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
Z
Z
Z
Z
Z
Z
Z
Z
H
USB D– Signal. Connect to the USB D– signal.
USB D+ Signal. Connect to the USB D+ signal.
94
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
I/O/Z
8051 Address Bus. This bus is driven at all times. When the
8051 is addressing the internal RAM it reflects the internal
address.
95
A1
96
A2
97
A3
117
118
119
120
126
127
128
21
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
D0
22
23
24
25
59
8051 Data Bus. This bidirectional bus is high impedance when
inactive, input for bus reads, and output for bus writes. The data
bus is used for external 8051 program and data memory. The
data bus is active only for external bus accesses, and is driven
LOW in suspend.
60
D1
I/O/Z
61
D2
I/O/Z
62
D3
I/O/Z
63
D4
I/O/Z
86
D5
I/O/Z
87
D6
I/O/Z
88
D7
I/O/Z
39
PSEN#
Output
Program Store Enable. This active LOW signal indicates an
8051 code fetch from external memory. It is active for program
memory fetches from 0x4000–0xFFFF when the EA pin is
LOW, or from 0x0000–0xFFFF when the EA pin is HIGH.
Note
7. Do not leave unused inputs floating. Tie either HIGH or LOW as appropriate. Pull outputs up or down to ensure signals at power up and in standby. Note that no
pins must be driven when the device is powered down.
Document Number: 38-08039 Rev. *K
Page 20 of 74
CY7C64713
Table 8. FX1 Pin Definitions (continued)
128-pin 100-pin 56-pin 56-pin
Name
Type Default
Description
TQFP TQFP SSOP
QFN
34
28
BKPT
Output
L
Breakpoint. This pin goes active (HIGH) when the 8051
address bus matches the BPADDRH/L registers and
breakpoints are enabled in the BREAKPT register (BPEN = 1).
If the BPPULSE bit in the BREAKPT register is HIGH, this
signal pulses HIGH for eight 12-/24-/48 MHz clocks. If the
BPPULSE bit is LOW, the signal remains HIGH until the 8051
clears the BREAK bit (by writing ‘1’ to it) in the BREAKPT
register.
99
35
77
11
49
12
42
RESET#
EA
Input
Input
N/A
N/A
Active LOW Reset. Resets the entire chip. See the section
Reset and Wakeup on page 8 for more details.
External Access. This pin determines where the 8051 fetches
code between addresses 0x0000 and 0x3FFF. If EA = 0 the
8051 fetches this code from its internal RAM. IF EA = 1 the 8051
fetches this code from external memory.
12
5
XTALIN
Input
N/A
N/A
Crystal Input. Connect this signal to
a
24 MHz
parallel-resonant, fundamental mode crystal and load capacitor
to GND.
It is also correct to drive the XTALIN with an external 24 MHz
square wave derived from another clock source. When driving
from an external source, the driving signal must be a 3.3 V
square wave.
11
1
10
11
5
4
XTALOUT Output
Crystal Output. Connect this signal to
a
24 MHz
parallel-resonant, fundamental mode crystal and load capacitor
to GND.
If an external clock is used to drive XTALIN, leave this pin open.
100
54
CLKOUT
O/Z
12 MHz CLKOUT. 12, 24 or 48 MHz clock, phase locked to the 24 MHz
input clock. The 8051 defaults to 12 MHz operation. The 8051
may three-state this output by setting CPUCS.1 = 1.
Port A
82
67
68
40
41
33
34
PA0 or
INT0#
I/O/Z
I/O/Z
I (PA0) Multiplexed pin whose function is selected by PORTACFG.0
PA0 is a bidirectional I/O port pin.
INT0# is the active-LOW 8051 INT0 interrupt input signal, which
is either edge triggered (IT0 = 1) or level triggered (IT0 = 0).
83
84
PA1 or
INT1#
I (PA1) Multiplexed pin whose function is selected by:
PORTACFG.1
PA1 is a bidirectional I/O port pin.
INT1# is the active-LOW 8051 INT1 interrupt input signal, which
is either edge triggered (IT1 = 1) or level triggered (IT1 = 0).
69
70
42
43
35
36
PA2 or
SLOE
I/O/Z
I/O/Z
I (PA2) Multiplexed pin whose function is selected by two bits:
IFCONFIG[1:0].
PA2 is a bidirectional I/O port pin.
SLOE is an input-only output enable with programmable
polarity (FIFOPINPOLAR.4) for the slave FIFOs connected to
FD[7..0] or FD[15..0].
85
PA3 or
WU2
I (PA3) Multiplexed pin whose function is selected by:
WAKEUP.7 and OEA.3
PA3 is a bidirectional I/O port pin.
WU2 is an alternate source for USB Wakeup, enabled by
WU2EN bit (WAKEUP.1) and polarity set by WU2POL
(WAKEUP.4). If the 8051 is in suspend and WU2EN = 1, a
transition on this pin starts up the oscillator and interrupts the
8051 to allow it to exit the suspend mode. Asserting this pin
inhibits the chip from suspending, if WU2EN = 1.
Document Number: 38-08039 Rev. *K
Page 21 of 74
CY7C64713
Table 8. FX1 Pin Definitions (continued)
128-pin 100-pin 56-pin 56-pin
Name
Type Default
Description
TQFP TQFP SSOP
QFN
89
90
91
71
72
73
44
45
46
37
PA4 or
FIFOADR0
I/O/Z
I/O/Z
I/O/Z
I (PA4) Multiplexed pin whose function is selected by:
IFCONFIG[1..0].
PA4 is a bidirectional I/O port pin.
FIFOADR0 is an input-only address select for the slave FIFOs
connected to FD[7..0] or FD[15..0].
38
39
PA5 or
FIFOADR1
I (PA5) Multiplexed pin whose function is selected by:
IFCONFIG[1..0].
PA5 is a bidirectional I/O port pin.
FIFOADR1 is an input-only address select for the slave FIFOs
connected to FD[7..0] or FD[15..0].
PA6 or
PKTEND
I (PA6) Multiplexed pin whose function is selected by the
IFCONFIG[1:0] bits.
PA6 is a bidirectional I/O port pin.
PKTEND is an input used to commit the FIFO packet data to
the endpoint and whose polarity is programmable via
FIFOPINPOLAR.5.
92
74
47
40
PA7 or
FLAGD or
SLCS#
I/O/Z
I (PA7) Multiplexed pin whose function is selected by the
IFCONFIG[1:0] and PORTACFG.7 bits.
PA7 is a bidirectional I/O port pin.
FLAGD is a programmable slave-FIFO output status flag
signal.
SLCS# gates all other slave FIFO enable/strobes
Port B
44
34
35
36
37
44
45
46
25
26
27
28
29
30
31
18
19
20
21
22
23
24
PB0 or
FD[0]
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I (PB0) Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
PB0 is a bidirectional I/O port pin.
FD[0] is the bidirectional FIFO/GPIF data bus.
45
46
47
54
55
56
PB1 or
FD[1]
I (PB1) Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
PB1 is a bidirectional I/O port pin.
FD[1] is the bidirectional FIFO/GPIF data bus.
PB2 or
FD[2]
I (PB2) Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
PB2 is a bidirectional I/O port pin.
FD[2] is the bidirectional FIFO/GPIF data bus.
PB3 or
FD[3]
I (PB3) Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
PB3 is a bidirectional I/O port pin.
FD[3] is the bidirectional FIFO/GPIF data bus.
PB4 or
FD[4]
I (PB4) Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
PB4 is a bidirectional I/O port pin.
FD[4] is the bidirectional FIFO/GPIF data bus.
PB5 or
FD[5]
I (PB5) Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
PB5 is a bidirectional I/O port pin.
FD[5] is the bidirectional FIFO/GPIF data bus.
PB6 or
FD[6]
I (PB6) Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
PB6 is a bidirectional I/O port pin.
FD[6] is the bidirectional FIFO/GPIF data bus.
Document Number: 38-08039 Rev. *K
Page 22 of 74
CY7C64713
Table 8. FX1 Pin Definitions (continued)
128-pin 100-pin 56-pin 56-pin
Name
Type Default
Description
TQFP TQFP SSOP
QFN
57
47
32
25
PB7 or
FD[7]
I/O/Z
I (PB7) Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
PB7 is a bidirectional I/O port pin.
FD[7] is the bidirectional FIFO/GPIF data bus.
PORT C
72
57
58
59
60
61
62
63
64
PC0 or
GPIFADR0
I/O/Z I (PC0) Multiplexed pin whose function is selected by PORTCCFG.0
PC0 is a bidirectional I/O port pin.
GPIFADR0 is a GPIF address output pin.
73
74
75
76
77
78
79
PC1 or
GPIFADR1
I/O/Z I (PC1) Multiplexed pin whose function is selected by PORTCCFG.1
PC1 is a bidirectional I/O port pin.
GPIFADR1 is a GPIF address output pin.
PC2 or
GPIFADR2
I/O/Z I (PC2) Multiplexed pin whose function is selected by PORTCCFG.2
PC2 is a bidirectional I/O port pin.
GPIFADR2 is a GPIF address output pin.
PC3 or
GPIFADR3
I/O/Z I (PC3) Multiplexed pin whose function is selected by PORTCCFG.3
PC3 is a bidirectional I/O port pin.
GPIFADR3 is a GPIF address output pin.
PC4 or
GPIFADR4
I/O/Z I (PC4) Multiplexed pin whose function is selected by PORTCCFG.4
PC4 is a bidirectional I/O port pin.
GPIFADR4 is a GPIF address output pin.
PC5 or
GPIFADR5
I/O/Z I (PC5) Multiplexed pin whose function is selected by PORTCCFG.5
PC5 is a bidirectional I/O port pin.
GPIFADR5 is a GPIF address output pin.
PC6 or
GPIFADR6
I/O/Z I (PC6) Multiplexed pin whose function is selected by PORTCCFG.6
PC6 is a bidirectional I/O port pin.
GPIFADR6 is a GPIF address output pin.
PC7 or
GPIFADR7
I/O/Z I (PC7) Multiplexed pin whose function is selected by PORTCCFG.7
PC7 is a bidirectional I/O port pin.
GPIFADR7 is a GPIF address output pin.
PORT D
102
80
81
82
83
95
96
97
52
53
54
55
56
1
45
46
47
48
49
50
51
PD0 or
FD[8]
I/O/Z I (PD0) Multiplexed pin whose function is selected by the
IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide) bits.
FD[8] is the bidirectional FIFO/GPIF data bus.
103
104
105
121
122
123
PD1 or
FD[9]
I/O/Z I (PD1) Multiplexed pin whose function is selected by the
IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide) bits.
FD[9] is the bidirectional FIFO/GPIF data bus.
PD2 or
FD[10]
I/O/Z I (PD2) Multiplexed pin whose function is selected by the
IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide) bits.
FD[10] is the bidirectional FIFO/GPIF data bus.
PD3 or
FD[11]
I/O/Z I (PD3) Multiplexed pin whose function is selected by the
IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide) bits.
FD[11] is the bidirectional FIFO/GPIF data bus.
PD4 or
FD[12]
I/O/Z I (PD4) Multiplexed pin whose function is selected by the
IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide) bits.
FD[12] is the bidirectional FIFO/GPIF data bus.
PD5 or
FD[13]
I/O/Z I (PD5) Multiplexed pin whose function is selected by the
IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide) bits.
FD[13] is the bidirectional FIFO/GPIF data bus.
2
PD6 or
FD[14]
I/O/Z I (PD6) Multiplexed pin whose function is selected by the
IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide) bits.
FD[14] is the bidirectional FIFO/GPIF data bus.
Document Number: 38-08039 Rev. *K
Page 23 of 74
CY7C64713
Table 8. FX1 Pin Definitions (continued)
128-pin 100-pin 56-pin 56-pin
Name
Type Default
Description
TQFP TQFP SSOP
QFN
124
98
3
52
PD7 or
FD[15]
I/O/Z I (PD7) Multiplexed pin whose function is selected by the
IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide) bits.
FD[15] is the bidirectional FIFO/GPIF data bus.
Port E
108
86
PE0 or
T0OUT
I/O/Z
I/O/Z
I (PE0) Multiplexed pin whose function is selected by the PORTECFG.0
bit.
PE0 is a bidirectional I/O port pin.
T0OUT is an active HIGH signal from 8051 Timer-counter0.
T0OUT outputs a high level for one CLKOUT clock cycle when
Timer0 overflows. If Timer0 is operated in Mode 3 (two separate
timer/counters), T0OUT is active when the low byte
timer/counter overflows.
109
87
PE1 or
T1OUT
I (PE1) Multiplexed pin whose function is selected by the PORTECFG.1
bit.
PE1 is a bidirectional I/O port pin.
T1OUT is an active HIGH signal from 8051 Timer-counter1.
T1OUT outputs a high level for one CLKOUT clock cycle when
Timer1 overflows. If Timer1 is operated in Mode 3 (two separate
timer/counters), T1OUT is active when the low byte
timer/counter overflows.
110
111
88
89
PE2 or
T2OUT
I/O/Z
I/O/Z
I (PE2) Multiplexed pin whose function is selected by the PORTECFG.2
bit.
PE2 is a bidirectional I/O port pin.
T2OUT is the active HIGH output signal from 8051 Timer2.
T2OUT is active (HIGH) for one clock cycle when
Timer/Counter 2 overflows.
PE3 or
RXD0OUT
I (PE3) Multiplexed pin whose function is selected by the PORTECFG.3
bit.
PE3 is a bidirectional I/O port pin.
RXD0OUT is an active HIGH signal from 8051 UART0. If
RXD0OUT is selected and UART0 is in Mode 0, this pin
provides the output data for UART0 only when it is in sync
mode. Otherwise it is a 1.
112
90
PE4 or
RXD1OUT
I/O/Z
I (PE4) Multiplexed pin whose function is selected by the PORTECFG.4
bit.
PE4 is a bidirectional I/O port pin.
RXD1OUT is an active HIGH output from 8051 UART1. When
the RXD1OUT is selected and UART1 is in Mode 0, this pin
provides the output data for UART1 only when it is in sync
mode. In Modes 1, 2, and 3, this pin is HIGH.
113
114
91
92
PE5 or
INT6
I/O/Z
I/O/Z
I (PE5) Multiplexed pin whose function is selected by the PORTECFG.5
bit.
PE5 is a bidirectional I/O port pin.
INT6 is the 8051 INT6 interrupt request input signal. The INT6
pin is edge-sensitive, active HIGH.
PE6 or
T2EX
I (PE6) Multiplexed pin whose function is selected by the PORTECFG.6
bit.
PE6 is a bidirectional I/O port pin.
T2EX is an active HIGH input signal to the 8051 Timer2. T2EX
reloads timer 2 on its falling edge. T2EX is active only if the
EXEN2 bit is set in T2CON.
115
93
PE7 or
GPIFADR8
I/O/Z
I (PE7) Multiplexed pin whose function is selected by the PORTECFG.7
bit.
PE7 is a bidirectional I/O port pin.
GPIFADR8 is a GPIF address output pin.
Document Number: 38-08039 Rev. *K
Page 24 of 74
CY7C64713
Table 8. FX1 Pin Definitions (continued)
128-pin 100-pin 56-pin 56-pin
Name
Type Default
Description
TQFP TQFP SSOP
QFN
4
3
8
1
RDY0 or
SLRD
Input
N/A
Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
RDY0 is a GPIF input signal.
SLRD is the input-only read strobe with programmable polarity
(FIFOPINPOLAR.3) for the slave FIFOs connected to FD[7..0]
or FD[15..0].
5
4
9
2
RDY1 or
SLWR
Input
N/A
Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
RDY1 is a GPIF input signal.
SLWR is the input-only write strobe with programmable polarity
(FIFOPINPOLAR.2) for the slave FIFOs connected to FD[7..0]
or FD[15..0].
6
7
5
6
RDY2
RDY3
RDY4
RDY5
Input
Input
Input
Input
O/Z
N/A
N/A
N/A
N/A
H
RDY2 is a GPIF input signal.
RDY3 is a GPIF input signal.
RDY4 is a GPIF input signal.
RDY5 is a GPIF input signal.
8
7
9
8
69
54
36
37
38
29
30
31
CTL0 or
FLAGA
Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
CTL0 is a GPIF control output.
FLAGA is a programmable slave-FIFO output status flag
signal.
Defaults to programmable for the FIFO selected by the
FIFOADR[1:0] pins.
70
71
55
56
CTL1 or
FLAGB
O/Z
O/Z
H
H
Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
CTL1 is a GPIF control output.
FLAGB is a programmable slave-FIFO output status flag
signal.
Defaults to FULL for the FIFO selected by the FIFOADR[1:0]
pins.
CTL2 or
FLAGC
Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
CTL2 is a GPIF control output.
FLAGC is a programmable slave-FIFO output status flag
signal.
Defaults to EMPTY for the FIFO selected by the FIFOADR[1:0]
pins.
66
67
98
32
51
52
76
26
CTL3
CTL4
CTL5
IFCLK
O/Z
H
H
H
Z
CTL3 is a GPIF control output.
CTL4 is a GPIF control output.
CTL5 is a GPIF control output.
Output
Output
I/O/Z
20
13
Interface Clock, used for synchronously clocking data into or
out of the slave FIFOs. IFCLK also serves as a timing reference
for all slave FIFO control signals and GPIF. When internal
clocking is used (IFCONFIG.7 = 1) the IFCLK pin is configured
to output 30/48 MHz by bits IFCONFIG.5 and IFCONFIG.6.
IFCLK may be inverted, whether internally or externally
sourced, by setting the bit IFCONFIG.4 = 1.
28
22
84
INT4
Input
Input
N/A
N/A
INT4 is the 8051 INT4 interrupt request input signal. The INT4
pin is edge-sensitive, active HIGH.
106
INT5#
INT5# is the 8051 INT5 interrupt request input signal. The INT5
pin is edge-sensitive, active LOW.
Document Number: 38-08039 Rev. *K
Page 25 of 74
CY7C64713
Table 8. FX1 Pin Definitions (continued)
128-pin 100-pin 56-pin 56-pin
Name
Type Default
Description
TQFP TQFP SSOP
QFN
31
30
29
25
24
23
T2
Input
Input
Input
N/A
N/A
N/A
T2 is the active-HIGH T2 input signal to 8051 Timer2, which
provides the input to Timer2 when C/T2 = 1. When C/T2 = 0,
Timer2 does not use this pin.
T1
T0
T1 is the active-HIGH T1 signal for 8051 Timer1, which provides
the input to Timer1 when C/T1 is 1. When C/T1 is 0, Timer1
does not use this bit.
T0 is the active-HIGH T0 signal for 8051 Timer0, which provides
the input to Timer0 when C/T0 is 1. When C/T0 is 0, Timer0
does not use this bit.
53
52
43
42
RXD1
TXD1
Input
N/A
H
RXD1 is an active-HIGH input signal for 8051 UART1, which
provides data to the UART in all modes.
Output
TXD1 is an active-HIGH output pin from 8051 UART1, which
provides the output clock in sync mode, and the output data in
async mode.
51
50
41
40
RXD0
TXD0
Input
N/A
H
RXD0 is the active-HIGH RXD0 input to 8051 UART0, which
provides data to the UART in all modes.
Output
TXD0 is the active-HIGH TXD0 output from 8051 UART0, which
provides the output clock in sync mode, and the output data in
async mode.
42
41
40
38
33
CS#
WR#
RD#
OE#
Output
Output
Output
Output
H
H
CS# is the active-LOW chip select for external memory.
WR# istheactive-LOWwritestrobeoutputforexternalmemory.
RD# is the active-LOW read strobe output for external memory.
OE# is the active LOW output enable for external memory.
Reserved. Connect to ground.
32
31
H
H
27
79
21
51
14
44
Reserved Input
N/A
101
WAKEUP Input
N/A
USB Wakeup. If the 8051 is in suspend, asserting this pin starts
up the oscillator and interrupts the 8051 to allow it to exit the
suspend mode. Holding WAKEUP asserted inhibits the
EZ-USB FX1 chip from suspending. This pin has
programmable polarity (WAKEUP.4).
36
37
29
30
22
23
15
16
SCL
SDA
OD
OD
Z
Z
Clock for the I2C interface. Connect to VCC with a 2.2K
resistor, even if no I2C peripheral is attached.
Data for I2C interface. Connect to VCC with a 2.2K resistor,
even if no I2C peripheral is attached.
2
1
6
55
11
17
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
Power
Power
Power
Power
Power
Power
Power
Power
Power
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
VCC. Connect to 3.3 V power source.
VCC. Connect to 3.3 V power source.
VCC. Connect to 3.3 V power source.
VCC. Connect to 3.3 V power source.
VCC. Connect to 3.3 V power source.
VCC. Connect to 3.3 V power source.
VCC. Connect to 3.3 V power source.
VCC. Connect to 3.3 V power source.
VCC. Connect to 3.3 V power source.
26
20
33
38
49
53
66
78
85
18
24
43
48
64
34
27
68
81
39
50
32
43
100
107
3
2
7
56
12
GND
GND
Ground
Ground
N/A
N/A
Ground.
Ground.
27
21
19
Document Number: 38-08039 Rev. *K
Page 26 of 74
CY7C64713
Table 8. FX1 Pin Definitions (continued)
128-pin 100-pin 56-pin 56-pin
Name
Type Default
Description
TQFP TQFP SSOP
QFN
49
58
39
48
50
65
75
94
99
GND
GND
GND
GND
GND
GND
GND
Ground
Ground
Ground
Ground
Ground
Ground
Ground
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
33
35
26
28
65
80
93
48
4
41
53
116
125
14
15
16
13
14
15
NC
NC
NC
N/A
N/A
N/A
N/A
N/A
N/A
No Connect. This pin must be left open.
No Connect. This pin must be left open.
No Connect. This pin must be left open.
Document Number: 38-08039 Rev. *K
Page 27 of 74
CY7C64713
Register Summary
FX1 register bit definitions are described in the EZ-USB TRM in greater detail.
Table 9. FX1 Register Summary
Hex Size
Name
Description
b7
b6
b5
b4
b3
b2
b1
b0
Default Access
GPIF Waveform Memories
E400 128 WAVEDATA
GPIF
D7
D6
D5
D4
D3
D2
D1
D0
xxxxxxxx
RW
Waveform
Descriptor 0,
1, 2, 3 data
E480 128 reserved
GENERAL CONFIGURATION
E600
E601
1
1
CPUCS
CPU Control
& Status
Interface
Configuration
(Ports, GPIF,
slave FIFOs)
Slave FIFO
FLAGA and
FLAGB Pin
Configuration
Slave FIFO
FLAGC and
FLAGD Pin
Configuration
Restore
FIFOS to
default state
0
0
PORTCSTB CLKSPD1 CLKSPD0
CLKINV
GSTATE
CLKOE
IFCFG1
8051RES 00000010 rrbbbbbr
IFCFG0 10000000 RW
IFCONFIG
IFCLKSRC 3048MHZ
IFCLKOE IFCLKPOL
ASYNC
FLAGA3
FLAGC3
EP3
[8]
[8]
E602
E603
E604
1
1
1
PINFLAGSAB
FLAGB3
FLAGD3
NAKALL
FLAGB2
FLAGD2
0
FLAGB1
FLAGD1
0
FLAGB0
FLAGD0
0
FLAGA2
FLAGC2
EP2
FLAGA1
FLAGC1
EP1
FLAGA0 00000000 RW
FLAGC0 00000000 RW
PINFLAGSCD
[8]
FIFORESET
EP0
xxxxxxxx
W
E605
E606
E607
E608
1
1
1
1
BREAKPT
BPADDRH
BPADDRL
UART230
Breakpoint
Control
Breakpoint
Address H
Breakpoint
Address L
230 Kbaud
internally
generatedref.
clock
0
A15
A7
0
0
A14
A6
0
0
A13
A5
0
0
A12
A4
0
BREAK
A11
A3
BPPULSE
BPEN
A9
0
00000000 rrrrbbbr
A10
A2
0
A8
A0
xxxxxxxx
xxxxxxxx
RW
RW
A1
0
230UART1 230UART0 00000000 rrrrrrbb
[8]
E609
1
FIFOPINPOLAR
Slave FIFO
Interface pins
polarity
0
0
PKTEND
SLOE
SLRD
SLWR
EF
FF
00000000 rrbbbbbb
E60A
E60B
1
1
REVID
Chip Revision
rv7
0
rv6
0
rv5
0
rv4
0
rv3
0
rv2
0
rv1
rv0
RevA
R
00000001
[8]
REVCTL
Chip Revision
Control
dyn_out
enh_pkt 00000000 rrrrrrbb
Note
8. Read and writes to these register may require synchronization delay, see the section “Synchronization Delay” in the EZ-USB TRM.
Document Number: 38-08039 Rev. *K
Page 28 of 74
CY7C64713
Table 9. FX1 Register Summary (continued)
Hex Size
Name
Description
b7
b6
b5
b4
b3
b2
b1
b0
Default Access
UDMA
E60C
1
GPIFHOLDAMOUNT
MSTB Hold
Time (for
UDMA)
0
0
0
0
0
0
HOLDTIME1 HOLDTIME0 00000000 rrrrrrbb
3
1
reserved
ENDPOINT CONFIGURATION
EP1OUTCFG
E610
Endpoint
VALID
0
TYPE1
TYPE0
0
0
0
0
10100000 brbbrrrr
1-OUT
Configuration
E611
E612
E613
E614
E615
1
1
1
1
1
EP1INCFG
EP2CFG
EP4CFG
EP6CFG
EP8CFG
Endpoint 1-IN
Configuration
Endpoint 2
Configuration
Endpoint 4
Configuration
Endpoint 6
Configuration
VALID
VALID
VALID
VALID
VALID
0
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE0
TYPE0
TYPE0
TYPE0
TYPE0
0
SIZE
0
0
0
0
0
0
0
BUF1
0
0
BUF0
0
10100000 brbbrrrr
10100010 bbbbbrbb
10100000 bbbbrrrr
11100010 bbbbbrbb
11100000 bbbbrrrr
DIR
DIR
DIR
DIR
SIZE
0
BUF1
0
BUF0
0
Endpoint 8
Configuration
2
1
reserved
EP2FIFOCFG
[9]
[9]
[9]
[9]
E618
E619
E61A
E61B
Endpoint 2 /
slave FIFO
configuration
Endpoint 4 /
slave FIFO
configuration
Endpoint 6 /
slave FIFO
configuration
Endpoint 8 /
slave FIFO
configuration
0
0
0
0
INFM1
INFM1
INFM1
INFM1
OEP1
OEP1
OEP1
OEP1
AUTOOUT
AUTOOUT
AUTOOUT
AUTOOUT
AUTOIN ZEROLENIN
AUTOIN ZEROLENIN
AUTOIN ZEROLENIN
AUTOIN ZEROLENIN
0
0
0
0
WORDWIDE 00000101 rbbbbbrb
WORDWIDE 00000101 rbbbbbrb
WORDWIDE 00000101 rbbbbbrb
WORDWIDE 00000101 rbbbbbrb
1
1
1
EP4FIFOCFG
EP6FIFOCFG
EP8FIFOCFG
reserved
E61C
E620
4
1
[9]
EP2AUTOINLENH
Endpoint 2
AUTOIN
Packet
0
0
0
0
0
PL10
PL2
PL9
PL1
PL8
PL0
00000010 rrrrrbbb
00000000 RW
Length H
[9]
E621
1
EP2AUTOINLENL
Endpoint 2
AUTOIN
Packet
PL7
PL6
PL5
PL4
PL3
Length L
Note
9. Read and writes to these register may require synchronization delay, see the section “Synchronization Delay” in the EZ-USB TRM.
Document Number: 38-08039 Rev. *K
Page 29 of 74
CY7C64713
Table 9. FX1 Register Summary (continued)
Hex Size
Name
EP4AUTOINLENH
Description
b7
0
b6
0
b5
0
b4
0
b3
0
b2
0
b1
PL9
b0
PL8
Default Access
00000010 rrrrrrbb
[10]
E622
E623
E624
E625
E626
E627
E628
1
1
1
1
1
1
1
Endpoint 4
AUTOIN
Packet
Length H
[10]
[10]
EP4AUTOINLENL
Endpoint 4
AUTOIN
Packet
PL7
0
PL6
0
PL5
0
PL4
0
PL3
0
PL2
PL10
PL2
0
PL1
PL9
PL1
PL9
PL1
0
PL0
PL8
00000000 RW
00000010 rrrrrbbb
00000000 RW
00000010 rrrrrrbb
00000000 RW
00000000 rrrrrrrb
Length L
EP6AUTOINLENH
Endpoint 6
AUTOIN
Packet
Length H
[10]
EP6AUTOINLENL
EP8AUTOINLENH
Endpoint 6
AUTOIN
Packet
PL7
0
PL6
0
PL5
0
PL4
0
PL3
0
PL0
Length L
[10]
Endpoint 8
AUTOIN
Packet
PL8
Length H
[10]
EP8AUTOINLENL
Endpoint 8
AUTOIN
Packet
Length L
ECC Configu-
ration
PL7
0
PL6
0
PL5
0
PL4
0
PL3
0
PL2
0
PL0
ECCCFG
ECCM
E629
E62A
1
1
ECCRESET
ECC1B0
ECC Reset
ECC1 Byte 0
Address
x
x
x
x
x
x
x
x
00000000
11111111
W
R
LINE15
LINE14
LINE13
LINE12
LINE11
LINE10
LINE9
LINE8
E62B
E62C
E62D
E62E
E62F
1
1
1
1
1
ECC1B1
ECC1B2
ECC2B0
ECC2B1
ECC2B2
ECC1 Byte 1
Address
ECC1 Byte 2
Address
ECC2 Byte 0
Address
ECC2 Byte 1
Address
LINE7
COL5
LINE6
COL4
LINE5
COL3
LINE4
COL2
LINE3
COL1
LINE11
LINE3
COL1
LINE2
COL0
LINE1
LINE17
LINE9
LINE1
0
LINE0
LINE16
LINE8
LINE0
0
11111111
11111111
11111111
11111111
11111111
R
R
R
R
R
LINE15
LINE7
COL5
LINE14
LINE6
COL4
LINE13
LINE5
COL3
LINE12
LINE4
COL2
LINE10
LINE2
COL0
ECC2 Byte 2
Address
Note
10. Read and writes to these register may require synchronization delay, see the section “Synchronization Delay” in the EZ-USB TRM.
Document Number: 38-08039 Rev. *K
Page 30 of 74
CY7C64713
Table 9. FX1 Register Summary (continued)
Hex Size
Name
Description
b7
b6
b5
b4
b3
b2
b1
b0
Default Access
[11]
Endpoint 2 /
slave FIFO
Programmable
Flag H ISO
Mode
E630
E630
1
1
EP2FIFOPFH
DECIS
PKTSTAT IN: PKTS[2] IN: PKTS[1] IN: PKTS[0]
OUT:PFC12 OUT:PFC11 OUT:PFC10
0
PFC9
PFC8
10001000 bbbbbrbb
[11]
Endpoint 2 /
slave FIFO
Programmable
Flag H
EP2FIFOPFH
DECIS
PKTSTAT OUT:PFC12 OUT:PFC11 OUT:PFC10
0
PFC9
PFC1
IN:PKTS[2] 10001000 bbbbbrbb
OUT:PFC8
Non-ISO Mode
[11]
[11]
Endpoint 2 /
slave FIFO
Programmable
Flag L
E631
1
EP2FIFOPFL
IN:PKTS[1] IN:PKTS[0]
OUT:PFC7 OUT:PFC6
PFC5
PFC4
PFC3
PFC2
PFC0
00000000 RW
Endpoint 4 /
slave FIFO
Programmable
Flag H ISO
Mode
E632
E632
1
1
EP4FIFOPFH
DECIS
DECIS
PKTSTAT
PKTSTAT
0
0
IN: PKTS[1] IN: PKTS[0]
OUT:PFC10 OUT:PFC9
0
0
0
0
PFC8
PFC8
10001000 bbrbbrrb
10001000 bbrbbrrb
[11]
Endpoint 4 /
slave FIFO
Programmable
Flag H
EP4FIFOPFH
OUT:PFC10 OUT:PFC9
Non-ISO Mode
[11]
[11]
Endpoint 4 /
slave FIFO
Programmable
Flag L
E633
1
EP4FIFOPFL
IN: PKTS[1] IN: PKTS[0]
OUT:PFC7 OUT:PFC6
PFC5
PFC4
PFC3
PFC2
PFC1
PFC0
PFC8
00000000 RW
Endpoint 6 /
slave FIFO
Programmable
Flag H ISO
Mode
E634
E634
1
1
EP6FIFOPFH
DECIS
DECIS
PKTSTAT INPKTS[2] IN: PKTS[1] IN: PKTS[0]
OUT:PFC12 OUT:PFC11 OUT:PFC10
0
0
PFC9
PFC9
00001000 bbbbbrbb
[11]
Endpoint 6 /
slave FIFO
Programmable
Flag H
EP6FIFOPFH
PKTSTAT OUT:PFC12 OUT:PFC11 OUT:PFC10
IN:PKTS[2] 00001000 bbbbbrbb
OUT:PFC8
Non-ISO Mode
Note
11. Read and writes to these register may require synchronization delay, see the section “Synchronization Delay” in the EZ-USB TRM.
Document Number: 38-08039 Rev. *K
Page 31 of 74
CY7C64713
Table 9. FX1 Register Summary (continued)
Hex Size
Name
Description
b7
b6
b5
b4
b3
b2
b1
b0
Default Access
[12]
Endpoint 6 /
slave FIFO
Programmable
Flag L
E635
1
EP6FIFOPFL
IN:PKTS[1] IN:PKTS[0]
OUT:PFC7 OUT:PFC6
PFC5
PFC4
PFC3
PFC2
PFC1
PFC0
00000000 RW
[12]
[12]
Endpoint 8 /
slave FIFO
Programmable
Flag H ISO
Mode
E636
E636
1
1
EP8FIFOPFH
DECIS
DECIS
PKTSTAT
PKTSTAT
0
0
IN: PKTS[1] IN: PKTS[0]
OUT:PFC10 OUT:PFC9
0
0
0
0
PFC8
PFC8
00001000 bbrbbrrb
00001000 bbrbbrrb
Endpoint 8 /
slave FIFO
Programmable
Flag H
EP8FIFOPFH
OUT:PFC10 OUT:PFC9
Non-ISO Mode
[12]
[12]
Endpoint 8 /
slave FIFO
Programmable
Flag L
E637
E637
1
1
EP8FIFOPFL
Mode
ISO
PFC7
PFC6
PFC5
PFC5
PFC4
PFC4
PFC3
PFC3
PFC2
PFC2
PFC1
PFC1
PFC0
PFC0
00000000 RW
00000000 RW
Endpoint 8 /
slave FIFO
Programmable
Flag L
EP8FIFOPFL
IN: PKTS[1] IN: PKTS[0]
OUT:PFC7 OUT:PFC6
Non-ISO Mode
8
1
1
1
1
4
1
reserved
reserved
reserved
reserved
reserved
reserved
E640
E641
E642
E643
E644
E648
[12]
INPKTEND
Force IN
Skip
Skip
0
0
0
0
0
0
EP3
EP3
EP2
EP2
EP1
EP1
EP0
EP0
xxxxxxxx
xxxxxxxx
W
W
Packet End
[12]
E649
7
OUTPKTEND
Force OUT
Packet End
INTERRUPTS
[14]
E650
1
EP2FIFOIE
Endpoint 2
slave FIFO
Flag Interrupt
Enable
0
0
0
0
EDGEPF
PF
EF
FF
00000000 RW
Note
12. Read and writes to these register may require synchronization delay, see the section “Synchronization Delay” in the EZ-USB TRM.
Document Number: 38-08039 Rev. *K
Page 32 of 74
CY7C64713
Table 9. FX1 Register Summary (continued)
Hex Size
Name
EP2FIFOIRQ
Description
b7
0
b6
0
b5
0
b4
0
b3
0
b2
PF
b1
EF
b0
FF
Default Access
00000111 rrrrrbbb
[13, 14]
E651
E652
E653
E654
E655
E656
E657
1
1
1
1
1
1
1
Endpoint 2
slave FIFO
Flag Interrupt
Request
Endpoint 4
slave FIFO
Flag Interrupt
Enable
Endpoint 4
slave FIFO
Flag Interrupt
Request
Endpoint 6
slave FIFO
Flag Interrupt
Enable
Endpoint 6
slave FIFO
Flag Interrupt
Request
Endpoint 8
slave FIFO
Flag Interrupt
Enable
Endpoint 8
slave FIFO
Flag Interrupt
Request
IN-BULK-NA
K Interrupt
Enable
[14]
EP4FIFOIE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
EDGEPF
PF
PF
PF
PF
PF
PF
EF
EF
EF
EF
EF
EF
FF
FF
FF
FF
FF
FF
00000000 RW
00000111 rrrrrbbb
00000000 RW
00000110 rrrrrbbb
00000000 RW
00000110 rrrrrbbb
[13, 14]
[15, 16]
[13, 14]
EP4FIFOIRQ
0
[14]
EP6FIFOIE
EDGEPF
EP6FIFOIRQ
0
EDGEPF
0
[16]
EP8FIFOIE
EP8FIFOIRQ
IBNIE
E658
E659
E65A
1
1
1
0
0
0
0
EP8
EP8
EP4
EP6
EP6
EP2
EP4
EP4
EP1
EP2
EP2
EP0
EP1
EP1
0
EP0
EP0
IBN
00000000 RW
00xxxxxx rrbbbbbb
00000000 RW
[13]
IBNIRQ
IN-BULK-NA
K interrupt
Request
NAKIE
Endpoint
EP8
EP6
Ping-NAK /
IBN Interrupt
Enable
[13]
E65B
1
NAKIRQ
Endpoint
EP8
EP6
EP4
EP2
EP1
EP0
0
IBN
xxxxxx0x bbbbbbrb
Ping-NAK /
IBN Interrupt
Request
Notes
13. SFRs not part of the standard 8051 architecture.
14. Read and writes to these register may require synchronization delay, see the section “Synchronization Delay” in the EZ-USB TRM.
Document Number: 38-08039 Rev. *K
Page 33 of 74
CY7C64713
Table 9. FX1 Register Summary (continued)
Hex Size
Name
Description
b7
b6
b5
b4
b3
b2
b1
b0
Default Access
E65C
E65D
E65E
1
1
1
USBIE
USBIRQ
EPIE
USB Int
Enables
USB Interrupt
Requests
Endpoint
Interrupt
Enables
Endpoint
Interrupt
Requests
GPIFInterrupt
Enable
GPIFInterrupt
Request
USB Error
Interrupt
Enables
USB Error
Interrupt
Requests
USB Error
counter and
limit
Clear Error
Counter
EC3:0
0
EP0ACK
0
URES
SUSP
SUTOK
SOF
SUDAV
00000000 RW
[15]
0
EP0ACK
EP6
0
URES
EP2
SUSP
SUTOK
EP1IN
SOF
SUDAV
EP0IN
0xxxxxxx rbbbbbbb
00000000 RW
EP8
EP4
EP1OUT
EP0OUT
[15]
E65F
1
EPIRQ
EP8
EP6
EP4
EP2
EP1OUT
EP1IN
EP0OUT
EP0IN
0
RW
[16]
E660
E661
E662
1
1
1
GPIFIE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
GPIFWF
GPIFWF
0
GPIFDONE 00000000 RW
GPIFDONE 000000xx RW
[16]
GPIFIRQ
USBERRIE
ISOEP8
ISOEP6
ISOEP4
ISOEP2
ERRLIMIT 00000000 RW
ERRLIMIT 0000000x bbbbrrrb
[15]
E663
E664
E665
E666
E667
1
1
1
1
1
USBERRIRQ
ERRCNTLIM
ISOEP8
ISOEP6
ISOEP4
EC1
x
ISOEP2
EC0
x
0
LIMIT3
x
0
LIMIT2
x
0
EC3
EC2
x
LIMIT1
LIMIT0
xxxx0100 rrrrbbbb
CLRERRCNT
INT2IVEC
x
0
1
x
0
0
x
0
0
xxxxxxxx
00000000
10000000
W
R
Interrupt 2
(USB)
Autovector
I2V4
0
I2V3
I4V3
I2V2
I4V2
I2V1
I4V1
I2V0
I4V0
INT4IVEC
Interrupt 4
(slave FIFO &
GPIF)
R
Autovector
E668
E669
1
7
INTSETUP
Interrupt 2 & 4
setup
0
0
0
0
0
0
AV2EN
0
0
0
INT4SRC
INT1
AV4EN
INT0
00000000 RW
00000000 RW
reserved
INPUT / OUTPUT
PORTACFG
E670
1
I/O PORTA
Alternate
Configuration
FLAGD
SLCS
Notes
15. SFRs not part of the standard 8051 architecture.
16. Read and writes to these register may require synchronization delay, see the section “Synchronization Delay” in the EZ-USB TRM.
Document Number: 38-08039 Rev. *K
Page 34 of 74
CY7C64713
Table 9. FX1 Register Summary (continued)
Hex Size
Name
PORTCCFG
Description
b7
GPIFA7
b6
GPIFA6
b5
GPIFA5
b4
GPIFA4
b3
GPIFA3
b2
GPIFA2
b1
GPIFA1
b0
Default Access
E671
E672
E673
1
1
4
I/O PORTC
Alternate
Configuration
I/O PORTE
Alternate
Configuration
GPIFA0 00000000 RW
PORTECFG
XTALINSRC
GPIFA8
0
T2EX
0
INT6
0
RXD1OUT RXD0OUT
T2OUT
0
T1OUT
0
T0OUT
00000000 RW
XTALINClock
Source
0
0
EXTCLK 00000000 rrrrrrrb
E677
E678
1
1
reserved
I2CS
I²C Bus
Control &
Status
I²C Bus Data
I²C Bus
Control
START
STOP
LASTRD
ID1
ID0
BERR
ACK
DONE
d0
000xx000 bbbrrrrr
E679
E67A
1
1
I2DAT
I2CTL
d7
0
d6
0
d5
0
d4
0
d3
0
d2
0
d1
STOPIE
xxxxxxxx
RW
400KHZ 00000000 RW
E67B
1
XAUTODAT1
XAUTODAT2
UDMA CRC
Autoptr1
D7
D6
D5
D4
D3
D2
D1
D1
D0
D0
xxxxxxxx
xxxxxxxx
RW
RW
MOVX
access, when
APTREN = 1
Autoptr2
MOVX
access, when
APTREN = 1
E67C
1
D7
D6
D5
D4
D3
D2
[17]
E67D
E67E
E67F
1
1
1
UDMACRCH
UDMA CRC
MSB
UDMA CRC
LSB
CRC15
CRC7
CRC14
CRC6
0
CRC13
CRC5
0
CRC12
CRC4
0
CRC11
CRC3
CRC10
CRC2
CRC9
CRC1
CRC8
CRC0
01001010 RW
10111010 RW
[17]
UDMACRCL
UDMACRC-QUALIFIER UDMA CRC QENABLE
Qualifier
QSTATE
QSIGNAL2 QSIGNAL1 QSIGNAL0 00000000 brrrbbbb
USB CONTROL
E680
E681
E682
1
1
1
USBCS
USB Control
& Status
Put chip into
suspend
Wakeup
Control &
Status
Toggle
Control
0
x
0
x
0
x
0
x
DISCON NOSYNSOF
RENUM
x
SIGRSUME x0000000 rrrrbbbb
SUSPEND
WAKEUPCS
x
x
x
xxxxxxxx
W
WU2
WU
WU2POL
WUPOL
0
DPEN
WU2EN
WUEN
xx000101 bbbbrbbb
x0000000 rrrbbbbb
E683
E684
1
1
TOGCTL
Q
0
S
0
R
0
I/O
0
EP3
0
EP2
EP1
FC9
EP0
FC8
USBFRAMEH
USB Frame
count H
FC10
00000xxx
R
Note
17. Read and writes to these register may require synchronization delay, see the section “Synchronization Delay” in the EZ-USB TRM.
Document Number: 38-08039 Rev. *K
Page 35 of 74
CY7C64713
Table 9. FX1 Register Summary (continued)
Hex Size
Name
USBFRAMEL
Description
USB Frame
count L
b7
FC7
b6
FC6
b5
FC5
b4
FC4
b3
FC3
b2
FC2
b1
FC1
b0
FC0
Default Access
E685
1
xxxxxxxx
R
E686
E687
1
1
reserved
FNADDR
USB Function
address
0
FA6
FA5
FA4
FA3
FA2
FA1
FA0
0xxxxxxx
R
E688
2
reserved
ENDPOINTS
[18]
E68A
E68B
1
1
EP0BCH
Endpoint 0
(BC15)
(BC7)
(BC14)
BC6
(BC13)
BC5
(BC12)
BC4
(BC11)
BC3
(BC10)
BC2
(BC9)
BC1
(BC8)
BC0
xxxxxxxx
xxxxxxxx
RW
RW
Byte Count H
[18]
EP0BCL
Endpoint 0
Byte Count L
E68C
E68D
1
1
reserved
EP1OUTBC
Endpoint 1
OUT Byte
Count
0
BC6
BC5
BC4
BC3
BC2
BC1
BC0
xxxxxxxx
RW
E68E
E68F
1
1
reserved
EP1INBC
Endpoint 1 IN
Byte Count
Endpoint 2
Byte Count H
Endpoint 2
Byte Count L
0
0
BC6
0
BC5
0
BC4
0
BC3
0
BC2
BC10
BC2
BC1
BC9
BC1
BC0
BC8
BC0
xxxxxxxx
xxxxxxxx
xxxxxxxx
RW
RW
RW
[18]
E690
E691
1
1
EP2BCH
[18]
EP2BCL
BC7/SKIP
BC6
BC5
BC4
BC3
E692
E694
2
1
reserved
EP4BCH
[18]
Endpoint 4
0
0
0
0
0
0
BC9
BC1
BC8
BC0
xxxxxxxx
xxxxxxxx
RW
RW
Byte Count H
[18]
E695
1
EP4BCL
Endpoint 4
Byte Count L
BC7/SKIP
BC6
BC5
BC4
BC3
BC2
E696
E698
2
1
reserved
EP6BCH
[18]
Endpoint 6
0
0
0
0
0
BC10
BC2
BC9
BC1
BC8
BC0
xxxxxxxx
xxxxxxxx
RW
RW
Byte Count H
[18]
E699
1
EP6BCL
Endpoint 6
Byte Count L
BC7/SKIP
BC6
BC5
BC4
BC3
E69A
E69C
2
1
reserved
EP8BCH
[18]
Endpoint 8
0
0
0
0
0
0
BC9
BC1
BC8
BC0
xxxxxxxx
xxxxxxxx
RW
RW
Byte Count H
[18]
E69D
E69E
1
2
EP8BCL
Endpoint 8
Byte Count L
BC7/SKIP
BC6
BC5
BC4
BC3
BC2
reserved
Note
18. Read and writes to these register may require synchronization delay, see the section “Synchronization Delay” in the EZ-USB TRM.
Document Number: 38-08039 Rev. *K
Page 36 of 74
CY7C64713
Table 9. FX1 Register Summary (continued)
Hex Size
Name
Description
b7
b6
b5
b4
b3
b2
b1
b0
Default Access
E6A0
E6A1
E6A2
E6A3
E6A4
E6A5
E6A6
E6A7
E6A8
E6A9
E6AA
E6AB
1
1
1
1
1
1
1
1
1
1
1
1
EP0CS
Endpoint 0
Control and
Status
Endpoint 1
OUT Control
and Status
Endpoint 1 IN
Control and
Status
Endpoint 2
Control and
Status
Endpoint 4
Control and
Status
Endpoint 6
Control and
Status
Endpoint 8
Control and
Status
Endpoint 2
slave FIFO
Flags
Endpoint 4
slave FIFO
Flags
Endpoint 6
slave FIFO
Flags
Endpoint 8
slave FIFO
Flags
Endpoint 2
slave FIFO
total byte
count H
HSNAK
0
0
0
0
0
BUSY
STALL
10000000 bbbbbbrb
EP1OUTCS
EP1INCS
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BUSY
BUSY
0
STALL
STALL
STALL
STALL
STALL
STALL
FF
00000000 bbbbbbrb
00000000 bbbbbbrb
00101000 rrrrrrrb
00101000 rrrrrrrb
00000100 rrrrrrrb
00000100 rrrrrrrb
0
0
0
NPAK0
NPAK0
NPAK0
NPAK0
0
EP2CS
NPAK2
NPAK1
FULL
FULL
FULL
FULL
0
EMPTY
EMPTY
EMPTY
EMPTY
PF
EP4CS
0
NPAK1
0
EP6CS
NPAK2
NPAK1
0
EP8CS
0
0
0
0
0
0
NPAK1
0
EP2FIFOFLGS
EP4FIFOFLGS
EP6FIFOFLGS
EP8FIFOFLGS
EP2FIFOBCH
0
0
0
0
0
EF
EF
EF
EF
BC9
00000010
00000010
00000110
00000110
00000000
R
R
R
R
R
0
0
PF
FF
0
0
PF
FF
0
0
PF
FF
BC12
BC11
BC10
BC8
E6AC
E6AD
1
1
EP2FIFOBCL
EP4FIFOBCH
Endpoint 2
slave FIFO
total byte
count L
Endpoint 4
slave FIFO
total byte
count H
BC7
0
BC6
0
BC5
0
BC4
0
BC3
0
BC2
BC1
BC9
BC0
BC8
00000000
00000000
R
R
BC10
Document Number: 38-08039 Rev. *K
Page 37 of 74
CY7C64713
Table 9. FX1 Register Summary (continued)
Hex Size
Name
EP4FIFOBCL
Description
b7
BC7
b6
BC6
b5
BC5
b4
BC4
b3
BC3
b2
BC2
b1
BC1
b0
BC0
Default Access
E6AE
E6AF
E6B0
E6B1
E6B2
1
1
1
1
1
Endpoint 4
slave FIFO
total byte
count L
Endpoint 6
slave FIFO
total byte
count H
Endpoint 6
slave FIFO
total byte
count L
Endpoint 8
slave FIFO
total byte
count H
Endpoint 8
slave FIFO
total byte
count L
Setup Data
Pointer high
address byte
Setup Data
Pointer low
address byte
Setup Data
Pointer Auto
Mode
00000000
00000000
00000000
00000000
00000000
xxxxxxxx
R
EP6FIFOBCH
EP6FIFOBCL
EP8FIFOBCH
EP8FIFOBCL
0
0
0
0
BC11
BC3
0
BC10
BC2
BC9
BC1
BC9
BC1
BC8
BC0
BC8
BC0
R
BC7
0
BC6
0
BC5
0
BC4
0
R
BC10
BC2
R
BC7
BC6
BC5
BC4
BC3
R
E6B3
E6B4
E6B5
1
1
1
SUDPTRH
SUDPTRL
A15
A7
0
A14
A6
0
A13
A5
0
A12
A4
0
A11
A3
0
A10
A2
0
A9
A1
0
A8
0
RW
xxxxxxx0 bbbbbbbr
SUDPTRCTL
SDPAUTO 00000001 RW
2
8
reserved
SETUPDAT
E6B8
8 bytes of
setup data
D7
D6
D5
D4
D3
D2
D1
D0
xxxxxxxx
R
SETUPDAT[0]
=
bmRequestTy
pe
SETUPDAT[1]
= bmRequest
SETUPDAT[2:
3] = wValue
SETUPDAT[4:
5] = wIndex
SETUPDAT[6:
7] = wLength
GPIF
SINGLEWR1 SINGLEWR0
E6C0
1
GPIFWFSELECT
Waveform
Selector
SINGLERD1 SINGLERD0 FIFOWR1
FIFOWR0
FIFORD1
FIFORD0 11100100
RW
Document Number: 38-08039 Rev. *K
Page 38 of 74
CY7C64713
Table 9. FX1 Register Summary (continued)
Hex Size
Name
GPIFIDLECS
Description
b7
DONE
b6
0
b5
0
b4
0
b3
0
b2
0
b1
0
b0
Default Access
E6C1
1
GPIF Done,
GPIF IDLE
drive mode
IDLEDRV 10000000 RW
E6C2
E6C3
E6C4
E6C5
1
1
1
1
GPIFIDLECTL
GPIFCTLCFG
Inactive Bus,
CTL states
CTL Drive
Type
GPIFAddress
H
GPIFAddress GPIFA7
L
0
TRICTL
0
0
CTL5
CTL5
0
CTL4
CTL4
0
CTL3
CTL3
0
CTL2
CTL2
0
CTL1
CTL1
0
CTL0
CTL0
11111111
RW
0
0
00000000 RW
[19]
GPIFADRH
GPIFA8 00000000 RW
GPIFA0 00000000 RW
[19]
GPIFADRL
GPIFA6
GPIFA5
GPIFA4
GPIFA3
GPIFA2
GPIFA1
FLOWSTATE
FLOWSTATE
E6C6
1
Flowstate
Enable and
Selector
FSE
0
0
0
0
FS2
FS1
FS0
00000000 brrrrbbb
E6C7
E6C8
1
1
FLOWLOGIC
Flowstate
Logic
LFUNC1
CTL0E3
LFUNC0
CTL0E2
TERMA2
TERMA1
TERMA0
CTL3
TERMB2
CTL2
TERMB1
CTL1
TERMB0 00000000 RW
CTL0E1/CTL5 CTL0E0/CTL4
CTL0E1/CTL5 CTL0E0/CTL4
FLOWEQ0CTL
CTL-Pin
States in
Flowstate
(when
CTL0
00000000 RW
Logic = 0)
CTL-Pin
States in
Flowstate
(when
E6C9
1
FLOWEQ1CTL
CTL0E3
CTL0E2
CTL3
CTL2
CTL1
CTL0
00000000 RW
Logic = 1)
HOPERIOD3 HOPERIOD2 HOPERIOD1 HOPERIOD0
E6CA
E6CB
1
1
FLOWHOLDOFF
FLOWSTB
Holdoff
HOSTATE
0
HOCTL2
MSTB2
HOCTL1
MSTB1
HOCTL0 00000000 RW
MSTB0 00100000 RW
Configuration
Flowstate
Strobe
Configuration
SLAVE
0
RDYASYNC CTLTOGL SUSTAIN
E6CC
1
FLOWSTBEDGE
Flowstate
Rising/Falling
Edge
0
0
0
0
0
FALLING
RISING 00000001 rrrrrrbb
Configuration
Master-Strobe
Half-Period
E6CD
E6CE
1
1
FLOWSTBPERIOD
D7
D6
D5
D4
D3
D2
D1
D0
00000010 RW
00000000 RW
[19]
GPIFTCB3
GPIF
Transaction
Count Byte 3
GPIF
Transaction
Count Byte 2
TC31
TC30
TC29
TC28
TC27
TC26
TC25
TC24
[19]
E6CF
1
GPIFTCB2
TC23
TC22
TC21
TC20
TC19
TC18
TC17
TC16
00000000 RW
Note
19. Read and writes to these register may require synchronization delay, see the section “Synchronization Delay” in the EZ-USB TRM.
Document Number: 38-08039 Rev. *K
Page 39 of 74
CY7C64713
Table 9. FX1 Register Summary (continued)
Hex Size
Name
GPIFTCB1
Description
b7
TC15
b6
TC14
b5
TC13
b4
TC12
b3
TC11
b2
TC10
b1
TC9
b0
TC8
Default Access
00000000 RW
[20]
E6D0
1
1
2
GPIF
Transaction
Count Byte 1
GPIF
Transaction
Count Byte 0
[20]
E6D1
GPIFTCB0
TC7
TC6
TC5
TC4
TC3
TC2
TC1
TC0
00000001 RW
00000000 RW
reserved
reserved
reserved
[20]
E6D2
E6D3
1
1
EP2GPIFFLGSEL
Endpoint 2
GPIF Flag
select
Endpoint 2
GPIF stop
transactionon
prog. flag
0
0
0
0
0
0
0
0
0
0
0
0
FS1
0
FS0
00000000 RW
EP2GPIFPFSTOP
FIFO2FLAG 00000000 RW
[20]
E6D4
1
3
EP2GPIFTRIG
Endpoint 2
GPIF Trigger
x
x
x
x
x
x
x
x
xxxxxxxx
W
reserved
reserved
reserved
[20]
E6DA
E6DB
1
1
EP4GPIFFLGSEL
Endpoint 4
GPIF Flag
select
Endpoint 4
GPIF stop
transactionon
GPIF Flag
Endpoint 4
GPIF Trigger
0
0
0
0
0
0
0
0
0
0
0
0
FS1
0
FS0
00000000 RW
EP4GPIFPFSTOP
FIFO4FLAG 00000000 RW
[20]
E6DC
1
3
EP4GPIFTRIG
x
x
x
x
x
x
x
x
xxxxxxxx
W
reserved
reserved
reserved
[20]
E6E2
E6E3
1
1
EP6GPIFFLGSEL
Endpoint 6
GPIF Flag
select
Endpoint 6
GPIF stop
transactionon
prog. flag
0
0
0
0
0
0
0
0
0
0
0
0
FS1
0
FS0
00000000 RW
EP6GPIFPFSTOP
FIFO6FLAG 00000000 RW
[20]
E6E4
1
EP6GPIFTRIG
Endpoint 6
GPIF Trigger
x
x
x
x
x
x
x
x
xxxxxxxx
W
Note
20. Read and writes to these register may require synchronization delay, see the section “Synchronization Delay” in the EZ-USB TRM.
Document Number: 38-08039 Rev. *K
Page 40 of 74
CY7C64713
Table 9. FX1 Register Summary (continued)
Hex Size
Name
Description
b7
b6
b5
b4
b3
b2
b1
b0
Default Access
3
reserved
reserved
reserved
EP8GPIFFLGSEL
[21]
E6EA
E6EB
1
1
Endpoint 8
GPIF Flag
select
Endpoint 8
GPIF stop
transactionon
prog. flag
0
0
0
0
0
0
0
0
0
0
0
0
FS1
0
FS0
00000000 RW
EP8GPIFPFSTOP
FIFO8FLAG 00000000 RW
[21]
E6EC
1
EP8GPIFTRIG
Endpoint 8
GPIF Trigger
x
x
x
x
x
x
x
x
xxxxxxxx
W
3
1
reserved
XGPIFSGLDATH
E6F0
E6F1
GPIF Data H
(16-bit mode
only)
D15
D7
D14
D6
D13
D5
D12
D4
D11
D3
D10
D2
D9
D1
D8
D0
xxxxxxxx
xxxxxxxx
RW
RW
1
1
1
XGPIFSGLDATLX
XGPIFSGLDATLNOX
GPIFREADYCFG
Read/Write
GPIFDataL&
trigger
transaction
E6F2
E6F3
Read GPIF
Data L, no
transaction
trigger
D7
D6
D5
D4
0
D3
0
D2
0
D1
0
D0
0
xxxxxxxx
R
Internal RDY,
Sync/Async,
RDY pin
INTRDY
SAS
TCXRDY5
00000000 bbbrrrrr
states
E6F4
E6F5
E6F6
1
1
2
GPIFREADYSTAT
GPIFABORT
GPIF Ready
Status
Abort GPIF
Waveforms
0
x
0
x
RDY5
x
RDY4
x
RDY3
x
RDY2
x
RDY1
x
RDY0
x
00xxxxxx
xxxxxxxx
R
W
reserved
ENDPOINT BUFFERS
E740 64 EP0BUF
EP0-IN/-OUT
buffer
EP1-OUT
buffer
D7
D7
D7
D6
D6
D6
D5
D5
D5
D4
D4
D4
D3
D3
D3
D2
D2
D2
D1
D1
D1
D0
D0
D0
xxxxxxxx
xxxxxxxx
xxxxxxxx
RW
RW
E780 64 EP10UTBUF
E7C0 64 EP1INBUF
2048 reserved
EP1-IN buffer
RW
RW
Note
21. Read and writes to these register may require synchronization delay, see the section “Synchronization Delay” in the EZ-USB TRM.
Document Number: 38-08039 Rev. *K
Page 41 of 74
CY7C64713
Table 9. FX1 Register Summary (continued)
Hex Size
Name
Description
b7
b6
b5
b4
b3
b2
b1
b0
Default Access
F000 1023 EP2FIFOBUF
64/1023-byte
EP 2 / slave
FIFO buffer
(IN or OUT)
D7
D6
D5
D4
D3
D2
D1
D0
xxxxxxxx
RW
F400 64 EP4FIFOBUF
64 byte EP 4 /
slave FIFO
buffer (IN or
OUT)
D7
D6
D5
D4
D3
D2
D1
D0
xxxxxxxx
RW
F600 64 reserved
F800 1023 EP6FIFOBUF
64/1023-byte
EP 6 / slave
FIFO buffer
(IN or OUT)
64 byte EP 8 /
slave FIFO
buffer (IN or
OUT)
D7
D7
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
xxxxxxxx
xxxxxxxx
RW
RW
FC00 64 EP8FIFOBUF
FE00 64 reserved
[23]
xxxxxxxx
xxxx
I²C Configuration Byte
Special Function Registers (SFRs)
IOA
0
DISCON
D6
0
0
0
0
0
400KHZ
D0
n/a
[22]
80
1
Port A (bit
addressable)
Stack Pointer
DataPointer0
L
DataPointer0
H
DataPointer1
L
DataPointer1
H
Data Pointer
0/1 select
D7
D5
D4
D3
D2
D1
xxxxxxxx
00000111
RW
RW
81
82
1
1
SP
D7
A7
D6
A6
D5
A5
D4
A4
D3
A3
D2
A2
D1
A1
D0
A0
DPL0
DPH0
00000000 RW
00000000 RW
00000000 RW
00000000 RW
00000000 RW
83
84
85
86
1
1
1
1
A15
A7
A15
0
A14
A6
A14
0
A13
A5
A13
0
A12
A4
A12
0
A11
A3
A11
0
A10
A2
A10
0
A9
A1
A9
0
A8
A0
[22]
DPL1
DPH1
[22]
A8
[22]
DPS
SEL
87
88
1
1
PCON
TCON
Power Control SMOD0
x
TR1
1
TF0
1
TR0
x
IE1
x
IT1
x
IE0
IDLE
IT0
00110000
00000000 RW
RW
Timer/Counter
Control (bit
TF1
addressable)
Timer/Counter
Mode Control
89
1
1
TMOD
TL0
GATE
D7
CT
D6
M1
D5
M0
D4
GATE
D3
CT
D2
M1
D1
M0
D0
00000000 RW
00000000 RW
8A
Timer0reload
L
Notes
22. SFRs not part of the standard 8051 architecture.
23. If no EEPROM is detected by the SIE then the default is 00000000.
Document Number: 38-08039 Rev. *K
Page 42 of 74
CY7C64713
Table 9. FX1 Register Summary (continued)
Hex Size
Name
Description
b7
b6
b5
b4
b3
b2
b1
b0
Default Access
8B
8C
8D
1
1
1
TL1
Timer1reload
L
Timer0reload
H
Timer1reload
H
Clock Control
D7
D6
D5
D4
D3
D2
D1
D0
00000000 RW
TH0
D15
D15
x
D14
D14
x
D13
D13
T2M
D12
D12
T1M
D11
D11
T0M
D10
D10
MD2
D9
D9
D8
D8
00000000 RW
00000000 RW
00000001 RW
TH1
[24]
8E
8F
90
1
1
1
CKCON
reserved
IOB
MD1
MD0
[24]
Port B (bit
addressable)
D7
D6
D5
D4
D3
1
D2
0
D1
0
D0
0
xxxxxxxx
RW
[24]
91
92
1
1
EXIF
External
Interrupt
Flag(s)
Upper Addr
ByteofMOVX
using @R0 /
@R1
IE5
IE4
I²CINT
USBNT
00001000 RW
00000000 RW
[24]
MPAGE
A15
A14
A13
A12
A11
A10
A9
A8
93
98
5
1
reserved
SCON0
Serial Port 0
Control (bit
addressable)
SM0_0
SM1_0
SM2_0
REN_0
TB8_0
RB8_0
TI_0
RI_0
00000000 RW
99
9A
9B
1
1
1
SBUF0
Serial Port 0
Data Buffer
Autopointer 1
Address H
Autopointer 1
Address L
D7
A15
A7
D6
A14
A6
D5
A13
A5
D4
A12
A4
D3
A11
A3
D2
A10
A2
D1
A9
A1
D0
A8
A0
00000000 RW
00000000 RW
00000000 RW
[24]
AUTOPTRH1
[24]
AUTOPTRL1
reserved
9C
9D
1
1
[24]
AUTOPTRH2
Autopointer 2
Address H
Autopointer 2
Address L
A15
A7
A14
A6
A13
A5
A12
A4
A11
A3
A10
A2
A9
A1
A8
A0
00000000 RW
00000000 RW
[24]
9E
1
AUTOPTRL2
9F
A0
1
1
reserved
IOC
[24]
Port C (bit
D7
x
D6
x
D5
x
D4
x
D3
x
D2
x
D1
x
D0
x
xxxxxxxx
xxxxxxxx
xxxxxxxx
RW
W
addressable)
[24]
A1
A2
A3
1
1
5
INT2CLR
Interrupt 2
clear
Interrupt 4
clear
[24]
INT4CLR
x
x
x
x
x
x
x
x
W
reserved
Note
24. SFRs not part of the standard 8051 architecture.
Document Number: 38-08039 Rev. *K
Page 43 of 74
CY7C64713
Table 9. FX1 Register Summary (continued)
Hex Size
Name
Description
b7
b6
b5
b4
b3
b2
b1
b0
Default Access
A8
1
IE
Interrupt
Enable (bit
addressable)
EA
ES1
ET2
ES0
ET1
EX1
ET0
EX0
00000000 RW
A9
AA
1
1
reserved
[25]
EP2468STAT
EP24FIFOFLGS
EP68FIFOFLGS
reserved
Endpoint 2, 4,
6, 8 status
flags
Endpoint 2, 4
slave FIFO
status flags
Endpoint 6, 8
slave FIFO
status flags
EP8F
EP8E
EP4PF
EP8PF
EP6F
EP4EF
EP8EF
EP6E
EP4FF
EP8FF
EP4F
EP4E
EP2PF
EP6PF
EP2F
EP2EF
EP6EF
EP2E
EP2FF
EP6FF
01011010
00100010
01100110
R
R
R
[25]
[25]
AB
AC
1
1
0
0
0
0
AD
AF
2
1
[25]
AUTOPTRSETUP
Autopointer
1&2 setup
Port D (bit
addressable)
Port E
(NOT bit
addressable)
Port A Output
Enable
Port B Output
Enable
Port C Output
Enable
Port D Output
Enable
Port E Output
Enable
0
0
0
0
0
APTR2INC APTR1INC
APTREN 00000110
RW
RW
RW
[24]
B0
B1
1
1
IOD
D7
D7
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
xxxxxxxx
xxxxxxxx
[25]
IOE
[25]
B2
B3
B4
B5
B6
1
1
1
1
1
OEA
D7
D7
D7
D7
D7
D6
D6
D6
D6
D6
D5
D5
D5
D5
D5
D4
D4
D4
D4
D4
D3
D3
D3
D3
D3
D2
D2
D2
D2
D2
D1
D1
D1
D1
D1
D0
D0
D0
D0
D0
00000000 RW
00000000 RW
00000000 RW
00000000 RW
00000000 RW
[25]
OEB
[25]
OEC
[25]
OED
[25]
OEE
B7
B8
1
1
reserved
IP
Interrupt
Priority (bit
addressable)
1
PS1
PT2
PS0
PT1
PX1
PT0
PX0
10000000 RW
B9
BA
1
1
reserved
EP01STAT
[25]
Endpoint 0&1
Status
Endpoint 2, 4,
6, 8 GPIF
slave FIFO
Trigger
0
0
0
0
0
0
0
0
0
EP1INBSY EP1OUTBSY EP0BSY 00000000
R
[25, 26]
BB
1
GPIFTRIG
DONE
RW EP1 EP0 10000xxx brrrrbbb
Notes
25. SFRs not part of the standard 8051 architecture.
26. Read and writes to these register may require synchronization delay, see the section “Synchronization Delay” in the EZ-USB TRM.
Document Number: 38-08039 Rev. *K
Page 44 of 74
CY7C64713
Table 9. FX1 Register Summary (continued)
Hex Size
Name
Description
b7
b6
b5
b4
b3
b2
b1
b0
Default Access
BC
BD
1
1
reserved
GPIFSGLDATH
[27]
GPIF Data H
(16-bit mode
only)
GPIF Data L
w/ Trigger
GPIF Data L
w/ No Trigger
Serial Port 1
Control (bit
addressable)
D15
D14
D13
D12
D11
D10
D9
D8
xxxxxxxx
RW
[27]
BE
BF
C0
1
1
1
GPIFSGLDATLX
D7
D7
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
xxxxxxxx
xxxxxxxx
RW
R
[27]
GPIFSGLDATLNOX
[27]
SCON1
SM0_1
SM1_1
SM2_1
REN_1
TB8_1
RB8_1
TI_1
RI_1
00000000 RW
00000000 RW
[27]
C1
1
SBUF1
Serial Port 1
Data Buffer
D7
D6
D5
D4
D3
D2
D1
D0
C2
C8
6
1
reserved
T2CON
Timer/Counter
2 Control (bit
addressable)
TF2
EXF2
RCLK
TCLK
EXEN2
TR2
CT2
CPRL2
00000000 RW
C9
CA
1
1
reserved
RCAP2L
Capture for
Timer 2,
D7
D7
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
00000000 RW
00000000 RW
auto-reload,
up-counter
CB
1
RCAP2H
Capture for
Timer 2,
auto-reload,
up-counter
CC
CD
1
1
TL2
TH2
Timer2reload
L
Timer2reload
H
D7
D6
D5
D4
D3
D2
D1
D9
D0
D8
00000000 RW
00000000 RW
D15
D14
D13
D12
D11
D10
CE
D0
2
1
reserved
PSW
Program
Status Word
(bit
CY
AC
F0
RS1
RS0
OV
F1
P
00000000 RW
addressable)
D1
D8
7
1
reserved
EICON
[27]
External
Interrupt
Control
SMOD1
D7
1
ERESI
D5
RESI
D4
INT6
D3
0
0
0
01000000 RW
00000000 RW
D9
E0
7
1
reserved
ACC
Accumulator
(bit
addressable)
D6
D2
D1
D0
Note
27. SFRs not part of the standard 8051 architecture.
Document Number: 38-08039 Rev. *K
Page 45 of 74
CY7C64713
Table 9. FX1 Register Summary (continued)
Hex Size
Name
Description
b7
b6
b5
b4
b3
b2
b1
b0
Default Access
E1
E8
7
1
reserved
EIE
[28]
External
Interrupt
Enable(s)
1
1
1
EX6
EX5
EX4
EI²C
EUSB
11100000
RW
E9
F0
7
1
reserved
B
B (bit
D7
1
D6
1
D5
1
D4
D3
D2
D1
D0
00000000 RW
addressable)
F1
F8
7
1
reserved
[28]
EIP
External
Interrupt
Priority
PX6
PX5
PX4
PI²C
PUSB
11100000
RW
Control
F9
7
reserved
Legend (For the Access column)
R = all bits read-only
W = all bits write-only
r = read-only bit
w = write-only bit
b = both read/write bit
Note
28. SFRs not part of the standard 8051 architecture.
Document Number: 38-08039 Rev. *K
Page 46 of 74
CY7C64713
Absolute Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Max Output Current, per I/O port................................ 10 mA
Max Output Current, all five I/O ports
Storage Temperature................................ –65 °C to +150 °C
Ambient Temperature with Power Supplied.... 0 °C to +70 °C
Supply Voltage to Ground Potential..............–0.5 V to +4.0 V
DC Input Voltage to Any Input Pin......................... 5.25 V[29]
(128 and 100 pin packages)....................................... 50 mA
Operating Conditions
TA (Ambient Temperature Under Bias)........... 0 °C to +70 °C
Supply Voltage..........................................+3.15 V to +3.45 V
Ground Voltage................................................................. 0 V
DC Voltage Applied to Outputs
in High Z State................................... –0.5 V to VCC + 0.5 V
Power Dissipation.................................................... 235 mW
Static Discharge Voltage......................................... > 2000 V
F
OSC (Oscillator or Crystal Frequency).... 24 MHz ± 100 ppm
Parallel Resonant
DC Characteristics
Parameter
VCC
VCC Ramp Up 0 to 3.3 V
Description
Conditions
Min
3.15
200
2
Typ
3.3
–
Max
3.45
–
Unit
V
Supply Voltage
s
V
VIH
VIL
Input HIGH Voltage
Input LOW Voltage
–
5.25
0.8
5.25
0.8
±10
–
–0.5
2
–
V
VIH_X
VIL_X
II
Crystal input HIGH Voltage
Crystal input LOW Voltage
Input Leakage Current
Output Voltage HIGH
Output LOW Voltage
Output Current HIGH
Output Current LOW
Input Pin Capacitance
–
V
–0.05
–
–
V
0 < VIN < VCC
–
A
V
VOH
VOL
IOH
IOL
IOUT = 4 mA
2.4
–
–
IOUT = –4 mA
–
0.4
4
V
–
–
mA
mA
pF
pF
mA
mA
mA
ms
s
–
–
4
CIN
Except D+/D–
–
3.29
12.96
0.5
0.3
35
–
10
15
1.2
1.0
65
–
D+/D–
–
ISUSP
Suspend Current
Connected
–
Disconnected
–
ICC
Supply Current
8051 running, connected to USB
VCC min = 3.0 V
–
TRESET
Reset Time after Valid Power
Pin Reset after powered on
5.0
200
–
–
USB Transceiver
USB 2.0 compliant in full speed mode.
Note
29. It is recommended to not power I/O when chip power is off.
Document Number: 38-08039 Rev. *K
Page 47 of 74
CY7C64713
AC Electrical Characteristics
USB Transceiver
USB 2.0 compliant in full speed mode.
Figure 12. Program Memory Read Timing Diagram
t
CL
CLKOUT[30]
t
t
AV
AV
A[15..0]
t
t
STBH
STBL
PSEN#
D[7..0]
[31]
ACC1
t
DH
t
data in
t
SOEL
OE#
CS#
t
SCSL
Table 10. Program Memory Read Parameters
Parameter Description
tCL 1/CLKOUT Frequency
Min
–
Typ
Max
–
Unit
Notes
48 MHz
24 MHz
12 MHz
20.83
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
–
41.66
–
–
83.2
–
–
tAV
Delay from Clock to Valid Address
Clock to PSEN Low
Clock to PSEN High
Clock to OE Low
0
10.7
8
tSTBL
tSTBH
tSOEL
tSCSL
tDSU
tDH
0
–
0
–
8
–
–
11.1
13
–
Clock to CS Low
–
–
Data Setup to Clock
Data Hold Time
9.6
0
–
–
–
Notes
30. CLKOUT is shown with positive polarity.
31. t
is computed from the parameters in Table 10 as follows:
ACC1
ACC1
ACC1
t
t
(24 MHz) = 3 × t – t – t
= 106 ns
= 43 ns.
CL
AV
DSU
DSU
(48 MHz) = 3 × t – t – t
CL
AV
Document Number: 38-08039 Rev. *K
Page 48 of 74
CY7C64713
Figure 13. Data Memory Read Timing Diagram
t
CL
Stretch = 0
CLKOUT[32]
t
t
AV
AV
A[15..0]
t
t
STBH
STBL
RD#
t
SCSL
CS#
OE#
t
SOEL
t
DSU
[33]
t
DH
t
ACC1
D[7..0]
data in
Stretch = 1
t
CL
CLKOUT[32]
t
AV
A[15..0]
RD#
CS#
t
DSU
t
[33]
DH
t
ACC1
D[7..0]
data in
Table 11. Data Memory Read Parameters
Parameter Description
tCL 1/CLKOUT Frequency
Min
Typ
Max
–
Unit
Notes
48 MHz
24 MHz
12 MHz
–
–
20.83
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
41.66
–
–
83.2
–
–
tAV
Delay from Clock to Valid Address
Clock to RD LOW
–
10.7
11
11
13
11.1
–
tSTBL
tSTBH
tSCSL
tSOEL
tDSU
tDH
–
–
Clock to RD HIGH
–
–
Clock to CS LOW
–
–
Clock to OE LOW
–
–
Data Setup to Clock
Data Hold Time
9.6
0
–
–
–
When using the AUTPOPTR1 or AUTOPTR2 to address external memory, the address of AUTOPTR1 is active only when either RD#
or WR# are active. The address of AUTOPTR2 is active throughout the cycle and meets the above address valid time for which is
based on the stretch value.
Notes
32. CLKOUT is shown with positive polarity.
33. t
and t
are computed from the parameters in Table 11 as follows:
ACC2
ACC2
ACC2
ACC3
t
t
(24 MHz) = 3 × t – t – t
= 106 ns
= 43 ns
CL
AV
DSU
DSU
(48 MHz) = 3 × t – t – t
CL
AV
t
t
(24 MHz) = 5 × t – t – t
= 190 ns
= 86 ns.
ACC3
ACC3
CL
AV
DSU
DSU
(48 MHz) = 5 × t – t – t
CL
AV
Document Number: 38-08039 Rev. *K
Page 49 of 74
CY7C64713
Figure 14. Data Memory Write Timing Diagram
t
CL
CLKOUT
A[15..0]
t
AV
t
t
t
STBL
STBH
AV
WR#
CS#
t
SCSL
t
ON1
t
OFF1
data out
D[7..0]
Stretch = 1
t
CL
CLKOUT
A[15..0]
t
AV
WR#
CS#
t
ON1
t
OFF1
data out
D[7..0]
Table 12. Data Memory Write Parameters
Parameter Description
tAV
Min
0
Max
10.7
11.2
11.2
13.0
13.1
13.1
Unit
ns
Notes
Delay from Clock to Valid Address
Clock to WR Pulse LOW
Clock to WR Pulse HIGH
Clock to CS Pulse LOW
Clock to Data Turn-on
tSTBL
tSTBH
tSCSL
tON1
0
ns
0
ns
–
ns
0
ns
tOFF1
Clock to Data Hold Time
0
ns
When using the AUTPOPTR1 or AUTOPTR2 to address external memory, the address of AUTOPTR1 is active only when either RD#
or WR# are active. The address of AUTOPTR2 is active throughout the cycle and meets the above address valid time for which is
based on the stretch value.
Document Number: 38-08039 Rev. *K
Page 50 of 74
CY7C64713
In this feature the RD# signal prompts the external logic to
prepare the next data byte. Nothing gets sampled internally on
assertion of the RD# signal itself. It is just a “prefetch” type signal
to get the next data byte prepared. Therefore, using it meets the
set up time to the next read.
PORTC Strobe Feature Timings
The RD# and WR# are present in the 100 pin version and the
128 pin package. In these 100 pin and 128 pin versions, an 8051
control bit is set to pulse the RD# and WR# pins when the 8051
reads from or writes to the PORTC. This feature is enabled by
setting the PORTCSTB bit in CPUCS register.
The purpose of this pulsing of RD# is to let the external peripheral
know that the 8051 is done reading PORTC and that the data
was latched into the PORTC three CLKOUT cycles prior to
asserting the RD# signal. After the RD# is pulsed the external
logic may update the data on PORTC.
The RD# and WR# strobes are asserted for two CLKOUT cycles
when the PORTC is accessed.
The WR# strobe is asserted two clock cycles after the PORTC is
updated and is active for two clock cycles after that as shown in
Figure 16.
The timing diagram of the read and write strobing function on
accessing PORTC follows. Refer to Figure 13 on page 49 and
Figure 14 on page 50 for details on propagation delay of RD#
and WR# signals.
As for read, the value of the PORTC three clock cycles before
the assertion of RD# is the value that the 8051 reads in. The RD#
is pulsed for 2 clock cycles after 3 clock cycles from the point
when the 8051 has performed a read function on PORTC.
Figure 16. WR# Strobe Function when PORTC is Accessed by 8051
t
CLKOUT
CLKOUT
PORTC IS UPDATED
WR#
t
t
STBL
STBH
Figure 17. RD# Strobe Function when PORTC is Accessed by 8051
t
CLKOUT
CLKOUT
8051 READS PORTC
RD#
DATA IS UPDATED BY EXTERNAL LOGIC
DATA MUST BE HELD FOR 3 CLK CYLCES
t
t
STBL
STBH
Document Number: 38-08039 Rev. *K
Page 51 of 74
CY7C64713
GPIF Synchronous Signals
In the following figure, dashed lines indicate signals with programmable polarity.
Figure 18. GPIF Synchronous Signals Timing Diagram
t
IFCLK
IFCLK
t
SGA
GPIFADR[8:0]
RDY
X
t
SRY
t
RYH
DATA(input)
valid
t
SGD
t
DAH
CTLX
t
XCTL
DATA(output)
N
N+1
t
XGD
The following table provides the GPIF Synchronous Signals Parameters with Internally Sourced IFCLK. [34, 35]
Table 13. GPIF Synchronous Signals Parameters with Internally Sourced IFCLK
Parameter
tIFCLK
tSRY
Description
Min
20.83
8.9
0
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
IFCLK Period
–
–
RDYX to Clock Setup Time
Clock to RDYX
tRYH
–
tSGD
GPIF Data to Clock Setup Time
GPIF Data Hold Time
9.2
0
–
tDAH
–
tSGA
Clock to GPIF Address Propagation Delay
Clock to GPIF Data Output Propagation Delay
Clock to CTLX Output Propagation Delay
–
7.5
11
6.7
tXGD
–
tXCTL
–
The following table provides the GPIF Synchronous Signals Parameters with Externally Sourced IFCLK.[35]
Table 14. GPIF Synchronous Signals Parameters with Externally Sourced IFCLK
Parameter
tIFCLK
tSRY
Description
Min
20.83
2.9
3.7
3.2
4.5
–
Max
200
–
Unit
ns
ns
ns
ns
ns
ns
ns
ns
IFCLK Period
RDYX to Clock Setup Time
Clock to RDYX
tRYH
–
tSGD
GPIF Data to Clock Setup Time
GPIF Data Hold Time
–
tDAH
–
tSGA
Clock to GPIF Address Propagation Delay
Clock to GPIF Data Output Propagation Delay
Clock to CTLX Output Propagation Delay
11.5
15
10.7
tXGD
–
tXCTL
–
Notes
34. GPIF asynchronous RDY signals have a minimum Setup time of 50 ns when using internal 48-MHz IFCLK.
x
35. IFCLK must not exceed 48 MHz.
Document Number: 38-08039 Rev. *K
Page 52 of 74
CY7C64713
Slave FIFO Synchronous Read
In the following figure, dashed lines indicate signals with programmable polarity.
Figure 19. Slave FIFO Synchronous Read Timing Diagram
t
IFCLK
IFCLK
SLRD
t
RDH
t
SRD
t
XFLG
FLAGS
DATA
N+1
N
t
t
XFD
OEon
t
OEoff
SLOE
The following table provides the Slave FIFO Synchronous Read Parameters with Internally Sourced IFCLK. [36]
Table 15. Slave FIFO Synchronous Read Parameters with Internally Sourced IFCLK
Parameter
tIFCLK
tSRD
Description
Min
Max
Unit
ns
IFCLK Period
20.83
–
–
SLRD to Clock Setup Time
Clock to SLRD Hold Time
18.7
ns
tRDH
0
–
–
–
–
–
ns
tOEon
SLOE Turn on to FIFO Data Valid
10.5
10.5
9.5
11
ns
tOEoff
SLOE Turn off to FIFO Data Hold
ns
tXFLG
tXFD
Clock to FLAGS Output Propagation Delay
Clock to FIFO Data Output Propagation Delay
ns
ns
The following table provides the Slave FIFO Synchronous Read Parameters with Externally Sourced IFCLK.[36]
Table 16. Slave FIFO Synchronous Read Parameters with Externally Sourced IFCLK
Parameter
tIFCLK
tSRD
Description
Min
20.83
12.7
3.7
–
Max
200
–
Unit
ns
IFCLK Period
SLRD to Clock Setup Time
Clock to SLRD Hold Time
ns
tRDH
–
ns
tOEon
SLOE Turn on to FIFO Data Valid
10.5
10.5
13.5
15
ns
tOEoff
SLOE Turn off to FIFO Data Hold
–
ns
tXFLG
tXFD
Clock to FLAGS Output Propagation Delay
Clock to FIFO Data Output Propagation Delay
–
ns
–
ns
Note
36. IFCLK must not exceed 48 MHz.
Document Number: 38-08039 Rev. *K
Page 53 of 74
CY7C64713
Slave FIFO Asynchronous Read
In the following figure, dashed lines indicate signals with programmable polarity.
Figure 20. Slave FIFO Asynchronous Read Timing Diagram
t
RDpwh
SLRD
t
RDpwl
t
XFLG
t
FLAGS
XFD
DATA
SLOE
N+1
N
t
t
OEoff
OEon
In the following table, the Slave FIFO asynchronous parameter values use internal IFCLK setting at 48 MHz.
Table 17. Slave FIFO Asynchronous Read Parameters
Parameter
tRDpwl
tRDpwh
tXFLG
Description
Min
50
50
–
Max
Unit
ns
SLRD Pulse Width LOW
SLRD Pulse Width HIGH
–
–
ns
SLRD to FLAGS Output Propagation Delay
SLRD to FIFO Data Output Propagation Delay
SLOE Turn-on to FIFO Data Valid
70
ns
tXFD
–
15
ns
tOEon
–
10.5
10.5
ns
tOEoff
SLOE Turn-off to FIFO Data Hold
–
ns
Document Number: 38-08039 Rev. *K
Page 54 of 74
CY7C64713
Slave FIFO Synchronous Write
In the following figure, dashed lines indicate signals with programmable polarity.
Figure 21. Slave FIFO Synchronous Write Timing Diagram
t
IFCLK
IFCLK
SLWR
DATA
t
WRH
t
SWR
N
Z
Z
t
t
FDH
SFD
FLAGS
t
XFLG
The following table provides the Slave FIFO Synchronous Write Parameters with Internally Sourced IFCLK. [37]
Table 18. Slave FIFO Synchronous Write Parameters with Internally Sourced IFCLK
Parameter
tIFCLK
tSWR
Description
Min
20.83
18.1
0
Max
Unit
ns
IFCLK Period
–
–
SLWR to Clock Setup Time
Clock to SLWR Hold Time
FIFO Data to Clock Setup Time
Clock to FIFO Data Hold Time
ns
tWRH
–
ns
tSFD
9.2
0
–
ns
tFDH
–
ns
tXFLG
Clock to FLAGS Output Propagation Time
–
9.5
ns
The following table provides the Slave FIFO Synchronous Write Parameters with Externally Sourced IFCLK. [37]
Table 19. Slave FIFO Synchronous Write Parameters with Externally Sourced IFCLK [37]
Parameter
tIFCLK
tSWR
Description
Min
20.83
12.1
3.6
Max
200
–
Unit
ns
IFCLK Period
SLWR to Clock Setup Time
Clock to SLWR Hold Time
FIFO Data to Clock Setup Time
Clock to FIFO Data Hold Time
ns
tWRH
–
ns
tSFD
3.2
–
ns
tFDH
4.5
–
ns
tXFLG
Clock to FLAGS Output Propagation Time
–
13.5
ns
Note
37. IFCLK must not exceed 48 MHz.
Document Number: 38-08039 Rev. *K
Page 55 of 74
CY7C64713
Slave FIFO Asynchronous Write
In the following figure, dashed lines indicate signals with programmable polarity.
Figure 22. Slave FIFO Asynchronous Write Timing Diagram
t
WRpwh
SLWR/SLCS#
t
WRpwl
t
t
FDH
SFD
DATA
t
XFD
FLAGS
In the following table, the Slave FIFO asynchronous parameter values use internal IFCLK setting at 48 MHz.
Table 20. Slave FIFO Asynchronous Write Parameters with Internally Sourced IFCLK
Parameter
tWRpwl
tWRpwh
tSFD
Description
Min
50
70
10
10
–
Max
Unit
ns
SLWR Pulse LOW
SLWR Pulse HIGH
–
–
ns
SLWR to FIFO DATA Setup Time
FIFO DATA to SLWR Hold Time
–
ns
tFDH
–
ns
tXFD
SLWR to FLAGS Output Propagation Delay
70
ns
Slave FIFO Synchronous Packet End Strobe
In the following figure, dashed lines indicate signals with programmable polarity.
Figure 23. Slave FIFO Synchronous Packet End Strobe Timing Diagram
IFCLK
t
PEH
PKTEND
FLAGS
t
SPE
t
XFLG
The following table provides the Slave FIFO Synchronous Packet End Strobe Parameters with Internally Sourced IFCLK. [38]
Table 21. Slave FIFO Synchronous Packet End Strobe Parameters with Internally Sourced IFCLK
Parameter
tIFCLK
tSPE
Description
Min
20.83
14.6
0
Max
–
Unit
ns
IFCLK Period
PKTEND to Clock Setup Time
Clock to PKTEND Hold Time
–
ns
tPEH
–
ns
tXFLG
Clock to FLAGS Output Propagation Delay
–
9.5
ns
Note
38. IFCLK must not exceed 48 MHz.
Document Number: 38-08039 Rev. *K
Page 56 of 74
CY7C64713
The following table provides the Slave FIFO Synchronous Packet End Strobe Parameters with Externally Sourced IFCLK. [39]
Table 22. Slave FIFO Synchronous Packet End Strobe Parameters with Externally Sourced IFCLK
Parameter
tIFCLK
tSPE
Description
Min
20.83
8.6
Max
200
–
Unit
ns
IFCLK Period
PKTEND to Clock Setup Time
Clock to PKTEND Hold Time
ns
tPEH
2.5
–
ns
tXFLG
Clock to FLAGS Output Propagation Delay
–
13.5
ns
There is no specific timing requirement that needs to be met for
asserting the PKTEND pin concerning asserting SLWR.
PKTEND is asserted with the last data value clocked into the
FIFOs or thereafter. The only consideration is that the set up time
tSPE and the hold time tPEH for PKTEND must be met.
In this particular scenario, the developer must assert the
PKTEND at least one clock cycle after the rising edge that
caused the last byte or word to be clocked into the previous auto
committed packet. Figure 24 shows this scenario. X is the value
the AUTOINLEN register is set to when the IN endpoint is
configured to be in auto mode.
Although there are no specific timing requirements for asserting
PKTEND in relation to SLWR, there exists a specific case
condition that needs attention. When using the PKTEND to
commit a one byte or word packet, an additional timing
requirement must be met when the FIFO is configured to operate
in auto mode and it is necessary to send two packets back to
back:
Figure 24 shows a scenario where two packets are being
committed. The first packet is committed automatically when the
number of bytes in the FIFO reaches X (value set in AUTOINLEN
register) and the second one byte or word short packet being
committed manually using PKTEND. Note that there is at least
one IFCLK cycle timing between asserting PKTEND and
clocking of the last byte of the previous packet (causing the
packet to be committed automatically). Failing to adhere to this
timing results in the FX2 failing to send the one byte or word short
packet.
■ A full packet (defined as the number of bytes in the FIFO
meeting the level set in the AUTOINLEN register) committed
automatically followed by
■ A short one byte or word packet committed manually using the
PKTEND pin.
Figure 24. Slave FIFO Synchronous Write Sequence and Timing Diagram
t
IFCLK
IFCLK
t
t
SFA
FAH
FIFOADR
>= t
WRH
>= t
SWR
SLWR
DATA
t
t
t
FDH
t
t
t
FDH
t
t
t
SFD
t
SFD
FDH
SFD
t
SFD
t
FDH
SFD
SFD
FDH
FDH
X-4
X-2
X-1
1
X-3
X
At least one IFCLK cycle
t
SPE
t
PEH
PKTEND
Note
39. IFCLK must not exceed 48 MHz.
Document Number: 38-08039 Rev. *K
Page 57 of 74
CY7C64713
Slave FIFO Asynchronous Packet End Strobe
In the following figure, dashed lines indicate signals with programmable polarity.
Figure 25. Slave FIFO Asynchronous Packet End Strobe Timing Diagram
t
PEpwh
PKTEND
FLAGS
t
PEpwl
t
XFLG
In the following table, the Slave FIFO asynchronous parameter values use internal IFCLK setting at 48 MHz.
Table 23. Slave FIFO Asynchronous Packet End Strobe Parameters
Parameter
tPEpwl
Description
Min
50
50
–
Max
Unit
ns
PKTEND Pulse Width LOW
PKTEND Pulse Width HIGH
–
–
tPWpwh
tXFLG
ns
PKTEND to FLAGS Output Propagation Delay
115
ns
Slave FIFO Output Enable
In the following figure, dashed lines indicate signals with programmable polarity.
Figure 26. Slave FIFO Output Enable Timing Diagram
SLOE
DATA
t
OEoff
t
OEon
Table 24. Slave FIFO Output Enable Parameters
Parameter
Description
Max
10.5
10.5
Unit
ns
tOEon
tOEoff
SLOE Assert to FIFO DATA Output
SLOE Deassert to FIFO DATA Hold
ns
Slave FIFO Address to Flags/Data
In the following figure, dashed lines indicate signals with programmable polarity.
Figure 27. Slave FIFO Address to Flags/Data Timing Diagram
FIFOADR [1.0]
FLAGS
t
XFLG
t
XFD
N
DATA
N+1
Table 25. Slave FIFO Address to Flags/Data Parameters
Parameter
tXFLG
Description
FIFOADR[1:0] to FLAGS Output Propagation Delay
FIFOADR[1:0] to FIFODATA Output Propagation Delay
Max
10.7
14.3
Unit
ns
tXFD
ns
Document Number: 38-08039 Rev. *K
Page 58 of 74
CY7C64713
Slave FIFO Synchronous Address
Figure 28. Slave FIFO Synchronous Address Timing Diagram
IFCLK
SLCS/FIFOADR [1:0]
t
t
FAH
SFA
The following table provides the Slave FIFO Synchronous Address Parameters.[40]
Table 26. Slave FIFO Synchronous Address Parameters
Parameter
tIFCLK
Description
Min
20.83
25
Max
Unit
ns
Interface Clock Period
200
–
tSFA
FIFOADR[1:0] to Clock Setup Time
Clock to FIFOADR[1:0] Hold Time
ns
tFAH
10
–
ns
Slave FIFO Asynchronous Address
In the following figure, dashed lines indicate signals with programmable polarity.
Figure 29. Slave FIFO Asynchronous Address Timing Diagram
SLCS/FIFOADR [1:0]
RD/WR/PKTEND
t
FAH
t
SFA
In the following table, the Slave FIFO asynchronous parameter values use internal IFCLK setting at 48 MHz.
Table 27. Slave FIFO Asynchronous Address Parameters
Parameter
tSFA
Description
FIFOADR[1:0] to RD/WR/PKTEND Setup Time
RD/WR/PKTEND to FIFOADR[1:0] Hold Time
Min
10
Unit
ns
tFAH
10
ns
Note
40. IFCLK must not exceed 48 MHz.
Document Number: 38-08039 Rev. *K
Page 59 of 74
CY7C64713
Sequence Diagram
Single and Burst Synchronous Read Example
Figure 30. Slave FIFO Synchronous Read Sequence and Timing Diagram
t
IFCLK
IFCLK
t
t
SFA
SFA
t
t
FAH
FAH
FIFOADR
t=0
T=0
t
t
>= t
SRD
>= t
RDH
RDH
SRD
SLRD
SLCS
t=3
t=2
T=3
T=2
t
XFLG
FLAGS
DATA
SLOE
t
t
XFD
t
XFD
t
XFD
XFD
N+4
Data Driven: N
N+2
N+3
N+1
N+1
t
t
t
OEon
t
OEoff
OEoff
OEon
t=4
T=4
T=1
t=1
Figure 31. Slave FIFO Synchronous Sequence of Events Diagram
IFCLK
IFCLK
N
IFCLK
N+1
IFCLK
N+1
IFCLK
N+1
IFCLK
N+2
IFCLK
N+3
IFCLK
N+4
IFCLK
N+4
IFCLK
N+4
N
FIFO POINTER
SLOE
SLRD
SLOE
SLRD
SLOE
SLRD
SLRD
SLOE
FIFO DATA BUS Not Driven
Driven: N
N+1
Not Driven
N+1
N+2
N+3
N+4
N+4
Not Driven
Figure 30 shows the timing relationship of the SLAVE FIFO
signals during a synchronous FIFO read using IFCLK as the
synchronizing clock. This diagram illustrates a single read
followed by a burst read.
■ At t = 2, SLRD is asserted. SLRD must meet the setup time of
SRD (time from asserting the SLRD signal to the rising edge of
the IFCLK) and maintain a minimum hold time of tRDH (time
from the IFCLK edge to the deassertion of the SLRD signal).
If the SLCS signal is used, it must be asserted with SLRD, or
before SLRD is asserted (that is, the SLCS and SLRD signals
must both be asserted to start a valid read condition).
t
■ At t = 0 the FIFO address is stable and the signal SLCS is
asserted (SLCS may be tied low in some applications).
Note tSFA has a minimum of 25 ns. This means when IFCLK is
running at 48 MHz, the FIFO address setup time is more than
one IFCLK cycle.
■ The FIFO pointer is updated on the rising edge of the IFCLK,
while SLRD is asserted. This starts the propagation of data
from the newly addressed location to the data bus. After a
propagation delay of tXFD (measured from the rising edge of
IFCLK) the new data value is present. N is the first data value
read from the FIFO. To have data on the FIFO data bus, SLOE
MUST also be asserted.
■ At t = 1, SLOE is asserted. SLOE is an output enable only,
whose sole function is to drive the data bus. The data that is
driven on the bus is the data that the internal FIFO pointer is
currently pointing to. In this example it is the first data value in
the FIFO.
The same sequence of events are shown for a burst read and
are marked with the time indicators of T = 0 through 5.
Note The data is pre-fetched and is driven on the bus when
SLOE is asserted.
Document Number: 38-08039 Rev. *K
Page 60 of 74
CY7C64713
Note For the burst mode, the SLRD and SLOE are left asserted during the entire duration of the read. In the burst read mode, when
SLOE is asserted, data indexed by the FIFO pointer is on the data bus. During the first read cycle, on the rising edge of the clock the
FIFO pointer is updated and increments to point to address N + 1. For each subsequent rising edge of IFCLK, while the SLRD is
asserted, the FIFO pointer is incremented and the next data value is placed on the data bus.
Single and Burst Synchronous Write
In the following figure, dashed lines indicate signals with programmable polarity.
Figure 32. Slave FIFO Synchronous Write Sequence and Timing Diagram
t
IFCLK
IFCLK
t
t
SFA
t
SFA
t
FAH
FAH
FIFOADR
>= t
t=0
WRH
t
t
>= t
T=0
SWR
WRH
SWR
SLWR
SLCS
T=2
T=5
t=2
t=3
t
XFLG
t
XFLG
FLAGS
DATA
t
t
t
t
t
FDH
t
t
t
SFD
SFD
FDH
FDH
SFD
SFD
FDH
N+1
N+3
N
N+2
T=4
T=3
t=1
T=1
t
SPE
t
PEH
PKTEND
Figure 32 shows the timing relationship of the SLAVE FIFO
signals during a synchronous write using IFCLK as the
synchronizing clock. This diagram illustrates a single write
followed by burst write of 3 bytes and committing all 4 bytes as
a short packet using the PKTEND pin.
The FIFO flag is also updated after a delay of tXFLG from the
rising edge of the clock.
The same sequence of events are also shown for a burst write
and are marked with the time indicators of T = 0 through 5.
Note For the burst mode, SLWR and SLCS are left asserted for
the entire duration of writing all the required data values. In this
burst write mode, after the SLWR is asserted, the data on the
FIFO data bus is written to the FIFO on every rising edge of
IFCLK. The FIFO pointer is updated on each rising edge of
IFCLK. In Figure 32, after the four bytes are written to the FIFO,
SLWR is deasserted. The short 4-byte packet is committed to the
host by asserting the PKTEND signal.
■ At t = 0 the FIFO address is stable and the signal SLCS is
asserted (SLCS may be tied low in some applications).
Note tSFA has a minimum of 25 ns. This means when IFCLK is
running at 48 MHz, the FIFO address setup time is more than
one IFCLK cycle.
■ At t = 1, the external master or peripheral must output the data
value onto the data bus with a minimum set up time of tSFD
before the rising edge of IFCLK.
There is no specific timing requirement that must be met for
asserting the PKTEND signal with regards to asserting the
SLWR signal. PKTEND is asserted with the last data value or
thereafter. The only consideration is the setup time tSPE and the
hold time tPEH must be met. In the scenario of Figure 32, the
number of data values committed includes the last value written
to the FIFO. In this example, both the data value and the
PKTEND signal are clocked on the same rising edge of IFCLK.
PKTEND is asserted in subsequent clock cycles. The
FIFOADDR lines must be held constant during the PKTEND
assertion.
■ At t = 2, SLWR is asserted. The SLWR must meet the setup
time of tSWR (time from asserting the SLWR signal to the rising
edge of IFCLK) and maintain a minimum hold time of tWRH (time
from the IFCLK edge to the deassertion of the SLWR signal).
If SLCS signal is used, it must be asserted with SLWR or before
SLWR is asserted. (that is the SLCS and SLWR signals must
both be asserted to start a valid write condition).
■ While the SLWR is asserted, data is written to the FIFO and on
the rising edge of the IFCLK, the FIFO pointer is incremented.
Document Number: 38-08039 Rev. *K
Page 61 of 74
CY7C64713
Although there are no specific timing requirement for asserting
PKTEND, there is a specific corner case condition that needs
attention while using the PKTEND to commit a one byte or word
packet. Additional timing requirements exist when the FIFO is
configured to operate in auto mode and it is necessary to send
two packets: a full packet (full defined as the number of bytes in
the FIFO meeting the level set in AUTOINLEN register)
committed automatically followed by a short one byte or word
packet committed manually using the PKTEND pin. In this case,
the external master must make sure to assert the PKTEND pin
at least one clock cycle after the rising edge that caused the last
byte or word to be clocked into the previous auto committed
packet (the packet with the number of bytes equal to what is set
in the AUTOINLEN register). Refer to Table 19 on page 55 for
further details on this timing.
Sequence Diagram of a Single and Burst Asynchronous Read
Figure 33. Slave FIFO Asynchronous Read Sequence and Timing Diagram
t
t
t
t
FAH
SFA
SFA
FAH
FIFOADR
t=0
t
t
t
t
t
RDpwh
t
t
RDpwh
t
T=0
RDpwl
RDpwh
RDpwl
RDpwl
RDpwl
RDpwh
SLRD
SLCS
t=3
t=2
T=2
T=3
T=5
T=4
T=6
t
XFLG
t
XFLG
FLAGS
DATA
SLOE
t
t
XFD
t
XFD
XFD
t
XFD
Data (X)
Driven
N+3
N
N+1
N+2
N
t
t
OEon
t
t
OEoff
OEoff
OEon
t=4
T=1
T=7
t=1
Figure 34. Slave FIFO Asynchronous Read Sequence of Events Diagram
SLOE
SLRD
SLRD
SLOE
SLOE
SLRD
N+1
SLRD
N+1
SLRD
N+2
SLRD
N+2
SLOE
FIFO POINTER
N
N
N
N
N+1
N
N+1
N+3
N+2
N+3
FIFO DATA BUS Not Driven
Driven: X
Not Driven
N
N+1
N+1
N+2
Not Driven
Figure 33 shows the timing relationship of the SLAVE FIFO
signals during an asynchronous FIFO read. It shows a single
read followed by a burst read.
■ The data that drives after asserting SLRD, is the updated data
from the FIFO. This data is valid after a propagation delay of
tXFD from the activating edge of SLRD. In Figure 33, data N is
the first valid data read from the FIFO. For data to appear on
the data bus during the read cycle (that is, SLRD is asserted),
SLOE MUST be in an asserted state. SLRD and SLOE can
also be tied together.
■ At t = 0 the FIFO address is stable and the SLCS signal is
asserted.
■ At t = 1, SLOE is asserted. This results in the data bus being
driven. The data that is driven on to the bus is previous data,
it data that was in the FIFO from a prior read cycle.
The same sequence of events is also shown for a burst read
marked with T = 0 through 5.
■ At t = 2, SLRD is asserted. The SLRD must meet the minimum
active pulse of tRDpwl and minimum de-active pulse width of
Note In burst read mode, during SLOE is assertion, the data bus
is in a driven state and outputs the previous data. After the SLRD
is asserted, the data from the FIFO is driven on the data bus
(SLOE must also be asserted) and then the FIFO pointer is
incremented.
t
RDpwh. If SLCS is used then, SLCS must be in asserted with
SLRD or before SLRD is asserted (that is, the SLCS and SLRD
signals must both be asserted to start a valid read condition).
Document Number: 38-08039 Rev. *K
Page 62 of 74
CY7C64713
Sequence Diagram of a Single and Burst Asynchronous Write
In the following figure, dashed lines indicate signals with programmable polarity.
Figure 35. Slave FIFO Asynchronous Write Sequence and Timing Diagram
t
t
t
FAH
t
SFA
SFA
FAH
FIFOADR
t=0
T=0
t
t
t
t
t
t
t
t
WRpwh
WRpwl
WRpwh
WRpwl
WRpwl
WRpwl
WRpwh
WRpwh
SLWR
SLCS
t=3
t =1
T=1
T=4
T=3
T=7
T=6
T=9
t
XFLG
t
XFLG
FLAGS
DATA
t
t
t
t
t
t
t
SFD
t
SFD FDH
SFD FDH
SFD FDH
FDH
N
N+1
N+2
N+3
t=2
T=8
T=2
T=5
t
t
PEpwl
PEpwh
PKTEND
Figure 35 shows the timing relationship of the SLAVE FIFO write
in an asynchronous mode. This diagram shows a single write
followed by a burst write of 3 bytes and committing the
4-byte-short packet using PKTEND.
The same sequence of events are shown for a burst write and is
indicated by the timing marks of T = 0 through 5.
Note In the burst write mode, after SLWR is deasserted, the data
is written to the FIFO and then the FIFO pointer is incremented
to the next byte in the FIFO. The FIFO pointer is post
incremented.
■ At t = 0 the FIFO address is applied, insuring that it meets the
setup time of tSFA. If SLCS is used, it must also be asserted
(SLCS may be tied low in some applications).
In Figure 35, after the four bytes are written to the FIFO and
SLWR is deasserted, the short 4-byte packet is committed to the
host using the PKTEND. The external device must be designed
to not assert SLWR and the PKTEND signal at the same time. It
must be designed to assert the PKTEND after SLWR is
deasserted and has met the minimum deasserted pulse width.
The FIFOADDR lines are to be held constant during the
PKTEND assertion.
■ At t = 1 SLWR is asserted. SLWR must meet the minimum
active pulse of tWRpwl and minimum de-active pulse width of
t
WRpwh. If the SLCS is used, it must be in asserted with SLWR
or before SLWR is asserted.
■ At t = 2, data must be present on the bus tSFD before the
deasserting edge of SLWR.
■ At t = 3, deasserting SLWR causes the data to be written from
the data bus to the FIFO and then increments the FIFO pointer.
The FIFO flag is also updated after tXFLG from the deasserting
edge of SLWR.
Document Number: 38-08039 Rev. *K
Page 63 of 74
CY7C64713
Ordering Information
8051
Ordering Code
Package Type
128-pin TQFP - Pb-free
RAM Size
# Prog I/Os
Address/Data
Busses
CY7C64713-128AXC
CY7C64713-100AXC
CY7C64713-56PVXC
CY7C64713-56LTXC
CY3674
16K
16K
16K
16K
40
40
24
24
16/8 bit
100-pin TQFP - Pb-free
56-pin SSOP - Pb-free
56-pin QFN - Pb-free
–
–
–
EZ-USB FX1 Development Kit
Ordering Code Definitions
CY
XXXXX
64 713 -
X
7
C
X
X
Tape and Reel
Temperature Range: X = C or I or A
C = Commercial grade; I = Industrial grade; A = Automotive grade
X = Pb-free
Package Type: XXXXX = 128A or 100A or 56PV or 56LT
128A = 128-pin TQFP;
100A = 100-pin TQFP;
56PV = 56-pin SSOP;
56LT = 56-pin QFN
Part Number
Family Code: 64 = USB
Technology Code: C = CMOS
Marketing Code: 7 = Cypress Products
Company ID: CY = Cypress
Document Number: 38-08039 Rev. *K
Page 64 of 74
CY7C64713
Package Diagrams
The FX1 is available in four packages:
■ 56-pin SSOP
■ 56-pin QFN
■ 100-pin TQFP
■ 128-pin TQFP
Figure 36. 56-pin SSOP 300 Mils O563
51-85062 *F
Document Number: 38-08039 Rev. *K
Page 65 of 74
CY7C64713
Figure 37. 56-pin QFN (8 × 8 × 1 mm) LT56B 4.5 × 5.2 EPAD (Sawn)
001-53450 *C
Document Number: 38-08039 Rev. *K
Page 66 of 74
CY7C64713
Figure 38. 100-pin TQFP (14 × 20 × 1.4 mm) A100RA
51-85050 *D
Document Number: 38-08039 Rev. *K
Page 67 of 74
CY7C64713
Figure 39. 128-pin TQFP (14 × 20 × 1.4 mm) A128RA
51-85101 *E
For further information on this package design please refer to
‘Application Notes for Surface Mount Assembly of Amkor's
MicroLeadFrame (MLF) Packages’. This can be found on
Amkor's website http://www.amkor.com.
Quad Flat Package No Leads (QFN) Package
Design Notes
Electrical contact of the part to the Printed Circuit Board (PCB)
is made by soldering the leads on the bottom surface of the
package to the PCB. As a result, special attention is required to
the heat transfer area below the package to provide a good
thermal bond to the circuit board. A Copper (Cu) fill is to be
designed into the PCB as a thermal pad under the package. Heat
is transferred from the FX1 through the device’s metal paddle on
the bottom side of the package. Heat from here, is conducted to
the PCB at the thermal pad. It is then conducted from the thermal
pad to the PCB inner ground plane by a 5 × 5 array of via. A via
is a plated through hole in the PCB with a finished diameter of
13 mil. The QFN’s metal die paddle must be soldered to the
PCB’s thermal pad. Solder mask is placed on the board top side
over each via to resist solder flow into the via. The mask on the
top side also minimizes outgassing during the solder reflow
process.
The application note provides detailed information on board
mounting guidelines, soldering flow, rework process, and so on.
Figure 40 on page 69 displays a cross-sectional area underneath
the package. The cross section is of only one via. The solder
paste template needs to be designed to allow at least 50% solder
coverage. The thickness of the solder paste template must be
5 mil. It is recommended that ‘No Clean’ type 3 solder paste is
used for mounting the part. Nitrogen purge is recommended
during reflow.
Figure 41 on page 69 is a plot of the solder mask pattern and
Figure 42 on page 69 displays an X-Ray image of the assembly
(darker areas indicate solder).
Document Number: 38-08039 Rev. *K
Page 68 of 74
CY7C64713
Figure 40. Cross section of the Area Underneath the QFN Package
0.017” dia
Solder Mask
Cu Fill
Cu Fill
0.013” dia
PCB Material
PCB Material
Via hole for thermally connecting the
This figure only shows the top three layers of the
circuit board: Top Solder, PCB Dielectric, and
the Ground Plane.
QFN to the circuit board ground plane.
Figure 41. Plot of the Solder Mask (White Area)
Figure 42. X-ray Image of the Assembly
Document Number: 38-08039 Rev. *K
Page 69 of 74
CY7C64713
Acronyms
Document Conventions
Units of Measure
Acronym
Description
ASIC
ATA
application specific integrated circuit
advanced technology attachment
central processing unit
device identifier
Symbol
cm
Unit of Measure
centi meter
CPU
DID
°C
degree Celsius
kilo Hertz
kHZ
k
DSL
DSP
ECC
digital service line
kilo ohms
digital signal processor
error correction code
Mbps
MBPs
MHz
µA
Mega bits per second
Mega bytes per second
Mega Hertz
micro Amperes
micro seconds
micro Watts
milli Amperes
milli meter
EEPROM electrically erasable programmable read-only
memory
EPP
enhanced parallel port
first in first out
µs
FIFO
GPIF
GPIO
I/O
µW
mA
mm
ms
general programmable interface
general purpose input/output
input/output
milli seconds
milli Watts
LAN
local area network
mW
ns
LSB
least significant bit
nano seconds
ohms
MSB
PCB
PCMCIA
most significant bit
printed circuit board
ppm
%
parts per million
percent
personal computer memory card international
association
pF
pico Farad
PID
product identifier
V
Volts
PLL
phase-locked loop
QFN
quad flat no leads
RAM
SFR
random access memory
special function register
serial interface engine
start of frame
SIE
SOF
SSOP
TQFP
USARTS
USB
shrink small-outline package
thin quad flat pack
universal serial asynchronous receiver/transmitter
universal serial bus
UTOPIA
universal test and operations physical-layer
interface
VID
vendor identifier
Document Number: 38-08039 Rev. *K
Page 70 of 74
CY7C64713
Errata
This section describes the errata for the EZ-USB FX1/CY7C64713/4. Details include errata trigger conditions, scope of impact,
available workaround, and silicon revision applicability.
Contact your local Cypress Sales Representative if you have further questions.
Part Numbers Affected
Part Number
Device Characteristics
Operating Range
CY7C64713/4
ALL
Commercial
EZ-USB FX1 Qualification Status
In Production
EZ-USB FX1 Errata Summary
The following table defines the errata applicability to available EZ-USB FX1™ family devices.
Items
Part Number
Silicon Revision
Fix Status
[1]. Empty Flag Assertion
CY7C64713/4
B
No silicon fix planned currently. Use
workaround
1. Empty Flag Assertion
■ Problem Definition
When Configured in Slave FIFO Asynchronous Word Wide mode and if only single word data transferred from USB Host to EP2
configured as OUT End Point (EP) in the very first transaction then Empty flag behaves incorrectly. This does not happened if data
size is more than a word length in the first transaction.
■ Parameters Affected
NA
■ Trigger Condition(S)
In Slave FIFO Word Wide Mode, after firmware boot and initialization, EP2 OUT Endpoint empty flag indicates status as Empty.
Upon data reception in EP2 it changes to Not-Empty. But if data transferred to EP2 is single word only, then asserting SLRD with
FIFOADR pointing to any other Endpoint, changes Not-Empty status to Empty for EP2 even though a word data is there (or it is
untouched) in EP2. This is noticed only when the single word is sent as the very first transaction and does not happen if it follows
multi-word packet as the first transaction.
■ Scope of Impact
External interface does not see data available in EP2 OUT Endpoint and might end up waiting for data to be read.
■ Workaround
Any one of the following workaround can be used
i.Give out Pulse signal to the SLWR pin, with FIFOADR pins pointing to an Endpoint other than EP2, after firmware initialization
and before/after transferring the data to EP2 from Host, or
ii.Set length of very first data to EP2 to be more than a word, or
iii.Prioritize EP2 read from Master in case of multiple OUT EPs and single word write to EP2, or
iv.Write to any IN EP, if any, from Master before reading from other OUT EPs (other than EP2) from Master.
■ Fix Status
There is no silicon fix planned for this currently, you can use above workaround.
Document Number: 38-08039 Rev. *K
Page 71 of 74
CY7C64713
Document History Page
Document Title: CY7C64713, EZ-USB FX1™ USB Microcontroller Full Speed USB Peripheral Controller
Document Number: 38-08039
Orig. of
Change
Submission
Date
Revision
ECN
Description of Change
**
132091
230709
KKU
KKU
02/10/04
New Datasheet.
*A
SEE ECN
Changed Lead free Marketing part numbers in Ordering Information according
to spec change in 28-00054.
*B
307474
BHA
SEE ECN
Changed default PID in Table 2 on page 5.
Updated register table.
Removed word compatible where associated with I2C.
Changed Set-up to Setup.
Added Power Dissipation.
Changed Vcc from ± 10% to ± 5%
Added values for VIH_X, VIL_X
Added values for ICC
Added values for ISUSP
Removed IUNCONFIGURED from DC Characteristics on page 47.
Changed PKTEND to FLAGS output propagation delay (asynchronous
interface) in Table 10-14 from a maximum value of 70 ns to 115 ns.
Removed 56 SSOP and added 56 QFN package.
Provided additional timing restrictions and requirement regarding the use of
PKTEND pin to commit a short one byte/word packet subsequent to committing
a packet automatically (when in auto mode).
Added part number CY7C64714 ideal for battery powered applications.
Changed Supply Voltage in section 8 to read +3.15V to +3.45V.
Added Min Vcc Ramp Up time (0 to 3.3 V).
Removed Preliminary.
*C
*D
392702
BHA
SEE ECN
Corrected signal name for pin 54 in Figure 10 on page 18.
Added information on the AUTOPTR1/AUTOPTR2 address timing with regards
to data memory read/write timing diagram.
Removed TBD in Table 15 on page 53.
Added section PORTC Strobe Feature Timings on page 51.
1664787
CMCC/
JASM
See ECN
See ECN
Added the 56 pin SSOP pinout and package information.
Delete CY7C64714.
*E
*F
2088446
2710327
JASM
DPT
Updated package diagrams.
05/22/2009 Added 56-Pin QFN (8 × 8 mm) package diagram
Updated ordering information for CY7C64713-56LTXC part
*G
2765406
ODC
09/17/2009 Added Pb-free for the CY7C64713-56LTXC part in the ordering information
table.
Updated 56-Pin Sawn QFN package diagram.
*H
*I
2896318
3186891
ODC
ODC
03/18/2010 Removed obsolete part CY7C64713-56LFXC. Updated all package diagrams.
03/03/2011 Template updates.
Updated package diagrams: 51-85144 , 51-85050, 51-85101
*J
3259101
ODC
05/17/2011 Added Ordering Code Definitions.
Updated Package Diagrams.
Added Acronyms and Units of Measure.
Updated in new template.
Document Number: 38-08039 Rev. *K
Page 72 of 74
CY7C64713
Document History Page (continued)
Document Title: CY7C64713, EZ-USB FX1™ USB Microcontroller Full Speed USB Peripheral Controller
Document Number: 38-08039
Orig. of
Change
Submission
Date
Revision
ECN
Description of Change
*K
3999873
SIRK
07/22/2013 Added Errata footnote (Note 3).
Updated Functional Overview:
Updated Interrupt System:
Updated FIFO/GPIF Interrupt (INT4):
Added Note 3 and referred the same note in “Endpoint 2 empty flag” in Table 4.
Updated Package Diagrams:
spec 51-85062 – Changed revision from *D to *F.
spec 001-53450 – Changed revision from *B to *C.
Added Errata.
Updated in new template.
Document Number: 38-08039 Rev. *K
Page 73 of 74
CY7C64713
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© Cypress Semiconductor Corporation, 2004-2013. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
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Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-08039 Rev. *K
Revised July 22, 2013
Page 74 of 74
EZ-USB FX1, EZ-USB FX2LP, EZ-USB FX2, and ReNumeration are trademarks, and EZ-USB is a registered trademark, of Cypress Semiconductor. All product and company names mentioned in this
document are the trademarks of their respective holders.
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