DS1265AB-100 [ROCHESTER]
1MX8 NON-VOLATILE SRAM MODULE, 100ns, DMA36, 0.740 INCH, DIP-36;
| 型号： | DS1265AB-100 |
| 厂家： | 
Rochester Electronics |
| 描述： | 1MX8 NON-VOLATILE SRAM MODULE, 100ns, DMA36, 0.740 INCH, DIP-36 静态存储器 内存集成电路 |
| 文件： | 总9页 (文件大小：869K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS1265Y/AB
8M Nonvolatile SRAM
www.maxim-ic.com
FEATURES
PIN ASSIGNMENT
Cꢀ10 years minimum data retention in the
absence of external power
NC
NC
A18
A16
A14
A12
A7
1
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
VCC
A19
NC
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
CꢀData is automatically protected during power
loss
A15
A17
WE
A13
A8
CꢀUnlimited write cycles
CꢀLow-power CMOS operation
CꢀRead and write access times as fast as 70 ns
CꢀLithium energy source is electrically
disconnected to retain freshness until power is
applied for the first time
A6
A9
A5
A4
A11
OE
A3
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
A2
A1
CꢀFull M10% VCC operating range (DS1265Y)
CꢀOptional M5% VCC operating range
(DS1265AB)
A0
DQ0
DQ1
CꢀOptional industrial temperature range of
-40LC to +85LC, designated IND
20
19
DQ2
GND
36-Pin ENCAPSULATED PACKAGE
740-mil EXTENDED
PIN DESCRIPTION
A0 - A19
DQ0 - DQ7
CE
- Address Inputs
- Data In/Data Out
- Chip Enable
- Write Enable
- Output Enable
- Power (+5V)
- Ground
WE
OE
VCC
GND
NC
- No Connect
DESCRIPTION
The DS1265 8M Nonvolatile SRAMs are 8,388,608-bit, fully static nonvolatile SRAMs organized as
1,048,576 words by 8 bits. Each NV SRAM has a self-contained lithium energy source and control
circuitry which constantly monitors VCC for an out-of-tolerance condition. When such a condition occurs,
the lithium energy source is automatically switched on and write protection is unconditionally enabled to
prevent data corruption. There is no limit on the number of write cycles which can be executed and no
additional support circuitry is required for microprocessor interfacing.
1 of 8
083006
DS1265Y/AB
READ MODE
The DS1265 devices execute a read cycle whenever WE (Write Enable) is inactive (high) and CE (Chip
Enable) and OE (Output Enable) are active (low). The unique address specified by the 20 address inputs
(A0 - A19) defines which of the 1,048,576 bytes of data is accessed. Valid data will be available to the
eight data output drivers within tACC (Access Time) after the last address input signal is stable, providing
that CE and OE (Output Enable) access times are also satisfied. If OE and CE access times are not
satisfied, then data access must be measured from the later-occurring signal (CE or OE ) and the limiting
parameter is either tCO for CE or tOE for OE rather than tACC
.
WRITE MODE
The DS1265 devices execute a write cycle whenever WE and CE signals are active (low) after address
inputs are stable. The later-occurring falling edge of CE or WE will determine the start of the write cycle.
The write cycle is terminated by the earlier rising edge of CE or WE . All address inputs must be kept
valid throughout the write cycle. WE must return to the high state for a minimum recovery time (tWR)
before another cycle can be initiated. The OE control signal should be kept inactive (high) during write
cycles to avoid bus contention. However, if the output drivers are enabled (CE and OE active) then WE
will disable the outputs in tODW from its falling edge.
DATA RETENTION MODE
The DS1265AB provides full functional capability for VCC greater than 4.75 volts and write protects by
4.5 volts. The DS1265Y provides full functional capability for VCC greater than 4.5 volts and write
protects by 4.25 volts. Data is maintained in the absence of VCC without any additional support circuitry.
The nonvolatile static RAMs constantly monitor VCC. Should the supply voltage decay, the NV SRAMs
automatically write protect themselves, all inputs become don’t care, and all outputs become high-
impedance. As VCC falls below approximately 3.0 volts, a power switching circuit connects the lithium
energy source to RAM to retain data. During power-up, when VCC rises above approximately 3.0 volts,
the power switching circuit connects external VCC to RAM and disconnects the lithium energy source.
Normal RAM operation can resume after VCC exceeds 4.75 volts for the DS1265AB and 4.5 volts for the
DS1265Y.
FRESHNESS SEAL
Each DS1265 device is shipped from Dallas Semiconductor with its lithium energy source disconnected,
guaranteeing full energy capacity. When VCC is first applied at a level greater than VTP, the lithium
energy source is enabled for battery backup operation.
2 of 8
DS1265Y/AB
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground
Operating Temperature
-0.3V to +6.0V
0°C to 70°C; -40°C to +85°C for IND parts
-40°C to +70°C; -40°C to +85°C for IND parts
+260°C for 10 seconds
Storage Temperature
Soldering Temperature
Caution: Do Not Reflow
(Wave or Hand Solder Only)
* This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operation sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
(tA: See Note 10)
PARAMETER
SYMBOL MIN
TYP
5.0
5.0
MAX
5.25
5.5
VCC
+0.8
UNITS NOTES
DS1265AB Power Supply Voltage
DS1265Y Power Supply Voltage
Logic 1 Input Voltage
VCC
VCC
VIH
VIL
4.75
4.5
2.2
0
V
V
V
V
Logic 0 Input Voltage
DC ELECTRICAL
CHARACTERISTICS
PARAMETER
Input Leakage Current
I/O Leakage Current
Output Current @ 2.4V
Output Current @ 0.4V
Standby Current CE =2.2V
Standby Current CE =VCC-0.5V
Operating Current
Write Protection Voltage (DS1265AB)
Write Protection Voltage (DS1265Y)
(VCC=5V Mꢀ5% for DS1265AB)
(tA: See Note 10) (VCC=5V Mꢀ10% for DS1265Y)
SYMBOL MIN
TYP
MAX
+2.0
+2.0
UNITS NOTES
IIL
IIO
IOH
IOL
-2.0
-2.0
-1.0
2.0
ꢀA
ꢀA
mA
mA
mA
ICCS1
ICCS2
ICCO1
VTP
VTP
1.0
100
1.5
200
85
4.75
4.5
ꢀA
mA
V
4.50
4.25
4.62
4.37
V
CAPACITANCE
PARAMETER
Input Capacitance
Output Capacitance
(tA=25LC)
SYMBOL MIN
TYP
10
10
MAX
20
20
UNITS NOTES
CIN
CI/O
pF
pF
3 of 8
DS1265Y/AB
(VCC=5V Mꢀ5% for DS1265AB)
AC ELECTRICAL
CHARACTERISTICS
(tA: See Note 10) (VCC=5V Mꢀ10% for DS1265Y)
DS1265AB-70 DS1265AB-100
DS1265Y-70
DS1265Y-100
PARAMETER
Read Cycle Time
Access Time
OE to Output Valid
SYMBOL
tRC
UNITS NOTES
MIN MAX MIN MAX
70
100
ns
ns
ns
ns
tACC
tOE
tCO
70
35
70
100
50
100
CE to Output Valid
tCOE
tOD
tOH
tWC
tWP
5
5
ns
ns
ns
ns
ns
ns
5
5
OE or CE to Output Active
Output High Z from Deselection
Output Hold from Address Change
Write Cycle Time
Write Pulse Width
Address Setup Time
Write Recovery Time
25
25
35
5
70
55
0
5
100
75
0
3
tAW
tWR1
5
5
ns
12
13
5
5
4
tWR2
15
15
ns
tODW
tOEW
tDS
35
ns
ns
ns
Output High Z from WE
Output Active from WE
Data Setup Time
5
30
5
40
Data Hold Time
tDH1
0
0
ns
12
tDH2
10
10
ns
13
TIMING DIAGRAM: READ CYCLE
SEE NOTE 1
4 of 8
DS1265Y/AB
TIMING DIAGRAM: WRITE CYCLE 1
TIMING DIAGRAM: WRITE CYCLE 2
SEE NOTES 2, 3, 4, 6, 7, 8 AND 13
5 of 8
DS1265Y/AB
POWER-DOWN/POWER-UP CONDITION
SEE NOTE 11
POWER-DOWN/POWER-UP TIMING
(tA: See Note 10)
PARAMETER
SYMBOL MIN
TYP
TYP
MAX
1.5
UNITS NOTES
tPD
tF
tR
11
ꢀs
ꢀs
VCC Fail Detect to CE and WE Inactive
VCC slew from VTP to 0V
VCC slew from 0V to VTP
150
150
ꢀs
ms
ms
tPU
tREC
2
125
VCC Valid to CE and WE Inactive
VCC Valid to End of Write Protection
(tA=25LC)
PARAMETER
Expected Data Retention Time
SYMBOL MIN
tDR 10
MAX
UNITS NOTES
years
9
WARNING:
Under no circumstance are negative undershoots, of any amplitude, allowed when device is in battery
backup mode.
NOTES:
1. WE is high for a Read Cycle.
2. OE = VIH or VIL. If OE = VIH during write cycle, the output buffers remain in a high-impedance state.
3. tWP is specified as the logical AND of CE or WE . tWP is measured from the latter of CE or WE going
low to the earlier of CE or WE going high.
4. tDS is measured from the earlier of CE or WE going high.
5. These parameters are sampled with a 5 pF load and are not 100% tested.
6. If the CE low transition occurs simultaneously with or latter than the WE low transition, the output
buffers remain in a high-impedance state during this period.
7. If the CE high transition occurs prior to or simultaneously with the WE high transition, the output
buffers remain in high-impedance state during this period.
6 of 8
DS1265Y/AB
8. If WE is low or the WE low transition occurs prior to or simultaneously with the CE low transition,
the output buffers remain in a high-impedance state during this period.
9. Each DS1265 has a built-in switch that disconnects the lithium source until the user first applies VCC.
The expected tDR is defined as accumulative time in the absence of VCC starting from the time power
is first applied by the user. This parameter is assured by component selection, process control, and
design. It is not measured directly during production testing.
10. All AC and DC electrical characteristics are valid over the full operating temperature range. For
commercial products, this range is 0LC to 70LC. For industrial products (IND), this range is -40LC to
+85LC.
11. In a power-down condition the voltage on any pin may not exceed the voltage on VCC.
12. tWR1 and tDH1 are measured from WE going high.
13. tWR2 and tDH2 are measured from CE going high.
14. DS1265 modules are recognized by Underwriters Laboratory (U.L.ꢁ) under file E99151.
DC TEST CONDITIONS
Outputs Open
AC TEST CONDITIONS
Output Load: 100 pF + 1TTL Gate
Input Pulse Levels: 0V to 3.0V
Timing Measurement Reference Levels
Input: 1.5V
Cycle = 200ns for operating current
All voltages are referenced to ground
Output: 1.5V
Input pulse Rise and Fall Times: 5 ns
ORDERING INFORMATION
TEMPERATURE
PART NUMBER
SUPPLY
TOLERANCE
5V M 5%
SPEED
PIN/PACKAGE
RANGE
GRADE
DS1265AB-70
0°C to +70°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
0°C to +70°C
0°C to +70°C
36 / 740 EMOD
36 / 740 EMOD
36 / 740 EMOD
36 / 740 EMOD
36 / 740 EMOD
36 / 740 EMOD
36 / 740 EMOD
36 / 740 EMOD
36 / 740 EMOD
36 / 740 EMOD
36 / 740 EMOD
36 / 740 EMOD
70ns
70ns
70ns
70ns
100ns
100ns
70ns
70ns
70ns
70ns
100ns
100ns
DS1265AB-70+
DS1265AB-70IND
DS1265AB-70IND+
DS1265AB-100
DS1265AB-100+
DS1265Y-70
5V M 5%
5V M 5%
5V M 5%
5V M 5%
5V M 5%
5V M 10%
5V M 10%
5V M 10%
5V M 10%
5V M 10%
5V M 10%
DS1265Y-70+
DS1265Y-70IND
DS1265Y-70IND+
DS1265Y-100
DS1265Y-100+
+ Denotes lead-free/RoHS-compliant product.
* DS9034PC or DS9034PCI (PowerCap) required. Must be ordered separately.
7 of 8
DS1265Y/AB
DS1265Y/AB NONVOLATILE SRAM 36-PIN 740-MIL EXTENDED MODULE, LONG
PKG
DIM
36-PIN
MIN
MAX
A IN.
MM
2.080
52.83
2.100
53.34
B IN.
MM
0.720
18.29
0.740
18.80
C IN.
MM
0.355
9.02
0.405
10.29
D IN.
MM
0.180
4.57
0.210
5.33
E IN.
MM
0.015
0.38
0.025
0.63
F IN.
MM
0.120
3.05
0.150
4.06
G IN.
MM
0.090
2.29
0.110
2.79
H IN.
MM
0.590
14.99
0.630
16.00
J IN.
MM
0.008
0.20
0.012
0.30
K IN.
MM
0.015
0.38
0.025
0.58
8 of 8
相关型号：
DS1265AB-70IND+
Non-Volatile SRAM Module, 1MX8, 70ns, CMOS, 0.740 INCH, ROHS COMPLIANT, DIP-36
MAXIM
DS1265AB-70IND+
1MX8 NON-VOLATILE SRAM MODULE, 70ns, DMA36, 0.740 INCH, ROHS COMPLIANT, DIP-36
ROCHESTER
©2020 ICPDF网 联系我们和版权申明