DS21Q352B+ [ROCHESTER]
DATACOM, PCM TRANSCEIVER, PBGA256, 27 X 27 MM, ROHS COMPLIANT, MCMBGA-256;
| 型号： | DS21Q352B+ |
| 厂家： | 
Rochester Electronics |
| 描述： | DATACOM, PCM TRANSCEIVER, PBGA256, 27 X 27 MM, ROHS COMPLIANT, MCMBGA-256 PC 电信 电信集成电路 |
| 文件： | 总15页 (文件大小：930K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DALLAS SEMICONDUCTOR
Quad T1/E1 Transceiver (5V)
Quad T1/E1 Transceiver (3.3V)
Preliminary
DS21Q552/DS21Q554
DS21Q352/DS21Q354
FEATURES
P
·
Four (4) Completely Independent T1 or E1 Transceivers
In One Small 27mm x 27mm Package
·
Each Transceiver Contains a Short & Long Haul Line Interface
Plus a Full Featured Framer with Alarm Detection/Generation,
Elastic Stores, Hardware Based Signaling Support, Per DS0
Channel Control and HDLC Controller
·
·
Each Multi-Chip Module (MCM) Contains Four Die of:
DS21352 (DS21Q352)
DS21552 (DS21Q552)
DS21354 (DS21Q354)
DS21554 (DS21Q554)
Selection Guide:
Supply
Device
T1
T1
E1
E1
3.3V
5V
3.3V
5V
DS21Q352
DS21Q552
DS21Q354
DS21Q554
·
·
See the Specific DS21352/DS21552 and DS21354/DS21554
Data Sheets for Details on their Feature Set and Operation
All Four T1 or E1 Transceivers Can be Concatenated into a Single
8.192MHz Backplane Data Stream
·
·
IEEE 1149.1 JTAG-Boundary Scan Architecture
DS21Q352/DS21Q552 and DS21Q354/DS21Q554 are Pin Compatible
to Allow the Same Footprint to Support T1 and E1 Applications
·
·
256–lead MCM BGA package (27mm X 27mm)
Low Power 5V CMOS or Low Power 3.3V CMOS with 5V
Tolerant Input & Outputs
DESCRIPTION
The Quad T1 and E1 Transceiver MCMs offer a high density packaging arrangement for the
DS21352/DS21552 T1 Single-Chip Transceivers and the DS21354/DS21554 E1 Single-Chip Transceivers.
Four silicon die of one of these devices is packaged in a Multi-Chip Module (MCM) with the electrical
connections as shown in Figure 1. All of the functions available on the DS21352/DS21552 and
DS21354/DS21554 are also available in the MCM packaged version however in order to minimize package
size, some signals have been deleted. These differences are detailed in Table 1.
This data sheet describes the electrical connections and the mechanical dimensions only. Please see the
DS21352/DS21552 and DS21354/DS21554 data sheets for full details on all of the features and the
operating characteristics of the device.
December 29, 1998
DALLAS SEMICONDUCTOR
DS21Q352/DS21Q552/DS21Q354/DS21Q554 Preliminary Data Sheet
Changes from Normal DS21Q352/DS21Q552 & DS21Q354/DS21Q554 Configuration Table 1
1. The following signals are not available: XTALD / 8XCLK / TESO / TDATA / RCL / RDATA
DS21Q352 / DS21Q552 / DS21Q354 / DS21Q554 Schematic Figure 1
RCLKO
SCT # 1
DS21352 / DS21552 /
RPOSO
RNEGO
RCLKI
DS21354 / DS21554
RPOSI
Signals Not Connected & Left Open Circuited
RNEGI
TCLKO
TPOSO
TNEGO
TCLKI
TPOSI
TNEGI
LIUC
CO
CI
Include: 8XCLK / XTALD / RDATA / RCL
RCLK
RLOS/LOTC
8MCLK
RLINK
RLCLK
RCHBLK
RCHCLK
RSIGF
TEST
BTS
RSIG
MUX
RSER
WR*
RSYSCLK
RSYNC
RMSYMC
RFSYNC
RD*
8
8
A0 to A7/ALE
D0/AD0 to D7/AD7
CS*
TESO
TDATA
TSYNC
INT*
JTRST
JTMS
TSSYNC
TSYSCLK
TSER
JTCLK
JTDI
JTDO
TSIG
MCLK
TCLK
TCHBLK
TCHCLK
TLINK
RTIP
RRING
TTIP
TLCLK
FMS
TRING
DVSS
RVSS
TVSS
DVDD
RVDD
TVDD
See Connecting Page
December 29, 1998
2
DALLAS SEMICONDUCTOR
DS21Q352/DS21Q552/DS21Q354/DS21Q554 Preliminary Data Sheet
DS21Q352 / DS21Q552 / DS21Q354 / DS21Q554 Schematic Figure 1 (continued)
See Connecting Page
RCLKO
SCT # 2
DS21352 / DS21552 /
RPOSO
RNEGO
RCLKI
DS21354 / DS21554
RPOSI
Signals Not Connected & Left Open Circuited
RNEGI
TCLKO
TPOSO
TNEGO
TCLKI
TPOSI
TNEGI
LIUC
CO
CI
Include: 8XCLK / XTALD / RDATA / RCL
RCLK
RLOS/LOTC
8MCLK
RLINK
RLCLK
RCHBLK
RCHCLK
RSIGF
TEST
BTS
RSIG
MUX
RSER
WR*
RSYSCLK
RSYNC
RMSYMC
RFSYNC
RD*
A0 to A7/ALE
D0/AD0 to D7/AD7
CS*
TESO
TDATA
TSYNC
INT*
JTRST
JTMS
TSSYNC
TSYSCLK
TSER
JTCLK
JTDI
JTDO
TSIG
MCLK
TCLK
TCHBLK
TCHCLK
TLINK
RTIP
RRING
TTIP
TLCLK
FMS
TRING
DVSS
RVSS
TVSS
DVDD
RVDD
TVDD
See Connecting Page
December 29, 1998
3
DALLAS SEMICONDUCTOR
DS21Q352/DS21Q552/DS21Q354/DS21Q554 Preliminary Data Sheet
DS21Q352 / DS21Q552 / DS21Q354 / DS21Q554 Schematic Figure 1 (continued)
See Connecting Page
RCLKO
SCT # 3
DS21352 / DS21552 /
RPOSO
RNEGO
RCLKI
DS21354 / DS21554
RPOSI
Signals Not Connected & Left Open Circuited
RNEGI
TCLKO
TPOSO
TNEGO
TCLKI
TPOSI
TNEGI
LIUC
CO
CI
Include: 8XCLK / XTALD / RDATA / RCL
RCLK
RLOS/LOTC
8MCLK
RLINK
RLCLK
RCHBLK
RCHCLK
RSIGF
TEST
BTS
RSIG
MUX
RSER
WR*
RSYSCLK
RSYNC
RMSYMC
RFSYNC
RD*
A0 to A7/ALE
D0/AD0 to D7/AD7
CS*
TESO
TDATA
TSYNC
INT*
JTRST
JTMS
TSSYNC
TSYSCLK
TSER
JTCLK
JTDI
JTDO
TSIG
MCLK
TCLK
TCHBLK
TCHCLK
TLINK
RTIP
RRING
TTIP
TLCLK
FMS
TRING
DVSS
RVSS
TVSS
DVDD
RVDD
TVDD
See Connecting Page
December 29, 1998
4
DALLAS SEMICONDUCTOR
DS21Q352/DS21Q552/DS21Q354/DS21Q554 Preliminary Data Sheet
DS21Q352 / DS21Q552 / DS21Q354 / DS21Q554 Schematic Figure 1 (continued)
See Connecting Page
RCLKO
SCT # 4
DS21352 / DS21552 /
RPOSO
RNEGO
RCLKI
DS21354 / DS21554
RPOSI
Signals Not Connected & Left Open Circuited
RNEGI
TCLKO
TPOSO
TNEGO
TCLKI
TPOSI
TNEGI
LIUC
CO
CI
Include: 8XCLK / XTALD / RDATA / RCL
RCLK
RLOS/LOTC
8MCLK
RLINK
RLCLK
RCHBLK
RCHCLK
RSIGF
TEST
BTS
RSIG
MUX
RSER
WR*
RSYSCLK
RSYNC
RMSYMC
RFSYNC
RD*
A0 to A7/ALE
D0/AD0 to D7/AD7
CS*
TESO
TDATA
TSYNC
INT*
JTRST
JTMS
TSSYNC
TSYSCLK
TSER
JTCLK
JTDI
JTDO
TSIG
MCLK
TCLK
TCHBLK
TCHCLK
TLINK
RTIP
RRING
TTIP
TLCLK
FMS
TRING
DVSS
RVSS
TVSS
DVDD
RVDD
TVDD
December 29, 1998
5
DALLAS SEMICONDUCTOR
DS21Q352/DS21Q552/DS21Q354/DS21Q554 Preliminary Data Sheet
Lead Description Sorted by Symbol Table 2
Lead Symbol
I/O
O
O
O
O
I
Description
M1
H17
F4
8MCLK1
8MCLK2
8MCLK3
8MCLK4
A0
8.192 MHz Clock Based on RCLK1.
8.192 MHz Clock Based on RCLK2.
8.192 MHz Clock Based on RCLK3.
8.192 MHz Clock Based on RCLK4.
Address Bus Bit 0 (lsb).
V13
U3
L17
V2
A1
A2
I
I
Address Bus Bit 1.
Address Bus Bit 2.
T4
A3
I
Address Bus Bit 3.
V8
A4
I
Address Bus Bit 4.
H4
A5
I
Address Bus Bit 5.
U8
A6
I
Address Bus Bit 6.
P4
P2
A7/ALE
BTS
CI1
CI2
CI3
I
I
I
I
I
I
O
O
O
O
I
I
I
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
–
–
–
–
–
–
–
–
–
–
–
–
–
Address Bus Bit 7 (msb) / Address Latch Enable.
Bus Type Select (0 = Intel / 1 = Motorola),
Carry Input for Interleaved Bus Operation for SCT1.
Carry Input for Interleaved Bus Operation for SCT2.
Carry Input for Interleaved Bus Operation for SCT3.
Carry Input for Interleaved Bus Operation for SCT4.
Carry Output for Interleaved Bus Operation for SCT1.
Carry Output for Interleaved Bus Operation for SCT2.
Carry Output for Interleaved Bus Operation for SCT3.
Carry Output for Interleaved Bus Operation for SCT4.
Chip Select for SCT1.
W6
F18
D7
T20
V9
B17
A6
J20
P3
A14
B5
K17
U11
J19
W15 D2/AD2
U7
U9
U5
V4
U4
J3
N4
CI4
CO1
CO2
CO3
CO4
CS1*
CS2*
CS3*
CS4*
D0/AD0
D1/AD1
Chip Select for SCT2.
Chip Select for SCT3.
Chip Select for SCT4.
Data Bus Bit 0/ Address/Data Bus Bit 0 (lsb).
Data Bus Bit 1/ Address/Data Bus Bit 1.
Data Bus Bit 2/Address/Data Bus Bit 2.
Data Bus Bit 3/Address/Data Bus Bit 3.
Data Bus Bit 4/Address/Data Bus Bit 4.
Data Bus Bit 5/Address/Data Bus Bit 5.
Data Bus Bit 6/Address/Data Bus Bit 6.
Data Bus Bit 7/Address/Data Bus Bit 7 (msb).
Digital Positive Supply.
Digital Positive Supply.
Digital Positive Supply.
Digital Positive Supply.
Digital Positive Supply.
Digital Positive Supply.
Digital Positive Supply.
Digital Positive Supply.
Digital Positive Supply.
Digital Positive Supply.
Digital Positive Supply.
Digital Positive Supply.
Digital Positive Supply.
D3/AD3
D4/AD4
D5/AD5
D6/AD6
D7/AD7
DVDD1
DVDD1
DVDD1
DVDD1
DVDD2
DVDD2
DVDD2
DVDD2
DVDD3
DVDD3
DVDD3
DVDD3
DVDD4
DVDD4
DVDD4
DVDD4
DVSS1
DVSS1
DVSS1
DVSS1
U2
V5
B12
C12
C16
D18
A9
B3
B6
C4
G20
M17
M20
P18
H3
J4
U6
W8
–
–
–
–
–
–
–
Digital Positive Supply.
Digital Positive Supply.
Digital Positive Supply.
Digital Signal Ground.
Digital Signal Ground.
Digital Signal Ground.
Digital Signal Ground.
December 29, 1998
6
DALLAS SEMICONDUCTOR
DS21Q352/DS21Q552/DS21Q354/DS21Q554 Preliminary Data Sheet
A17
A20
B11
C13
A5
B7
B9
C3
H20
L20
N17
U13
U1
DVSS2
DVSS2
DVSS2
DVSS2
DVSS3
DVSS3
DVSS3
DVSS3
DVSS4
DVSS4
DVSS4
DVSS4
INT*
–
–
–
–
–
–
–
–
–
–
–
–
O
I
I
Digital Signal Ground.
Digital Signal Ground.
Digital Signal Ground.
Digital Signal Ground.
Digital Signal Ground.
Digital Signal Ground.
Digital Signal Ground.
Digital Signal Ground.
Digital Signal Ground
Digital Signal Ground
Digital Signal Ground
Digital Signal Ground
Interrupt for all four SCTs.
JTAG Clock.
JTAG Data Input.
Y15
N1
JTCLK
JTDI
H18
V17
V19
JTDO2
JTDO3
JTDO4
O
O
O
I
JTAG Data Output from SCT2.
JTAG Data Output from SCT3.
JTAG Data Output from SCT4.
JTAG Test Mode Select.
W13 JTMS
V18
K2
T1
W20 MCLK2
U10
M2
G17
G4
Y12
J1
D14
F3
U14
N3
B13
E3
M18
M4
A15
A4
R17
M3
C14
B4
T17
N2
K4
D17
A2
JTRST*
LIUC
MCLK1
I
I
I
I
JTAG Reset.
Line Interface Connect for all Four SCTs.
Master Clock for SCT1 and SCT3.
Master Clock for SCT2 and SCT4.
Mux Bus Select.
MUX
I
RCHBLK1
RCHBLK2
RCHBLK3
RCHBLK4
RCHCLK1
RCHCLK2
RCHCLK3
RCHCLK4
RCLK1
RCLK2
RCLK3
RCLK4
RCLKI1
O
O
O
O
O
O
O
O
O
O
O
O
I
Receive Channel Block for SCT1.
Receive Channel Block for SCT2.
Receive Channel Block for SCT3.
Receive Channel Block for SCT4.
Receive Channel Clock for SCT1.
Receive Channel Clock for SCT2.
Receive Channel Clock for SCT3.
Receive Channel Clock for SCT4.
Receive Clock Output from the Framer on SCT1.
Receive Clock Output from the Framer on SCT2.
Receive Clock Output from the Framer on SCT3.
Receive Clock Output from the Framer on SCT4.
Receive Clock Input for the LIU on SCT1.
Receive Clock Input for the LIU on SCT2.
Receive Clock Input for the LIU on SCT3.
Receive Clock Input for the LIU on SCT4.
Receive Clock Output from the LIU on SCT1.
Receive Clock Output from the LIU on SCT2.
Receive Clock Output from the LIU on SCT3.
Receive Clock Output from the LIU on SCT4.
Read Input (Data Strobe)
Receive Frame Sync (before the receive elastic store) for SCT1.
Receive Frame Sync (before the receive elastic store) for SCT2.
Receive Frame Sync (before the receive elastic store) for SCT3.
Receive Frame Sync (before the receive elastic store) for SCT4.
Receive Link Clock for SCT1.
Receive Link Clock for SCT2.
Receive Link Clock for SCT3.
Receive Link Clock for SCT4.
Receive Link Data for SCT1.
RCLKI2
RCLKI3
RCLKI4
I
I
I
RCLKO1
RCLKO2
RCLKO3
RCLKO4
RD*(DS*)
RFSYNC1
RFSYNC2
RFSYNC3
RFSYNC4
RLCLK1
RLCLK2
RLCLK3
RLCLK4
RLINK1
O
O
O
O
I
O
O
O
O
O
O
O
O
O
O
O
O
V14
F1
A12
D3
K18
G2
A13
A3
RLINK2
RLINK3
RLINK4
Receive Link Data for SCT2.
Receive Link Data for SCT3.
Receive Link Data for SCT4.
U12
December 29, 1998
7
DALLAS SEMICONDUCTOR
DS21Q352/DS21Q552/DS21Q354/DS21Q554 Preliminary Data Sheet
H2
E17
E1
V11
L1
D16
F2
RLOS/LOTC1
RLOS/LOTC2
RLOS/LOTC3
RLOS/LOTC4
RMSYNC1
O
O
O
O
O
O
O
O
I
Receive Loss Of Sync / Loss Of Transmit Clock for SCT1.
Receive Loss Of Sync / Loss Of Transmit Clock for SCT2.
Receive Loss Of Sync / Loss Of Transmit Clock for SCT3.
Receive Loss Of Sync / Loss Of Transmit Clock for SCT4.
Receive Multiframe Sync for SCT1.
Receive Multiframe Sync for SCT2.
Receive Multiframe Sync for SCT3.
Receive Multiframe Sync for SCT4.
RMSYNC2
RMSYNC3
W16 RMSYNC4
R3
RNEGI1
RNEGI2
RNEGI3
RNEGI4
RNEGO1
RNEGO2
RNEGO3
RNEGO4
RPOSI1
RPOSI2
RPOSI3
RPOSI4
RPOSO1
RPOSO2
RPOSO3
RPOSO4
RRING1
RRING2
RRING3
RRING4
RSER1
Receive Negative Data for the Framer on SCT1.
Receive Negative Data for the Framer on SCT2.
Receive Negative Data for the Framer on SCT3.
Receive Negative Data for the Framer on SCT4.
Receive Negative Data from the LIU on SCT1.
Receive Negative Data from the LIU on SCT2.
Receive Negative Data from the LIU on SCT3.
Receive Negative Data from the LIU on SCT4.
Receive Positive Data for the Framer on SCT1.
Receive Positive Data for the Framer on SCT2.
Receive Positive Data for the Framer on SCT3.
Receive Positive Data for the Framer on SCT4.
Receive Positive Data from the LIU on SCT1.
Receive Positive Data from the LIU on SCT2.
Receive Positive Data from the LIU on SCT3.
Receive Positive Data from the LIU on SCT4.
Receive Analog Ring Input for SCT1.
Receive Analog Ring Input for SCT2.
Receive Analog Ring Input for SCT3.
Receive Analog Ring Input for SCT4.
Receive Serial Data for SCT1.
D13
A1
P17
L3
B15
C2
U17
R4
B14
B2
V15
L4
A16
B1
U15
Y11
Y14
Y17
Y20
J2
I
I
I
O
O
O
O
I
I
I
I
O
O
O
O
I
I
I
I
O
O
O
O
O
O
O
O
O
O
O
O
I/O
I/O
I/O
I/O
I
D15
E2
RSER2
RSER3
Receive Serial Data for SCT2.
Receive Serial Data for SCT3.
Receive Serial Data for SCT4.
W17 RSER4
L2
B16
C1
Y18
K1
C15
D2
V16
G1
D12
D1
V12
H1
F17
G3
RSIG1
RSIG2
RSIG3
RSIG4
Receive Signaling Output for SCT1.
Receive Signaling Output for SCT2.
Receive Signaling Output for SCT3.
Receive Signaling Output for SCT4.
Receive Signaling Freeze Output for SCT1.
Receive Signaling Freeze Output for SCT2.
Receive Signaling Freeze Output for SCT3.
Receive Signaling Freeze Output for SCT4.
Receive Sync for SCT1.
Receive Sync for SCT2.
Receive Sync for SCT3.
Receive Sync for SCT4.
Receive System Clock for SCT1.
RSIGF1
RSIGF2
RSIGF3
RSIGF4
RSYNC1
RSYNC2
RSYNC3
RSYNC4
RSYSCLK1
RSYSCLK2
RSYSCLK3
I
I
Receive System Clock for SCT2.
Receive System Clock for SCT3.
W14 RSYSCLK4
I
Receive System Clock for SCT4.
Y10
Y13
Y16
Y19
P1
RTIP1
RTIP2
RTIP3
RTIP4
RVDD1
RVDD2
RVDD3
I
I
I
I
–
–
–
Receive Analog Tip Input for SCT1.
Receive Analog Tip Input for SCT2.
Receive Analog Tip Input for SCT3.
Receive Analog Tip Input for SCT4.
Receive Analog Positive Supply.
Receive Analog Positive Supply.
Receive Analog Positive Supply.
J17
E4
W18 RVDD4
R2 RVSS1
–
–
Receive Analog Positive Supply.
Receive Analog Signal Ground
December 29, 1998
8
DALLAS SEMICONDUCTOR
DS21Q352/DS21Q552/DS21Q354/DS21Q554 Preliminary Data Sheet
T2
RVSS1
RVSS2
RVSS2
RVSS3
RVSS3
RVSS4
–
–
–
–
–
–
–
O
O
O
O
O
O
O
O
I
Receive Analog Signal Ground
Receive Analog Signal Ground
Receive Analog Signal Ground
Receive Analog Signal Ground
Receive Analog Signal Ground
Receive Analog Signal Ground
Receive Analog Signal Ground
Transmit Channel Block for SCT1.
Transmit Channel Block for SCT2.
Transmit Channel Block for SCT3.
Transmit Channel Block for SCT4.
Transmit Channel Clock for SCT1.
Transmit Channel Clock for SCT2.
Transmit Channel Clock for SCT3.
Transmit Channel Clock for SCT4.
Transmit Clock for SCT1.
H19
J18
D4
D5
V20
W19 RVSS4
W1
F20
C11
U20
V10
A18
B8
TCHBLK1
TCHBLK2
TCHBLK3
TCHBLK4
TCHCLK1
TCHCLK2
TCHCLK3
TCHCLK4
TCLK1
L18
Y9
B19
B10
M19
V6
D19
C8
P20
W7
E18
A7
P19
U16
V3
E20
D6
T18
W5
E19
C6
TCLK2
TCLK3
TCLK4
TCLKI1
TCLKI2
TCLKI3
TCLKI4
TCLKO1
TCLKO2
TCLKO3
TCLKO4
TEST
TLCLK1
TLCLK2
TLCLK3
TLCLK4
TLINK1
I
I
I
I
I
I
I
O
O
O
O
I
O
O
O
O
I
Transmit Clock for SCT2.
Transmit Clock for SCT3.
Transmit Clock for SCT4.
Transmit Clock Input for the LIU on SCT1.
Transmit Clock Input for the LIU on SCT2.
Transmit Clock Input for the LIU on SCT3.
Transmit Clock Input for the LIU on SCT4.
Transmit Clock Output from the Framer on SCT1.
Transmit Clock Output from the Framer on SCT2.
Transmit Clock Output from the Framer on SCT3.
Transmit Clock Output from the Framer on SCT4.
Test (0 = normal operation / 1 = tri-state all outputs).
Transmit Link Clock for SCT1.
Transmit Link Clock for SCT2.
Transmit Link Clock for SCT3.
Transmit Link Clock for SCT4.
Transmit Link Data for SCT1.
Transmit Link Data for SCT2.
Transmit Link Data for SCT3.
TLINK2
TLINK3
I
I
T19
R1
F19
D8
R20
T3
B20
D9
N20
W3
C20
A8
R19
V7
C19
C9
N19
Y2
TLINK4
I
I
I
I
Transmit Link Data for SCT4.
TNEGI1
TNEGI2
TNEGI3
TNEGI4
TNEGO1
TNEGO2
TNEGO3
TNEGO4
TPOSI1
TPOSI2
TPOSI3
TPOSI4
TPOSO1
TPOSO2
TPOSO3
TPOSO4
TRING1
TRING2
TRING3
TRING4
TSER1
Transmit Negative Data Input for the LIU on SCT1.
Transmit Negative Data Input for the LIU on SCT2.
Transmit Negative Data Input for the LIU on SCT3.
Transmit Negative Data Input for the LIU on SCT4.
Transmit Negative Data Output from Framer on SCT1.
Transmit Negative Data Output from Framer on SCT2.
Transmit Negative Data Output from Framer on SCT3.
Transmit Negative Data Output from Framer on SCT4.
Transmit Positive Data Input for the LIU on SCT1.
Transmit Positive Data Input for the LIU on SCT2.
Transmit Positive Data Input for the LIU on SCT3.
Transmit Positive Data Input for the LIU on SCT4.
Transmit Positive Data Output from Framer on SCT1.
Transmit Positive Data Output from Framer on SCT2.
Transmit Positive Data Output from Framer on SCT3.
Transmit Positive Data Output from Framer on SCT4.
Transmit Analog Ring Output for SCT1.
Transmit Analog Ring Output for SCT2.
Transmit Analog Ring Output for SCT3.
Transmit Analog Ring Output for SCT4.
Transmit Serial Data for SCT1.
I
O
O
O
O
I
I
I
I
O
O
O
O
O
O
O
O
I
Y4
Y6
Y8
W9
December 29, 1998
9
DALLAS SEMICONDUCTOR
DS21Q352/DS21Q552/DS21Q354/DS21Q554 Preliminary Data Sheet
C17
C10
K20
TSER2
TSER3
TSER4
I
I
I
I
I
I
I
I
Transmit Serial Data for SCT2.
Transmit Serial Data for SCT3.
Transmit Serial Data for SCT4.
Transmit Signaling Input for SCT1.
Transmit Signaling Input for SCT2.
Transmit Signaling Input for SCT3.
Transmit Signaling Input for SCT4.
Transmit System Sync for SCT1.
Transmit System Sync for SCT2.
Transmit System Sync for SCT3.
Transmit System Sync for SCT4.
Transmit Sync for SCT1.
W10 TSIG1
C18
A10
L19
TSIG2
TSIG3
TSIG4
W12 TSSYNC1
B18
D10
K19
V1
D20
C7
TSSYNC2
TSSYNC3
TSSYNC4
TSYNC1
TSYNC2
TSYNC3
TSYNC4
I
I
I
I/O
I/O
I/O
I/O
I
Transmit Sync for SCT2.
Transmit Sync for SCT3.
Transmit Sync for SCT4.
R18
W11 TSYSCLK1
Transmit System Clock for SCT1.
Transmit System Clock for SCT2.
Transmit System Clock for SCT3.
Transmit System Clock for SCT4.
Transmit Analog Tip Output for SCT1.
Transmit Analog Tip Output for SCT2.
Transmit Analog Tip Output for SCT3.
Transmit Analog Tip Output for SCT4.
Transmit Analog Positive Supply.
Transmit Analog Positive Supply.
Transmit Analog Positive Supply.
Transmit Analog Positive Supply.
Transmit Analog Signal Ground.
Transmit Analog Signal Ground.
Transmit Analog Signal Ground.
Transmit Analog Signal Ground.
Write Input (Read/Write).
A19
A11
N18
Y1
Y3
Y5
TSYSCLK2
TSYSCLK3
TSYSCLK4
TTIP1
TTIP2
TTIP3
I
I
I
O
O
O
O
–
–
–
–
–
–
–
–
I
Y7
TTIP4
W2
G19
D11
U19
W4
G18
C5
TVDD1
TVDD2
TVDD3
TVDD4
TVSS1
TVSS2
TVSS3
TVSS4
WR* (R/W*)
U18
K3
December 29, 1998
10
DALLAS SEMICONDUCTOR
DS21Q352/DS21Q552/DS21Q354/DS21Q554 Preliminary Data Sheet
DS21Q352 / DS21Q552 / DS21Q354 / DS21Q554 PCB Land Pattern Figure 2
The diagram shown below is the lead pattern that will be placed on the target PCB. This is the same
pattern that would be seen as viewed through the MCM from the top.
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
rneg
rf
sync
3
rlink
3
rclk
dvss
3
co
3
tclko
3
tpos
dvdd
3
tsig
3
tsys
clk
3
rlclk
3
rlink
2
cs
2*
rclki
2
rpos
o
dvss
2
tch
clk
2
tsys
clk
2
dvss
2
A
B
C
D
E
F
i
3
i
3
i
3
2
rpos
o
3
rsig
3
rposi
3
dvdd
3
rclk
o
3
dvdd
3
cs
3*
dvdd
3
dvss
3
tch
clk
3
tclk
i
3
tneg
i
dvss
3
tclk
3
dvss
2
dvdd
2
rclk
2
rpos
i
2
rclk
o
2
rch
clk
2
rneg
o
2
rsigf
2
rsig
2
co
2
ts
sync
2
tsig
2
tclk
2
tneg
o
2
tpos
i
2
rneg
o
3
rsigf
3
dvss
3
tvss
3
tlink
3
tsync
3
tpos
o
3
tneg
o
3
tser
3
tch
blk
3
tvdd
3
dvdd
2
dvss
2
dvdd
2
tser
2
tpos
o
2
tclk
i
2
rsync
3
rlclk
3
rvss
3
rvss
3
tlclk
3
ci
3
ts
sync
3
rsync
2
rneg
i
2
rser
2
rm
sync
2
rf
sync
2
rlos
2
dvdd
2
tsync
2
3
rlos
3
rser
3
rclk
3
rvdd
3
tclk
o
2
ci
2
tlink
2
tlclk
2
rlclk
1
rm
sync
3
rch
clk
3
8m
clk
3
rsys
clk
2
tneg
i
2
tch
blk
2
rsync
1
rlink
1
rsys
clk
3
dvss
1
rch
blk
3
rch
blk
2
8m
clk
2
tvss
2
tvdd
2
dvdd
4
G
H
J
rsys
clk
1
rch
clk
1
rlos
1
A5
jtdo
2
rvss
2
dvss
4
rser
1
dvdd
1
dvss
1
rvdd
2
rvss
2
D1/
AD1
co
4
rsigf
1
liuc
wr*
rf
sync
1
rpos
o
cs
4*
rlclk
4
ts
sync
4
tsig
4
tser
4
K
L
rm
sync
1
rsig
1
rneg
o
1
A1
tch
clk
4
dvss
4
1
8m
clk
1
rch
blk
1
rclk
o
1
rclk
1
rclk
i
1
dvdd
1
dvdd
4
rclk
4
tclk
4
dvdd
4
M
N
P
R
T
jtdi
rd*
dvss
4
tsys
clk
4
dvdd
4
tpos
o
4
tclk
o
4
tpos
i
4
tlink
4
tneg
o
4
tclk
i
4
tneg
i
rvdd
1
bts
cs
1*
A7/
ALE
rneg
i
4
rclk
i
4
rclk
o
4
tneg
i
1
mclk
1
rvss
1
rneg
i
1
tneg
o
1
rpos
i
1
A3
tsync
4
4
ci
4
rvss
1
tlclk
4
int*
dvdd
1
A0
D7/
AD7
D5/
AD5
dvss
1
D3/
AD3
A6
A4
D4/
AD4
mux
D0/
AD0
rlink
4
dvss
4
rch
clk
4
rf
sync
4
rsys
clk
4
rring
2
rpos
o
4
rpos
i
4
test
rneg
o
4
tvss
4
tvdd
4
tch
blk
4
rvss
4
U
V
W
Y
tsync
1
A2
tlclk
1
D6/
AD6
dvdd
1
tclk
i
1
ci
1
tpos
o
1
tclk
o
1
co
1
tch
clk
1
tsig
1
rlos
4
rsync
4
8m
clk
4
rsigf
4
jtdo3
jtrst*
jtdo4
tch
blk
1
ttip
1
tvdd
1
tpos
i
1
ttip
2
tvss
1
tlink
1
dvss
1
tser
1
tsys
clk
1
rring
1
ts
sync
1
rch
blk
4
jtms
D2/
AD2
rm
sync
4
rtip
3
rser
4
rvdd
4
rvss
4
mclk
2
tring
1
tring
2
ttip
3
tring
3
ttip
4
tring
4
tclk
1
rtip
1
rtip
2
jtclk
rring
3
rsig
4
rtip
4
rring
4
December 29, 1998
11
DALLAS SEMICONDUCTOR
DS21Q352/DS21Q552/DS21Q354/DS21Q554 Preliminary Data Sheet
POWER SUPPLY DE-COUPLING
In a typical PCB layout for the DS21x5y, all of the VDD pins will connect to a common power plane and all
the VSS lines will connect to a common ground plane. There are three recommended methods for de-
coupling shown below in both schematic and pictorial form. As shown in the pictorials, the capacitors
should be symmetrically located about the device. The first shown in figure 3 uses standard capacitors,
two 33uf tantalums, two .33uf ceramics and two .01uf ceramics. The second method shown in figure 4
uses a single 68uf tantalum, two .33uf ceramics and two .01uf ceramics. The third method shown in figure
5 uses only four capacitors, two 1.5uf MLC and two .01uf ceramics. The 1.5uf is an MLC (Multi Layer
Ceramic) type. The MLC construction is a low inductance type, which allows a smaller value of
capacitance to be used. Since VDD and VSS signals will typically pass vertically to the power and ground
planes of a PCB, the de-coupling caps must be placed as close to the DS21Qx5y as possible and routed
vertically to power and ground planes.
De-coupling scheme using standard tantalum caps. Figure 3
VDD
VDD
33
.33
.01
33
DS21Qx5y
DS21Qx5y
.33
.01
33 .33 .01
33 .33 .01
De-coupling scheme using single 68uf cap. Figure 4
VDD
VDD
68
.33
.01
.33
DS21Qx5y
DS21Qx5y
.01
68 .33 .01
.33
.01
De-coupling scheme using MCL caps. Figure 5
VDD
VDD
1.5
.01
1.5
.01
DS21Qx5y
DS21Qx5y
1.5 .01
1.5 .01
All capacitor values in figures 3, 4 and 5 are in uf.
December 29, 1998
12
DALLAS SEMICONDUCTOR
DS21Q352/DS21Q552/DS21Q354/DS21Q554 Preliminary Data Sheet
DS21Q352 / DS21Q552 / DS21Q354 / DS21Q554 Mechanical Dimensions
December 29, 1998
13
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C o p y r i g h t 2 0 0 7 b y M a x i m I n t e g r a t e d P r o d u c t s , D a l l a s S e m i c o n d u c t o r • L e g a l N o t i c e s • P r i v a c y P o l i c y
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