DS21Q42T [DALLAS]
Enhanced QUAD T1 FRAMER; 增强型四T1成帧器
| 型号： | DS21Q42T |
| 厂家： | 
DALLAS SEMICONDUCTOR |
| 描述： | Enhanced QUAD T1 FRAMER |
| 文件： | 总119页 (文件大小：1304K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS21Q42
Enhanced QUAD T1 FRAMER
www.dalsemi.com
FEATURES
FUNCTIONAL DIAGRAM
ꢀ Four T1 DS1/ISDN–PRI/J1 framing
transceivers
Elastic
Store
Receive
Framer
ꢀ All four framers are fully independent
ꢀ Each of the four framers contain dual two–
Elastic
Store
Transmit
Formatter
ꢀ frame elastic store slip buffers that can connect
to asynchronous backplanes up to 8.192 MHz
FRAMER #0
FRAMER #1
FRAMER #2
FRAMER #3
ꢀ 8–bit parallel control port that can be used
directly on either multiplexed or non–
multiplexed buses (Intel or Motorola)
Control Port
ꢀ Programmable output clocks for Fractional T1
ꢀ Fully independent transmit and receive
functionality
ꢀ Integral HDLC controller with 64-byte buffers
ACTUAL SIZE
configurable for FDL or DS0 operation
ꢀ Generates and detects in–band loop codes from
1 to 8 bits in length including CSU loop codes
QUAD
T1
FRAMER
ꢀ Pin compatible with DS21Q44 E1 Enhanced
Quad E1 Framer
ꢀ 3.3V supply with 5V tolerant I/O; low power
CMOS
ORDERING INFORMATION
DS21Q42T (00 C to 700 C)
ꢀ Available in 128–pin TQFP package
ꢀ IEEE 1149.1 support
DS21Q42TN (-400 C to +850 C)
DESCRIPTION
The DS21Q42 is an enhanced version of the DS21Q41B Quad T1 Framer. The DS21Q42 contains four
framers that are configured and read through a common microprocessor compatible parallel port. Each
framer consists of a receive framer, receive elastic store, transmit formatter and transmit elastic store. All
four framers in the DS21Q42 are totally independent, they do not share a common framing synchronizer.
Also the transmit and receive sides of each framer are totally independent. The dual two-frame elastic
stores contained in each of the four framers can be independently enabled and disabled as required. The
device fully meets all of the latest T1 specifications including ANSI T1.403–1995, ANSI T1.231–1993,
AT&T TR 62411 (12–90), AT&T TR54016, and ITU G.704 and G.706.
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031500
DS21Q42
1. INTRODUCTION
The DS21Q42 is a superset version of the popular DS21Q41 Quad T1 framer offering the new features
listed below. All of the original features of the DS21Q41 have been retained and software created for the
original device is transferable to the DS21Q42.
New Features
•
Additional hardware signaling capability including:
– Receive signaling re-insertion to a backplane multiframe sync
– Availability of signaling in a separate PCM data stream
– Signaling freezing
– Interrupt generated on change of signaling data
Full HDLC controller with 64–byte buffers in both transmit and receive paths. Configurable for FDL
orDS0 access
•
•
•
•
•
•
•
•
•
•
Per–channel code insertion in both transmit and receive paths
Ability to monitor one DS0 channel in both the transmit and receive paths
RCL, RLOS, RRA, and RAIS alarms now interrupt on change of state
Detects AIS-CI
8.192 MHz clock synthesizer
Per–channel loopback
Ability to calculate and check CRC6 according to the Japanese standard
Ability to pass the F–Bit position through the elastic stores in the 2.048 MHz backplane mode
IEEE 1149.1 support
Features
•
•
•
•
Four T1 DS1/ISDN–PRI/J1 framing transceivers
All four framers are fully independent
Frames to D4, ESF, and SLC–96 R formats
Each of the four framers contain dual two–frame elastic store slip buffers that can connect to
asynchronous backplanes up to 8.192 MHz
•
8–bit parallel control port that can be used directly on either multiplexed or non–multiplexed buses
(Intel or Motorola)
•
•
•
•
•
•
•
•
•
•
Extracts and inserts robbed bit signaling
Detects and generates yellow (RAI) and blue (AIS) alarms
Programmable output clocks for Fractional T1
Fully independent transmit and receive functionality
Generates and detects in–band loop codes from 1 to 8 bits in length including CSU loop codes
Contains ANSI one’s density monitor and enforcer
Large path and line error counters including BPV, CV, CRC6, and framing bit errors
Pin compatible with DS21Q44 E1 Enhanced Quad E1 Framer
3.3V supply with 5V tolerant I/O; low power CMOS
Available in 128–pin TQFP package
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DS21Q42
Functional Description
The receive side framer locates D4 (SLC–96) or ESF multiframe boundaries as well as detects incoming
alarms including, carrier loss, loss of synchronization, blue (AIS) and yellow alarms. If needed, the
receive side elastic store can be enabled in order to absorb the phase and frequency differences between
the recovered T1 data stream and an asynchronous backplane clock which is provided at the RSYSCLK
input. The clock applied at the RSYSCLK input can be either a 2.048 MHz clock or a 1.544 MHz clock.
The RSYSCLK can be a burst clock with speeds up to 8.192 MHz.
The transmit side of the DS21Q42 is totally independent from the receive side in both the clock
requirements and characteristics. Data off of a backplane can be passed through a transmit side elastic
store if necessary. The transmit formatter will provide the necessary frame/multiframe data overhead for
T1 transmission.
Reader’s Note:
This data sheet assumes a particular nomenclature of the T1 operating environment. In each 125 us frame,
there are 24 eight–bit channels plus a framing bit. It is assumed that the framing bit is sent first followed
by channel 1. Each channel is made up of eight bits which are numbered 1 to 8. Bit number 1 is the MSB
and is transmitted first. Bit number 8 is the LSB and is transmitted last. Throughout this data sheet, the
following abbreviations will be used:
D4
Superframe (12 frames per multiframe) Multiframe Structure
Subscriber Loop Carrier – 96 Channels (SLC–96 is an AT&T registered trademark)
Extended Superframe (24 frames per multiframe) Multiframe Structure
Bipolar with 8 Zero Substitution
Cyclical Redundancy Check
Terminal Framing Pattern in D4
SLC–96
ESF
B8ZS
CRC
Ft
Fs
Signaling Framing Pattern in D4
FPS
Framing Pattern in ESF
MF
Multiframe
BOC
HDLC
FDL
Bit Oriented Code
High Level Data Link Control
Facility Data Link
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DS21Q42
DS21Q42 ENHANCED QUAD T1 FRAMER Figure 1-1
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DS21Q42
TABLE OF CONTENTS
1. INTRODUCTION .............................................................................................................................. 2
2. DS21Q42 PIN DESCRIPTION ......................................................................................................... 8
3. DS21Q42 PIN FUNCTION DESCRIPTION ................................................................................ 15
4. DS21Q42 REGISTER MAP............................................................................................................. 22
5. PARALLEL PORT........................................................................................................................... 26
6. CONTROL, ID AND TEST REGISTERS ..................................................................................... 26
7. STATUS AND INFORMATION REGISTERS............................................................................. 37
8. ERROR COUNT REGISTERS....................................................................................................... 45
9. DS0 MONITORING FUNCTION................................................................................................... 48
10. SIGNALING OPERATION ............................................................................................................ 50
10.1. PROCESSOR BASED SIGNALING ................................................................................... 50
10.2. HARDWARE BASED SIGNALING ................................................................................... 52
11. PER–CHANNEL CODE (IDLE) GENERATION AND LOOPBACK....................................... 53
11.1. TRANSMIT SIDE CODE GENERATION ............................................................................ 53
11.1.1. Simple Idle Code Insertion and Per–Channel Loopback................................................. 54
11.1.2. Per–Channel Code Insertion ........................................................................................... .55
11.2. RECEIVE SIDE CODE GENERATION ................................................................................ 55
11.2.1. Simple Code Insertion .................................................................................................... 55
11.2.2. Per–Channel Code Insertion ............................................................................................. 56
12. CLOCK BLOCKING REGISTERS.............................................................................................. 57
13. ELASTIC STORES OPERATION .............................................................................................. 58
13.1. RECEIVE SIDE ....................................................................................................................... 58
13.2. TRANSMIT SIDE ................................................................................................................... 58
13.3. MINIMUM DELAY SYNCHRONOUS RSYSCLK/TSYSCLK MODE .............................. 59
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DS21Q42
14. HDLC CONTROLLER................................................................................................................... 59
14.1. HDLC FOR DS0S ................................................................................................................... 59
15. FDL/FS EXTRACTION AND INSERTION.................................................................................. 60
15.1. HDLC AND BOC CONTROLLER FOR THE FDL .............................................................. 60
15.1.1. General Overvie ............................................................................................................ .60
15.1.2. Status Register for the HDLC ........................................................................................ 61
15.1.3. HDLC/BOC Register Description ................................................................................. 63
15.2. LEGACY FDL SUPPORT ...................................................................................................... 71
15.2.1. Ov_2.1.71...................................................................................................................... 71
15.2.2. Receive Section............................................................................................................. 71
15.2.3. Transmit Section ........................................................................................................... 72
15.2.4. D4/SLC–96 OPERATION ............................................................................................ 73
16. PROGRAMMABLE IN–BAND CODE GENERATION AND DETECTION.......................... 73
17. TRANSMIT TRANSPARENCY.................................................................................................... 76
18. INTERLEAVED PCM BUS OPERATION ................................................................................... 76
19. JTAG-BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT .......................... 79
19.1. DESCRIPTION ....................................................................................................................... 79
19.2. TAP CONTROLLER STATE MACHINE.............................................................................. 80
19.3. INSTRUCTION REGISTER AND INSTRUCTIONS ........................................................... 82
19.4. TEST REGISTERS ................................................................................................................. 84
20. TIMING DIAGRAMS...................................................................................................................... 89
21. OPERATING PARAMETERS .................................................................................................... 104
22. 128-PIN TQFP PACKAGE SPECIFICATIONS ........................................................................ 119
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DS21Q42
DOCUMENT REVISION HISTORY
Revision
Notes
12-22-98 Initial Release
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DS21Q42
2. DS21Q42 PIN DESCRIPTION
Pin Description Sorted by Pin Number Table 2-1
PIN
1
2
3
4
5
6
7
8
SYMBOL
TCHBLK0
TPOS0
TNEG0
RLINK0
RLCLK0
RCLK0
RNEG0
RPOS0
TYPE DESCRIPTION
O
O
O
O
O
I
Transmit Channel Block from Framer 0
Transmit Bipolar Data from Framer 0
Transmit Bipolar Data from Framer 0
Receive Link Data from Framer 0
Receive Link Clock from Framer 0
Receive Clock for Framer 0
I
I
Receive Bipolar Data for Framer 0
Receive Bipolar Data for Framer 0
9
RSIG0
O
[O]
O
I
I/O
O
-
Receive Signaling Output from Framer 0 [Receive Channel
Clock from Framer 0]
Receive Channel Block from Framer 0
Receive System Clock for Elastic Store in Framer 0
Receive Sync for Framer 0
Receive Serial Data from Framer 0
Signal Ground
Positive Supply Voltage
[RCHCLK0]
RCHBLK0
RSYSCLK0
RSYNC0
RSER0
10
11
12
13
14
15
16
VSS
VDD
-
-
SPARE1
[RMSYNC0]
RFSYNC0
JTRST*
[RLOS/LOTC0]
TCLK0
TLCLK0
TSYNC0
TLINK0
A0
RESERVED - must be left unconnected for normal operation
[Receive Multiframe Sync from Framer 0]
Receive Frame Sync from Framer 0
[O]
O
17
18
I [O] JTAG Reset [Receive Loss of Sync/Loss of Transmit clock
from Framer 0]
I
O
I/O
I
I
I
I
I
19
20
21
22
23
24
25
26
27
28
29
Transmit Clock for Framer 0
Transmit Link Clock from Framer 0
Transmit Sync for Framer 0
Transmit Link Data for Framer 0
Address Bus Bit 0; LSB
Address Bus Bit 1
Address Bus Bit 2
Address Bus Bit 3
Address Bus Bit 4
A1
A2
A3
A4
I
I
I
A5
Address Bus Bit 5
Address Bus Bit 6; MSB or Address Latch Enable (Address
Strobe)
A6/ALE (AS)
30
31
32
33
34
INT*
TSYSCLK1
TSER1
TSSYNC1
TSIG1
[TCHCLK1]
TCHBLK1
TPOS1
O
I
I
Receive Alarm Interrupt for all Four Framers
Transmit System Clock for Elastic Store in Framer 1
Transmit Serial Data for Framer 1
Transmit Sync for Elastic Store in Framer 1
I
I [O] Transmit Signaling Input for Framer 1
[Transmit Channel Clock from Framer 1]
O
O
O
O
35
36
37
38
Transmit Channel Block from Framer 1
Transmit Bipolar Data from Framer 1
Transmit Bipolar Data from Framer 1
Receive Link Data from Framer 1
TNEG1
RLINK1
8 of 119
DS21Q42
PIN
39
40
SYMBOL
RLCLK1
RCLK1
TYPE DESCRIPTION
O
I
Receive Link Clock from Framer 1
Receive Clock for Framer 1
41
42
43
RNEG1
RPOS1
RSIG1
I
I
Receive Bipolar Data for Framer 1
Receive Bipolar Data for Framer 1
Receive Signaling output from Framer 1
[Receive Channel Clock from Framer 1]
Receive Channel Block from Framer 1
Receive System Clock for Elastic Store in Framer 1
Address Bus Bit 7
Framer Mode Select
Receive Sync for Framer 1
Receive Serial Data from Framer 1
JTAG Test Mode Select
O
[O]
O
I
I
I
I/O
O
I
[RCHCLK1]
RCHBLK1
RSYSCLK1
A7
FMS
RSYNC1
RSER1
44
45
46
47
48
49
50
JTMS
[RMSYNC1]
RFSYNC1
JTCLK
[O]
O
I
[Receive Multiframe Sync from Framer 1]
Receive Frame Sync from Framer 1
JTAG Test Clock
51
52
[RLOS/LOTC1]
[O]
[Receive Loss of Sync/Loss of Transmit clock from Framer 1]
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
TCLK1
I
Transmit Clock for Framer 1
Transmit Link Clock from Framer 1
Transmit Sync for Framer 1
Transmit Link Data for Framer 1
3-state Control for all Output and I/O Pins
Framer Select 0 for Parallel Control Port
Framer Select 1 for Parallel Control Port
Chip Select
TLCLK1
TSYNC1
TLINK1
TEST
O
I/O
I
I
I
I
I
I
I
I
I
I
I
I
I
[O]
O
O
O
O
O
I
FS0
FS1
CS*
BTS
Bus Type Select for Parallel Control Port
Read Input (Data Strobe)
Write Input (Read/Write)
RD*/(DS*)
WR*/(R/W*)
MUX
TSYSCLK2
TSER2
TSSYNC2
TSIG2
[TCHCLK2]
TCHBLK2
TPOS2
Non-Multiplexed or Multiplexed Bus Select
Transmit System Clock for Elastic Store in Framer 2
Transmit Serial Data for Framer 2
Transmit Sync for Elastic Store in Framer 2
Transmit Signaling Input for Framer 2
[Transmit Channel Clock from Framer 2]
Transmit Channel Block from Framer 2
Transmit Bipolar Data from Framer 2
Transmit Bipolar Data from Framer 2
Receive Link Data from Framer 2
Receive Link Clock from Framer 2
Receive Clock for Framer 2
Receive Bipolar Data for Framer 2
Receive Bipolar Data for Framer 2
Receive Signaling Output from Framer 2
[Receive Channel Clock from Framer 2]
Signal Ground
69
70
71
72
73
74
75
76
77
TNEG2
RLINK2
RLCLK2
RCLK2
RNEG2
RPOS2
RSIG2
[RCHCLK2]
VSS
VDD
RCHBLK2
I
I
O
[O]
-
-
O
78
79
80
Positive Supply Voltage
Receive Channel Block from Framer 2
9 of 119
DS21Q42
PIN
81
82
83
84
SYMBOL
RSYSCLK2
RSYNC2
RSER2
TYPE DESCRIPTION
I
I/O
O
I
Receive System Clock for Elastic Store in Framer 2
Receive Sync for Framer 2
Receive Serial Data from Framer 2
JTAG Test Data Input
JTDI
[RMSYNC2]
RFSYNC2
JTDO
[RLOS/LOTC2]
TCLK2
TLCLK2
TSYNC2
TLINK2
TSYSCLK3
TSER3
TSSYNC3
TSIG3
[TCHCLK3]
TCHBLK3
TPOS3
[O]
O
O
[O]
I
O
I/O
I
I
I
I
I
[O]
O
O
O
O
O
I
[Receive Multiframe Sync from Framer 2]
Receive Frame Sync from Framer 2
JTAG Test Data Output
[Receive Loss of Sync/Loss of Transmit clock from Framer 2]
Transmit Clock for Framer 2
85
86
87
88
89
90
91
92
93
94
Transmit Link Clock from Framer 2
Transmit Sync for Framer 2
Transmit Link Data for Framer 2
Transmit System Clock for Elastic Store in Framer 3
Transmit Serial Data for Framer 3
Transmit Sync for Elastic Store in Framer 3
Transmit Signaling Input for Framer 3
[Transmit Channel Clock from Framer 3]
Transmit Channel Block from Framer 3
Transmit Bipolar Data from Framer 3
Transmit Bipolar Data from Framer 3
Receive Link Data from Framer 3
Receive Link Clock from Framer 3
Receive Clock for Framer 3
Receive Bipolar Data for Framer 3
Receive Bipolar Data for Framer 3
Receive Signaling Output from Framer 3
[Receive Channel Clock from Framer 3]
Receive Channel Block from Framer 3
Receive System Clock for Elastic Store in Framer 3
Receive Sync for Framer 3
95
96
97
98
99
100
101
102
103
TNEG3
RLINK3
RLCLK3
RCLK3
RNEG3
RPOS3
I
I
RSIG3
O
[O]
O
I
I/O
O
O
[O]
O
-
[RCHCLK3]
RCHBLK3
RSYSCLK3
RSYNC3
RSER3
104
105
106
107
108
Receive Serial Data from Framer 3
8 MHz Clock
[Receive Multiframe Sync from Framer 3]
Receive Frame Sync from Framer 3
Signal Ground
8MCLK
[RMSYNC3]
RFSYNC3
VSS
109
110
111
112
VDD
CLKSI
-
I
Positive Supply Voltage
8MCLK Clock Reference Input
[RLOS/LOTC3]
TCLK3
[O]
I
O
I/O
I
I/O
I/O
I/O
I/O
I/O
[Receive Loss of Sync/Loss of Transmit clock from Framer 3]
Transmit Clock for Framer 3
Transmit Link Clock from Framer 3
Transmit Sync for Framer 3
Transmit Link Data for Framer 3
Data Bus Bit or Address/Data Bit 0; LSB
Data Bus Bit or Address/Data Bit 1
Data Bus Bit or Address/Data Bit 2
Data Bus Bit or Address/Data Bit 3
Data Bus Bit or Address/Data Bit 4
113
114
115
116
117
118
119
120
121
TLCLK3
TSYNC3
TLINK3
D0 or AD0
D1 or AD1
D2 or AD2
D3 or AD3
D4 or AD4
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DS21Q42
PIN
122
123
124
125
126
127
128
SYMBOL
D5 or AD5
D6 or AD6
D7 or AD7
TSYSCLK0
TSER0
TSSYNC0
TSIG0
[TCHCLK0]
TYPE DESCRIPTION
I/O
I/O
I/O
I
Data Bus Bit or Address/Data Bit 5
Data Bus Bit or Address/Data Bit 6
Data Bus Bit or Address/Data Bit 7; MSB
Transmit System Clock for Elastic Store in Framer 0
Transmit Serial Data for Framer 0
I
I
I
Transmit Sync for Elastic Store in Framer 0
Transmit Signaling Input for Framer 0
[Transmit Channel Clock from Framer 0]
[O]
Note:
1. Brackets [ ] indicate pin function when the DS21Q42 is configured for emulation of the DS21Q41B,
(FMS = 1).
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DS21Q42
Pin Description Sorted by Pin Function, FMS = 0 Table 2-2
PIN
108
23
SYMBOL
8MCLK
TYPE DESCRIPTION
O
I
8 MHz Clock
Address Bus Bit 0; LSB
A0
24
A1
I
Address Bus Bit 1
25
A2
I
Address Bus Bit 2
26
27
A3
A4
I
I
Address Bus Bit 3
Address Bus Bit 4
28
A5
I
Address Bus Bit 5
29
A6/ALE (AS)
I
Address Bus Bit 6; MSB or Address Latch Enable
(Address Strobe)
46
61
112
60
A7
BTS
CLKSI
CS*
I
I
I
Address Bus Bit 7
Bus Type Select for Parallel Control Port
8MCLK Clock Reference Input
Chip Select
I
117
118
119
120
121
122
123
124
47
D0 or AD0
D1 or AD1
D2 or AD2
D3 or AD3
D4 or AD4
D5 or AD5
D6 or AD6
D7 or AD7
FMS
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
Data Bus Bit or Address/Data Bit 0; LSB
Data Bus Bit or Address/Data Bit 1
Data Bus Bit or Address/Data Bit 2
Data Bus Bit or Address/Data Bit 3
Data Bus Bit or Address/Data Bit 4
Data Bus Bit or Address/Data Bit 5
Data Bus Bit or Address/Data Bit 6
Data Bus Bit or Address/Data Bit 7; MSB
Framer Mode Select
58
59
30
52
FS0
FS1
INT*
JTCLK
I
I
O
I
Framer Select 0 for Parallel Control Port
Framer Select 1 for Parallel Control Port
Receive Alarm Interrupt for all Four Framers
JTAG Test Clock
84
JTDI
I
JTAG Test Data Input
86
50
JTDO
JTMS
O
I
JTAG Test Data Output
JTAG Test Mode Select
18
64
JTRST*
MUX
I
I
JTAG Reset
Non-Multiplexed or Multiplexed Bus Select
Receive Channel Block from Framer 0
Receive Channel Block from Framer 1
Receive Channel Block from Framer 2
Receive Channel Block from Framer 3
Receive Clock for Framer 0
Receive Clock for Framer 1
Receive Clock for Framer 2
Receive Clock for Framer 3
Read Input (Data Strobe)
Receive Frame Sync from Framer 0
Receive Frame Sync from Framer 1
Receive Frame Sync from Framer 2
Receive Frame Sync from Framer 3
Receive Link Clock from Framer 0
10
44
80
104
6
40
74
100
62
17
RCHBLK0
RCHBLK1
RCHBLK2
RCHBLK3
RCLK0
RCLK1
RCLK2
RCLK3
RD*/(DS*)
RFSYNC0
RFSYNC1
RFSYNC2
RFSYNC3
RLCLK0
O
O
O
O
I
I
I
I
I
O
O
O
O
O
51
85
109
5
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DS21Q42
PIN
39
73
99
4
38
72
98
7
41
75
101
8
42
76
102
13
49
83
107
9
43
77
103
12
48
82
106
11
45
81
105
16
1
35
69
95
19
53
87
113
57
20
54
88
114
22
56
SYMBOL
RLCLK1
RLCLK2
RLCLK3
RLINK0
RLINK1
RLINK2
RLINK3
RNEG0
RNEG1
RNEG2
RNEG3
RPOS0
RPOS1
RPOS2
RPOS3
RSER0
RSER1
RSER2
RSER3
RSIG0
TYPE DESCRIPTION
O
O
O
O
O
O
O
I
I
I
I
I
Receive Link Clock from Framer 1
Receive Link Clock from Framer 2
Receive Link Clock from Framer 3
Receive Link Data from Framer 0
Receive Link Data from Framer 1
Receive Link Data from Framer 2
Receive Link Data from Framer 3
Receive Bipolar Data for Framer 0
Receive Bipolar Data for Framer 1
Receive Bipolar Data for Framer 2
Receive Bipolar Data for Framer 3
Receive Bipolar Data for Framer 0
Receive Bipolar Data for Framer 1
Receive Bipolar Data for Framer 2
Receive Bipolar Data for Framer 3
Receive Serial Data from Framer 0
Receive Serial Data from Framer 1
Receive Serial Data from Framer 2
Receive Serial Data from Framer 3
Receive Signaling Output from Framer 0
Receive Signaling output from Framer 1
Receive Signaling Output from Framer 2
Receive Signaling Output from Framer 3
Receive Sync for Framer 0
I
I
I
O
O
O
O
O
O
O
O
I/O
I/O
I/O
I/O
I
RSIG1
RSIG2
RSIG3
RSYNC0
RSYNC1
RSYNC2
RSYNC3
RSYSCLK0
RSYSCLK1
RSYSCLK2
RSYSCLK3
SPARE1
TCHBLK0
TCHBLK1
TCHBLK2
TCHBLK3
TCLK0
TCLK1
TCLK2
TCLK3
TEST
TLCLK0
TLCLK1
TLCLK2
TLCLK3
TLINK0
TLINK1
Receive Sync for Framer 1
Receive Sync for Framer 2
Receive Sync for Framer 3
Receive System Clock for Elastic Store in Framer 0
Receive System Clock for Elastic Store in Framer 1
Receive System Clock for Elastic Store in Framer 2
Receive System Clock for Elastic Store in Framer 3
I
I
I
-
RESERVED - must be left unconnected for normal operation
Transmit Channel Block from Framer 0
Transmit Channel Block from Framer 1
Transmit Channel Block from Framer 2
Transmit Channel Block from Framer 3
Transmit Clock for Framer 0
O
O
O
O
I
I
Transmit Clock for Framer 1
I
Transmit Clock for Framer 2
I
Transmit Clock for Framer 3
I
3-state Control for all Output and I/O Pins
Transmit Link Clock from Framer 0
Transmit Link Clock from Framer 1
Transmit Link Clock from Framer 2
Transmit Link Clock from Framer 3
Transmit Link Data for Framer 0
O
O
O
O
I
I
Transmit Link Data for Framer 1
13 of 119
DS21Q42
PIN
90
116
3
37
71
97
2
SYMBOL
TLINK2
TLINK3
TNEG0
TNEG1
TNEG2
TNEG3
TPOS0
TPOS1
TPOS2
TPOS3
TSER0
TSER1
TSER2
TSER3
TSIG0
TSIG1
TSIG2
TSIG3
TSSYNC0
TSSYNC1
TSSYNC2
TSSYNC3
TSYNC0
TSYNC1
TSYNC2
TSYNC3
TSYSCLK0
TSYSCLK1
TSYSCLK2
TSYSCLK3
VDD
TYPE DESCRIPTION
I
I
Transmit Link Data for Framer 2
Transmit Link Data for Framer 3
Transmit Bipolar Data from Framer 0
Transmit Bipolar Data from Framer 1
Transmit Bipolar Data from Framer 2
Transmit Bipolar Data from Framer 3
Transmit Bipolar Data from Framer 0
Transmit Bipolar Data from Framer 1
Transmit Bipolar Data from Framer 2
Transmit Bipolar Data from Framer 3
Transmit Serial Data for Framer 0
Transmit Serial Data for Framer 1
Transmit Serial Data for Framer 2
Transmit Serial Data for Framer 3
Transmit Signaling Input for Framer 0
Transmit Signaling Input for Framer 1
Transmit Signaling Input for Framer 2
Transmit Signaling Input for Framer 3
Transmit Sync for Elastic Store in Framer 0
Transmit Sync for Elastic Store in Framer 1
Transmit Sync for Elastic Store in Framer 2
Transmit Sync for Elastic Store in Framer 3
Transmit Sync for Framer 0
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I/O
I/O
I/O
I/O
I
I
I
I
-
36
70
96
126
32
66
92
128
34
68
94
127
33
67
93
21
55
89
115
125
31
65
91
15
79
111
14
78
110
63
Transmit Sync for Framer 1
Transmit Sync for Framer 2
Transmit Sync for Framer 3
Transmit System Clock for Elastic Store in Framer 0
Transmit System Clock for Elastic Store in Framer 1
Transmit System Clock for Elastic Store in Framer 2
Transmit System Clock for Elastic Store in Framer 3
Positive Supply Voltage
VDD
VDD
VSS
VSS
-
Positive Supply Voltage
-
Positive Supply Voltage
-
Signal Ground
-
Signal Ground
VSS
WR*/(R/W*)
-
Signal Ground
I
Write Input (Read/Write)
14 of 119
DS21Q42
3. DS21Q42 PIN FUNCTION DESCRIPTION
TRANSMIT SIDE PINS
Signal Name: TCLK
Signal Description: Transmit Clock
Signal Type: Input
A 1.544 MHz primary clock. Used to clock data through the transmit side formatter.
Signal Name: TSER
Signal Description: Transmit Serial Data
Signal Type: Input
Transmit NRZ serial data. Sampled on the falling edge of TCLK when the transmit side elastic store is
disabled. Sampled on the falling edge of TSYSCLK when the transmit side elastic store is enabled.
Signal Name: TCHCLK
Signal Description: Transmit Channel Clock
Signal Type: Output
A 192 KHz clock which pulses high during the LSB of each channel. Synchronous with TCLK when the
transmit side elastic store is disabled. Synchronous with TSYSCLK when the transmit side elastic store is
enabled. Useful for parallel to serial conversion of channel data. This function is available when FMS = 1
(DS21Q41 emulation).
Signal Name: TCHBLK
Signal Description: Transmit Channel Block
Signal Type: Output
A user programmable output that can be forced high or low during any of the 24 T1 channels.
Synchronous with TCLK when the transmit side elastic store is disabled. Synchronous with TSYSCLK
when the transmit side elastic store is enabled. Useful for blocking clocks to a serial UART or LAPD
controller in applications where not all T1 channels are used such as Fractional T1, 384 Kbps service, 768
Kbps or ISDN–PRI . Also useful for locating individual channels in drop–and–insert applications, for
external per–channel loopback, and for per–channel conditioning. See Section 12 for details.
Signal Name: TSYSCLK
Signal Description: Transmit System Clock
Signal Type: Input
1.544 MHz or 2.048 MHz clock. Only used when the transmit side elastic store function is enabled.
Should be tied low in applications that do not use the transmit side elastic store. Can be burst at rates up
to 8.192 MHz.
Signal Name: TLCLK
Signal Description: Transmit Link Clock
Signal Type: Output
4 KHz or 2 KHz (ZBTSI) demand clock for the TLINK input. See Section 15 for details.
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DS21Q42
Signal Name: TLINK
Signal Description: Transmit Link Data
Signal Type: Input
If enabled via TCR1.2, this pin will be sampled on the falling edge of TCLK for data insertion into either
the FDL stream (ESF) or the Fs–bit position (D4) or the Z–bit position (ZBTSI). See Section 15 for
details.
Signal Name: TSYNC
Signal Description: Transmit Sync
Signal Type: Input /Output
A pulse at this pin will establish either frame or multiframe boundaries for the transmit side. Via TCR2.2,
the DS21Q42 can be programmed to output either a frame or multiframe pulse at this pin. If this pin is set
to output pulses at frame boundaries, it can also be set via TCR2.4 to output double–wide pulses at
signaling frames. See Section 20 for details.
Signal Name: TSSYNC
Signal Description: Transmit System Sync
Signal Type: Input
Only used when the transmit side elastic store is enabled. A pulse at this pin will establish either frame or
multiframe boundaries for the transmit side. Should be tied low in applications that do not use the
transmit side elastic store.
Signal Name: TSIG
Signal Description: Transmit Signaling Input
Signal Type: Input
When enabled, this input will sample signaling bits for insertion into outgoing PCM T1 data stream.
Sampled on the falling edge of TCLK when the transmit side elastic store is disabled. Sampled on the
falling edge of TSYSCLK when the transmit side elastic store is enabled. This function is available when
FMS = 0.
Signal Name: TPOS
Signal Description: Transmit Positive Data Output
Signal Type: Output
Updated on the rising edge of TCLK with the bipolar data out of the transmit side formatter. Can be
programmed to source NRZ data via the Output Data Format (CCR1.6) control bit.
Signal Name: TNEG
Signal Description: Transmit Negative Data Output
Signal Type: Output
Updated on the rising edge of TCLK with the bipolar data out of the transmit side formatter.
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DS21Q42
RECEIVE SIDE PINS
Signal Name: RLINK
Signal Description: Receive Link Data
Signal Type: Output
Updated with either FDL data (ESF) or Fs bits (D4) or Z bits (ZBTSI) one RCLK before the start of a
frame. See Section 20 for details.
Signal Name: RLCLK
Signal Description: Receive Link Clock
Signal Type: Output
A 4 KHz or 2 KHz (ZBTSI) clock for the RLINK output.
Signal Name: RCHCLK
Signal Description: Receive Channel Clock
Signal Type: Output
A 192 KHz clock which pulses high during the LSB of each channel. Synchronous with RCLK when the
receive side elastic store is disabled. Synchronous with RSYSCLK when the receive side elastic store is
enabled. Useful for parallel to serial conversion of channel data. This function is available when FMS = 1
(DS21Q41 emulation).
Signal Name: RCHBLK
Signal Description: Receive Channel Block
Signal Type: Output
A user programmable output that can be forced high or low during any of the 24 T1 channels.
Synchronous with RCLK when the receive side elastic store is disabled. Synchronous with RSYSCLK
when the receive side elastic store is enabled. Useful for blocking clocks to a serial UART or LAPD
controller in applications where not all T1 channels are used such as Fractional T1, 384K bps service,
768K bps, or ISDN–PRI. Also useful for locating individual channels in drop–and–insert applications, for
external per–channel loopback, and for per–channel conditioning. See Section 12 for details.
Signal Name: RSER
Signal Description: Receive Serial Data
Signal Type: Output
Received NRZ serial data. Updated on rising edges of RCLK when the receive side elastic store is
disabled. Updated on the rising edges of RSYSCLK when the receive side elastic store is enabled.
Signal Name: RSYNC
Signal Description: Receive Sync
Signal Type: Input /Output
An extracted pulse, one RCLK wide, is output at this pin which identifies either frame (RCR2.4 = 0) or
multiframe (RCR2.4 = 1) boundaries. If set to output frame boundaries then via RCR2.5, RSYNC can
also be set to output double–wide pulses on signaling frames. If the receive side elastic store is enabled
via CCR1.2, then this pin can be enabled to be an input via RCR2.3 at which a frame or multiframe
boundary pulse is applied. See Section 20 for details.
Signal Name: RFSYNC
Signal Description: Receive Frame Sync
Signal Type: Output
An extracted 8 KHz pulse, one RCLK wide, is output at this pin which identifies frame boundaries.
17 of 119
DS21Q42
Signal Name: RMSYNC
Signal Description: Receive Multiframe Sync
Signal Type: Output
An extracted pulse, one RSYSCLK wide, is output at this pin which identifies multiframe boundaries. If
the receive side elastic store is disabled, then this output will output multiframe boundaries associated
with RCLK. This function is available when FMS = 1 (DS21Q41 emulation).
Signal Name: RSYSCLK
Signal Description: Receive System Clock
Signal Type: Input
1.544 MHz or 2.048 MHz clock. Only used when the elastic store function is enabled. Should be tied low
in applications that do not use the elastic store. Can be burst at rates up to 8.192 MHz.
Signal Name: RSIG
Signal Description: Receive Signaling Output
Signal Type: Output
Outputs signaling bits in a PCM format. Updated on rising edges of RCLK when the receive side elastic
store is disabled. Updated on the rising edges of RSYSCLK when the receive side elastic store is enabled.
This function is available when FMS = 0.
Signal Name: RLOS/LOTC
Signal Description: Receive Loss of Sync / Loss of Transmit Clock
Signal Type: Output
A dual function output that is controlled by the CCR3.5 control bit. This pin can be programmed to either
toggle high when the synchronizer is searching for the frame and multiframe or to toggle high if the
TCLK pin has not been toggled for 5 usec. This function is available when FMS = 1 (DS21Q41
emulation).
Signal Name: CLKSI
Signal Description: 8 MHz Clock Reference
Signal Type: Input
A 1.544 MHz reference clock used in the generation of 8MCLK. This function is available when
FMS = 0.
Signal Name: 8MCLK
Signal Description: 8 MHz Clock
Signal Type: Output
A 8.192 MHz output clock that is referenced to the clock that is input at the CLKSI pin. This function is
available when FMS = 0.
18 of 119
DS21Q42
Signal Name: RPOS
Signal Description: Receive Positive Data Input
Signal Type: Input
Sampled on the falling edge of RCLK for data to be clocked through the receive side framer. RPOS and
RNEG can be tied together for an NRZ interface. Connecting RPOS to RNEG disables the bipolar
violation monitoring circuitry.
Signal Name: RNEG
Signal Description: Receive Negative Data Input
Signal Type: Input
Sampled on the falling edge of RCLK for data to be clocked through the receive side framer. RPOS and
RNEG can be tied together for an NRZ interface. Connecting RPOS to RNEG disables the bipolar
violation monitoring circuitry.
Signal Name: RCLK
Signal Description: Receive Clock Input
Signal Type: Input
Clock used to clock data through the receive side framer.
PARALLEL CONTROL PORT PINS
Signal Name: INT*
Signal Description: Interrupt
Signal Type: Output
Flags host controller during conditions and change of conditions defined in the Status Registers 1 and 2
and the HDLC Status Register. Active low, open drain output.
Signal Name: FMS
Signal Description: Framer Mode Select
Signal Type: Input
Set low to select DS21Q42 feature set. Set high to select DS21Q41 emulation.
Signal Name: MUX
Signal Description: Bus Operation
Signal Type: Input
Set low to select non–multiplexed bus operation. Set high to select multiplexed bus operation.
Signal Name: D0 to D7/ AD0 to AD7
Signal Description: Data Bus or Address/Data Bus
Signal Type: Input /Output
In non–multiplexed bus operation (MUX = 0), serves as the data bus. In multiplexed bus operation (MUX
= 1), serves as a 8–bit multiplexed address / data bus.
Signal Name: A0 to A5, A7
Signal Description: Address Bus
Signal Type: Input
In non–multiplexed bus operation (MUX = 0), serves as the address bus. In multiplexed bus operation
(MUX = 1), these pins are not used and should be tied low.
19 of 119
DS21Q42
Signal Name: ALE(AS)/A6
Signal Description: A6 or Address Latch Enable (Address Strobe)
Signal Type: Input
In non–multiplexed bus operation (MUX = 0), serves as address bit 6. In multiplexed bus operation
(MUX = 1), serves to demultiplex the bus on a positive–going edge.
Signal Name: BTS
Signal Description: Bus Type Select
Signal Type: Input
Strap high to select Motorola bus timing; strap low to select Intel bus timing. This pin controls the
function of the RD*(DS*), ALE(AS), and WR*(R/W*) pins. If BTS = 1, then these pins assume the
function listed in parenthesis ().
Signal Name: RD*(DS*)
Signal Description: Read Input (Data Strobe)
Signal Type: Input
RD* and DS* are active low signals. Note: DS is active high when MUX=1. Refer to bus timing
diagrams in section 21 .
Signal Name: FS0 AND FS1
Signal Description: Framer Selects
Signal Type: Input
Selects which of the four framers to be accessed.
Signal Name: CS*
Signal Description: Chip Select
Signal Type: Input
Must be low to read or write to the device. CS* is an active low signal.
Signal Name: WR*( R/W*)
Signal Description: Write Input(Read/Write)
Signal Type: Input
WR* is an active low signal.
TEST ACCESS PORT PINS
Signal Name: TEST
Signal Description: 3–State Control
Signal Type: Input
Set high to 3–state all output and I/O pins (including the parallel control port) when FMS = 1 or when
FMS = 0 and JTRST* is tied low. Set low for normal operation. Ignored when FMS = 0 and JTRST* = 1.
Useful in board level testing.
20 of 119
DS21Q42
Signal Name: JTRST*
Signal Description: IEEE 1149.1 Test Reset
Signal Type: Input
This signal is used to asynchronously reset the test access port controller. At power up, JTRST* must be
set low and then high. This action will set the device into the DEVICE ID mode allowing normal device
operation. If boundary scan is not used and FMS = 0, this pin should be held low. This function is
available when FMS = 0. When FMS=1, this pin is held LOW internally. This pin is pulled up internally
by a 10K ohm resistor.
Signal Name: JTMS
Signal Description: IEEE 1149.1 Test Mode Select
Signal Type: Input
This pin is sampled on the rising edge of JTCLK and is used to place the test port into the various defined
IEEE 1149.1 states. This pin is pulled up internally by a 10K ohm resistor. If not used, this pin should be
left unconnected. This function is available when FMS = 0.
Signal Name: JTCLK
Signal Description: IEEE 1149.1 Test Clock Signal
Signal Type: Input
This signal is used to shift data into JTDI pin on the rising edge and out of JTDO pin on the falling edge.
If not used, this pin should be connected to VSS. This function is available when FMS = 0.
Signal Name: JTDI
Signal Description: IEEE 1149.1 Test Data Input
Signal Type: Input
Test instructions and data are clocked into this pin on the rising edge of JTCLK. This pin is pulled up
internally by a 10K ohm resistor. If not used, this pin should be left unconnected. This function is
available when FMS = 0.
Signal Name: JTDO
Signal Description: IEEE 1149.1 Test Data Output
Signal Type: Output
Test instructions and data are clocked out of this pin on the falling edge of JTCLK. If not used, this pin
should be left unconnected. This function is available when FMS = 0.
SUPPLY PINS
Signal Name: VDD
Signal Description: Positive Supply
Signal Type: Supply
2.97 to 3.63 volts.
Signal Name: VSS
Signal Description: Signal Ground
Signal Type: Supply
0.0 volts.
21 of 119
DS21Q42
4. DS21Q42 REGISTER MAP
Register Map Sorted by Address Table 4-1
REGISTER
ADDRESS
00
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
W
–
R/W
–
–
–
REGISTER NAME
ABBREVIATION
HCR
HDLC Control
HDLC Status
01
02
03
04
05
06
07
08
HSR
HIMR
RHIR
RBOC
RHFR
THIR
TBOC
THFR
HDLC Interrupt Mask
Receive HDLC Information
Receive Bit Oriented Code
Receive HDLC FIFO
Transmit HDLC Information
Transmit Bit Oriented Code
Transmit HDLC FIFO
Not used
09
(set to 00H)
CCR7
0A
0B
0C
0D
0E
0F
10
11
12
13
14
Common Control 7
Not used
Not used
Not used
Not used
(set to 00H)
(set to 00H)
(set to 00H)
(set to 00H)
IDR
RIR3
CCR4
IBCC
TCD
RUPCD
RDNCD
TCC1
TCC2
TCC3
CCR5
TDS0M
RCC1
RCC2
RCC3
CCR6
RDS0M
SR1
SR2
RIR1
LCVCR1
CVCR2
PCVCR1
PCVCR2
MOSCR2
RFDL
–
R
Device ID
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
R
R
R
R
R
R
R/W
Receive Information 3
Common Control 4
In–Band Code Control
Transmit Code Definition
Receive Up Code Definition
Receive Down Code Definition
Transmit Channel Control 1
Transmit Channel Control 2
Transmit Channel Control 3
Common Control 5
Transmit DS0 Monitor
Receive Channel Control 1
Receive Channel Control 2
Receive Channel Control 3
Common Control 6
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
Receive DS0 Monitor
Status 1
Status 2
Receive Information 1
Line Code Violation Count 1
Line Code Violation Count 2
Path Code Violation Count 1
Path Code violation Count 2
Multiframe Out of Sync Count 2
Receive FDL Register
Receive FDL Match 1
25
26
27
28
29
RMTCH1
22 of 119
DS21Q42
REGISTER
ADDRESS
2A
2B
2C
2D
2E
2F
30
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
REGISTER NAME
Receive FDL Match 2
Receive Control 1
Receive Control 2
Receive Mark 1
ABBREVIATION
RMTCH2
RCR1
RCR2
RMR1
RMR2
RMR3
CCR3
RIR2
Receive Mark 2
Receive Mark 3
Common Control 3
Receive Information 2
Transmit Channel Blocking 1
Transmit Channel blocking 2
Transmit Channel Blocking 3
Transmit Control 1
Transmit Control 2
Common Control 1
Common Control 2
Transmit Transparency 1
Transmit Transparency 2
Transmit Transparency 3
Transmit Idle 1
31
32
33
34
35
36
37
38
TCBR1
TCBR2
TCBR3
TCR1
TCR2
CCR1
CCR2
TTR1
TTR2
TTR3
TIR1
39
3A
3B
3C
3D
3E
3F
40
41
42
43
44
Transmit Idle 2
Transmit Idle 3
TIR2
TIR3
TIDR
TC9
Transmit Idle Definition
Transmit Channel 9
Transmit Channel 10
Transmit Channel 11
Transmit Channel 12
Transmit Channel 13
Transmit Channel 14
Transmit Channel 15
Transmit Channel 16
Transmit Channel 17
Transmit Channel 18
Transmit Channel 19
Transmit Channel 20
Transmit Channel 21
Transmit Channel 22
Transmit Channel 23
Transmit Channel 24
Transmit Channel 1
Transmit Channel 2
Transmit Channel 3
Transmit Channel 4
Transmit Channel 5
Transmit Channel 6
Transmit Channel 7
Transmit Channel 8
TC10
TC11
TC12
TC13
TC14
TC15
TC16
TC17
TC18
TC19
TC20
TC21
TC22
TC23
TC24
TC1
TC2
TC3
TC4
TC5
TC6
TC7
TC8
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
23 of 119
DS21Q42
REGISTER
ADDRESS
58
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R
R
R
R
R
REGISTER NAME
Receive Channel 17
ABBREVIATION
RC17
RC18
RC19
RC20
RC21
RC22
RC23
RC24
RS1
59
Receive Channel 18
Receive Channel 19
Receive Channel 20
Receive Channel 21
Receive Channel 22
Receive Channel 23
Receive Channel 24
Receive Signaling 1
Receive Signaling 2
Receive Signaling 3
Receive Signaling 4
Receive Signaling 5
Receive Signaling 6
Receive Signaling 7
Receive Signaling 8
Receive Signaling 9
Receive Signaling 10
Receive Signaling 11
Receive Signaling 12
Receive Channel Blocking 1
Receive Channel Blocking 2
Receive Channel Blocking 3
Interrupt Mask 2
Transmit Signaling 1
Transmit Signaling 2
Transmit Signaling 3
Transmit Signaling 4
Transmit Signaling 5
Transmit Signaling 6
Transmit Signaling 7
Transmit Signaling 8
Transmit Signaling 9
Transmit Signaling 10
Transmit Signaling 11
Transmit Signaling 12
Not used
5A
5B
5C
5D
5E
5F
60
61
62
63
64
RS2
RS3
RS4
RS5
RS6
RS7
RS8
RS9
RS10
RS11
RS12
RCBR1
RCBR2
RCBR3
IMR2
TS1
TS2
TS3
TS4
TS5
65
66
67
68
69
R
R
R
6A
6B
6C
6D
6E
6F
70
71
72
73
74
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
–
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
75
76
77
78
TS6
TS7
TS8
TS9
79
TS10
TS11
TS12
(set to 00H)
TEST1 (set to 00h)
TFDL
IMR1
RC1
7A
7B
7C
7D
7E
7F
80
81
82
83
84
Test 1
Transmit FDL Register
Interrupt Mask Register 1
Receive Channel 1
Receive Channel 2
Receive Channel 3
Receive Channel 4
Receive Channel 5
Receive Channel 6
RC2
RC3
RC4
RC5
85
RC6
24 of 119
DS21Q42
REGISTER
ADDRESS
86
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
–
R/W
–
–
–
–
–
–
–
–
REGISTER NAME
Receive Channel 7
Receive Channel 8
ABBREVIATION
RC7
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
94
95
96
97
RC8
RC9
RC10
RC11
RC12
RC13
RC14
RC15
RC16
RDC1
RDC2
TDC1
TDC2
IBO
Receive Channel 9
Receive Channel 10
Receive Channel 11
Receive Channel 12
Receive Channel 13
Receive Channel 14
Receive Channel 15
Receive Channel 16
Receive HDLC DS0 Control Register 1
Receive HDLC DS0 Control Register 2
Transmit HDLC DS0 Control Register 1
Transmit HDLC DS0 Control Register 2
Interleave Bus Operation Register
Not used
(set to 00H)
TEST2 (set to 00h)
(set to 00H)
(set to 00H)
(set to 00H)
(set to 00H)
Test 2
Not used
Not used
Not used
98
99
9A
9B
9C
9D
9E
9F
Not used
Not used (set to 00H)
Not used (set to 00H)
Not used (set to 00H)
Not used (set to 00H)
Not used (set to 00H)
–
Notes:
1. Test Registers 1 and 2 are used only by the factory; these registers must be cleared (set to all zeros) on
power– up initialization to insure proper operation.
2. Register banks AxH, BxH, CxH, DxH, ExH, and FxH are not accessible.
25 of 119
DS21Q42
5. PARALLEL PORT
The DS21Q42 is controlled via either a nonmultiplexed (MUX = 0) or a multiplexed (MUX = 1) bus by
an external microcontroller or microprocessor. The DS21Q42 can operate with either Intel or Motorola
bus timing configurations. If the BTS pin is tied low, Intel timing will be selected; if tied high, Motorola
timing will be selected. All Motorola bus signals are listed in parenthesis (). See the timing diagrams in
the A.C. Electrical Characteristics in Section 21 for more details.
6. CONTROL, ID AND TEST REGISTERS
The operation of each framer within the DS21Q42 is configured via a set of eleven control registers.
Typically, the control registers are only accessed when the system is first powered up. Once a channel in
the DS21Q42 has been initialized, the control registers will only need to be accessed when there is a
change in the system configuration. There are two Receive Control Register (RCR1 and RCR2), two
Transmit Control Registers (TCR1 and TCR2), and seven Common Control Registers (CCR1 to CCR7).
Each of the eleven registers are described in this section. There is a device Identification Register (IDR)
at address 0Fh. The MSB of this read–only register is fixed to a zero indicating that the DS21Q42 is
present. The E1 pin–for–pin compatible version of the DS21Q42 is the DS21Q44 and it also has an ID
register at address 0Fh and the user can read the MSB to determine which chip is present since in the
DS21Q42 the MSB will be set to a zero and in the DS21Q44 it will be set to a one. The lower four bits of
the IDR are used to display the die revision of the chip.
Power–Up Sequence
The DS21Q42 does not automatically clear its register space on power–up. After the supplies are stable,
each of the four framer’s register space should be configured for operation by writing to all of the internal
registers. This includes setting the Test and all unused registers to 00Hex.
This can be accomplished using a two-pass approach on each framer within the DS21Q42.
1. Clear framer’s register space by writing 00H to the addresses 00H through 09FH.
2. Program required registers to achieve desired operating mode.
Note:
When emulating the DS21Q41 feature set (FMS = 1), the full address space (00H through 09FH) must be
initialized. DS21Q41 emulation requires address pin A7 to be used.
Finally, after the TSYSCLK and RSYSCLK inputs are stable, the ESR bit should be toggled from a zero
to a one (this step can be skipped if the elastic stores are disabled).
26 of 119
DS21Q42
IDR: DEVICE IDENTIFICATION REGISTER (Address=0F Hex)
(MSB)
(LSB)
T1E1
0
0
0
ID3
ID2
ID1
ID0
SYMBOL
POSITION
NAME AND DESCRIPTION
T1E1
IDR.7
T1 or E1 Chip Determination Bit.
0=T1 chip
1=E1 chip
ID3
IDR.3
Chip Revision Bit 3. MSB of a decimal code that represents the chip
revision.
ID2
ID1
ID0
IDR.1
IDR.2
IDR.0
Chip Revision Bit 2.
Chip Revision Bit 1.
Chip Revision Bit 0. LSB of a decimal code that represents the chip
revision.
RCR1: RECEIVE CONTROL REGISTER 1 (Address=2B Hex)
(MSB)
(LSB)
LCVCRF
ARC
OOF1
OOF2
SYNCC
SYNCT
SYNCE
RESYNC
SYMBOL
POSITION
NAME AND DESCRIPTION
LCVCRF
RCR1.7
RCR1.6
RCR1.5
RCR1.4
RCR1.3
Line Code Violation Count Register Function Select.
0 = do not count excessive zeros
1 = count excessive zeros
Auto Resync Criteria.
0 = Resync on OOF or RCL event
1 = Resync on OOF only
Out Of Frame Select 1.
0 = 2/4 frame bits in error
1 = 2/5 frame bits in error
Out Of Frame Select 2.
0 = follow RCR1.5
ARC
OOF1
OOF2
1 = 2/6 frame bits in error
Sync Criteria.
SYNCC
In D4 Framing Mode.
0 = search for Ft pattern, then search for Fs pattern
1 = cross couple Ft and Fs pattern
In ESF Framing Mode.
0 = search for FPS pattern only
1 = search for FPS and verify with CRC6
Sync Time.
0 = qualify 10 bits
1 = qualify 24 bits
Sync Enable.
0 = auto resync enabled
SYNCT
SYNCE
RCR1.2
RCR1.1
RCR1.0
1 = auto resync disabled
Resync. When toggled from low to high, a resynchronization of the
RESYNC
receive side framer is initiated. Must be cleared and set again for a
subsequent resync.
27 of 119
DS21Q42
RCR2: RECEIVE CONTROL REGISTER 2 (Address=2C Hex)
(MSB)
RCS
(LSB)
MOSCRF
RZBTSI
RSDW
RSM
RSIO
RD4YM
FSBE
SYMBOL
POSITION
NAME AND DESCRIPTION
RCS
RCR2.7
RCR2.6
RCR2.5
Receive Code Select. See Section 11 for more details.
0 = idle code (7F Hex)
1 = digital milliwatt code (1E/0B/0B/1E/9E/8B/8B/9E Hex)
Receive Side ZBTSI Enable.
0 = ZBTSI disabled
1 = ZBTSI enabled
RSYNC Double–Wide. (note: this bit must be set to zero when
RCR2.4 = 1 or when RCR2.3 = 1)
RZBTSI
RSDW
0 = do not pulse double wide in signaling frames
1 = do pulse double wide in signaling frames
RSYNC Mode Select. (A Don’t Care if RSYNC is programmed as
an input)
0 = frame mode (see the timing in Section 20)
1 = multiframe mode (see the timing in Section 20)
RSYNC I/O Select. (note: this bit must be set to zero when CCR1.2
= 0)
RSM
RSIO
RCR2.4
RCR2.3
0 = RSYNC is an output
1 = RSYNC is an input (only valid if elastic store enabled)
Receive Side D4 Yellow Alarm Select.
0 = zeros in bit 2 of all channels
1 = a one in the S–bit position of frame 12
PCVCR Fs–Bit Error Report Enable.
0 = do not report bit errors in Fs–bit position; only Ft bit position
1 = report bit errors in Fs–bit position as well as Ft bit position
Multiframe Out of Sync Count Register Function Select.
0 = count errors in the framing bit position
1 = count the number of multiframes out of sync
RD4YM
FSBE
RCR2.2
RCR2.1
RCR2.0
MOSCRF
28 of 119
DS21Q42
TCR1: TRANSMIT CONTROL REGISTER 1 (Address=35 Hex)
(MSB)
(LSB)
LOTCMC
SYMBOL
LOTCMC
TFPT
TCPT
TSSE
GB7S
TFDLS
TBL
TYEL
POSITION
NAME AND DESCRIPTION
TCR1.7
Loss Of Transmit Clock Mux Control. Determines whether the
transmit side formatter should switch to RCLK if the TCLK input
should fail to transition (see Figure 1.1 for details).
0 = do not switch to RCLK if TCLK stops
1 = switch to RCLK if TCLK stops
TFPT
TCPT
TSSE
TCR1.6
TCR1.5
TCR1.4
Transmit F–Bit Pass Through. (see note below)
0 = F bits sourced internally
1 = F bits sampled at TSER
Transmit CRC Pass Through. (see note below)
0 = source CRC6 bits internally
1 = CRC6 bits sampled at TSER during F–bit time
Software Signaling Insertion Enable. (see note below)
0 = no signaling is inserted in any channel
1 = signaling is inserted in all channels from the TS1-TS12 registers
(the TTR registers can be used to block insertion on a channel by
channel basis)
GB7S
TCR1.3
TCR1.2
Global Bit 7 Stuffing. (see note below)
0 = allow the TTR registers to determine which channels containing
all zeros are to be Bit 7 stuffed
1 = force Bit 7 stuffing in all zero byte channels regardless of how
the
TTR registers are programmed
TFDLS
TFDL Register Select. (see note below)
0 = source FDL or Fs bits from the internal TFDL register (legacy
FDL support mode)
1 = source FDL or Fs bits from the internal HDLC/BOC controller
or the TLINK pin
TBL
TCR1.1
TCR1.0
Transmit Blue Alarm. (see note below)
0 = transmit data normally
1 = transmit an unframed all one’s code at TPOS and TNEG
Transmit Yellow Alarm. (see note below)
0 = do not transmit yellow alarm
TYEL
1 = transmit yellow alarm
Note:
For a description of how the bits in TCR1 affect the transmit side formatter, see Figure 20-15.
29 of 119
DS21Q42
TCR2: TRANSMIT CONTROL REGISTER 2 (Address=36 Hex)
(MSB)
(LSB)
TEST1
TEST0
TZBTSI
TSDW
TSM
TSIO
TD4YM
TB7ZS
SYMBOL
POSITION
NAME AND DESCRIPTION
TEST1
TEST0
TZBTSI
TCR2.7
TCR2.6
TCR2.5
Test Mode Bit 1 for Output Pins. See Table 6–1.
Test Mode Bit 0 for Output Pins. See Table 6–1.
Transmit Side ZBTSI Enable.
0 = ZBTSI disabled
1 = ZBTSI enabled
TSDW
TCR2.4
TSYNC Double–Wide. (note: this bit must be set to zero when
TCR2.3=1 or when TCR2.2=0)
0 = do not pulse double–wide in signaling frames
1 = do pulse double–wide in signaling frames
TSYNC Mode Select.
0 = frame mode (see the timing in Section 20)
1 = multiframe mode (see the timing in Section 20)
TSYNC I/O Select.
TSM
TSIO
TCR2.3
TCR2.2
TCR2.1
TCR2.0
0 = TSYNC is an input
1 = TSYNC is an output
TD4YM
TB7ZS
Transmit Side D4 Yellow Alarm Select.
0 = zeros in bit 2 of all channels
1 = a one in the S–bit position of frame 12
Transmit Side Bit 7 Zero Suppression Enable.
0 = no stuffing occurs
1 = Bit 7 force to a one in channels with all zeros
OUTPUT PIN TEST MODES Table 6-1
TEST 1
TEST 0
EFFECT ON OUTPUT PINS
0
0
0
1
operate normally
force all of the selected framer’s output pins 3–state (excludes other
framers I/O pins and parallel port pins)
1
1
0
1
force all of the selected framer’s output pins low (excludes other
framers I/O pins and parallel port pins)
force all of the selected framer’s output pins high (excludes other
framers I/O pins and parallel port pins)
30 of 119
DS21Q42
CCR1: COMMON CONTROL REGISTER 1 (Address=37 Hex)
(MSB)
TESE
(LSB)
FLB
ODF
RSAO
POSITION
TSCLKM RSCLKM RESE
PLB
SYMBOL
NAME AND DESCRIPTION
TESE
ODF
CCR1.7
CCR1.6
CCR1.5
Transmit Elastic Store Enable.
0 = elastic store is bypassed
1 = elastic store is enabled
Output Data Format.
0 = bipolar data at TPOS and TNEG
1 = NRZ data at TPOS; TNEG = 0
Receive Signaling All One’s. This bit should not be enabled if
hardware signaling is being utilized. See Section 10 for more details.
0 = allow robbed signaling bits to appear at RSER
1 = force all robbed signaling bits at RSER to one
TSYSCLK Mode Select.
0 = if TSYSCLK is 1.544 MHz
1 = if TSYSCLK is 2.048 MHz
RSYSCLK Mode Select.
0 = if RSYSCLK is 1.544 MHz
1 = if RSYSCLK is 2.048 MHz
Receive Elastic Store Enable.
0 = elastic store is bypassed
RSAO
TSCLKM
RSCLKM
RESE
CCR1.4
CCR1.3
CCR1.2
CCR1.1
CCR1.0
1 = elastic store is enabled
Payload Loopback.
0 = loopback disabled
1 = loopback enabled
PLB
FLB
Framer Loopback.
0 = loopback disabled
1 = loopback enabled
Payload Loopback
When CCR1.1 is set to a one, the DS21Q42 will be forced into Payload LoopBack (PLB). Normally, this
loopback is only enabled when ESF framing is being performed but can be enabled also in D4 framing
applications. In a PLB situation, the DS21Q42 will loop the 192 bits of payload data (with BPVs
corrected) from the receive section back to the transmit section. The FPS framing pattern, CRC6
calculation, and the FDL bits are not looped back, they are reinserted by the DS21Q42. When PLB is
enabled, the following will occur:
1. Data will be transmitted from the TPOS and TNEG pins synchronous with RCLK instead of TCLK
2. All of the receive side signals will continue to operate normally
3. The TCHCLK and TCHBLK signals are forced low
4. Data at the TSER, and TSIG pins is ignored
5. The TLCLK signal will become synchronous with RCLK instead of TCLK.
31 of 119
DS21Q42
Framer Loopback
When CCR1.0 is set to a one, the DS21Q42 will enter a Framer LoopBack (FLB) mode. This loopback is
useful in testing and debugging applications. In FLB, the DS21Q42 will loop data from the transmit side
back to the receive side. When FLB is enabled, the following will occur:
1. an unframed all one’s code will be transmitted at TPOS and TNEG
2. data at RPOS and RNEG will be ignored
3. all receive side signals will take on timing synchronous with TCLK instead of RCLK
Please note that it is not acceptable to have RCLK tied to TCLK during this loopback because this will
cause an unstable condition.
CCR2: COMMON CONTROL REGISTER 2 (Address=38 Hex)
(MSB)
(LSB)
TFM
TB8ZS
TSLC96
TZSE
RFM
RB8ZS
RSLC96
RZSE
SYMBOL
POSITION
NAME AND DESCRIPTION
TFM
CCR2.7
CCR2.6
CCR2.5
Transmit Frame Mode Select.
0 = D4 framing mode
1 = ESF framing mode
Transmit B8ZS Enable.
0 = B8ZS disabled
TB8ZS
1 = B8ZS enabled
TSLC96
Transmit SLC–96 / Fs–Bit Insertion Enable. Only set this bit to a
one in D4 framing applications. Must be set to one to source the Fs
pattern. See Section 15 for details.
0 = SLC–96/Fs–bit insertion disabled
1 = SLC–96/Fs–bit insertion enabled
Transmit FDL Zero Stuffer Enable. Set this bit to zero if using
the internal HDLC/BOC controller instead of the legacy support for
the FDL. See Section 15 for details.
0 = zero stuffer disabled
TZSE
CCR2.4
1 = zero stuffer enabled
RFM
CCR2.3
CCR2.2
CCR2.1
Receive Frame Mode Select.
0 = D4 framing mode
1 = ESF framing mode
Receive B8ZS Enable.
0 = B8ZS disabled
1 = B8ZS enabled
Receive SLC–96 Enable. Only set this bit to a one in D4/SLC–96
framing applications. See Section 15 for details.
0 = SLC–96 disabled
RB8ZS
RSLC96
1 = SLC–96 enabled
32 of 119
DS21Q42
SYMBOL
POSITION
NAME AND DESCRIPTION
RZSE
CCR2.0
Receive FDL Zero Destuffer Enable. Set this bit to zero if using
the internal HDLC/BOC controller instead of the legacy support for
the FDL. See Section 15 for details.
0 = zero destuffer disabled
1 = zero destuffer enabled
CCR3: COMMON CONTROL REGISTER 3 (Address=30 Hex)
(MSB)
LSB)
RESMDM TCLKSRC RLOSF
RSMS
PDE
ECUS
TLOOP
TESMDM
SYMBOL
POSITION
NAME AND DESCRIPTION
RESMDM
CCR3.7
Receive Elastic Store Minimum Delay Mode. See Section 13 for
details.
0 = elastic stores operate at full two frame depth
1 = elastic stores operate at 32–bit depth
Transmit Clock Source Select. This function allows the user to
internally select RCLK as the clock source for the transmit side
formatter.
TCLKSRC
CCR3.6
0 = Transmit side formatter clocked with signal applied at TCLK
pin.
LOTC Mux function is operational (TCR1.7)
1 = Transmit side formatter clocked with RCLK.
Function of the RLOS/LOTC Output. Active only when FMS = 1
(DS21Q41 emulation).
0 = Receive Loss of Sync (RLOS)
1 = Loss of Transmit Clock (LOTC)
RSYNC Multiframe Skip Control. Useful in framing format
conversions from D4 to ESF. This function is not available when
the receive side elastic store is enabled.
RLOSF
RSMS
CCR3.5
CCR3.4
0 = RSYNC will output a pulse at every multiframe
1 = RSYNC will output a pulse at every other multiframe note: for
this
bit to have any affect, the RSYNC must be set to output multiframe
pulses (RCR2.4=1 and RCR2.3=0).
PDE
ECUS
TLOOP
CCR3.3
CCR3.2
CCR3.1
Pulse Density Enforcer Enable.
0 = disable transmit pulse density enforcer
1 = enable transmit pulse density enforcer
Error Counter Update Select. See Section 8 for details.
0 = update error counters once a second
1 = update error counters every 42 ms (333 frames)
Transmit Loop Code Enable. See Section 16 for details.
0 = transmit data normally
1 = replace normal transmitted data with repeating code as defined
in TCD register
33 of 119
DS21Q42
SYMBOL
POSITION
NAME AND DESCRIPTION
TESMDM
CCR3.0
Transmit Elastic Store Minimum Delay Mode. See Section 13
for details.
0 = elastic stores operate at full two frame depth
1 = elastic stores operate at 32–bit depth
Pulse Density Enforcer
The Framer always examines both the transmit and receive data streams for violations of the following
rules which are required by ANSI T1.403:
– no more than 15 consecutive zeros
– at least N ones in each and every time window of 8 x (N +1) bits where N = 1 through 23
Violations for the transmit and receive data streams are reported in the RIR2.0 and RIR2.1 bits
respectively. When the CCR3.3 is set to one, the DS21Q42 will force the transmitted stream to meet this
requirement no matter the content of the transmitted stream. When running B8ZS, the CCR3.3 bit should
be set to zero since B8ZS encoded data streams cannot violate the pulse density requirements.
CCR4: COMMON CONTROL REGISTER 4 (Address=11 Hex)
(MSB)
(LSB)
RSRE
RPCSI
RFSA1
POSITION
CCR4.7
RFE
RFF
THSE
TPCSI
TIRFS
SYMBOL
NAME AND DESCRIPTION
RSRE
Receive Side Signaling Re–Insertion Enable. See Section 10 for
details.
0 = do not re–insert signaling bits into the data stream presented at
the RSER pin
1 = reinsert the signaling bits into data stream presented at the
RSER pin
RPCSI
CCR4.6
Receive Per–Channel Signaling Insert. See Section 10 for more
details.
0 = do not use RCHBLK to determine which channels should have
signaling re–inserted
1 = use RCHBLK to determine which channels should have
signaling re–inserted
RFSA1
RFE
CCR4.5
CCR4.4
Receive Force Signaling All Ones. See Section 10 for more
details.
0 = do not force extracted robbed–bit signaling bit positions to a one
1 = force extracted robbed–bit signaling bit positions to a one
Receive Freeze Enable. See Section 10 for details.
0 = no freezing of receive signaling data will occur
1 = allow freezing of receive signaling data at RSIG (and RSER if
CCR4.7 = 1).
34 of 119
DS21Q42
SYMBOL
POSITION
NAME AND DESCRIPTION
RFF
CCR4.3
Receive Force Freeze. Freezes receive side signaling at RSIG (and
RSER if CCR4.7=1); will override Receive Freeze Enable (RFE).
See Section 10 for details.
0 = do not force a freeze event
1 = force a freeze event
THSE
TPCSI
TIRFS
CCR4.2
CCR4.1
CCR4.0
Transmit Hardware Signaling Insertion Enable. See Section 10
for details.
0 = do not insert signaling from the TSIG pin into the data stream
presented at the TSER pin.
1 = Insert the signaling from the TSIG pin into data stream
presented at the TSER pin.
Transmit Per–Channel Signaling Insert. See Section 10 for
details.
0 = do not use TCHBLK to determine which channels should have
signaling inserted from the TSIG pin.
1 = use TCHBLK to determine which channels should have
signaling inserted from the TSIG pin.
Transmit Idle Registers (TIR) Function Select. See Section 11
for timing details.
0 = TIRs define in which channels to insert idle code
1 = TIRs define in which channels to insert data from RSER (i.e.,
Per = Channel Loopback function)
CCR5: COMMON CONTROL REGISTER 5 (Address=19 Hex)
(MSB)
(LSB)
TJC
–
–
POSITION
CCR5.7
TCM4
NAME AND DESCRIPTION
Transmit Japanese CRC6 Enable.
TCM3
TCM2
TCM1
TCM0
SYMBOL
TJC
0 = use ANSI/AT&T/ITU CRC6 calculation (normal operation)
1 = use Japanese standard JT–G704 CRC6 calculation
Not Assigned. Must be set to zero when written.
Not Assigned. Must be set to zero when written.
Transmit Channel Monitor Bit 4. MSB of a channel decode that
determines which transmit channel data will appear in the TDS0M
register. See Section 9 for details.
–
–
CCR5.6
CCR5.5
CCR5.4
TCM4
TCM3
TCM2
TCM1
TCM0
CCR5.3
CCR5.2
CCR5.1
CCR5.0
Transmit Channel Monitor Bit 3.
Transmit Channel Monitor Bit 2.
Transmit Channel Monitor Bit 1.
Transmit Channel Monitor Bit 0. LSB of the channel decode.
35 of 119
DS21Q42
CCR6: COMMON CONTROL REGISTER 6 (Address=1E Hex)
(MSB)
RJC
(LSB)
RCM0
RESALGN TESALGN RCM4
RCM3
RCM2
RCM1
SYMBOL
POSITION
CCR6.7
NAME AND DESCRIPTION
Receive Japanese CRC6 Enable.
RJC
0 = use ANSI/AT&T/ITU CRC6 calculation (normal operation)
1 = use Japanese standard JT–G704 CRC6 calculation
Receive Elastic Store Align. Setting this bit from a zero to a one
may force the receive elastic store’s write/read pointers to a
minimum separation of half a frame. No action will be taken if the
pointer separation is already greater or equal to half a frame. If
pointer separation is less then half a frame, the command will be
executed and data will be disrupted. Should be toggled after
RSYSCLK has been applied and is stable. Must be cleared and set
again for a subsequent align. See Section 13 for details.
Transmit Elastic Store Align. Setting this bit from a zero to a one
may force the transmit elastic store’s write/read pointers to a
minimum separation of half a frame. No action will be taken if the
pointer separation is already greater or equal to half a frame. If
pointer separation is less then half a frame, the command will be
executed and data will be disrupted. Should be toggled after
TSYSCLK has been applied and is stable. Must be cleared and set
again for a subsequent align. See Section 13 for details.
Receive Channel Monitor Bit 4. MSB of a channel decode that
determines which receive channel data will appear in the RDS0M
register. See Section 9 for details.
RESALGN
CCR6.6
CCR6.5
CCR6.4
TESALGN
RCM4
RCM3
RCM2
RCM1
RCM0
CCR6.3
CCR6.2
CCR6.1
CCR6.0
Receive Channel Monitor Bit 3.
Receive Channel Monitor Bit 2.
Receive Channel Monitor Bit 1.
Receive Channel Monitor Bit 0. LSB of the channel decode.
36 of 119
DS21Q42
CCR7: COMMON CONTROL REGISTER 7 (Address=0A Hex)
(MSB)
(LSB)
-
RLB
RESR
TESR
-
-
-
-
SYMBOL
POSITION
NAME AND DESCRIPTION
–
RLB
CCR7.7
CCR7.6
Not Assigned. Should be set to zero when written to.
Remote Loopback.
0 = loopback disabled
1 = loopback enabled
RESR
TESR
CCR7.5
CCR7.4
Receive Elastic Store Reset. Setting this bit from a zero to a one
will force the receive elastic store to a depth of one frame. Receive
data is lost during the reset. Should be toggled after RSYSCLK has
been applied and is stable. Do not leave this bit set high.
Transmit Elastic Store Reset. Setting this bit from a zero to a one
will force the transmit elastic store to a depth of one frame.
Transmit data is lost during the reset. Should be toggled after
TSYSCLK has been applied and is stable. Do not leave this bit set
high.
–
–
–
–
CCR7.3
CCR7.2
CCR7.1
CCR7.0
Not Assigned. Should be set to zero when written to.
Not Assigned. Should be set to zero when written to.
Not Assigned. Should be set to zero when written to.
Not Assigned. Should be set to zero when written to.
Remote Loopback
When CCR7.6 is set to a one, the DS21Q42 will be forced into Remote LoopBack (RLB). In this
loopback, data input via the RPOS and RNEG pins will be transmitted back to the TPOS and TNEG pins.
Data will continue to pass through the receive side framer of the DS21Q42 as it would normally and the
data from the transmit side formatter will be ignored. Please see Figure 1-1 for more details.
7. STATUS AND INFORMATION REGISTERS
There is a set of nine registers per channel that contain information on the current real time status of a
framer in the DS21Q42, Status Register 1 (SR1), Status Register 2 (SR2), Receive Information Registers
1 to 3 (RIR1/RIR2/RIR3) and a set of four registers for the onboard HDLC and BOC controller. The
specific details on the four registers pertaining to the HDLC and BOC controller are covered in Section
15 but they operate the same as the other status registers in the DS21Q42 and this operation is described
below.
When a particular event has occurred (or is occurring), the appropriate bit in one of these nine registers
will be set to a one. All of the bits in SR1, SR2, RIR1, RIR2, and RIR3 registers operate in a latched
fashion. This means that if an event or an alarm occurs and a bit is set to a one in any of the registers, it
will remain set until the user reads that bit. The bit will be cleared when it is read and it will not be set
again until the event has occurred again (or in the case of the RBL, RYEL, LRCL, and RLOS alarms, the
bit will remain set if the alarm is still present). There are bits in the four HDLC and BOC status registers
that are not latched and these bits are listed in Section 15.
37 of 119
DS21Q42
The user will always precede a read of any of the nine registers with a write. The byte written to the
register will inform the DS21Q42 which bits the user wishes to read and have cleared. The user will write
a byte to one of these registers, with a one in the bit positions he or she wishes to read and a zero in the
bit positions he or she does not wish to obtain the latest information on. When a one is written to a bit
location, the read register will be updated with the latest information. When a zero is written to a bit
position, the read register will not be updated and the previous value will be held. A write to the status
and information registers will be immediately followed by a read of the same register. The read result
should be logically AND’ed with the mask byte that was just written and this value should be written
back into the same register to insure that bit does indeed clear. This second write step is necessary
because the alarms and events in the status registers occur asynchronously in respect to their access via
the parallel port. This write–read– write scheme allows an external microcontroller or microprocessor to
individually poll certain bits without disturbing the other bits in the register. This operation is key in
controlling the DS21Q42 with higher–order software languages.
The SR1, SR2, and FDLS registers have the unique ability to initiate a hardware interrupt via the INT*
output pin. Each of the alarms and events in the SR1, SR2, and HSR can be either masked or unmasked
from the interrupt pin via the Interrupt Mask Register 1 (IMR1), Interrupt Mask Register 2 (IMR2), and
HDLC Interrupt Mask Register (HIMR) respectively. The FIMR register is covered in Section 15. The
INTERRUPT STATUS REGISTER can be used to determine which framer is requesting interrupt
servicing and the type of the request: status or the HDLC controller.
The interrupts caused by alarms in SR1 (namely RYEL, RCL, RBL, RLOS and LOTC) act differently
than the interrupts caused by events in SR1 and SR2 (namely LUP, LDN, RSLIP, RMF, TMF, SEC,
RFDL, TFDL, RMTCH, RAF, and RSC) and HIMR. The alarm caused interrupts will force the INT* pin
low whenever the alarm changes state (i.e., the alarm goes active or inactive according to the set/clear
criteria in Table 7-1). The INT* pin will be allowed to return high (if no other interrupts are present)
when the user reads the alarm bit that caused the interrupt to occur even if the alarm is still present.
The event caused interrupts will force the INT* pin low when the event occurs. The INT* pin will be
allowed to return high (if no other interrupts are present) when the user reads the event bit that caused the
interrupt to occur.
ISR: INTERRUPT STATUS REGISTER (Any address from A0H to FFH)
(MSB)
(LSB)
F3HDLC
F3SR
F2HDLC
POSITION
ISR.7
F2SR
F1HDLC
F1SR
F0HDLC
F0SR
SYMBOL
NAME AND DESCRIPTION
F3HDLC
FRAMER 3 HDLC CONTROLLER INTERRUPT
REQUEST.
0 = No interrupt request pending.
1 = Interrupt request pending.
F3SR
ISR.6
ISR.5
FRAMER 3 SR1 or SR2 INTERRUPT REQUEST.
0 = No interrupt request pending.
1 = Interrupt request pending.
FRAMER 2 HDLC CONTROLLER INTERRUPT
REQUEST.
F2HDLC
0 = No interrupt request pending.
1 = Interrupt request pending.
38 of 119
DS21Q42
SYMBOL
POSITION
NAME AND DESCRIPTION
F2SR
ISR.4
FRAMER 2 SR1 or SR2 INTERRUPT REQUEST.
0 = No interrupt request pending.
1 = Interrupt request pending.
F1HDLC
ISR.3
FRAMER 1 HDLC CONTROLLER INTERRUPT
REQUEST.
0 = No interrupt request pending.
1 = Interrupt request pending.
F1SR
ISR.2
ISR.1
FRAMER 1 SR1 or SR2 INTERRUPT REQUEST.
0 = No interrupt request pending.
1 = Interrupt request pending.
FRAMER 0 HDLC CONTROLLER INTERRUPT
REQUEST.
F0HDLC
0 = No interrupt request pending.
1 = Interrupt request pending.
F0SR ISR
0
FRAMER 0 SR1 or SR2 INTERRUPT REQUEST.
0 = No interrupt request pending.
1 = Interrupt request pending.
RIR1: RECEIVE INFORMATION REGISTER 1 (Address=22 Hex)
(MSB)
(LSB)
COFA
8ZD
16ZD
POSITION
RIR1.7
RESF
RESE
SEFE
B8ZS
FBE
SYMBOL
NAME AND DESCRIPTION
COFA
8ZD
Change of Frame Alignment. Set when the last resync
resulted in a change of frame or multiframe alignment.
Eight Zero Detect. Set when a string of at least eight
consecutive zeros (regardless of the length of the string) have
been received at RPOS and RNEG.
RIR1.6
16ZD
RIR1.5
Sixteen Zero Detect. Set when a string of at least sixteen
consecutive zeros (regardless of the length of the string) have
been received at RPOS and RNEG.
RESF
RESE
SEFE
B8ZS
RIR1.4
RIR1.3
RIR1.2
RIR1.1
Receive Elastic Store Full. Set when the receive elastic store
buffer fills and a frame is deleted.
Receive Elastic Store Empty. Set when the receive elastic
store buffer empties and a frame is repeated.
Severely Errored Framing Event. Set when 2 out of 6
framing bits (Ft or FPS) are received in error.
B8ZS Code Word Detect. Set when a B8ZS code word is
detected at RPOS and RNEG independent of whether the
B8ZS mode is selected or not via CCR2.6. Useful for
automatically setting the line coding.
FBE
RIR1.0
Frame Bit Error. Set when a Ft (D4) or FPS (ESF) framing
bit is received in error.
39 of 119
DS21Q42
RIR2: RECEIVE INFORMATION REGISTER 2 (Address=31 Hex)
(MSB)
(LSB)
RLOSC
RCLC
TESF
TESE
TSLIP
RBLC
RPDV
TPDV
SYMBOL
POSITION
NAME AND DESCRIPTION
RLOSC
RCLC
TESF
RIR2.7
Receive Loss of Sync Clear. Set when the framer achieves
synchronization; will remain set until read.
Receive Carrier Loss Clear. Set when the carrier signal is
restored; will remain set until read. See Table 7-1.
Transmit Elastic Store Full. Set when the transmit elastic
store buffer fills and a frame is deleted.
RIR2.6
RIR2.5
RIR2.4
RIR2.3
RIR2.2
RIR2.1
TESE
Transmit Elastic Store Empty. Set when the transmit elastic
store buffer empties and a frame is repeated.
TSLIP
RBLC
RPDV
Transmit Elastic Store Slip Occurrence. Set when the
transmit elastic store has either repeated or deleted a frame.
Receive Blue Alarm Clear. Set when the Blue Alarm (AIS)
is no longer detected; will remain set until read. See Table 7-1.
Receive Pulse Density Violation. Set when the receive data
stream does not meet the ANSI T1.403 requirements for pulse
density.
TPDV
RIR2.0
Transmit Pulse Density Violation. Set when the transmit
data stream does not meet the ANSI T1.403 requirements for
pulse density.
RIR3: RECEIVE INFORMATION REGISTER 3 (Address=10 Hex)
(MSB)
(LSB)
LORC
-
-
-
RAIS-CI
-
-
-
SYMBOL
POSITION
NAME AND DESCRIPTION
–
–
–
RIR3.7
RIR3.6
RIR3.5
RIR3.4
Not Assigned. Could be any value when read.
Not Assigned. Could be any value when read.
Not Assigned. Could be any value when read.
Loss of Receive Clock. Set when the RCLK pin has not
transitioned for at least 2 us (3 us ˜˜1 us).
Not Assigned. Could be any value when read.
Not Assigned. Could be any value when read.
Not Assigned. Could be any value when read.
Receive AIS-CI Detect. Set when the AIS-CI pattern is
detected.
LORC
–
–
–
RIR3.3
RIR3.2
RIR3.1
RIR3.0
RAIS-CI
40 of 119
DS21Q42
SR1: STATUS REGISTER 1 (Address=20 Hex)
(MSB)
LUP
(LSB)
RLOS
LDN
LOTC
RSLIP
RBL
RYEL
RCL
SYMBOL
POSITION
SR1.7
NAME AND DESCRIPTION
LUP
LDN
Loop Up Code Detected. Set when the loop up code as
defined in the RUPCD register is being received. See Section
16 for details.
Loop Down Code Detected. Set when the loop down code as
defined in the RDNCD register is being received. See Section
16 for details.
Loss of Transmit Clock. Set when the TCLK pin has not
transitioned for one channel time (or 5.2 us). Will force the
RLOS/LOTC pin high if enabled via CCR3.5. Also will force
transmit side formatter to switch to RCLK if so enabled via
TCR1.7.
SR1.6
SR1.5
LOTC
RSLIP
RBL
SR1.4
SR1.3
SR1.2
SR1.1
SR1.0
Receive Elastic Store Slip Occurrence. Set when the receive
elastic store has either repeated or deleted a frame.
Receive Blue Alarm. Set when an unframed all one’s code is
received at RPOS and RNEG.
Receive Yellow Alarm. Set when a yellow alarm is received
at RPOS and RNEG.
Receive Carrier Loss. Set when a red alarm is received at
RPOS and RNEG.
Receive Loss of Sync. Set when the device is not
synchronized to the receive T1 stream.
RYEL
RCL
RLOS
41 of 119
DS21Q42
ALARM CRITERIA Table 7-1
ALARM
SET CRITERIA
CLEAR CRITERIA
Blue Alarm (AIS)
(see note 1 below)
when over a 3 ms window, 5 or
less zeros are received
when over a 3 ms window, 6 or
more zeros are received
Yellow Alarm (RAI)
when bit 2 of 256 consecutive
when bit 2 of 256 consecutive
1. D4 bit 2 mode(RCR2.2=0)
channels is set to zero for at least channels is set to zero for less
254 occurrences
than 254 occurrences
2. D4 12th F–bit mode
when the 12th framing bit is set
when the 12th framing bit is set
to zero for two consecutive
occurrences
(RCR2.2=1; this mode is also to one for two consecutive
referred to as the “Japanese
Yellow Alarm”)
occurrences
3. ESF mode
when 16 consecutive patterns of
00FF appear in the FDL
when 14 or less patterns of 00FF
hex out of 16 possible appear in
the FDL
Red Alarm (RCL) (this alarm is when 192 consecutive zeros are
when 14 or more ones out of 112
possible bit positions are received
starting with the first one
received
also referred to as Loss Of
Signal)
received
Notes:
1. The definition of Blue Alarm (or Alarm Indication Signal) is an unframed all ones signal. Blue alarm
detectors should be able to operate properly in the presence of a 10–3 error rate and they should not
falsely trigger on a framed all ones signal. The blue alarm criteria in the DS21Q42 has been set to
achieve this performance. It is recommended that the RBL bit be qualified with the RLOS bit.
2. ANSI specifications use a different nomenclature than the DS21Q42 does; the following terms are
equivalent:
RBL = AIS
RCL = LOS
RLOS = LOF
RYEL = RAI
42 of 119
DS21Q42
SR2: STATUS REGISTER 2 (Address=21 Hex)
(MSB)
(LSB)
RMF
TMF
SEC
RFDL
TFDL
RMTCH
RAF
RSC
SYMBOL
POSITION
NAME AND DESCRIPTION
RMF
TMF
SEC
SR2.7
SR2.6
SR2.5
Receive Multiframe. Set on receive multiframe boundaries.
Transmit Multiframe. Set on transmit multiframe boundaries.
One Second Timer. Set on increments of one second based on
RCLK; will be set in increments of 999 ms, 999 ms, and 1002
ms every 3 seconds.
RFDL
TFDL
RMTCH
RAF
SR2.4
SR2.3
SR2.2
SR2.1
SR2.0
Receive FDL Buffer Full. Set when the receive FDL buffer
(RFDL) fills to capacity (8 bits).
Transmit FDL Buffer Empty. Set when the transmit FDL
buffer (TFDL) empties.
Receive FDL Match Occurrence. Set when the RFDL
matches either RMTCH1 or RMTCH2.
Receive FDL Abort. Set when eight consecutive one’s are
received in the FDL.
RSC
Receive Signaling Change. Set when the DS21Q42 detects a
change of state in any of the robbed–bit signaling bits.
IMR1: INTERRUPT MASK REGISTER 1 (Address=7F Hex)
(MSB)
(LSB)
(LSB)
LUP
LDN
LOTC
SLIP
RBL
RYEL
RCL
RLOS
SYMBOL
POSITION
IMR1.7
NAME AND DESCRIPTION
LUP
LDN
LOTC
SLIP
RBL
Loop Up Code Detected.
0 = interrupt masked
1 = interrupt enabled
Loop Down Code Detected.
0 = interrupt masked
1 = interrupt enabled
Loss of Transmit Clock.
0 = interrupt masked
1 = interrupt enabled
Elastic Store Slip Occurrence.
0 = interrupt masked
1 = interrupt enabled
Receive Blue Alarm.
0 = interrupt masked
1 = interrupt enabled
Receive Yellow Alarm.
0 = interrupt masked
1 = interrupt enabled
IMR1.6
IMR1.5
IMR1.4
IMR1.3
IMR1.2
RYE
43 of 119
DS21Q42
SYMBOL
POSITION
NAME AND DESCRIPTION
Receive Carrier Loss.
0 = interrupt masked
RCL
IMR1.1
1 = interrupt enabled
Receive Loss of Sync.
0 = interrupt masked
RLOS
IMR1.0
1 = interrupt enabled
IMR2: INTERRUPT MASK REGISTER 2 (Address=6F Hex)
(MSB)
(LSB)
(LSB)
RMF
TMF
SEC
RFDL
TFDL
RMTCH
RAF
RSC
SYMBOL
POSITION
NAME AND DESCRIPTION
Receive Multiframe.
0 = interrupt masked
RMF
IMR2.7
1 = interrupt enabled
Transmit Multiframe.
0 = interrupt masked
1 = interrupt enabled
One Second Timer.
TMF
IMR2.6
IMR2.5
IMR2.4
IMR2.3
IMR2.2
IMR2.1
IMR2.0
SEC
0 = interrupt masked
1 = interrupt enabled
Receive FDL Buffer Full.
0 = interrupt masked
1 = interrupt enabled
Transmit FDL Buffer Empty.
0 = interrupt masked
1 = interrupt enabled
Receive FDL Match Occurrence.
0 = interrupt masked
1 = interrupt enabled
Receive FDL Abort.
0 = interrupt masked
RFDL
TFDL
RMTCH
RAF
1 = interrupt enabled
Receive Signaling Change.
0 = interrupt masked
RSC
1 = interrupt enabled
44 of 119
DS21Q42
8. ERROR COUNT REGISTERS
There are a set of three counters in each framer that record bipolar violations, excessive zeros, errors in
the CRC6 code words, framing bit errors, and number of multiframes that the device is out of receive
synchronization. Each of these three counters are automatically updated on either one second boundaries
(CCR3.2=0) or every 42 ms (CCR3.2=1) as determined by the timer in Status Register 2 (SR2.5). Hence,
these registers contain performance data from either the previous second or the previous 42 ms. The user
can use the interrupt from the one second timer to determine when to read these registers. The user has a
full second (or 42 ms) to read the counters before the data is lost. All three counters will saturate at their
respective maximum counts and they will not rollover (note: only the Line Code Violation Count Register
has the potential to overflow but the bit error would have to exceed 10 -2 before this would occur).
Line Code Violation Count Register (LCVCR)
Line Code Violation Count Register 1 (LCVCR1) is the most significant word and LCVCR2 is the least
significant word of a 16–bit counter that records code violations (CVs). CVs are defined as Bipolar
Violations (BPVs) or excessive zeros. See Table 8-1 for details of exactly what the LCVCRs count. If the
B8ZS mode is set for the receive side via CCR2.2, then B8ZS code words are not counted. This counter is
always enabled; it is not disabled during receive loss of synchronization (RLOS=1) conditions.
LCVCR1: LINE CODE VIOLATION COUNT REGISTER 1 (Address = 23 Hex)
LCVCR2: LINE CODE VIOLATION COUNT REGISTER 2 (Address = 24 Hex)
(MSB)
LCV15
LCV7
(LSB)
LCV8
LCV0
LCV14
LCV6
LCV13
LCV5
LCV12
LCV4
LCV11
LCV3
LCV10
LCV2
LCV9
LCV1
LCVCR1
LCVCR2
SYMBOL
POSITION
NAME AND DESCRIPTION
LCV15
LCV0
LCVCR1.7
LCVCR2.0
MSB of the 16–bit code violation count
LSB of the 16–bit code violation count
LINE CODE VIOLATION COUNTING ARRANGEMENTS Table 8-1
COUNT EXCESSIVE
B8ZS ENABLED?
(CCR2.2)
WHAT IS COUNTED
IN THE LCVCRs
ZEROS?
(RCR1.7)
no
no
no
yes
BPVs
yes
no
BPVs + 16 consecutive zeros
BPVs (B8ZS code words not
counted)
yes
yes
BPV’s + 8 consecutive zeros
45 of 119
DS21Q42
Path Code Violation Count Register
(PCVCR) When the receive side of a framer is set to operate in the ESF framing mode (CCR2.3=1),
PCVCR will automatically be set as a 12–bit counter that will record errors in the CRC6 code words.
When set to operate in the D4 framing mode (CCR2.3=0), PCVCR will automatically count errors in the
Ft framing bit position. Via the RCR2.1 bit, a framer can be programmed to also report errors in the Fs
framing bit position. The PCVCR will be disabled during receive loss of synchronization (RLOS=1)
conditions. See Table 8-2 for a detailed description of exactly what errors the PCVCR counts.
PCVCR1: PATH VIOLATION COUNT REGISTER 1 (Address = 25 Hex)
PCVCR2: PATH VIOLATION COUNT REGISTER 2 (Address = 26 Hex)
(MSB)
(note 1)
(LSB)
CRC/
FB8
CRC/
FB0
(note 1)
(note 1)
(note 1)
CRC/
FB11
CRC/
FB3
CRC/
FB10
CRC/
FB2
CRC/
FB9
CRC/
FB1
PCVCR1
PCVCR2
CRC/
FB7
CRC/
FB6
CRC/
FB5
CRC/
FB4
SYMBOL
CRC/FB11
CRC/FB0
POSITION
PCVCR1.3
PCVCR2.0
NAME AND DESCRIPTION
MSB of the 12–Bit CRC6 Error or Frame Bit Error
Count (note#2)
LSB of the 12–Bit CRC6 Error or Frame Bit Error Count
(note#2)
Notes:
1. The upper nibble of the counter at address 25 is used by the Multiframes Out of Sync Count Register
2. PCVCR counts either errors in CRC code words (in the ESF framing mode; CCR2.3=1) or errors in
the framing bit position (in the D4 framing mode; CCR2.3=0).
PATH CODE VIOLATION COUNTING ARRANGEMENTS Table 8-2
FRAMING MODE
COUNT Fs ERRORS?
WHAT IS COUNTED IN THE
PCVCRs
errors in the Ft pattern
errors in both the Ft & Fs
patterns
(CCR2.3)
D4
(RCR2.1)
no
D4
yes
ESF
don’t care
errors in the CRC6 code words
46 of 119
DS21Q42
MULTIFRAMES OUT OF SYNC COUNT REGISTER (MOSCR)
Normally the MOSCR is used to count the number of multiframes that the receive synchronizer is out of
sync (RCR2.0=1). This number is useful in ESF applications needing to measure the parameters Loss Of
Frame Count (LOFC) and ESF Error Events as described in AT&T publication TR54016. When the
MOSCR is operated in this mode, it is not disabled during receive loss of synchronization (RLOS=1)
conditions. The MOSCR has alternate operating mode whereby it will count either errors in the Ft
framing pattern (in the D4 mode) or errors in the FPS framing pattern (in the ESF mode). When the
MOSCR is operated in this mode, it is disabled during receive loss of synchronization (RLOS = 1)
conditions.
See Table 8-3 for a detailed description of what the MOSCR is capable of counting.
MOSCR1: MULTIFRAMES OUT OF SYNC COUNT REGISTER 1
(Address = 25 Hex)
MOSCR2: MULTIFRAMES OUT OF SYNC COUNT REGISTER 2
(Address = 27 Hex)
(MSB)
MOS/
FB11
MOS/
FB7
(LSB)
(note 1) MOSCR
1
MOS/
FB10
MOS/
FB6
MOS/
FB9
MOS/
FB5
MOS/
FB8
MOS/
FB4
(note 1)
(note 1)
(note 1)
MOS/
FB3
MOS/
FB2
MOS/
FB1
MOS/
FB0
MOSCR
2
SYMBOL
POSITION
MOSCR1.7
MOSCR2.0
NAME AND DESCRIPTION
MOS/FB11
MOS/FB0
MSB of the 12–Bit Multiframes Out of Sync or F–Bit Error
Count (note #2)
LSB of the 12–Bit Multiframes Out of Sync or F–Bit Error
Count (note #2)
Notes:
1. The lower nibble of the counter at address 25 is used by the Path Code Violation Count Register
2. MOSCR counts either errors in framing bit position (RCR2.0=0) or the number of multiframes out of
sync (RCR2.0=1)
47 of 119
DS21Q42
MULTIFRAMES OUT OF SYNC COUNTING ARRANGEMENTS Table 8-3
FRAMING
MODE
(CCR2.3)
COUNT MOS
OR F–BIT
ERRORS
(RCR2.0)
MOS
WHAT IS COUNTED IN THE MOSCRs
D4
D4
number of multiframes out of sync
errors in the Ft pattern
F–Bit
ESF
ESF
MOS
F–Bit
number of multiframes out of sync
errors in the FPS pattern
9. DS0 MONITORING FUNCTION
Each framer in the DS21Q42 has the ability to monitor one DS0 64 Kbps channel in the transmit
direction and one DS0 channel in the receive direction at the same time. In the transmit direction the user
will determine which channel is to be monitored by properly setting the TCM0 to TCM4 bits in the CCR5
register. In the receive direction, the RCM0 to RCM4 bits in the CCR6 register need to be properly set.
The DS0 channel pointed to by the TCM0 to TCM4 bits will appear in the Transmit DS0 Monitor
(TDS0M) register and the DS0 channel pointed to by the RCM0 to RCM4 bits will appear in the Receive
DS0 (RDS0M) register. The TCM4 to TCM0 and RCM4 to RCM0 bits should be programmed with the
decimal decode of the appropriate T1 channel. For example, if DS0 channel 6 (timeslot 5) in the transmit
direction and DS0 channel 15 (timeslot 14) in the receive direction needed to be monitored, then the
following values would be programmed into CCR5 and CCR6:
TCM4 = 0
TCM3 = 0
TCM2 = 1
TCM1 = 0
TCM0 = 1
RCM4 = 0
RCM3 = 1
RCM2 = 1
RCM1 = 1
RCM0 = 0
CCR5: COMMON CONTROL REGISTER 5 (Address=19 Hex)
[repeated here from section 6 for convenience]
(MSB)
(LSB)
TJC
–
–
TCM4
TCM3
TCM2
TCM1
TCM0
SYMBOL
POSITION
NAME AND DESCRIPTION
TJC
–
–
CCR5.7
CCR5.5
CCR5.5
CCR5.4
Transmit Japanese CRC Enable. See Section 6 for details.
Not Assigned. Must be set to zero when written.
Not Assigned. Must be set to zero when written.
Transmit Channel Monitor Bit 4. MSB of a channel decode
that determines which transmit DS0 channel data will appear
in the TDS0M register.
TCM4
TCM3
TCM2
TCM1
TCM0
CCR5.3
CCR5.2
CCR5.1
CCR5.0
Transmit Channel Monitor Bit 3.
Transmit Channel Monitor Bit 2.
Transmit Channel Monitor Bit 1.
Transmit Channel Monitor Bit 0. LSB of the channel decode
that determines which transmit DS0 channel data will appear
in the TDS0M register.
48 of 119
DS21Q42
TDS0M: TRANSMIT DS0 MONITOR REGISTER (Address=1A Hex)
(MSB)
LSB)
B1
B2
B3
B4
B5
B6
B7
B8
SYMBOL
POSITION
TDS0M.7
NAME AND DESCRIPTION
B1
Transmit DS0 Channel Bit 1. MSB of the DS0 channel (first
bit to be transmitted).
B2
B3
B4
B5
B6
B7
B8
TDS0M.6
TDS0M.5
TDS0M.4
TDS0M.3
TDS0M.2
TDS0M.1
TDS0M.0
Transmit DS0 Channel Bit 2.
Transmit DS0 Channel Bit 3.
Transmit DS0 Channel Bit 4.
Transmit DS0 Channel Bit 5.
Transmit DS0 Channel Bit 6.
Transmit DS0 Channel Bit 7.
Transmit DS0 Channel Bit 8. LSB of the DS0 channel (last
bit to be transmitted).
CCR6: COMMON CONTROL REGISTER 6 (Address=1E Hex)
[repeated here from section 6 for convenience]
(MSB)
(LSB)
RJC
RESALGN TESALGN RCM4
RCM3
RCM2
RCM1
RCM0
SYMBOL
POSITION
NAME AND DESCRIPTION
Receive Japanese CRC6 Enable.
RJC
CCR6.7
0 = use ANSI/AT&T/ITU CRC6 calculation (normal
operation)
1 = use Japanese standard JT–G704 CRC6 calculation
Receive Elastic Store Align. Setting this bit from a zero to a
one will force the receive elastic store’s write/read pointers to
a minim separation of half a frame. If pointer separation is
already greater than half a frame, setting this bit will have no
effect. Should be toggled after RSYSCLK has been applied
and is stable. Must be cleared and set again for a subsequent
align. See Section 13 for details.
Transmit Elastic Store Align. Setting this bit from a zero to a
one will force the transmit elastic store’s write/read pointers to
a minimum separation of half a frame. If pointer separation is
already greater than half a frame, setting this bit will have no
effect. Should be toggled after TSYSCLK has been applied
and is stable. Must be cleared and set again for a subsequent
align. See Section 13 for details.
RESALGN
TESALGN
RCM4
CCR6.6
CCR6.5
CCR6.4
Receive Channel Monitor Bit 4. MSB of a channel decode
that determines which receive channel data will appear in the
RDS0M register. See Section 9 for details.
49 of 119
DS21Q42
SYMBOL
RCM3
RCM2
RCM1
RCM0
POSITION
CCR6.3
CCR6.2
CCR6.1
CCR6.0
NAME AND DESCRIPTION
Receive Channel Monitor Bit 3.
Receive Channel Monitor Bit 2.
Receive Channel Monitor Bit 1.
Receive Channel Monitor Bit 0. LSB of the channel decode.
RDS0M: RECEIVE DS0 MONITOR REGISTER (Address=1F Hex)
(MSB)
(LSB)
B1
B2
B3
B4
B5
B6
B7
B8
SYMBOL
POSITION
RDS0M.7
NAME AND DESCRIPTION
B1
Receive DS0 Channel Bit 1. MSB of the DS0 channel (first
bit to be received).
B2
B3
B4
B5
B6
B7
B8
RDS0M.6
RDS0M.5
RDS0M.4
RDS0M.3
RDS0M.2
RDS0M.1
RDS0M.0
Receive DS0 Channel Bit 2.
Receive DS0 Channel Bit 3.
Receive DS0 Channel Bit 4.
Receive DS0 Channel Bit 5.
Receive DS0 Channel Bit 6.
Receive DS0 Channel Bit 7.
Receive DS0 Channel Bit 8. LSB of the DS0 channel (last bit
to be received).
10. SIGNALING OPERATION
Each framer in the DS21Q42 contains provisions for both processor based (i.e., software based) signaling
bit access and for hardware based access. Both the processor based access and the hardware based access
can be used simultaneously if necessary. The processor based signaling is covered in Section 10.1 and the
hardware based signaling is covered in Section 10.2.
10.1 PROCESSOR BASED SIGNALING
The robbed–bit signaling bits embedded in the T1 stream can be extracted from the receive stream and
inserted into the transmit stream by each framer. There is a set of 12 registers for the receive side (RS1 to
RS12) and 12 registers on the transmit side (TS1 to TS12). The signaling registers are detailed below.
The CCR1.5 bit is used to control the robbed signaling bits as they appear at RSER. If CCR1.5 is set to
zero, then the robbed signaling bits will appear at the RSER pin in their proper position as they are
received. If CCR1.5 is set to a one, then the robbed signaling bit positions will be forced to a one at
RSER. If hardware based signaling is being used, then CCR1.5 must be set to zero.
50 of 119
DS21Q42
RS1 TO RS12: RECEIVE SIGNALING REGISTERS (Address=60 to 6B Hex)
(MSB)
A(8)
(LSB)
A(1)
A(7)
A(6)
A(5)
A(4)
A(3)
A(2)
RS1 (60)
A(16)
A(24)
B(8)
B(16)
B(24)
A/C(8)
A/C(16) A/C(15)
A/C(24) A/C(23)
B/D(8)
A(15)
A(23)
B(7)
B(15)
B(23)
A/C(7)
A(14)
A(22)
B(6)
B(14)
A(13)
A(21)
B(5)
B(13)
B(21)
A/C(5)
A(12)
A(20)
B(4)
B(12)
B(20)
A/C(4)
A(11)
A(19)
B(3)
B(11)
B(19)
A/C(3)
A(10)
A(18)
B(2)
B(10)
B(18)
A/C(2)
A(9)
A(17)
B(1)
B(9)
B(17)
RS2 (61)
RS3 (62)
RS4 (63)
RS5 (64)
RS6 (65)
B(22)
A/C(6)
A/C(14)
A/C(22)
B/D(6)
B/D(14)
B/D(22)
A/C(1) RS7 (66)
A/C(13) A/C(12) A/C(11) A/C(10) A/C(9) RS8 (67)
A/C(21) A/C(20) A/C(19) A/C(18) A/C(17) RS9 (68)
B/D(5)
B/D(13) B/D(12) B/D(11) B/D(10) B/D(9) RS11 (6A)
B/D(21) B/D(20) B/D(19) B/D(18) B/D(17) RS12 (6B)
B/D(7)
B/D(4)
B/D(3)
B/D(2)
B/D(1) RS10 (69)
B/D(16) B/D(15)
B/D(24) B/D(23)
SYMBOL
POSITION
NAME AND DESCRIPTION
D(24)
A(1)
RS12.7
RS1.0
Signaling Bit D in Channel 24
Signaling Bit A in Channel 1
Each Receive Signaling Register (RS1 to RS12) reports the incoming robbed bit signaling from eight
DS0 channels. In the ESF framing mode, there can be up to four signaling bits per channel (A, B, C,
and D). In the D4 framing mode, there are only two signaling bits per channel (A and B). In the D4
framing mode, the framer will replace the C and D signaling bit positions with the A and B signaling bits
from the previous multiframe. Hence, whether the framer is operated in either framing mode, the user
needs only to retrieve the signaling bits every 3 ms. The bits in the Receive Signaling Registers are
updated on multiframe boundaries so the user can utilize the Receive Multiframe Interrupt in the Receive
Status Register 2 (SR2.7) to know when to retrieve the signaling bits. The Receive Signaling Registers
are frozen and not updated during a loss of sync condition (SR1.0=1). They will contain the most recent
signaling information before the “OOF” occurred. The signaling data reported in RS1 to RS12 is also
available at the RSIG and RSER pins.
A change in the signaling bits from one multiframe to the next will cause the RSC status bit (SR2.0) to be
set. The user can enable the INT* pin to toggle low upon detection of a change in signaling by setting the
IMR2.0 bit. Once a signaling change has been detected, the user has at least 2.75 ms to read the data out
of the RS1 to RS12 registers before the data will be lost.
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DS21Q42
TS1 TO TS12: TRANSMIT SIGNALING REGISTERS (Address=70 to 7B Hex)
(MSB)
A(8)
A(16)
A(24)
B(8)
B(16)
B(24)
A/C(8)
LSB)
A(1)
A(9)
A(17)
B(1)
A(7)
A(6)
A(5)
A(4)
A(3)
A(2)
TS1 (70)
TS2 (71)
TS3 (72)
TS4 (73)
TS5 (74)
TS7 (75)
TS7 (76)
TS8 (77)
A(15)
A(23)
B(7)
B(15)
B(23)
A/C(7)
A(14)
A(22)
B(6)
B(14)
B(22)
A(13)
A(21)
B(5)
B(13)
B(21)
A(12)
A(20)
B(4)
B(12)
B(20)
A/C(4)
A(11)
A(19)
B(3)
B(11)
B(19)
A/C(3)
A(10)
A(18)
B(2)
B(10)
B(18)
B(9)
B(17)
A/C(6) A/C(5)
A/C(2) A/C(1)
A/C(16) A/C(15) A/C(14) A/C(13) A/C(12) A/C(11) A/C(10) A/C(9)
A/C(24) A/C(23) A/C(22) A/C(21) A/C(20) A/C(19) A/C(18) A/C(17) TS9 (78)
B/D(8)
B/D(7)
B/D(6)
B/D(5)
B/D(4)
B/D(3)
B/D(2)
B/D(1)
TS10 (79)
TS11 (7A)
B/D(16) B/D(15) B/D(14) B/D(13) B/D(12) B/D(11) B/D(10) B/D(9)
B/D(24) B/D(23) B/D(22) B/D(21) B/D(20) B/D(19) B/D(18) B/D(17) TS12 (7B)
SYMBOL
POSITION
NAME AND DESCRIPTION
D(24)
A(1)
TS12.7
TS1.0
Signaling Bit D in Channel 24
Signaling Bit A in Channel 1
Each Transmit Signaling Register (TS1 to TS12) contains the Robbed Bit signaling for eight DS0
channels that will be inserted into the outgoing stream if enabled to do so via TCR1.4. In the ESF framing
mode, there can be up to four signaling bits per channel (A, B, C, and D). On multiframe boundaries, the
framer will load the values present in the Transmit Signaling Register into an outgoing signaling shift
register that is internal to the device. The user can utilize the Transmit Multiframe Interrupt in Status
Register 2 (SR2.6) to know when to update the signaling bits. In the ESF framing mode, the interrupt will
come every 3 ms and the user has a full 3ms to update the TSRs. In the D4 framing mode, there are only
two signaling bits per channel (A and B). However in the D4 framing mode, the framer uses the C and D
bit positions as the A and B bit positions for the next multiframe. The framer will load the values in the
TSRs into the outgoing shift register every other D4 multiframe.
10.2 HARDWARE BASED SIGNALING
Receive Side
In the receive side of the hardware based signaling, there are two operating modes for the signaling
buffer; signaling extraction and signaling re–insertion. Signaling extraction involves pulling the signaling
bits from the receive data stream and buffering them over a four multiframe buffer and outputting them in
a serial PCM fashion on a channel–by–channel basis at the RSIG output. This mode is always enabled. In
this mode, the receive elastic store may be enabled or disabled. If the receive elastic store is enabled, then
the backplane clock (RSYSCLK) can be either 1.544 MHz or 2.048 MHz. In the ESF framing mode, the
ABCD signaling bits are output on RSIG in the lower nibble of each channel. The RSIG data is updated
once a multiframe (3 ms) unless a freeze is in effect. In the D4 framing mode, the AB signaling bits are
output twice on RSIG in the lower nibble of each channel. Hence, bits 5 and 6 contain the same data as
bits 7 and 8 respectively in each channel. The RSIG data is updated once a multiframe (1.5 ms) unless a
freeze is in effect. See the timing diagrams in Section 20 for some examples.
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DS21Q42
The other hardware based signaling operating mode called signaling re–insertion can be invoked by
setting the RSRE control bit high (CCR4.7=1). In this mode, the user will provide a multiframe sync at
the RSYNC pin and the signaling data will be re–aligned at the RSER output according to this applied
multiframe boundary. In this mode, the elastic store must be enabled however the backplane clock can be
either 1.544 MHz or 2.048 MHz.
If the signaling re–insertion mode is enabled, the user can control which channels have signaling re–
insertion performed on a channel–by–channel basis by setting the RPCSI control bit high (CCR4.6) and
then programming the RCHBLK output pin to go high in the channels in which the signaling re–insertion
should not occur. If the RPCSI bit is set low, then signaling re–insertion will occur in all channels when
the signaling re–insertion mode is enabled (RSRE=1). How to control the operation of the RCHBLK
output pin is covered in Section 12.
In both hardware based signaling operating modes, the user has the option to replace all of the extracted
robbed–bit signaling bit positions with ones. This option is enabled via the RFSA1 control bit (CCR4.5)
and it can be invoked on a per–channel basis by setting the RPCSI control bit (CCR4.6) high and then
programming RCHBLK appropriately just like the per–channel signaling re–insertion operates.
The signaling data in the four multiframe buffer will be frozen in a known good state upon either a loss of
synchronization (OOF event), carrier loss, or frame slip. This action meets the requirements of BellCore
TR– TSY–000170 for signaling freezing. To allow this freeze action to occur, the RFE control bit
(CCR4.4) should be set high. The user can force a freeze by setting the RFF control bit (CCR4.3) high.
The four multiframe buffer provides a three multiframe delay in the signaling bits provided at the RSIG
pin (and at the RSER pin if RSRE=1). When freezing is enabled (RFE=1), the signaling data will be held
in the last known good state until the corrupting error condition subsides. When the error condition
subsides, the signaling data will be held in the old state for at least an additional 9 ms (or 4.5 ms in D4
framing mode) before being allowed to be updated with new signaling data.
Transmit Side
Via the THSE control bit (CCR4.2), the framer can be set up to take the signaling data presented at the
TSIG pin and insert the signaling data into the PCM data stream that is being input at the TSER pin. The
user has the ability to control which channels are to have signaling data from the TSIG pin inserted into
them on a channel–by–channel basis by setting the TPCSI control bit (CCR4.1) high. When TPCSI is
enabled, channels in which the TCHBLK output has been programmed to be set high in, will not have
signaling data from the TSIG pin inserted into them. The hardware signaling insertion capabilities of the
framer are available whether the transmit side elastic store is enabled or disabled. If the elastic store is
enabled, the backplane clock (TSYSCLK) can be either 1.544 MHz or 2.048 MHz.
11. PER–CHANNEL CODE (IDLE) GENERATION AND LOOPBACK
Each framer in the DS21Q42 can replace data on a channel–by–channel basis in both the transmit and
receive directions. The transmit direction is from the backplane to the T1 line and is covered in Section
11.1. The receive direction is from the T1 line to the backplane and is covered in Section 11.2.
11.1 TRANSMIT SIDE CODE GENERATION
In the transmit direction there are two methods by which channel data from the backplane can be
overwritten with data generated by the framer. The first method which is covered in Section 11.1.1 was a
feature contained in the original DS21Q41 while the second method which is covered in Section 11.1.2 is
a new feature of the DS21Q42.
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DS21Q42
11.1.1 Simple Idle Code Insertion and Per–Channel Loopback
The first method involves using the Transmit Idle Registers (TIR1/2/3) to determine which of the 24 T1
channels should be overwritten with the code placed in the Transmit Idle Definition Register (TIDR).
This method allows the same 8–bit code to be placed into any of the 24 T1 channels. If this method is
used, then the CCR4.0 control bit must be set to zero.
Each of the bit position in the Transmit Idle Registers (TIR1/TIR2/TIR3) represent a DS0 channel in the
outgoing frame. When these bits are set to a one, the corresponding channel will transmit the Idle Code
contained in the Transmit Idle Definition Register (TIDR). Robbed bit signaling and Bit 7 stuffing will
occur over the programmed Idle Code unless the DS0 channel is made transparent by the Transmit
Transparency Registers.
The Transmit Idle Registers (TIRs) have an alternate function that allow them to define a Per–Channel
LoopBack (PCLB). If the TIRFS control bit (CCR4.0) is set to one, then the TIRs will determine which
channels (if any) from the backplane should be replaced with the data from the receive side or in other
words, off of the T1 line. If this mode is enabled, then transmit and receive clocks and frame syncs must
be synchronized. One method to accomplish this would be to tie RCLK to TCLK and RFSYNC to
TSYNC.
TIR1/TIR2/TIR3: TRANSMIT IDLE REGISTERS (Address=3C to 3E Hex)
[Also used for Per–Channel Loopback]
(MSB)
CH8
CH16
CH24
(LSB)
CH1
CH9
CH7
CH15
CH23
CH6
CH14
CH22
CH5
CH13
CH21
CH4
CH12
CH20
CH3
CH11
CH19
CH2
CH10
CH18
TIR1 (3C)
TIR2 (3D)
TIR3 (3E)
CH17
SYMBOLS POSITIONS NAME AND DESCRIPTION
CH1 – 24
TIR1.0 - 3.7
Transmit Idle Code Insertion Control Bits.
0 = do not insert the Idle Code in the TIDR into this channel
1 = insert the Idle Code in the TIDR into this channel
Note:
If CCR4.0=1, then a zero in the TIRs implies that channel data is to be sourced from TSER and a one
implies that channel data is to be sourced from the output of the receive side framer (i.e., Per–Channel
Loopback; see Figure 1–1).
TIDR: TRANSMIT IDLE DEFINITION REGISTER (Address=3F Hex)
(MSB)
(LSB)
TIDR7
TIDR6
TIDR5
TIDR4
TIDR3
TIDR2
TIDR1
TIDR0
SYMBOL
POSITION
NAME AND DESCRIPTION
TIDR7
TIDR0
TIDR.7
TIDR.0
MSB of the Idle Code (this bit is transmitted first)
LSB of the Idle Code (this bit is transmitted last)
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DS21Q42
11.1.2 Per–Channel Code Insertion
The second method involves using the Transmit Channel Control Registers (TCC1/2/3) to determine
which of the 24 T1 channels should be overwritten with the code placed in the Transmit Channel
Registers (TC1 to TC24). This method is more flexible than the first in that it allows a different 8–bit
code to be placed into each of the 24 T1 channels.
TC1 TO TC24: TRANSMIT CHANNEL REGISTERS
(Address=40 to 4F and 50 to 57 Hex)
(for brevity, only channel one is shown; see Table 4-1 for other register address)
(MSB)
(LSB)
C7
C6
C5
C4
C3
C2
C1
C0
TC1 (50)
SYMBOL
POSITION
TC1.7
NAME AND DESCRIPTION
MSB of the Code (this bit is transmitted first)
LSB of the Code (this bit is transmitted last)
C7
C0
TC1.0
TCC1/TCC2/TCC3: TRANSMIT CHANNEL CONTROL REGISTER
(Address=16 to 18 Hex)
(MSB)
CH8
CH16
CH24
(LSB)
CH1
CH9
CH7
CH15
CH23
CH6
CH14
CH22
CH5
CH13
CH21
CH4
CH12
CH20
CH3
CH11
CH19
CH2
CH10
CH18
TCC1 (16)
TCC2 (17)
TCC3 (18)
CH17
SYMBOL
CH1 – 24
POSITION
TCC1.0 - 3.7
NAME AND DESCRIPTION
Transmit Code Insertion Control Bits
0 = do not insert data from the TC register into the transmit
data stream
1 = insert data from the TC register into the transmit data
stream
11.2 RECEIVE SIDE CODE GENERATION
In the receive direction there are also two methods by which channel data to the backplane can be
overwritten with data generated by the framer. The first method which is covered in Section 11.2.1 was a
feature contained in the original DS21Q41 while the second method which is covered in Section 11.2.2 is
a new feature of the DS21Q42.
11.2.1 Simple Code Insertion
The first method on the receive side involves using the Receive Mark Registers (RMR1/2/3) to determine
which of the 24 T1 channels should be overwritten with either a 7Fh idle code or with a digital milliwatt
pattern. The RCR2.7 bit will determine which code is used. The digital milliwatt code is an eight byte
repeating pattern that represents a 1 KHz sine wave (1E/0B/0B/1E/9E/8B/8B/9E). Each bit in the RMRs,
represents a particular channel. If a bit is set to a one, then the receive data in that channel will be
replaced with one of the two codes. If a bit is set to zero, no replacement occurs.
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DS21Q42
RMR1/RMR2/RMR3: RECEIVE MARK REGISTERS
(Address=2D to 2F Hex)
(MSB)
(LSB)
CH1
CH9
CH8
CH16
CH24
CH7
CH15
CH23
CH6
CH14
CH22
CH5
CH13
CH21
CH4
CH12
CH20
CH3
CH11
CH19
CH2
CH10
CH18
RMR1 (2D)
RMR2 (2E)
RMR3 (2F)
CH17
SYMBOLS
POSITIONS
NAME AND DESCRIPTION
CH1 – 24
RMR1.0 - 3.7
Receive Channel Mark Control Bits
0 =do not affect the receive data associated with this channel
1 = replace the receive data associated with this channel with
either the idle code or the digital milliwatt code (depends on
the RCR2.7 bit)
11.2.2 Per–Channel Code Insertion
The second method involves using the Receive Channel Control Registers (RCC1/2/3) to determine
which of the 24 T1 channels off of the T1 line and going to the backplane should be overwritten with the
code placed in the Receive Channel Registers (RC1 to RC24). This method is more flexible than the first
in that it allows a different 8–bit code to be placed into each of the 24 T1 channels.
RC1 TO RC24: RECEIVE CHANNEL REGISTERS
(Address=58 to 5F and 80 to 8F Hex)
(for brevity, only channel one is shown; see Table 4-1 for other register address)
(MSB)
(LSB)
C7
C6
C5
C4
C3
C2
C1
C0
RC1 (80)
SYMBOL
POSITION
NAME AND DESCRIPTION
C7
C0
RC1.7
RC1.0
MSB of the Code (this bit is sent first to the backplane)
LSB of the Code (this bit is sent last to the backplane)
RCC1/RCC2/RCC3: RECEIVE CHANNEL CONTROL REGISTER
(Address=1B to 1D Hex)
(MSB)
CH8
CH16
CH24
(LSB)
CH1
CH9
CH7
CH15
CH23
CH6
CH14
CH22
CH5
CH13
CH21
CH4
CH12
CH20
CH3
CH11
CH19
CH2
CH10
CH18
RCC1 (1B)
RCC2 (1C)
CH17 RCC3 (1D)
SYMBOL
CH1 – 24
POSITION
RCC1.0 - 3.7
NAME AND DESCRIPTION
Receive Code Insertion Control Bits
0 = do not insert data from the RC register into the receive data
stream
1 = insert data from the RC register into the receive data
stream
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DS21Q42
12. CLOCK BLOCKING REGISTERS
The Receive Channel Blocking Registers (RCBR1/RCBR2/RCBR3) and the Transmit Channel Blocking
Registers (TCBR1/TCBR2/TCBR3) control the RCHBLK and TCHBLK pins respectively. The
RCHBLK and TCHCLK pins are user programmable outputs that can be forced either high or low during
individual channels. These outputs can be used to block clocks to a USART or LAPD controller in
Fractional T1 or ISDN–PRI applications. When the appropriate bits are set to a one, the RCHBLK and
TCHCLK pins will be held high during the entire corresponding channel time. See the timing in Section
20 for an example.
RCBR1/RCBR2/RCBR3: RECEIVE CHANNEL BLOCKING REGISTERS
(Address=6C to 6E Hex)
(MSB)
CH8
CH16
CH24
(LSB)
CH1
CH9
CH7
CH15
CH23
CH6
CH14
CH22
CH5
CH13
CH21
CH4
CH12
CH20
CH3
CH11
CH19
CH2
CH10
CH18
RCBR1 (6C)
RCBR2 (6D)
RCBR3 (6E)
CH17
SYMBOLS
CH1 – 24
POSITIONS
RCBR1.0 - 3.7
NAME AND DESCRIPTION
Receive Channel Blocking Control Bits.
0 = force the RCHBLK pin to remain low during this channel
time
1 = force the RCHBLK pin high during this channel time
TCBR1/TCBR2/TCBR3: TRANSMIT CHANNEL BLOCKING REGISTERS
(Address=32 to 34 Hex)
(MSB)
CH8
CH16
CH24
(LSB)
CH1
CH9
CH7
CH15
CH23
CH6
CH14
CH22
CH5
CH13
CH21
CH4
CH12
CH20
CH3
CH11
CH19
CH2
CH10
CH18
TCBR1 (32)
TCBR2 (33)
CH17 TCBR3 (34)
SYMBOLS
CH1 – 24
POSITIONS
TCBR1.0 - 3.7
NAME AND DESCRIPTION
Transmit Channel Blocking Control Bits.
0 = force the TCHBLK pin to remain low during this channel
time
1 = force the TCHBLK pin high during this channel time
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DS21Q42
13. ELASTIC STORES OPERATION
Each framer in the DS21Q42 contains dual two–frame (386 bits) elastic stores, one for the receive
direction, and one for the transmit direction. These elastic stores have two main purposes. First, they can
be used to rate convert the T1 data stream to 2.048 Mbps (or a multiple of 2.048 Mbps) which is the E1
rate. Secondly, they can be used to absorb the differences in frequency and phase between the T1 data
stream and an asynchronous (i.e., not frequency locked) backplane clock (which can be 1.544 MHz or
2.048 MHz). The backplane clock can burst at rates up to 8.192 MHz. Both elastic stores contain full
controlled slip capability which is necessary for this second purpose. Both elastic stores within the framer
are fully independent and no restrictions apply to the sourcing of the various clocks that are applied to
them. The transmit side elastic store can be enabled whether the receive elastic store is enabled or
disabled and vice versa. Also, each elastic store can interface to either a 1.544 MHz or 2.048 MHz
backplane without regard to the backplane rate the other elastic store is interfacing.
Two mechanisms are available to the user for resetting the elastic stores. The Elastic Store Reset (TX -
CCR7.4 & RX - CCR7.5) function forces the elastic stores to a depth of one frame unconditionally. Data
is lost during the reset. The second method, the Elastic Store Align (TX - CCR6.5 & RX - CCR6.6)
forces the elastic store depth to a minimum depth of half a frame only if the current pointer separation is
already less then half a frame. If a realignment occurs data is lost. In both mechanisms, independent
resets are provided for both the receive and transmit elastic stores.
13.1 RECEIVE SIDE
If the receive side elastic store is enabled (CCR1.2=1), then the user must provide either a 1.544 MHz
(CCR1.3=0) or 2.048 MHz (CCR1.3=1) clock at the RSYSCLK pin. The user has the option of either
providing a frame/multiframe sync at the RSYNC pin (RCR2.3=1) or having the RSYNC pin provide a
pulse on frame boundaries (RCR2.3=0). If the user wishes to obtain pulses at the frame boundary, then
RCR2.4 must be set to zero and if the user wishes to have pulses occur at the multiframe boundary, then
RCR2.4 must be set to one. The framer will always indicate frame boundaries via the RFSYNC output
whether the elastic store is enabled or not. If the elastic store is enabled, then multiframe boundaries will
be indicated via the RMSYNC output. If the user selects to apply a 2.048 MHz clock to the RSYSCLK
pin, then the data output at RSER will be forced to all ones every fourth channel. Hence channels 1
(except for the MSB), 5, 9, 13, 17, 21, 25, and 29 (timeslots 0, 4, 8, 12, 16, 20, 24, and 28) will be forced
to a one. The F–bit will be passed in the MSB of channel 1. Also, in 2.048 MHz applications, the
RCHBLK output will be forced high during the same channels as the RSER pin. See Section 19 for more
details. This is useful in T1 to CEPT (E1) conversion applications. If the 386–bit elastic buffer either fills
or empties, a controlled slip will occur. If the buffer empties, then a full frame of data (193 bits) will be
repeated at RSER and the SR1.4 and RIR1.3 bits will be set to a one. If the buffer fills, then a full frame
of data will be deleted and the SR1.4 and RIR1.4 bits will be set to a one.
13.2 TRANSMIT SIDE
The operation of the transmit elastic store is very similar to the receive side. The transmit side elastic
store is enabled via CCR1.7. A 1.544 MHz (CCR1.4=0) or 2.048 MHz (CCR1.4=1) clock can be applied
to the TSYSCLK input. If the user selects to apply a 2.048 MHz clock to the TSYSCLK pin, then the data
input at TSER will be ignored every fourth channel. Hence channels 1 (except for the MSB), 5, 9, 13, 17,
21, 25, and 29 (timeslots 0, 4, 8, 12, 16, 20, 24, and 28) will be ignored. A special case exists for the MSB
of channel 1. Via TCR1.6 the MSB of channel 1 can be sampled as the F-bit. The user must supply a 8
KHz frame sync pulse to the TSSYNC input. Also, in 2.048 MHz applications, the TCHBLK output will
be forced high during the channels ignored by the framer. See Section 19 for more details. Controlled
slips in the transmit elastic store are reported in the RIR2.3 bit and the direction of the slip is reported in
the RIR2.5 and RIR2.4 bits.
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DS21Q42
13.3 MINIMUM DELAY SYNCHRONOUS RSYSCLK/TSYSCLK MODE
In applications where the framer is connected to backplanes that are frequency locked to the recovered T1
clock (i.e., the RCLK output), the full two frame depth of the onboard elastic stores is really not needed.
In fact, in some delay sensitive applications, the normal two frame depth may be excessive. Register bits
CCR3.7 and CCR3.0 control the RX and TX elastic stores depths. In this mode, RSYSCLK and
TSYSCLK must be tied together and they must be frequency locked to RCLK. All of the slip contention
logic in the framer is disabled (since slips cannot occur). Also, since the buffer depth is no longer two
frames deep, the framer must be set up to source a frame pulse at the RSYNC pin and this output must be
tied to the TSSYNC input. On power–up after the RSYSCLK and TSYSCLK signals have locked to the
RCLK signal, the elastic stores should be reset.
14. HDLC CONTROLLER
The DS21Q42 has an enhanced HDLC controller configurable for use with the Facilities Data Link or
DS0s. There are 64 byte buffers in both the transmit and receive paths. The user can select any DS0 or
multiple DS0s as well as any specific bits within the DS0(s) to pass through the HDLC controller. See
Figure 20-15 for details on formatting the transmit side. Note that TBOC.6 = 1 and TDC1.7 = 1 cannot
exist without corrupting the data in the FDL. For use with the FDL, see section 15.1. See Table 14-1 for
configuring the transmit HDLC controller.
Four new registers were added for the enhanced functionality of the HDLC controller; RDC1, RDC2,
TDC1, and TDC2. Note that the BOC controller is functional when the HDLC controller is used for
DS0s. Section 15 contains all of the HDLC and BOC registers and information on FDL/Fs Extraction and
Insertion with and without the HDLC controller.
Transmit HDLC Configuration Table 14-1
Function
TBOC.6
TDC1.7
TCR1.2
1 or 0
1
DS0(s)
FDL
Disable
0
1
0
1
0
0
1 or 0
14.1 HDLC for DS0s
When using the HDLC controllers for DS0s, the same registers shown in section 15 will be used except
for the TBOC and RBOC registers and bits HCR.7, HSR.7, and HIMR.7. As a basic guideline for
interpreting and sending HDLC messages and BOC messages, the following sequences can be applied.
Receive a HDLC Message
1. Enable RPS interrupts
2. Wait for interrupt to occur
3. Disable RPS interrupt and enable either RPE, RNE, or RHALF interrupt
4. Read RHIR to obtain REMPTY status
a. If REMPTY=0, then record OBYTE, CBYTE, and POK bits and then read the FIFO
a1. If CBYTE=0 then skip to step 5
a2. If CBYTE=1 then skip to step 7
b. If REMPTY=1, then skip to step 6
5. Repeat step 4
6. Wait for interrupt, skip to step 4
7. If POK=0, then discard whole packet, if POK=1, accept the packet
8. Disable RPE, RNE, or RHALF interrupt, enable RPS interrupt and return to step 1.
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Transmit a HDLC Message
1. Make sure HDLC controller is done sending any previous messages and is current sending flags by
checking that the FIFO is empty by reading the TEMPTY status bit in the THIR register
2. Enable either the THALF or TNF interrupt
3. Read THIR to obtain TFULL status
a. If TFULL=0, then write a byte into the FIFO and skip to next step (special case occurs when
the last byte is to be written, in this case set TEOM=1 before writing the byte and then skip to
step 6)
b. If TFULL=1, then skip to step 5
4. Repeat step 3
5. Wait for interrupt, skip to step 3
6. Disable THALF or TNF interrupt and enable TMEND interrupt
7. Wait for an interrupt, then read TUDR status bit to make sure packet was transmitted correctly.
15. FDL/Fs EXTRACTION AND INSERTION
Each Framer/Formatter has the ability to extract/insert data from/ into the Facility Data Link (FDL) in the
ESF framing mode and from/into Fs–bit position in the D4 framing mode. Since SLC–96 utilizes the Fs-
bit position, this capability can also be used in SLC–96 applications. The DS21Q42 contains a complete
HDLC and BOC controller for the FDL and this operation is covered in Section 15.1. To allow for
backward compatibility between the DS21Q42 and earlier devices, the DS21Q42 maintains some legacy
functionality for the FDL and this is covered in Section 15.2. Section 15.3 covers D4 and SLC–96
operation. Please contact the factory for a copy of C language source code for implementing the FDL on
the DS21Q42.
15.1 HDLC AND BOC CONTROLLER FOR THE FDL
15.1.1 General Overview
The DS21Q42 contains a complete HDLC controller with 64–byte buffers in both the transmit and
receive directions as well as separate dedicated hardware for Bit Oriented Codes (BOC). The HDLC
controller performs all the necessary overhead for generating and receiving Performance Report
Messages (PRM) as described in ANSI T1.403 and the messages as described in AT&T TR54016. The
HDLC controller automatically generates and detects flags, generates and checks the CRC check sum,
generates and detects abort sequences, stuffs and destuffs zeros (for transparency), and byte aligns to the
HDLC data stream. The 64–byte buffers in the HDLC controller are large enough to allow a full PRM to
be received or transmitted without host intervention. The BOC controller will automatically detect
incoming BOC sequences and alert the host. When the BOC ceases, the DS21Q42 will also alert the host.
The user can set the device up to send any of the possible 6–bit BOC codes.
There are thirteen registers that the host will use to operate and control the operation of the HDLC and
BOC controllers. A brief description of the registers is shown in Table 15–1.
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HDLC/BOC CONTROLLER REGISTER LIST Table 15-1
NAME
FUNCTION
HDLC Control Register (HCR)
general control over the HDLC and BOC
controllers
HDLC Status Register (HSR)
key status information for both transmit and receive
directions
HDLC Interrupt Mask Register (HIMR)
Receive HDLC Information Register (RHIR)
Receive BOC Register (RBOC)
Receive HDLC FIFO Register (RHFR)
Receive HDLC DS0 Control Register 1 (RDC1)
Receive HDLC DS0 Control Register 2 (RDC2)
Transmit HDLC Information Register (THIR)
Transmit BOC Register (TBOC)
allows/stops status bits to/from causing an interrupt
status information on receive HDLC controller
status information on receive BOC controller
access to 64–byte HDLC FIFO in receive direction
controls the HDLC function when used on DS0
channels
status information on transmit HDLC controller
enables/disables transmission of BOC codes
access to 64–byte HDLC FIFO in transmit
direction
Transmit HDLC FIFO Register (THFR)
Transmit HDLC DS0 Control Register 1 (TDC1)
Transmit HDLC DS0 Control Register 2 (TDC2)
controls the HDLC function when used on DS0
channels
15.1.2 Status Register for the HDLC
Four of the HDLC/BOC controller registers (HSR, RHIR, RBOC, and THIR) provide status information.
When a particular event has occurred (or is occurring), the appropriate bit in one of these four registers
will be set to a one. Some of the bits in these four HDLC status registers are latched and some are real
time bits that are not latched. Section 15.1.4 contains register descriptions that list which bits are latched
and which are not. With the latched bits, when an event occurs and a bit is set to a one, it will remain set
until the user reads that bit. The bit will be cleared when it is read and it will not be set again until the
event has occurred again. The real time bits report the current instantaneous conditions that are occurring
and the history of these bits is not latched.
Like the other status registers in the DS21Q42, the user will always proceed a read of any of the four
registers with a write. The byte written to the register will inform the DS21Q42 which of the latched bits
the user wishes to read and have cleared (the real time bits are not affected by writing to the status
register). The user will write a byte to one of these registers, with a one in the bit positions he or she
wishes to read and a zero in the bit positions he or she does not wish to obtain the latest information on.
When a one is written to a bit location, the read register will be updated with current value and it will be
cleared. When a zero is written to a bit position, the read register will not be updated and the previous
value will be held. A write to the status and information registers will be immediately followed by a read
of the same register. The read result should be logically AND’ed with the mask byte that was just written
and this value should be written back into the same register to insure that bit does indeed clear. This
second write step is necessary because the alarms and events in the status registers occur asynchronously
in respect to their access via the parallel port. This write–read–write (for polled driven access) or write–
read (for interrupt driven access) scheme allows an external microcontroller or microprocessor to
individually poll certain bits without disturbing the other bits in the register. This operation is key in
controlling the DS21Q42 with higher–order software languages.
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Like the SR1 and SR2 status registers, the HSR register has the unique ability to initiate a hardware
interrupt via the INT* output pin. Each of the events in the HSR can be either masked or unmasked from
the interrupt pin via the HDLC Interrupt Mask Register (HIMR). Interrupts will force the INT* pin low
when the event occurs. The INT* pin will be allowed to return high (if no other interrupts are present)
when the user reads the event bit that caused the interrupt to occur.
Basic Operation Details
To allow the framer to properly source/receive data from/to the HDLC and BOC controller the legacy
FDL circuitry (which is described in Section 15.2) should be disabled and the following bits should be
programmed as shown:
TCR1.2 = 1 (source FDL data from the HDLC and BOC controller)
TBOC.6 = 1 (enable HDLC and BOC controller)
CCR2.5 = 0 (disable SLC–96 and D4 Fs–bit insertion)
CCR2.4 = 0 (disable legacy FDL zero stuffer)
CCR2.1 = 0 (disable SLC–96 reception)
CCR2.0 = 0 (disable legacy FDL zero stuffer)
IMR2.4 = 0 (disable legacy receive FDL buffer full interrupt)
IMR2.3 = 0 (disable legacy transmit FDL buffer empty interrupt)
IMR2.2 = 0 (disable legacy FDL match interrupt)
IMR2.1 = 0 (disable legacy FDL abort interrupt).
As a basic guideline for interpreting and sending both HDLC messages and BOC messages, the following
sequences can be applied:
Receive a HDLC Message or a BOC
1. Enable RBOC and RPS interrupts
2. Wait for interrupt to occur
3. If RBOC=1, then follow steps 5 and 6
4. If RPS=1, then follow steps 7 through 12
5. If LBD=1, a BOC is present, then read the code from the RBOC register and take action as needed
6. If BD=0, a BOC has ceased, take action as needed and then return to step 1
7. Disable RPS interrupt and enable either RPE, RNE, or RHALF interrupt
8. Read RHIR to obtain REMPTY status a. if REMPTY=0, then record OBYTE, CBYTE, and POK bits
and then read the FIFO a1. if CBYTE=0 then skip to step 9 a2. if CBYTE=1 then skip to step 11 b. if
REMPTY=1, then skip to step 10
9. Repeat step 8
10. Wait for interrupt, skip to step 8
11. If POK=0, then discard whole packet, if POK=1, accept the packet 12. disable RPE, RNE, or RHALF
interrupt, enable RPS interrupt and return to step 1.
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Transmit a HDLC Message
1. Make sure HDLC controller is done sending any previous messages and is current sending flags by
checking that the FIFO is empty by reading the TEMPTY status bit in the THIR register
2. Enable either the THALF or TNF interrupt
3. Read THIR to obtain TFULL status a. if TFULL=0, then write a byte into the FIFO and skip to next
step (special case occurs when the last byte is to be written, in this case set TEOM=1 before writing
the byte and then skip to step 6) b. if TFULL=1, then skip to step 5
4. Repeat step 3
5. Wait for interrupt, skip to step 3
6. Disable THALF or TNF interrupt and enable TMEND interrupt
7. Wait for an interrupt, then read TUDR status bit to make sure packet was transmitted correctly.
Transmit a BOC
1. Write 6–bit code into TBOC
2. Set SBOC bit in TBOC=1
15.1.3 HDLC/BOC Register Description
HCR: HDLC CONTROL REGISTER (Address = 00 Hex)
(MSB)
(LSB)
RBR
RHR
TFS
POSITION
HCR.7
THR
TABT
TEOM
TZSD
TCRCD
SYMBOL
NAME AND DESCRIPTION
RBR
RHR
TFS
Receive BOC Reset. A 0 to 1 transition will reset the BOC
circuitry. Must be cleared and set again for a subsequent reset.
Receive HDLC Reset. A 0 to 1 transition will reset the HDLC
controller. Must be cleared and set again for a subsequent reset.
Transmit Flag/Idle Select.
HCR.6
HCR.5
0 = 7Eh
1 = FFh
THR
HCR.4
HCR.3
Transmit HDLC/BOC Reset. A 0 to 1 transition will reset
both the HDLC controller and the transmit BOC circuitry. Must
be cleared and set again for a subsequent reset.
Transmit Abort. A 0 to 1 transition will cause the FIFO
contents to be dumped and one FEh abort to be sent followed
by 7Eh or FFh flags/idle until a new packet is initiated by
writing new data into the FIFO. Must be cleared and set again
for a subsequent abort to be sent.
TABT
TEOM
HCR.2
Transmit End of Message. Should be set to a one just before
the last data byte of a HDLC packet is written into the transmit
FIFO at THFR. The HDLC controller will clear this bit when
the last byte has been transmitted.
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SYMBOL
POSITION
NAME AND DESCRIPTION
TZSD
HCR.1
Transmit Zero Stuffer Defeat. Overrides internal enable.
0 = enable the zero stuffer (normal operation)
1 = disable the zero stuffer
TCRCD
HCR.0
Transmit CRC Defeat.
0 = enable CRC generation (normal operation)
1 = disable CRC generation
HSR: HDLC STATUS REGISTER (Address = 01 Hex)
(MSB)
(LSB)
RBOC
RPE
RPS
POSITION
HSR.7
RHALF
RNE
THALF
TNF
TMEND
SYMBOL
RBOC
NAME AND DESCRIPTION
Receive BOC Detector Change of State. Set whenever the
BOC detector sees a change of state from a BOC Detected to a
No Valid Code seen or vice versa. The setting of this bit prompt
the user to read the RBOC register for details.
RPE
HSR.6
Receive Packet End. Set when the HDLC controller detects
either the finish of a valid message (i.e., CRC check complete)
or when the controller has experienced a message fault such as a
CRC checking error, or an overrun condition, or an abort has
been seen. The setting of this bit prompts the user to read the
RHIR register for details.
RPS
RHALF
RNE
HSR.5
HSR.4
HSR.3
HSR.2
HSR.1
HSR.0
Receive Packet Start. Set when the HDLC controller detects an
opening byte. The setting of this bit prompts the user to read the
RHIR register for details.
Receive FIFO Half Full. Set when the receive 64–byte FIFO
fills beyond the half way point. The setting of this bit prompts
the user to read the RHIR register for details.
Receive FIFO Not Empty. Set when the receive 64–byte FIFO
has at least one byte available for a read. The setting of this bit
prompts the user to read the RHIR register for details.
Transmit FIFO Half Empty. Set when the transmit 64–byte
FIFO empties beyond the half way point. The setting of this bit
prompts the user to read the THIR register for details.
Transmit FIFO Not Full. Set when the transmit 64–byte FIFO
has at least one byte available. The setting of this bit prompts the
user to read the THIR register for details.
THALF
TNF
TMEND
Transmit Message End. Set when the transmit HDLC
controller has finished sending a message. The setting of this bit
prompts the user to read the THIR register for details.
Note:
The RBOC, RPE, RPS, and TMEND bits are latched and will be cleared when read.
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HIMR: HDLC INTERRUPT MASK REGISTER (Address = 02 Hex)
(MSB)
(LSB)
RBOC
RPE
RPS
POSITION
HIMR.7
RHALF
RNE
THALF
TNF
TMEND
SYMBOL
RBOC
NAME AND DESCRIPTION
Receive BOC Detector Change of State.
0 = interrupt masked
1 = interrupt enabled
RPE
RPS
HIMR.6
HIMR.5
HIMR.4
HIMR.3
HIMR.2
HIMR.1
HIMR.0
Receive Packet End.
0 = interrupt masked
1 = interrupt enabled
Receive Packet Start.
0 = interrupt masked
1 = interrupt enabled
Receive FIFO Half Full.
0 = interrupt masked
1 = interrupt enabled
Receive FIFO Not Empty.
0 = interrupt masked
1 = interrupt enabled
Transmit FIFO Half Empty.
0 = interrupt masked
1 = interrupt enabled
Transmit FIFO Not Full.
0 = interrupt masked
1 = interrupt enabled
RHALF
RNE
THALF
TNF
TMEND
Transmit Message End.
0 = interrupt masked
1 = interrupt enabled
RHIR: RECEIVE HDLC INFORMATION REGISTER (Address = 03 Hex)
(MSB)
(LSB)
RABT
RCRCE
ROVR
POSITION
RHIR.7
RVM
REMPTY POK
CBYTE
OBYTE
SYMBOL
NAME AND DESCRIPTION
RABT
Abort Sequence Detected. Set whenever the HDLC controller
sees 7 or more ones in a row.
RCRCE
ROVR
RHIR.6
RHIR.5
CRC Error. Set when the CRC checksum is in error.
Overrun. Set when the HDLC controller has attempted to write
a byte into an already full receive FIFO.
RVM
RHIR.4
RHIR.3
Valid Message. Set when the HDLC controller has detected and
checked a complete HDLC packet.
Empty. A real–time bit that is set high when the receive FIFO is
empty.
REMPTY
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SYMBOL
POSITION
NAME AND DESCRIPTION
POK
RHIR.2
Packet OK. Set when the byte available for reading in the
receive FIFO at RHFR is the last byte of a valid message (and
hence no abort was seen, no overrun occurred, and the CRC was
correct).
CBYTE
OBYTE
RHIR.1
RHIR.0
Closing Byte. Set when the byte available for reading in the
receive FIFO at RHFR is the last byte of a message (whether the
message was valid or not).
Opening Byte. Set when the byte available for reading in the
receive FIFO at RHFR is the first byte of a message.
Note:
The RABT, RCRCE, ROVR, and RVM bits are latched and will be cleared when read.
RBOC: RECEIVE BIT ORIENTED CODE REGISTER (Address = 04 Hex)
(MSB)
LBD
(LSB)
BOC0
BD
BOC5
POSITION
RBOC.7
BOC4
BOC3
BOC2
BOC1
SYMBOL
NAME AND DESCRIPTION
LBD
BD
Latched BOC Detected. A latched version of the BD status bit
(RBOC.6). Will be cleared when read.
BOC Detected. A real–time bit that is set high when the BOC
detector is presently seeing a valid sequence and set low when
no BOC is currently being detected.
BOC Bit 5. Last bit received of the 6–bit code word.
BOC Bit 4.
RBOC.6
BOC5
BOC4
BOC3
BOC2
BOC1
BOC0
RBOC.5
RBOC.4
RBOC.3
RBOC.2
RBOC.1
RBOC.0
BOC Bit 3.
BOC Bit 2.
BOC Bit 1.
BOC Bit 0. First bit received of the 6–bit code word.
Note:
1. The LBD bit is latched and will be cleared when read.
2. The RBOC0 to RBOC5 bits display the last valid BOC code verified; these bits will be set to all ones
on reset.
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RHFR: RECEIVE HDLC FIFO (Address = 05 Hex)
(MSB)
(LSB)
HDLC7
HDLC6
HDLC5
HDLC4
HDLC3
HDLC2
HDLC1
HDLC0
SYMBOL
POSITION
NAME AND DESCRIPTION
HDLC7
HDLC6
HDLC5
HDLC4
HDLC3
HDLC2
HDLC1
HDLC0
RHFR.7
RHFR.6
RHFR.5
RHFR.4
RHFR.3
RHFR.2
RHFR.1
RHFR.0
HDLC Data Bit 7. MSB of a HDLC packet data byte.
HDLC Data Bit 6.
HDLC Data Bit 5.
HDLC Data Bit 4.
HDLC Data Bit 3.
HDLC Data Bit 2.
HDLC Data Bit 1.
HDLC Data Bit 0. LSB of a HDLC packet data byte.
THIR: TRANSMIT HDLC INFORMATION (Address = 06 Hex)
(MSB)
–
(LSB)
UDR
–
–
–
–
TEMPTY TFULL
SYMBOL
POSITION
NAME AND DESCRIPTION
–
–
–
–
–
THIR.7
THIR.6
THIR.5
THIR.4
THIR.3
THIR.2
Not Assigned. Could be any value when read.
Not Assigned. Could be any value when read.
Not Assigned. Could be any value when read.
Not Assigned. Could be any value when read.
Not Assigned. Could be any value when read.
TEMPTY
Transmit FIFO Empty. A real–time bit that is set high when
the FIFO is empty.
TFULL
UDR
THIR.1
THIR.0
Transmit FIFO Full. A real–time bit that is set high when the
FIFO is full.
Underrun. Set when the transmit FIFO unwantedly empties out
and an abort is automatically sent.
Note:
The UDR bit is latched and will be cleared when read.
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TBOC: TRANSMIT BIT ORIENTED CODE (Address = 07 Hex)
(MSB)
(LSB)
SBOC
HBEN
BOC5
POSITION
TBOC.7
BOC4
BOC3
BOC2
BOC1
BOC0
SYMBOL
SBOC
NAME AND DESCRIPTION
Send BOC. Rising edge triggered. Must be transitioned from a 0
to a
1 transmit the BOC code placed in the BOC0 to BOC5 bits
instead of data from the HDLC controller.
Transmit HDLC & BOC Controller Enable.
0 = source FDL data from the TLINK pin
1 = source FDL data from the onboard HDLC and BOC
controller
HBEN
TBOC.6
BOC5
BOC4
BOC3
BOC2
BOC1
BOC0
TBOC.5
TBOC.4
TBOC.3
TBOC.2
TBOC.1
TBOC.0
BOC Bit 5. Last bit transmitted of the 6–bit code word.
BOC Bit 4.
BOC Bit 3.
BOC Bit 2.
BOC Bit 1.
BOC Bit 0. First bit transmitted of the 6–bit code word.
THFR: TRANSMIT HDLC FIFO (Address = 08 Hex)
(MSB)
(LSB)
HDLC7
HDLC6
HDLC5
HDLC4
HDLC3
HDLC2
HDLC1
HDLC0
SYMBOL
POSITION
NAME AND DESCRIPTION
HDLC7
HDLC6
HDLC5
HDLC4
HDLC3
HDLC2
HDLC1
HDLC0
THFR.7
THFR.6
THFR.5
THFR.4
THFR.3
THFR.2
THFR.1
THFR.0
HDLC Data Bit 7. MSB of a HDLC packet data byte.
HDLC Data Bit 6.
HDLC Data Bit 5.
HDLC Data Bit 4.
HDLC Data Bit 3.
HDLC Data Bit 2.
HDLC Data Bit 1.
HDLC Data Bit 0. LSB of a HDLC packet data byte.
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RDC1: RECEIVE HDLC DS0 CONTROL REGISTER 1 (Address = 90 Hex)
(MSB)
(LSB)
RDS0E
-
RDS0M
RD4
RD3
RD2
RD1
RD0
SYMBOL
RDS0E
POSITION
RDC1.7
NAME AND DESCRIPTION
HDLC DS0 Enable.
0 = use receive HDLC controller for the FDL.
1 = use receive HDLC controller for one or more DS0 channels.
Not Assigned. Should be set to 0.
DS0 Selection Mode.
-
RDC1.6
RDC1.5
RDS0M
0 = utilize the RD0 to RD4 bits to select which single DS0
channel to use.
1 = utilize the RCHBLK control registers to select which DS0
channels to use.
RD4
RD3
RD2
RD1
RD0
RDC1.4
RDC1.3
RDC1.2
RDC1.1
RDC1.0
DS0 Channel Select Bit 4. MSB of the DS0 channel select.
DS0 Channel Select Bit 3.
DS0 Channel Select Bit 2.
DS0 Channel Select Bit 1.
DS0 Channel Select Bit 0. LSB of the DS0 channel select.
RDC2: RECEIVE HDLC DS0 CONTROL REGISTER 2 (Address = 91 Hex)
(MSB)
RDB8
(LSB)
RDB1
RDB7
RDB6
POSITION
RDC2.7
RDC2.6
RDC2.5
RDC2.4
RDC2.3
RDC2.2
RDC2.1
RDC2.0
RDB5
RDB4
RDB3
RDB2
SYMBOL
RDB8
RDB7
RDB6
RDB5
RDB4
RDB3
RDB2
RDB1
NAME AND DESCRIPTION
DS0 Bit 8 Suppress Enable. MSB of the DS0. Set to one to stop
this bit from being used.
DS0 Bit 7 Suppress Enable. Set to one to stop this bit from
being used.
DS0 Bit 6 Suppress Enable. Set to one to stop this bit from
being used.
DS0 Bit 5 Suppress Enable. Set to one to stop this bit from
being used.
DS0 Bit 4 Suppress Enable. Set to one to stop this bit from
being used.
DS0 Bit 3 Suppress Enable. Set to one to stop this bit from
being used.
DS0 Bit 2 Suppress Enable. Set to one to stop this bit from
being used.
DS0 Bit 1 Suppress Enable. LSB of the DS0. Set to one to stop
this bit from being used.
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TDC1: TRANSMIT HDLC DS0 CONTROL REGISTER 1 (Address = 92 Hex)
(MSB)
(LSB)
TDS0E
-
TDS0M
TD4
TD3
TD2
TD1
TD0
SYMBOL
TDS0E
POSITION
TDC1.7
NAME AND DESCRIPTION
HDLC DS0 Enable.
0 = use transmit HDLC controller for the FDL.
1 = use transmit HDLC controller for one or more DS0 channels.
Not Assigned. Should be set to 0.
DS0 Selection Mode.
-
TDC1.6
TDC1.5
TDS0M
0 = utilize the TD0 to TD4 bits to select which single DS0
channel to use.
1 = utilize the TCHBLK control registers to select which DS0
channels to use.
TD4
TD3
TD2
TD1
TD0
TDC1.4
TDC1.3
TDC1.2
TDC1.1
TDC1.0
DS0 Channel Select Bit 4. MSB of the DS0 channel select.
DS0 Channel Select Bit 3.
DS0 Channel Select Bit 2.
DS0 Channel Select Bit 1.
DS0 Channel Select Bit 0. LSB of the DS0 channel select.
TDC2: TRANSMIT HDLC DS0 CONTROL REGISTER 2 (Address = 93 Hex)
(MSB)
TDB8
(LSB)
TDB1
TDB7
TDB6
POSITION
TDC2.7
TDC2.6
TDC2.5
TDC2.4
TDC2.3
TDC2.2
TDC2.1
TDC2.0
TDB5
TDB4
TDB3
TDB2
SYMBOL
TDB8
TDB7
TDB6
TDB5
TDB4
TDB3
TDB2
TDB1
NAME AND DESCRIPTION
DS0 Bit 8 Suppress Enable. MSB of the DS0. Set to one to stop
this bit from being used.
DS0 Bit 7 Suppress Enable. Set to one to stop this bit from
being used.
DS0 Bit 6 Suppress Enable. Set to one to stop this bit from
being used.
DS0 Bit 5 Suppress Enable. Set to one to stop this bit from
being used.
DS0 Bit 4 Suppress Enable. Set to one to stop this bit from
being used.
DS0 Bit 3 Suppress Enable. Set to one to stop this bit from
being used.
DS0 Bit 2 Suppress Enable. Set to one to stop this bit from
being used.
DS0 Bit 1 Suppress Enable. LSB of the DS0. Set to one to stop
this bit from being used.
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DS21Q42
15.2 LEGACY FDL SUPPORT
15.2.1 Overview
The DS21Q42 maintains the circuitry that existed in the previous generation of Dallas Semiconductor’s
single chip transceivers and quad framers. Section 15.2 covers the circuitry and operation of this legacy
functionality. In new applications, it is recommended that the HDLC controller and BOC controller
described in Section 15.1 be used. On the receive side, it is possible to have both the new HDLC/BOC
controller and the legacy hardware working at the same time. However this is not possible on the transmit
side since their can be only one source the of the FDL data internal to the device.
15.2.2 Receive Section
In the receive section, the recovered FDL bits or Fs bits are shifted bit–by–bit into the Receive FDL
register (RFDL). Since the RFDL is 8 bits in length, it will fill up every 2 ms (8 times 250 us). The framer
will signal an external microcontroller that the buffer has filled via the SR2.4 bit. If enabled via IMR2.4,
the INT* pin will toggle low indicating that the buffer has filled and needs to be read. The user has 2 ms
to read this data before it is lost. If the byte in the RFDL matches either of the bytes programmed into the
RMTCH1 or RMTCH2 registers, then the SR2.2 bit will be set to a one and the INT* pin will toggled
low if enabled via IMR2.2. This feature allows an external microcontroller to ignore the FDL or Fs
pattern until an important event occurs.
The framer also contains a zero destuffer, which is controlled via the CCR2.0 bit. In both ANSI T1.403
and TR54016, communications on the FDL follows a subset of a LAPD protocol. The LAPD protocol
states that no more than 5 ones should be transmitted in a row so that the data does not resemble an
opening or closing flag (01111110) or an abort signal (11111111). If enabled via CCR2.0, the DS21Q42
will automatically look for 5 ones in a row, followed by a zero. If it finds such a pattern, it will
automatically remove the zero. If the zero destuffer sees six or more ones in a row followed by a zero, the
zero is not removed. The CCR2.0 bit should always be set to a one when the DS21Q42 is extracting the
FDL. More on how to use the DS21Q42 in FDL applications in this legacy support mode is covered in a
separate Application Note.
RFDL: RECEIVE FDL REGISTER (Address = 28 Hex)
(MSB)
(LSB)
RFDL7
RFDL6
RFDL5
RFDL4
RFDL3
RFDL2
RFDL1
RFDL0
SYMBOL
POSITION
NAME AND DESCRIPTION
RFDL7
RFDL0
RFDL.7
RFDL.0
MSB of the Received FDL Code
LSB of the Received FDL Code
The Receive FDL Register (RFDL) reports the incoming Facility Data Link (FDL) or the incoming Fs
bits. The LSB is received first.
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DS21Q42
RMTCH1: RECEIVE FDL MATCH REGISTER 1 (Address = 29 Hex)
RMTCH2: RECEIVE FDL MATCH REGISTER 2 (Address = 2A Hex)
(MSB)
(LSB)
RMFDL7 RMFDL6 RMFDL5 RMFDL4 RMFDL3 RMFDL2 RMFDL1 RMFDL0
SYMBOL
RMFDL7
POSITION
RMTCH1.7
RMTCH2.7
RMTCH1.0
RMTCH2.0
NAME AND DESCRIPTION
MSB of the FDL Match Code
RMFDL0
LSB of the FDL Match Code
When the byte in the Receive FDL Register matches either of the two Receive FDL Match Registers
(RMTCH1/RMTCH2), SR2.2 will be set to a one and the INT* will go active if enabled via IMR2.2.
15.2.3 Transmit Section
The transmit section will shift out into the T1 data stream, either the FDL (in the ESF framing mode) or
the Fs bits (in the D4 framing mode) contained in the Transmit FDL register (TFDL). When a new value
is written to the TFDL, it will be multiplexed serially (LSB first) into the proper position in the outgoing
T1 data stream. After the full eight bits has been shifted out, the framer will signal the host
microcontroller that the buffer is empty and that more data is needed by setting the SR2.3 bit to a one.
The INT* will also toggle low if enabled via IMR2.3. The user has 2 ms to update the TFDL with a new
value. If the TFDL is not updated, the old value in the TFDL will be transmitted once again. The framer
also contains a zero stuffer, which is controlled via the CCR2.4 bit. In both ANSI T1.403 and TR54016,
communications on the FDL follows a subset of a LAPD protocol. The LAPD protocol states that no
more than 5 ones should be transmitted in a row so that the data does not resemble an opening or closing
flag (01111110) or an abort signal (11111111). If enabled via CCR2.4, the framer will automatically look
for 5 ones in a row. If it finds such a pattern, it will automatically insert a zero after the five ones. The
CCR2.0 bit should always be set to a one when the framer is inserting the FDL. More on how to use the
DS21Q42 in FDL applications is covered in a separate Application Note.
TFDL: TRANSMIT FDL REGISTER (Address = 7E Hex)
[Also used to insert Fs framing pattern in D4 framing mode; see Section 15.3]
(MSB)
(LSB)
TFDL7
TFDL6
TFDL5
TFDL4
TFDL3
TFDL2
TFDL1
TFDL0
SYMBOL
POSITION
NAME AND DESCRIPTION
TFDL7
TFDL0
TFDL.7
TFDL.0
MSB of the FDL code to be transmitted
LSB of the FDL code to be transmitted
The Transmit FDL Register (TFDL) contains the Facility Data Link (FDL) information that is to be
inserted on a byte basis into the outgoing T1 data stream. The LSB is transmitted first.
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DS21Q42
15.2.4 D4/SLC–96 OPERATION
In the D4 framing mode, the framer uses the TFDL register to insert the Fs framing pattern. To allow the
device to properly insert the Fs framing pattern, the TFDL register at address 7Eh must be programmed to
1Ch and the following bits must be programmed as shown: TCR1.2=0 (source Fs data from the TFDL
register) CCR2.5=1 (allow the TFDL register to load on multiframe boundaries)
Since the SLC–96 message fields share the Fs–bit position, the user can access the these message fields
via the TFDL and RFDL registers. Please see the separate Application Note for a detailed description of
how to implement a SLC–96
16. PROGRAMMABLE IN–BAND CODE GENERATION AND DETECTION
Each framer in the DS21Q42 has the ability to generate and detect a repeating bit pattern that is from one
to eight bits in length. To transmit a pattern, the user will load the pattern to be sent into the Transmit
Code Definition (TCD) register and select the proper length of the pattern by setting the TC0 and TC1
bits in the In–Band Code Control (IBCC) register. Once this is accomplished, the pattern will be
transmitted as long as the TLOOP control bit (CCR3.1) is enabled. Normally (unless the transmit
formatter is programmed to not insert the F–bit position) the framer will overwrite the repeating pattern
once every 193 bits to allow the F–bit position to be sent. See Figure 20-15 for more details. As an
example, if the user wished to transmit the standard “loop up” code for Channel Service Units which is a
repeating pattern of ...10000100001... then 80h would be loaded into TDR and the length would set to 5
bits.
Each framer can detect two separate repeating patterns to allow for both a “loop up” code and a “loop
down” code to be detected. The user will program the codes to be detected in the Receive Up Code
Definition (RUPCD) register and the Receive Down Code Definition (RDNCD) register and the length of
each pattern will be selected via the IBCC register. The framer will detect repeating pattern codes in both
framed and unframed circumstances with bit error rates as high as 10**–2. The code detector has a
nominal integration period of 48 ms. Hence, after about 48 ms of receiving either code, the proper status
bit (LUP at SR1.7 and LDN at SR1.6) will be set to a one. Normally codes are sent for a period of 5
seconds. it is recommend that the software poll the framer every 100 ms to 1000 ms until 5 seconds has
relapsed to insure that the code is continuously present.
IBCC: IN–BAND CODE CONTROL REGISTER (Address=12 Hex)
(MSB)
(LSB)
TC1
TC0
RUP2
RUP1
RUP0
RDN2
RDN1
RDN0
SYMBOL
POSITION
NAME AND DESCRIPTION
TC1
TC0
IBCC.7
IBCC.6
IBCC.5
IBCC.4
IBCC.3
IBCC.2
IBCC.1
IBCC.0
Transmit Code Length Definition Bit 1. See Table 16–1
Transmit Code Length Definition Bit 0. See Table 16–1
Receive Up Code Length Definition Bit 2. See Table 16–2
Receive Up Code Length Definition Bit 1. See Table 16–2
Receive Up Code Length Definition Bit 0. See Table 16–2
Receive Down Code Length Definition Bit 2. See Table 16–2
Receive Down Code Length Definition Bit 1. See Table 16–2
Receive Down Code Length Definition Bit 0. See Table 16–2
RUP2
RUP1
RUP0
RDN2
RDN1
RDN0
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DS21Q42
Table 16-1
TC1
TC0
LENGTH SELECTED
5 bits
6 bits / 3 bits
0
0
1
1
0
1
0
1
7 bits
8 bits / 4 bits / 2 bits / 1 bits
RECEIVE CODE LENGTH Table 16-2
RUP2/RDN2
RUP1/RDN1
RUP0/RDN0
LENGTH
SELECTED
1 bits
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
2 bits
3 bits
4 bits
5 bits
6 bits
7 bits
8 bits
TCD: TRANSMIT CODE DEFINITION REGISTER (Address=13 Hex)
(MSB)
(LSB)
C7
C6
C5
POSITION
TCD.7
C4
C3
C2
C1
C0
SYMBOL
C7
NAME AND DESCRIPTION
Transmit Code Definition Bit 7. First bit of the repeating
pattern.
C6
C5
C4
C3
C2
TCD.6
TCD.5
TCD.4
TCD.3
TCD.2
Transmit Code Definition Bit 6.
Transmit Code Definition Bit 5.
Transmit Code Definition Bit 4.
Transmit Code Definition Bit 3.
Transmit Code Definition Bit 2. A Don’t Care if a 5 bit length
is selected.
C1
C0
TCD.1
TCD.0
Transmit Code Definition Bit 1. A Don’t Care if a 5 or 6 bit
length is selected.
Transmit Code Definition Bit 0. A Don’t Care if a 5, 6 or 7 bit
length is selected.
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DS21Q42
RUPCD: RECEIVE UP CODE DEFINITION REGISTER (Address=14 Hex)
(MSB)
(LSB)
C7
C6
C5
POSITION
RUPCD.7
RUPCD.6
RUPCD.5
RUPCD.4
RUPCD.3
RUPCD.2
RUPCD.1
RUPCD.0
C4
C3
C2
C1
C0
SYMBOL
C7
NAME AND DESCRIPTION
Receive Up Code Definition Bit 7. First bit of the repeating
pattern.
Receive Up Code Definition Bit 6. A Don’t Care if a 1 bit
length is selected.
Receive Up Code Definition Bit 5. A Don’t Care if a 1 or 2 bit
length is selected.
Receive Up Code Definition Bit 4. A Don’t Care if a 1 to 3 bit
length is selected.
Receive Up Code Definition Bit 3. A Don’t Care if a 1 to 4 bit
length is selected.
Receive Up Code Definition Bit 2. A Don’t Care if a 1 to 5 bit
length is selected.
Receive Up Code Definition Bit 1. A Don’t Care if a 1 to 6 bit
length is selected.
Receive Up Code Definition Bit 0. A Don’t Care if a 1 to 7 bit
length is selected.
C6
C5
C4
C3
C2
C1
C0
RDNCD: RECEIVE DOWN CODE DEFINITION REGISTER (Address=15 Hex)
(MSB)
(LSB)
C7
C6
C5
POSITION
RDNCD.7
RDNCD.6
RDNCD.5
RDNCD.4
RDNCD.3
RDNCD.2
RDNCD.1
RDNCD.0
C4
C3
C2
C1
C0
SYMBOL
NAME AND DESCRIPTION
C7
C6
C5
C4
C3
C2
C1
C0
Receive Down Code Definition Bit 7. First bit of the repeating
pattern.
Receive Down Code Definition Bit 6. A Don’t Care if a 1 bit
length is selected.
Receive Down Code Definition Bit 5. A Don’t Care if a 1 or 2
bit length is selected.
Receive Down Code Definition Bit 4. A Don’t Care if a 1 to 3
bit length is selected.
Receive Down Code Definition Bit 3. A Don’t Care if a 1 to 4
bit length is selected.
Receive Down Code Definition Bit 2. A Don’t Care if a 1 to 5
bit length is selected.
Receive Down Code Definition Bit 1. A Don’t Care if a 1 to 6
bit length is selected.
Receive Down Code Definition Bit 0. A Don’t Care if a 1 to 7
bit length is selected.
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DS21Q42
17. TRANSMIT TRANSPARENCY
Each of the 24 T1 channels in the transmit direction of the framer can be either forced to be transparent or
in other words, can be forced to stop Bit 7 Stuffing and/or Robbed Signaling from overwriting the data in
the channels. Transparency can be invoked on a channel by channel basis by properly setting the TTR1,
TTR2, and TTR3 registers.
TTR1/TTR2/TTR3: TRANSMIT TRANSPARENCY REGISTER
(Address=39 to 3B Hex)
(MSB)
CH8
CH16
CH24
(LSB)
CH1
CH9
CH7
CH15
CH23
CH6
CH14
CH22
CH5
CH13
CH21
CH4
CH12
CH20
CH3
CH11
CH19
CH2
CH10
CH18
TTR1 (39)
TTR2 (3A)
TTR3 (3B)
CH17
SYMBOLS
CH1-24
POSITIONS
NAME AND DESCRIPTION
TTR1.0-3.7
Transmit Transparency Registers.
0 = this DS0 channel is not transparent
1 = this DS0 channel is transparent
Each of the bit position in the Transmit Transparency Registers (TTR1/TTR2/TTR3) represent a DS0
channel in the outgoing frame. When these bits are set to a one, the corresponding channel is transparent
(or clear). If a DS0 is programmed to be clear, no robbed bit signaling will be inserted nor will the
channel have Bit 7 stuffing performed. However, in the D4 framing mode, bit 2 will be overwritten by a
zero when a Yellow Alarm is transmitted. Also the user has the option to prevent the TTR registers from
determining which channels are to have Bit 7 stuffing performed. If the TCR2.0 and TCR1.3 bits are set
to one, then all 24 T1 channels will have Bit 7 stuffing performed on them regardless of how the TTR
registers are programmed. In this manner, the TTR registers are only affecting which channels are to have
robbed bit signaling inserted into them. Please see Figure 20-15 for more details.
18. INTERLEAVED PCM BUS OPERATION
In many architectures, the outputs of individual framers are combined into higher speed serial buses to
simplify transport across the system. The DS21Q42 can be configured to allow each framer’s data and
signaling busses to be multiplexed into higher speed data and signaling busses eliminating external
hardware saving board space and cost.
The interleaved PCM bus option supports two bus speeds and interleave modes. The 4.096 MHz bus
speed allows two framers to share a common bus. The 8.192 MHz bus speed allows all four of the
DS21Q42’s framers to share a common bus. Framers can interleave their data either on byte or frame
boundaries. Framers that share a common bus must be configured through software and require several
device pins to be connected together externally (see figures 18-1 & 18-2). Each framer’s elastic stores
must be enabled and configured for 2.048 MHz operation. The signal RSYNC must be configured as an
input on each framer.
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DS21Q42
For all bus configurations, one framer will be configured as the master device and the remaining framers
on the shared bus will be configured as slave devices. Refer to the IBO register description below for
more detail. In the 4.096 MHz bus configuration there is one master and one slave per bus. Figure 18-1
shows the DS21Q42 configured to support two 4.096 MHz buses. Bus 1 consists of framers 0 and 1. Bus
2 consists of framers 2 and 3. Framers 0 and 2 are programmed as master devices. Framers 1 and 3 are
programmed as slave devices. In the 8.192 MHz bus configuration there is one master and three slaves.
Figure 18-2 shows the DS21Q42 configured to support a 8.192 MHz bus. Framers 0 is programmed as
the master device. Framers 1, 2 and 3 are programmed as slave devices. Consult timing diagrams in
section 20 for additional information.
When using the frame interleave mode, all framers that share an interleaved bus must have receive signals
(RPOS & RNEG) that are synchronous with each other. The received signals must originate from the
same clock reference. This restriction does not apply in the byte interleave mode.
IBO: INTERLEAVE BUS OPERATION REGISTER (Address = 94 Hex)
(MSB)
(LSB)
-
-
-
-
IBOEN
INTSEL
MSEL0
MSEL1
SYMBOL
POSITION
NAME AND DESCRIPTION
-
-
-
-
IBO.6
IBO.6
IBO.5
IBO.4
IBO.3
Not Assigned. Should be set to 0.
Not Assigned. Should be set to 0.
Not Assigned. Should be set to 0.
Not Assigned. Should be set to 0.
Interleave Bus Operation Enable
0 = Interleave Bus Operation disabled.
1 = Interleave Bus Operation enabled.
Interleave Type Select
IBOEN
INTSEL
IBO.2
0 = Byte interleave.
1 = Frame interleave.
MSEL0
MSEL1
IBO.1
IBO.0
Master Device Bus Select Bit 0 See table 18-1.
Master Device Bus Select Bit 1 See table 18-1.
Master Device Bus Select Table 18-1
MSEL1
MSEL0
Function
0
0
1
1
0
1
0
1
Slave device.
Master device with 1 slave device (4.096 MHz bus rate)
Master device with 3 slave devices (8.192 MHz bus rate)
Reserved
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DS21Q42
4.096 MHz Interleaved Bus External Pin Connection Example Figure 18-1
FRAMER 0
FRAMER 1
FRAMER 2
FRAMER 3
RSYSCLK0
TSYSCLK0
RSYNC0
TSSYNC0
RSER0
RSYSCLK1
TSYSCLK1
RSYNC1
TSSYNC1
RSER1
RSYSCLK2
TSYSCLK2
RSYNC2
TSSYNC2
RSER2
RSYSCLK3
TSYSCLK3
RSYNC3
TSSYNC3
RSER3
TSER0
TSER1
TSER2
TSER3
RSIG0
RSIG1
RSIG2
RSIG3
TSIG0
TSIG1
TSIG2
TSIG3
SYSCLK
SYNC INPUT
RSER
SYSCLK
SYNC INPUT
RSER
TSER
TSER
RSIG
RSIG
TSIG
TSIG
Bus 2
Bus 1
8.192 MHz Interleaved Bus External Pin Connection Example Figure 18-2
FRAMER 0
FRAMER 1
FRAMER 2
FRAMER 3
RSYSCLK0
TSYSCLK0
RSYNC0
TSSYNC0
RSER0
RSYSCLK1
TSYSCLK1
RSYNC1
TSSYNC1
RSER1
RSYSCLK2
TSYSCLK2
RSYNC2
TSSYNC2
RSER2
RSYSCLK3
TSYSCLK3
RSYNC3
TSSYNC3
RSER3
TSER0
TSER1
TSER2
TSER3
RSIG0
RSIG1
RSIG2
RSIG3
TSIG0
TSIG1
TSIG2
TSIG3
SYSCLK
SYNC INPUT
RSER
TSER
RSIG
TSIG
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DS21Q42
19. JTAG-BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT
19.1 Description
The DS21Q42 IEEE 1149.1 design supports the standard instruction codes SAMPLE/PRELOAD,
BYPASS, and EXTEST. Optional public instructions included with this design are HIGHZ, CLAMP, and
IDCODE. See Figure 19-1 for a block diagram. The DS21Q42 contains the following items, which meet
the requirements, set by the IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture.
Test Access Port (TAP)
TAP Controller
Instruction Register
Bypass Register
Boundary Scan Register
Device Identification Register
The JTAG feature is only available when the DS21Q42 feature set is selected (FMS = 0). The JTAG
feature is disabled when the DS21Q42 is configured for emulation of the DS21Q41B (FMS = 1). Details
on Boundary Scan Architecture and the Test Access Port can be found in IEEE 1149.1-1990, IEEE
1149.1a-1993, and IEEE 1149.1b-1994.
The Test Access Port has the necessary interface pins; JTRST*, JTCLK, JTMS, JTDI, and JTDO. See the
pin descriptions for details.
Boundary Scan Architecture Figure 19-1
Boundary Scan
Register
Identification
Register
Bypass
Register
MUX
Instruction
Register
Select
Test Access Port
Output Enable
Controller
+V
+V
+V
10K
10K
10K
JTDO
JTRST
JTDI
JTMS
JTCLK
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DS21Q42
19.2 TAP Controller State Machine
This section covers the details on the operation of the Test Access Port (TAP) Controller State Machine.
Please see Figure 19.2 for details on each of the states described below.
TAP Controller
The TAP controller is a finite state machine that responds to the logic level at JTMS on the rising edge of
JTCLK.
Test-Logic-Reset
Upon power up of the DS21Q42, the TAP Controller will be in the Test-Logic-Reset state. The
Instruction register will contain the IDCODE instruction. All system logic of the DS21Q42 will operate
normally.
Run-Test-Idle
The Run-Test-Idle is used between scan operations or during specific tests. The Instruction register and
Test registers will remain idle.
Select-DR-Scan
All test registers retain their previous state. With JTMS low, a rising edge of JTCLK moves the controller
into the Capture-DR state and will initiate a scan sequence. JTMS HIGH during a rising edge on JTCLK
moves the controller to the Select-IR
Capture-DR
Data may be parallel-loaded into the Test Data registers selected by the current instruction. If the
instruction does not call for a parallel load or the selected register does not allow parallel loads, the Test
register will remain at its current value. On the rising edge of JTCLK, the controller will go to the Shift-
DR state if JTMS is low or it will go to the Exit1-DR state if JTMS is high.
Shift-DR
The Test Data register selected by the current instruction will be connected between JTDI and JTDO and
will shift data one stage towards its serial output on each rising edge of JTCLK. If a Test Register
selected by the current instruction is not placed in the serial path, it will maintain its previous state.
Exit1-DR
While in this state, a rising edge on JTCLK with JTMS high will put the controller in the Update-DR
state, and terminate the scanning process. A rising edge on JTCLK with JTMS low will put the controller
in the Pause-DR state.
Pause-DR
Shifting of the test registers is halted while in this state. All Test registers selected by the current
instruction will retain their previous state. The controller will remain in this state while JTMS is low. A
rising edge on JTCLK with JTMS high will put the controller in the Exit2-DR state.
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DS21Q42
Exit2-DR
While in this state, a rising edge on JTCLK with JTMS high will put the controller in the Update-DR
state and terminate the scanning process. A rising edge on JTCLK with JTMS low will enter the Shift-DR
state.
Update-DR
A falling edge on JTCLK while in the Update-DR state will latch the data from the shift register path of
the Test registers into the data output latches. This prevents changes at the parallel output due to changes
in the shift register. A rising edge on JTCLK with JTMS low, will put the controller in the Run-Test-Idle
state. With JTMS high, the controller will enter the Select-DR-Scan state.
Select-IR-Scan
All test registers retain their previous state. The instruction register will remain unchanged during this
state. With JTMS low, a rising edge of JTCLK moves the controller into the Capture-IR state and will
initiate a scan sequence for the Instruction register. JTMS high during a rising edge on JTCLK puts the
controller back into the Test-Logic-Reset state.
Capture-IR
The Capture-IR state is used to load the shift register in the instruction register with a fixed value. This
value is loaded on the rising edge of JTCLK. If JTMS is high on the rising edge of JTCLK, the controller
will enter the Exit1-IR state. If JTMS is low on the rising edge of JTCLK, the controller will enter the
Shift-IR state.
Shift-IR
In this state, the shift register in the instruction register is connected between JTDI and JTDO and shifts
data one stage for every rising edge of JTCLK towards the serial output. The parallel registers, as well as
all Test registers remain at their previous states. A rising edge on JTCLK with JTMS high will move the
controller to the Exit1-IR state. A rising edge on JTCLK with JTMS low will keep the controller in the
Shift-IR state while moving data one stage thorough the instruction shift register.
Exit1-IR
A rising edge on JTCLK with JTMS low will put the controller in the Pause-IR state. If JTMS is high on
the rising edge of JTCLK, the controller will enter the Update-IR state and terminate the scanning
process.
Pause-IR
Shifting of the instruction shift register is halted temporarily. With JTMS high, a rising edge on JTCLK
will put the controller in the Exit2-IR state. The controller will remain in the Pause-IR state if JTMS is
low during a rising edge on JTCLK.
Exit2-IR
A rising edge on JTCLK with JTMS low will put the controller in the Update-IR state. The controller will
loop back to Shift-IR if JTMS is high during a rising edge of JTCLK in this state.
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DS21Q42
Update-IR
The instruction code shifted into the instruction shift register is latched into the parallel output on the
falling edge of JTCLK as the controller enters this state. Once latched, this instruction becomes the
current instruction. A rising edge on JTCLK with JTMS low, will put the controller in the Run-Test-Idle
state. With JTMS high, the controller will enter the Select-DR-Scan state.
TAP Controller State Machine Figure 19-2
Test Logic
Reset
1
0
1
1
1
Run Test/
Idle
Select
DR-Scan
Select
IR-Scan
0
0
0
1
1
Capture DR
Capture IR
0
0
Shift DR
Shift IR
0
1
0
1
1
1
Exit DR
Exit IR
0
0
Pause DR
Pause IR
0
0
1
1
0
0
Exit2 DR
Exit2 IR
1
1
Update DR
Update IR
0
0
1
1
19.3 Instruction Register and Instructions
The instruction register contains a shift register as well as a latched parallel output and is 3 bits in length.
When the TAP controller enters the Shift-IR state, the instruction shift register will be connected between
JTDI and JTDO. While in the Shift-IR state, a rising edge on JTCLK with JTMS low will shift the data
one stage towards the serial output at JTDO. A rising edge on JTCLK in the Exit1-IR state or the Exit 2-
IR state with JTMS high will move the controller to the Update-IR state The falling edge of that same
JTCLK will latch the data in the instruction shift register to the instruction parallel output. Instructions
supported by the DS21Q42 with their respective operational binary codes are shown in Table 19-1.
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DS21Q42
Instruction Codes For The DS21352/552 IEEE 1149.1 Architecture Table 19-1
Instruction
SAMPLE/PRELOAD
BYPASS
EXTEST
CLAMP
Selected Register
Boundary Scan
Bypass
Boundary Scan
Boundary Scan
Boundary Scan
Device Identification
Instruction Codes
010
111
000
011
100
001
HIGHZ
IDCODE
SAMPLE/PRELOAD
A mandatory instruction for the IEEE 1149.1 specification. This instruction supports two functions. The
digital I/Os of the DS21Q42 can be sampled at the boundary scan register without interfering with the
normal operation of the device by using the Capture-DR state. SAMPLE/PRELOAD also allows the
DS21Q42 to shift data into the boundary scan register via JTDI using the Shift-DR state.
EXTEST
EXTEST allows testing of all interconnections to the DS21Q42. When the EXTEST instruction is latched
in the instruction register, the following actions occur. Once enabled via the Update-IR state, the parallel
outputs of all digital output pins will be driven. The boundary scan register will be connected between
JTDI and JTDO. The Capture-DR will sample all digital inputs into the boundary scan register.
BYPASS
When the BYPASS instruction is latched into the parallel instruction register, JTDI connects to JTDO
through the one-bit bypass test register. This allows data to pass from JTDI to JTDO not affecting the
device’s normal operation.
IDCODE
When the IDCODE instruction is latched into the parallel instruction register, the Identification Test
register is selected. The device identification code will be loaded into the Identification register on the
rising edge of JTCLK following entry into the Capture-DR state. Shift-DR can be used to shift the
identification code out serially via JTDO. During Test-Logic-Reset, the identification code is forced into
the instruction register’s parallel output. The ID code will always have a ‘1’ in the LSB position. The next
11 bits identify the manufacturer’s JEDEC number and number of continuation bytes followed by 16 bits
for the device and 4 bits for the version. See Table 19-2. Table 19-3 lists the device ID codes for the
DS21Q42 and DS21Q44 devices.
ID Code Structure Table 19-2
MSB
LSB
Version
(Contact Factory)
4 bits
Device ID
(See Table 19-3)
16bits
JEDEC
“00010100001”
11bits
“1”
Contents
Length
1bit
83 of 119
DS21Q42
Device ID Codes Table 19-3
DEVICE
DS21Q42
DS21Q44
16-BIT NUMBER
0000h
0001h
HIGHZ
All digital outputs of the DS21Q42 will be placed in a high impedance state. The BYPASS register will
be connected between JTDI and JTDO.
CLAMP
All digital outputs of the DS21Q42 will output data from the boundary scan parallel output while
connecting the bypass register between JTDI and JTDO. The outputs will not change during the CLAMP
instruction.
19.4 Test Registers
IEEE 1149.1 requires a minimum of two test registers; the bypass register and the boundary scan register.
An optional test register has been included with the DS21Q42 design. This test register is the
identification register and is used in conjunction with the IDCODE instruction and the Test-Logic-Reset
state of the TAP controller.
Boundary Scan Register
This register contains both a shift register path and a latched parallel output for all control cells and
digital I/O cells and is 126 bits in length. Table 17-3 shows all of the cell bit locations and definitions.
Bypass Register
This is a single one-bit shift register used in conjunction with the BYPASS, CLAMP, and HIGHZ
instructions, which provides a short path between JTDI and JTDO.
Identification Register
The identification register contains a 32-bit shift register and a 32-bit latched parallel output. This register
is selected during the IDCODE instruction and when the TAP controller is in the Test-Logic-Reset state.
84 of 119
DS21Q42
Boundary Scan Register Description Table 19-4
DEVICE
SCAN
REGISTER BIT
CONTROL
BIT DESCRIPTION
PIN
1
2
3
4
5
6
7
8
SYMBOL
TCHBLK0
TPOS0
TYPE
81
80
79
78
77
76
75
74
73
72
71
70
O
O
O
O
O
I
I
I
O
O
I
TNEG0
RLINK0
RLCLK0
RCLK0
RNEG0
RPOS0
9
RSIG0
10
11
-
RCHBLK0
RSYSCLK0
RSYNC0.cntl
-
0 = RSYNCO an input
I = RSYNCO an output
12
13
14
15
16
17
18
19
20
-
69
68
-
RSYNC0
RSER0
I/O
O
-
-
-
O
I
I
O
-
VSS
VDD
-
67
66
-
65
64
63
SPARE1
RFSYNCO
JTRST*
TCLK0
TLCLK0
TSYNC0.cntl
0 = TSYNCO an input
I = TSYNCO an output
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
TSYNC0
TLINK0
A0
I/O
I
I
I
I
I
I
I
I
O
I
I
I
I
O
O
O
O
O
I
A1
A2
A3
A4
A5
A6/ALE (AS)
INT*
TSYSCLK1
TSER1
TSSYNC1
TSIG1
TCHBLK1
TPOS1
TNEG1
RLINK1
RLCLK1
RCLK1
85 of 119
DS21Q42
DEVICE
SCAN
REGISTER BIT
CONTROL
BIT DESCRIPTION
PIN
41
42
43
44
45
46
47
-
SYMBOL
RNEG1
RPOS1
TYPE
42
41
40
39
38
37
36
35
I
I
O
O
I
I
I
-
RSIG1
RCHBLK1
RSYSCLK1
A7
FMS
RSYNC1.cntl
0 = RSYNC1 an input
I = RSYNC1 an output
48
49
50
51
52
53
54
-
34
33
-
32
-
31
30
29
RSYNC1
RSER1
JTMS
RFSYNC1
JTCLK
TCLK1
I/O
O
I
O
I
I
O
-
TLCLK1
TSYNC1.cntl
0 = TSYNC1 an input
I = TSYNC1 an output
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
-
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
TSYNC1
TLINK1
TEST
I/O
I
I
I
I
I
I
I
I
I
I
I
I
FS0
FS1
CS*
BTS
RD*/(DS*)
WR*/(R/W*)
MUX
TSYSCLK2
TSER2
TSSYNC2
TSIG2
TCHBLK2
TPOS2
I
O
O
O
O
O
I
TNEG2
RLINK2
RLCLK2
RCLK2
RNEG2
RPOS2
RSIG2
VSS
VDD
8
7
6
-
-
5
4
3
I
I
O
-79
-
O
I
RCHBLK2
RSYSCLK2
RSYNC2.cntl
-
0 = RSYNC2 an input
86 of 119
DS21Q42
DEVICE
PIN
SCAN
REGISTER BIT
CONTROL
BIT DESCRIPTION
I = RSYNC2 an output
SYMBOL
TYPE
82
83
84
85
86
87
88
-
2
1
-
0
-
125
124
123
RSYNC2
RSER2
JTDI
RFSYNC2
JTDO
TCLK2
TLCLK2
TSYNC2.cntl
I/O
O
I
O
O
I
O
-
0 = TSYNC2 an input
I = TSYNC2 an output
89
90
91
92
93
94
95
96
97
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
TSYNC2
TLINK2
TSYSCLK3
TSER3
TSSYNC3
TSIG3
TCHBLK3
TPOS3
TNEG3
RLINK3
RLCLK3
RCLK3
RNEG3
RPOS3
I/O
I
I
I
I
I
O
O
O
O
O
I
I
I
O
O
I
98
99
100
101
102
103
104
105
-
RSIG3
RCHBLK3
RSYSCLK3
RSYNC3.cntl
-
0 = RSYNC3 an input
I = RSYNC3 an output
106
107
108
109
110
111
112
113
114
-
104
103
102
101
-
RSYNC3
RSER3
8MCLK
RFSYNC3
VSS
VDD
CLKSI
TCLK3
TLCLK3
TSYNC3.cntl
I/O
O
O
O
-
-
I
I
O
-
-
100
99
98
97
0 = TSYNC3 an input
I = TSYNC3 an output
115
116
-
96
95
94
TSYNC3
TLINK3
BUS.cntl
I/O
I
-
0 = D0-D7 or AD0-AD7 are inputs
I = D0-D7 or AD0-AD7 are outputs
117
118
93
92
D0 or AD0
D1 or AD1
I/O
I/O
87 of 119
DS21Q42
DEVICE
PIN
119
SCAN
REGISTER BIT
CONTROL
BIT DESCRIPTION
SYMBOL
D2 or AD2
D3 or AD3
D4 or AD4
D5 or AD5
D6 or AD6
D7 or AD7
TSYSCLK0
TSER0
TYPE
I/O
I/O
I/O
I/O
I/O
I/O
I
91
90
89
88
87
86
85
84
83
82
120
121
122
123
124
125
126
127
I
I
I
TSSYNC0
TSIG0
128
88 of 119
DS21Q42
20. TIMING DIAGRAMS
RECEIVE SIDE D4 TIMING Figure 20-1
Notes:
1. RSYNC in the frame mode (RCR2.4 = 0) and double-wide frame sync is not enabled (RCR2.5 = 0)
2. RSYNC in the frame mode (RCR2.4 = 0) and double-wide frame sync is enabled (RCR2.5 = 1)
3. RSYNC in the multiframe mode (RCR2.4 = 1)
4. RLINK data (Fs - bits) is updated one bit prior to even frames and held for two frames
5. RLINK and RLCLK are not synchronous with RSYNC when the receive side elastic store is enabled
89 of 119
DS21Q42
RECEIVE SIDE ESF TIMING Figure 20-2
Notes:
1. RSYNC in the frame mode (RCR2.4 = 0) and double-wide frame sync is not enabled (RCR2.5 = 0)
2. RSYNC in the frame mode (RCR2.4 = 0) and double-wide frame sync is enabled (RCR2.5 = 1)
3. RSYNC in the multiframe mode (RCR2.4 = 1)
4. ZBTSI mode disabled (RCR2.6 = 0)
5. RLINK data (FDL bits) is updated one bit time before odd frames and held for two frames
6. ZBTSI mode is enabled (RCR2.6 = 1)
7. RLINK data (Z bits) is updated one bit time before odd frames and held for four frames
8. RLINK and RLCLK are not synchronous with RSYNC when the receive side elastic store is enabled
90 of 119
DS21Q42
RECEIVE SIDE BOUNDARY TIMING (with elastic store disabled) Figure 20-3
Notes:
1. There is a 13 RCLK delay from RPOS/RNEG to RSER.
2. RCHBLK is programmed to block channel 24.
3. Shown is RLINK/RLCLK in the ESF framing mode.
91 of 119
DS21Q42
RECEIVE SIDE 1.544 MHz BOUNDARY TIMING (with elastic store enabled)
Figure 20-4
Notes:
1. RSYNC is in the output mode (RCR2.3 = 0)
2. RSYNC is in the input mode (RCR2.3 = 1)
3. RCHBLK is programmed to block channel 24
92 of 119
DS21Q42
RECEIVE SIDE 2.048 MHz BOUNDARY TIMING (with elastic store enabled)
Figure 20-5
Notes:
1. RSER data in channels 1, 5, 9, 13, 17, 21, 25, and 29 are forced to one
2. RSYNC is in the output mode (RCR2.3 = 0)
3. RSYNC is in the input mode (RCR2.3 = 1)
4. RCHBLK is forced to one in the same channels as RSER (see Note 1)
5. The F-Bit position is passed through the receive side elastic store and occupies the MSB position of
channel 1.
93 of 119
DS21Q42
RECEIVE SIDE INTERLEAVED BUS OPERATION BYTE MODE TIMING
Figure 20-6
Notes:
1. 4.096 MHz bus configuration.
2. 8.192 MHz bus configuration.
3. RSYNC is in the input mode (RCR2.3 = 1).
94 of 119
DS21Q42
RECEIVE SIDE INTERLEAVED BUS OPERATION FRAME MODE TIMING
Figure 20-7
Notes:
1. 4.096 MHz bus configuration.
2. 8.192 MHz bus configuration.
3. RSYNC is in the input mode (RCR2.3 = 1).
95 of 119
DS21Q42
TRANSMIT SIDE D4 TIMING Figure 20-8
Notes:
1. TSYNC in the frame mode (TCR2.3 = 0) and double-wide frame sync is not enabled (TCR2.4 = 0)
2. TSYNC in the frame mode (TCR2.3 = 0) and double-wide frame sync is enabled (TCR2.4 = 1)
3. TSYNC in the multiframe mode (TCR2.3 = 1)
4. TLINK data (Fs - bits) is sampled during the F-bit position of even frames for insertion into the
outgoing T1 stream when enabled via TCR1.2
5. TLINK and TLCLK are not synchronous with TFSYNC
96 of 119
DS21Q42
TRANSMIT SIDE ESF TIMING Figure 20-9
Notes:
1. TSYNC in the frame mode (TCR2.3 = 0) and double-wide frame sync is not enabled (TCR2.4 = 0)
2. TSYNC in the frame mode (TCR2.3 = 0) and double-wide frame sync is enabled (TCR2.4 = 1)
3. TSYNC in the multiframe mode (TCR2.3 = 1)
4. ZBTSI mode disabled (TCR2.5 = 0)
5. TLINK data (FDL bits) is sampled during the F-bit time of odd frame and inserted into the outgoing
T1 stream if enabled via TCR1.2
6. ZBTSI mode is enabled (TCR2.5 = 1)
7. TLINK data (Z bits) is sampled during the F-bit time of frames 1, 5, 9, 13, 17, and 21 and inserted
into the outgoing stream if enabled via TCR1.2
8. TLINK and TLCLK are not synchronous with TFSYNC
97 of 119
DS21Q42
TRANSMIT SIDE BOUNDARY TIMING (with elastic store disabled)
Figure 20-10
Notes:
1. There is a 10 TCLK delay from TSER to TPOS/TNEG.
2. TSYNC is in the output mode (TCR2.2 = 1)
3. TSYNC is in the input mode (TCR2.2 = 0)
4. TCHBLK is programmed to block channel 2
5. Shown is TLINK/TLCLK in the ESF framing mode
98 of 119
DS21Q42
TRANSMIT SIDE 1.544 MHz BOUNDARY TIMING (with elastic store enabled)
Figure 20-11
Note:
1. TCHBLK is programmed to block channel 24 (if the TPCSI bit is set, then the signaling data at TSIG
will be ignored during channel 24).
99 of 119
DS21Q42
TRANSMIT SIDE 2.048 MHz BOUNDARY TIMING (with elastic store enabled)
Figure 20-12
Notes:
1. TSER data in channels 1, 5, 9, 13, 17, 21, 25, and 29 is ignored
2. TCHBLK is programmed to block channel 31 (if the TPCSI bit is set, then the signaling data at TSIG
will be ignored).
3. TCHBLK is forced to one in the same channels as TSER is ignored (see Note 1)
4. The F-bit position (MSB position of channel 1) for the T1 frame is sampled and passed through the
transmit side elastic store (normally the transmit side formatter overwrites the F-bit position unless
the formatter is programmed to pass-through the F-bit position)
100 of 119
DS21Q42
TRANSMIT SIDE INTERLEAVED BUS OPERATION BYTE MODE TIMING
Figure 20-13
Notes:
1. 4.096 MHz bus configuration.
2. 8.192 MHz bus configuration.
101 of 119
DS21Q42
TRANSMIT SIDE INTERLEAVED BUS OPERATION FRAME MODE TIMING
Figure 20-14
Notes:
1. 4.096 MHz bus configuration.
2. 8.192 MHz bus configuration.
102 of 119
DS21Q42
DS21Q42 TRANSMIT DATA FLOW Figure 20-15
Notes:
1. TCLK should be tied to RCLK and TSYNC should be tied to RFSYNC for data to be properly
sourced from RSER.
103 of 119
DS21Q42
21. OPERATING PARAMETERS
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Non-Supply Pin Relative to Ground
Supply Voltage
Operating Temperature for DS21Q42T
Operating Temperature for DS21Q42TN
Storage Temperature
–1.0V to +5.5V
-0.3V to +3.63V
0°C to 70°C
–40°C to +85°C
–55°C to +125°C
* This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operation sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
(0°C to 70°C for DS21Q42T;
0°C to +85°C for DS21Q42TN)
PARAMETER
Logic 1
Logic 1
SYMBOL MIN
TYP
MAX
5.5
UNITS
NOTES
VIH
VIL
2.0
–0.3
2.97
V
V
V
+0.8
3.63
Supply
VDD
CAPACITANCE
PARAMETER
Input Capacitance
Output Capacitance
(tA =25°C)
SYMBOL MIN
TYP
5
7
MAX
UNITS
pF
NOTES
CIN
COUT
pF
DC CHARACTERISTICS
(0°C to 70°C; VDD = 2.97 to 3.63V for DS21Q42T;
-40°C to +85°C; VDD = 2.97 to 3.63V for DS21Q42TN)
PARAMETER
Supply Current @ 3.3V
Input Leakage
Output Leakage
Output Current (2.4V)
Output Current (0.4V)
SYMBOL MIN
TYP
MAX
UNITS
mA
NOTES
IDD
IIL
ILO
IOH
IOL
75
1
2
3
–1.0
+1.0
1.0
µA
µA
–1.0
+4.0
mA
mA
Notes:
1. TCLK=RCLK=TSYSCLK=RSYSCLK=1.544 MHz; outputs open circuited.
2. 0.0V < V IN < V DD .
3. Applied to INT* when 3–stated.
104 of 119
DS21Q42
AC CHARACTERISTICS–
MULTIPLEXED PARALLEL PORT (MUX=1)
(0ºC to 70ºC; VDD = 2.97 to 3.63V for DS21Q42T
– 40ºC to +85ºC; VDD = 2.97 to 3.63V for DS21Q42TN)
PARAMETER
Cycle Time
Pulse Width, DS low or
RD*high
SYMBOL MIN
TYP
MAX
UNITS
ns
NOTES
t CYC
200
100
PW EL
ns
Pulse Width, DS high or
RD* low
PW EH
100
ns
Input Rise/Fall times
R/W* Hold Time
R/W* Set Up time before
DS high
t R , t F
t RWH
t RWS
20
ns
ns
ns
10
50
CS*, FSO or FS1 Set Up
time before DS, WR* or
RD* active
CS*, FSO or FS1 Hold
time
t CS
20
0
ns
ns
t CH
Read Data Hold time
Write Data Hold time
Muxed Address valid to
AS or ALE fall
t DHR
t DHW
t ASL
10
0
15
50
ns
ns
ns
Muxed Address Hold
time
Delay time DS, WR* or
RD* to AS or ALE rise
Pulse Width AS or ALE
high
Delay time, AS or ALE
to DS, WR* or RD*
Output Data Delay time
from DS or RD*
Data Set Up time
t AHL
t ASD
10
20
30
10
20
50
ns
ns
ns
ns
ns
ns
PW ASH
t ASED
t DDR
80
t DSW
(see Figures 21-1 to 21-3 for details)
105 of 119
DS21Q42
AC CHARACTERISTICS –
NON–MULTIPLEXED PARALLEL PORT (MUX=0 )
(0ºC to 70ºC; VDD = 2.97 to 3.63V for DS21Q42T;
–40ºC to +85ºC; VDD = 2.97 to 3.63V for 21Q42TN)
PARAMETER
SYMBOL MIN
TYP
MAX
UNITS
NOTES
Set Up Time for A0 to
A7, FS0 or FS1 Valid to
CS*Active
Set Up Time for CS*
Active to either RD*,
WR*, or DS* Active
Delay Time from either
RD* or DS* Active to
Data Valid
Hold Time from either
RD*, WR*, or DS*
Inactive to CS* Inactive
Hold Time from CS*
Inactive to Data Bus 3–
state
Wait Time from either
WR* or DS* Active to
Latch Data
t1
t2
t3
t4
t5
t6
t7
t8
t9
0
ns
0
ns
ns
ns
ns
ns
ns
ns
ns
75
20
0
5
75
10
10
10
Data Set Up Time to
either WR* or DS*
Inactive
Data Hold Time from
either WR* or DS*
Inactive
Address Hold from either
WR* or DS* inactive
See Figures 21–4 to 21–7 for details.
106 of 119
DS21Q42
AC CHARACTERISTICS – RECEIVE SIDE
(0ºC to 70ºC; VDD = 2.97 to 3.63V for DS21Q42T;
–40ºC to +85ºC; VDD = 2.97 to 3.63V for DS21Q42TN)
PARAMETER
RCLK Period
SYMBOL MIN
TYP
MAX
UNITS
ns
NOTES
t CP
648
RCLK Pulse Width
t CH
t CL
t SP
t SP
t SH
75
75
122
122
t SL
ns
ns
ns
ns
RSYSCLK Period
648
488
50
1
2
RSYSCLK Pulse Width
ns
50
ns
RSYNC Set Up to
RSYSCLK Falling
RSYNC Pulse Width
RPOS/RNEG Set UP to
RCLK Falling
t SU
20
t SH –5
ns
t PW
t SU
50
20
ns
ns
RPOS/RNEG Hold From
RCLK Falling
RSYSCLK/RCLK Rise
and Fall Times
Delay RCLK to RSER,
RSIG, RLINK Valid
Delay RCLK to
t HD
t R , t F
t D1
20
ns
ns
ns
ns
25
50
50
t D2
RCHCLK, RSYNC,
RCHBLK, RFSYNC,
RLCLK
Delay RSYSCLK to
RSER, RSIG Valid
Delay RSYSCLK to
RCHCLK, RCHBLK,
RMSYNC, RSYNC
t D3
t D4
50
50
ns
ns
See Figures 21-8 to 21-10 for details.
Notes:
1. RSYSCLK = 1.544 MHz.
2. RSYSCLK = 2.048 MHz.
107 of 119
DS21Q42
AC CHARACTERISTICS – TRANSMIT SIDE
(0ºC to 70ºC; VDD = 2.97 to 3.63V for DS21Q42T;
–40ºC to +85ºC; VDD = 2.97 to 3.63V for DS21Q42TN)
PARAMETER
TCLK Period
SYMBOL MIN
TYP
MAX
UNITS
ns
NOTES
t CP
648
TCLK Pulse Width
t CH
t CL
t LH
t LL
t SP
t SP
t SH
t SL
t SU
75
75
75
ns
ns
ns
ns
ns
ns
ns
ns
TCLKI Pulse Width
TSYSCLK Period
75
122
122
50
50
20
648
448
1
2
TSYSCLK Pulse Width
TSYNC or TSSYNC Set
Up to TCLK or
t CH –5
ns
or
TSYSCLK falling
TSYNC or TSSYNC
Pulse Width
TSER, TSIG, TLINK Set
Up to TCLK, TSYSCLK
Falling
t
SH –5
t PW
t SU
50
20
ns
ns
TSER, TSIG, TLINK
Hold from TCLK,
TSYSCLK Falling
TCLK or TSYSCLK Rise
and Fall Times
Delay TCLK to TPOS,
TNEG Valid
Delay TCLK to
t HD
20
ns
t R , t F
t DD
25
50
50
ns
ns
ns
t D2
TCHBLK, TCHBLK,
TSYNC, TLCLK
Delay TSYSCLK to
TCHCLK, TCHBLK
t D3
75
ns
See Figures 21–11 to 21–13 for details.
Notes:
1. TSYSCLK = 1.544 MHz.
2. TSYSCLK = 2.048 MHz.
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DS21Q42
INTEL BUS READ AC TIMING (BTS=0 / MUX = 1) Figure 21-1
INTEL BUS WRITE TIMING (BTS=0 / MUX=1) Figure 21-2
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DS21Q42
MOTOROLA BUS AC TIMING (BTS = 1 / MUX = 1) Figure 21-3
INTEL BUS READ AC TIMING (BTS=0 / MUX=0) Figure 21-4
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DS21Q42
INTEL BUS WRITE AC TIMING (BTS=0 / MUX=0) Figure 21-5
MOTOROLA BUS READ AC TIMING (BTS=1 / MUX=0) Figure 21-6
Note:
1. The signal DS is active high when emulating the DS21Q41 (FMS = 1).
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DS21Q42
MOTOROLA BUS WRITE AC TIMING (BTS=1 / MUX=0) Figure 21-7
Note:
1. The signal DS is active high when emulating the DS21Q41 (FMS = 1).
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DS21Q42
RECEIVE SIDE AC TIMING Figure 21-8
Notes:
1. RSYNC is in the output mode (RCR2.3 = 0).
2. Shown is RLINK/RLCLK in the ESF framing mode.
3. No relationship between RCHCLK and RCHBLK and the other signals is implied.
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DS21Q42
RECEIVE SYSTEM SIDE AC TIMING Figure 21-9
Notes:
1. RSYNC is in the output mode (RCR2.3 = 0)
2. RSYNC is in the input mode (RCR2.3 = 1)
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DS21Q42
RECEIVE LINE INTERFACE AC TIMING Figure 21-10
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DS21Q42
TRANSMIT SIDE AC TIMING Figure 21-11
Notes:
1. TSYNC is in the output mode (TCR2.2 = 1).
2. TSYNC is in the input mode (TCR2.2 = 0).
3. TSER is sampled on the falling edge of TCLK when the transmit side elastic store is disabled.
4. TCHCLK and TCHBLK are synchronous with TCLK when the transmit side elastic store is disabled.
5. TLINK is only sampled during F-bit locations.
6. No relationship between TCHCLK and TCHBLK and the other signals is implied.
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DS21Q42
TRANSMIT SYSTEM SIDE AC TIMING Figure 21-12
Notes:
1. TSER is only sampled on the falling edge of TSYSCLK when the transmit side elastic store is
enabled.
2. TCHCLK and TCHBLK are synchronous with TSYSCLK when the transmit side elastic store is
enabled.
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DS21Q42
TRANSMIT LINE INTERFACE SIDE AC TIMING Figure 21-13
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DS21Q42
22. 128-Pin TQFP Package Specifications
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