DS92LX2121SQE/NOPB [ROCHESTER]
LINE DRIVER, QCC40, 6 X 6 MM, 0.80 MM HEIGHT, 0.50 MM PITCH, LLP-40;
| 型号： | DS92LX2121SQE/NOPB |
| 厂家： | 
Rochester Electronics |
| 描述： | LINE DRIVER, QCC40, 6 X 6 MM, 0.80 MM HEIGHT, 0.50 MM PITCH, LLP-40 驱动 接口集成电路 驱动器 |
| 文件： | 总39页 (文件大小：1518K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
January 14, 2011
DS92LX2121 / DS92LX2122
10 - 50 MHz DC-Balanced Channel Link III Bi-Directional
Control Serializer and Deserializer
General Description
Features
The DS92LX2121/DS92LX2122 chipset offers a Channel
Link III interface with a high-speed forward channel and a full-
duplex control channel for data transmission over a single
differential pair. The DS92LX2121/DS92LX2122 incorpo-
rates differential signaling on both the high-speed and bi-
directional back channel control data paths. The Serializer/
Deserializer pair is targeted for direct connections between
graphics host controller and displays modules. This chipset is
ideally suited for driving video data to displays requiring 18-
bit color depth (RGB666 + HS, VS, and DE) along with a bi-
directional back channel control bus. The primary transport
converts 21 bit data over a single high-speed serial stream,
along with a separate low latency bi-directional back channel
transport that accepts control information from an I2C port.
Using National’s embedded clock technology allows trans-
parent full-duplex communication over a single differential
pair, carrying asymmetrical bi-directional back channel con-
trol information in both directions. This single serial stream
simplifies transferring a wide data bus over PCB traces and
cable by eliminating the skew problems between parallel data
and clock paths. This significantly saves system cost by nar-
rowing data paths that in turn cable width, connector size and
pins.
Up to 1050 Mbits/sec data throughput
■
■
■
■
10 MHz to 50 MHz input clock support
Supports 18-bit color depth (RGB666 + HS, VS, DE)
Embedded clock with DC Balanced coding to support AC-
coupled interconnects
Capable to drive up to 10 meters shielded twisted-pair
Bi-directional control interface channel with I2C support
I2C interface for device configuration. Single-pin ID
addressing
■
■
■
Up to 4 GPI on DES and GPO on SER
■
■
■
■
AT-SPEED BIST diagnosis feature to validate link integrity
Individual power-down controls for both SER and DES
User-selectable clock edge for parallel data on both SER
and DES
Integrated termination resistors
■
■
■
■
1.8V- or 3.3V-compatible parallel bus interface
Single power supply at 1.8V
IEC 61000–4–2 ESD compliant
Temperature range −40°C to +85°C
■
DESERIALIZER — DS92LX2122
In addition, the Deserializer provides input equalization to
compensate for loss from the media over longer distances.
Internal DC balanced encoding/decoding is used to support
AC-Coupled interconnects.
No reference clock required on Deserializer
■
■
■
■
Programmable Receive Equalization
LOCK output reporting pin to ensure
EMI/EMC Mitigation
A sleep function provides a power-savings mode when the
high speed forward channel and embedded bi-directional
control channel are not needed.
Programmable Spread Spectrum (SSCG) outputs
Receiver Output Drive Strength control (RDS)
Receiver staggered outputs
The Serializer is offered in a 40-pin lead in LLP and Deseri-
alizer is offered in a 48-pin LLP packages.
Applications
Industrial Displays, Touch Screens
■
■
Medical Imaging
Typical Application Diagram
30125127
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 2011 National Semiconductor Corporation
301251
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Block Diagrams
30125128
FIGURE 1. Block Diagram
30125129
FIGURE 2. Application Block Diagram
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2
Ordering Information
NSID
Package Description
Quantity
250
SPEC
NOPB
NOPB
NOPB
NOPB
NOPB
NOPB
Package ID
SQA40A
SQA40A
SQA40A
SQA48A
SQA48A
SQA48A
DS92LX2121SQE
DS92LX2121SQ
DS92LX2121SQX
DS92LX2122SQE
DS92LX2122SQ
DS92LX2122SQX
40-pin LLP, 6.0 X 6.0 X 0.8 mm, 0.5 mm pitch
40-pin LLP, 6.0 X 6.0 X 0.8 mm, 0.5 mm pitch
40-pin LLP, 6.0 X 6.0 X 0.8 mm, 0.5 mm pitch
48-pin LLP, 7.0 X 7.0 X 0.8 mm, 0.5 mm pitch
48-pin LLP, 7.0 X 7.0 X 0.8 mm, 0.5 mm pitch
48-pin LLP, 7.0 X 7.0 X 0.8 mm, 0.5 mm pitch
1000
4500
250
1000
4500
DS92LX2121 Pin Diagram
30125119
Serializer - DS92LX2121 — Top View
3
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DS92LX2121 Serializer Pin Descriptions
Pin Name
Pin No.
I/O, Type
Description
LVCMOS PARALLEL INTERFACE
DIN[20:0]
5, 4, 3, 2, 1, 40, Inputs, LVCMOS w/ Parallel data inputs.
39, 38, 37, 36,
35, 33, 32, 30,
29, 28, 27, 26,
25, 24, 23
pull down
PCLK
6
Input, LVCMOS w/ Pixel Clock Input Pin. Strobe edge set by TRFB configuration.
pull down
GENERAL PURPOSE OUTPUT (GPO)
GPO[3:0] 22, 21, 20, 19
Output, LVCMOS General-purpose pins individually configured as outputs; which are used to
control and respond to various commands.
SERIAL CONTROL BUS - I2C COMPATIBLE
Clock line for the serial control bus communication
Input/Output, Open
Drain
SCL
SDA
7
8
SCL requires an external pull-up resistor to VDDIO
.
Data line for the serial control bus communication
Input/Output, Open
Drain
SDA requires an external pull-up resistor to VDDIO
.
I2C Mode Select
M/S = L, Master mode (default); device generates and drives the SCL clock
line. Device is connected to a slave peripheral on the bus. (Serializer initially
starts up in Standby mode and is enabled through remote wakeup by the
Deserializer)
Input, LVCMOS w/
pull down
M/S
12
M/S = H, Slave; device accepts SCL clock input
Continuous Address Decoder
Input pin to select the Slave Device Address.
Input is connect to external resistor divider to programmable Device ID
address (see Serial Control Bus Connection).
CAD
9
Input, analog
CONTROL AND CONFIGURATION
Power down Mode Input Pin.
Input, LVCMOS w/ PDB = H, Transmitter is enabled and is ON.
PDB
RES
13
pull down
PDB = L, Transmitter is in Sleep (Power Down). When the transmitter is in
the SLEEP state, the PLL is shutdown, and IDD is minimized.
Input, LVCMOS w/ Reserved. This pin MUST be tied LOW.
pull down
10, 11
Channel Link III INTERFACE
DOUT+
17
16
Input/Output, CML Non-inverting differential output, back-channel input.
Input/Output, CML Inverting differential output, back-channel input.
DOUT-
Power and Ground
VDDPLL
VDDT
14
15
18
34
31
Power, Analog
Power, Analog
Power, Analog
Power, Digital
Power, Digital
Ground, DAP
PLL Power, 1.8V ±5%
Tx Analog Power, 1.8V ±5%
VDDCML
VDDD
LVDS & BC Dr Power, 1.8V ±5%
Digital Power, 1.8V ±5%
Power for input stage, The single-ended inputs are powered from VDDIO
.
VDDIO
DAP must be grounded. Connect to the ground plane (GND) with at least 16
vias.
VSS
DAP
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4
DS92LX2122 Pin Diagram
30125120
Deserializer - DS92LX2122 — Top View
5
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DS92LX2122 Deserializer Pin Descriptions
Pin Name
Pin No.
I/O, Type
Description
LVCMOS PARALLEL INTERFACE
ROUT[20:0]
5, 6, 8, 9, 10, 11, Outputs, LVCMOS Parallel data outputs.
12, 13, 14, 15,
16, 18, 19, 21,
22, 23, 24, 25,
26, 27, 28
Pixel Clock Output Pin.
PCLK
4
Output, LVCMOS Strobe edge set by RFB configuration. In SLEEP, outputs are controlled by
the OSS_SEL.
General Purpose Input (GPI)
General-purpose pins individually configured as inputs; which are used to
control and respond to various commands.
GPI[3:0]
30, 31, 32, 33 Input/Output, Digital
SERIAL CONTROL BUS - I2C COMPATIBLE
Clock line for the serial control bus communication
Input/Output, Open
Drain
SCL
SDA
2
1
SCL requires an external pull-up resistor to VDDIO
.
Data line for serial control bus communication
Input/Output, Open
Drain
SDA requires an external pull-up resistor to VDDIO
I2C Mode Select
.
M/S = L, Master; device generates and drives the SCL clock line. Device is
connected to slave peripheral on teh bus.
Input, LVCMOS w/
pull up
M/S
47
M/S = H, Slave (default); device accepts SCL clock input and is attached to
an I2C controller master on the bus. Slave mode does not generate the SCL
clock, but uses the clock generated by teh Master for teh data transfer.
Continuous Address Decoder
Input pin to select the Slave Device Address.
Input is connect to external resistor divider to programmable Device ID
address (see Serial Control Bus Connection)
CAD
48
Input, analog
CONTROL AND CONFIGURATION
Power down Mode Input Pin.
PDB = H, Receiver is enabled and is ON.
Input, LVCMOS w/
pull down
PDB
35
PDB = L, Receiver is in Sleep (Power down mode). When the Receiver is in
the SLEEP state, the LVCMOS Outputs are in TRI-STATE, the PLL is
shutdown and IDD is minimized.
LOCK Status Output Pin.
LOCK = H, PLL is Locked, outputs are active
LOCK = L, PLL is unlocked, ROUT and PCLK output states are controlled by
OSS_SEL. May be used as Link Status.
LOCK
RES
34
Output, LVCMOS
Reserved.
Pin 43: Leave pin open.
Pin 46: This pin MUST be tied LOW.
38, 39, 43, 46
-
Pins 38, 39: Route to test point as differential pair or leave open if unused.
BIST MODE
BIST Enable Pin.
Input, LVCMOS w/
pull down
BISTEN
44
37
BISTEN = H, BIST Mode is enabled.
BISTEN = L, BIST Mode is disabled.
PASS Output Pin for BIST mode.
PASS = H, ERROR FREE Transmission
PASS = L, one or more errors were detected in the received payload.
Leave Open if unused. Route to test point (pad) recommended.
PASS
Output, LVCOMS
Channel Link III INTERFACE
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6
Pin Name
RIN+
RIN-
Pin No.
I/O, Type
Description
Non-inverting differential input, back channel output. The interconnect must
be AC coupled with a 0.1μF capacitor.
Inverting differential input, back channel output. The interconnect must be AC
coupled with a 0.1 μF capacitor.
41
Input/Output, CML
42
Input/Output, CML
POWER AND GROUND
SSCG Power, 1.8V ±5%
Power supply must be connect regardless if SSCG function is in operation
VDDSSCG
3
Digital Power
Digital Power
TTL Output Buffer Power, The single-ended outputs and control input are
powered from VDDIO. VDDIO can be connected to a 1.8V ±5% or 3.3V ±10%
VDDOR1/2/3
29, 20, 7
VDDD
17
36
40
45
Digital Power
Analog Power
Analog Power
Analog Power
Digital Core Power, 1.8V ±5%
Rx Analog Power, 1.8V ±5%
VDDR
VDDCML
VDDPLL
Bi-directional Channel Driver Power, 1.8V ±5%
PLL Power, 1.8V ±5%
DAP must be grounded. Connect to the ground plane (GND) with at least 16
vias.
VSS
DAP
Ground, DAP
7
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ESD Rating (IEC61000–4–2)
RD = 330Ω, CS = 150 pF
≥±25 kV
Absolute Maximum Ratings (Note 1)
Air Discharge
(DOUT+, DOUT-, RIN+, RIN-)
Contact Discharge
(DOUT+, DOUT-, RIN+, RIN-)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
≥±10 kV
≥±8 kV
Supply Voltage ( VDD1V8
Supply Voltage (VDD3V3
)
−0.3V to +2.5V
−0.3V to +4.0V
ESD Rating (HBM)
)
For soldering specifications:
see product folder at www.national.com and
www.national.com/ms/MS/MS-SOLDERING.pdf
LVCMOS Input Voltage (VDD1V8
LVCMOS Input Voltage (VDD3V3
)
)
−0.3V to +(VDD1V8 + 0.3V)
−0.3V to +(VDD3V3 + 0.3V)
−0.3V to +(VDD + 0.3V)
LVCMOS Output Voltage (VDD
)
Recommended Operating
Conditions
CML Receiver Input Voltage
(VDD1V8
CML Driver Output Voltage
(VDD1V8
)
−0.3V to (VDD1V8 + 0.3V)
Min
1.71
1.71
3
Nom
Max
1.89
1.89
3.6
Units
)
−0.3V to (VDD1V8 + 0.3V)
+150°C
VDD (1.8V)
1.8
V
V
V
Junction Temperature
Storage Temperature
Maximum Package Power
Dissipation Capacity
Package Derating:
DS92LX2121 40L LLP
VDDIO (1.8V Mode)
VDDIO (3.3V Mode)
Supply Noise
VDDn (1.8 V)
1.8
−65°C to +150°C
3.3
1/θJA °C/W above +25°
25
25
50
mVP-P
mVP-P
mVP-P
VDDIO (1.8 V)
VDDIO (3.3 V)
30.7 °C/W
6.8 °C/W
ꢀθJA(based on 16 thermal vias)
ꢀθJC(based on 16 thermal vias)
DS92LX2122 48L LLP
Operating Free Air
Temperature (TA)
-40
10
25
85
50
°C
Input Clock Rate
MHz
ꢀθJA(based on 16 thermal vias)
ꢀθJC(based on 16 thermal vias)
26.9 °C/W
4.4 °C/W
Serializer Electrical Characteristics (Note 2, Note 3, Note 4)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
LVCMOS DC SPECIFICATIONS 3.3V I/O (TX INPUTS, RX OUTPUTS, GPIO, CONTROL INPUTS AND OUTPUTS)
VIH
VIL
IIN
High Level Input Voltage
Low Level Input Voltage
Input Current
VIN = 3.0V to 3.6V
VIN = 3.0V to 3.6V
2.0
GND
-20
VIN
0.8
V
V
VIN = 0V or 3.6V
±1
+20
µA
VIN = 3.0V to 3.6V
VOH
VOL
High Level Output Voltage
Low Level Output Voltage
VDDIO = 3.0V to 3.6V
2.4
VDDIO
0.4
V
V
VDDIO = 3.0V to 3.6V
IOH = +4mA
GND
IOS
Output Short Circuit Current VOUT = 0V
Serializer GPO
Outputs
mA
µA
-24
-39
Deserializer
LVCMOS
Outputs
Register
Address
(OSS_SEL = 0)
RPWDNB = 0V,
IOZ
TRI-STATE® Output Current
-20
+20
VOUT = 0V or VDD
LVCMOS DC SPECIFICATIONS 1.8V I/O (TX INPUTS, RX OUTPUTS, GPIO, CONTROL INPUTS AND OUTPUTS)
VIH
VIL
IIN
High Level Input Voltage
Low Level Input Voltage
Input Current
VIN = 1.71V to 1.89V
VIN = 1.71V to 1.89V
0.65 VIN
GND
-20
VIN + 0.3
0.35 VIN
+20
V
VIN = 0V or 1.89V
±1
µA
VIN = 1.71V to 1.89V
VOH
VOL
High Level Output Voltage
Low Level Output Voltage
VDDIO = 1.71V to 1.89V
IOH = −4mA
VDDIO
0.45
-
VDDIO
0.45
V
V
VDDIO = 1.71V to 1.89V
IOL = +4 mA
GND
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8
Symbol
IOS
Parameter
Conditions
Min
Typ
Max
Units
mA
Output Short Circuit Current VOUT = 0V (Note 11)
Serializer GPO
Outputs
-11
Deserializer
LVCMOS
Outputs
-20
±1
IOZ
TRI-STATE® Output Current RPWDNB = 0V,
VOUT = 0V or VDD
Register
Address
-20
+20
µA
(OSS_SEL = 0)
CML DRIVER DC SPECIFICATIONS (DOUT+, DOUT-)
268
340
1
412
50
|VOD
|
Output Differential Voltage
RT = 100Ω (Figure 6)
mV
mV
Output Differential Voltage
Unbalance
ΔVOD
RL = 100Ω
VDD (MIN)
-
VDD - VOD VDD (MAX)
VOD (MIN)
-
Output Differential Offset
Voltage
VOS
RL = 100Ω (Figure 6)
RL = 100Ω
V
VOD (MAX)
Offset Voltage Unbalance
1
50
mV
mA
ΔVOS
IOS
Output Short Circuit Current DOUT+/- = 0V,
PDB = L or H (Note 11)
Differential across DOUT+ and DOUT-
-27
RT
Differential Internal
80
100
120
+90
Ω
Termination Resistance
CML RECEIVER DC SPECIFICATIONS (RIN+, RIN-)
Differential Threshold High
VTH
Voltage
VCM = 1.2V
mV
mV
VTL
VIN
Differential Threshold Low
Voltage
-90
180
-20
Differential Input Voltage
Range
RIN+ - RIN-
VIN = VDD or 0 V,
VDD = 1.89 V
±1
+20
120
IIN
Input Current
µA
RT
Differential Internal
Termination Resistance
80
100
Ω
Differential across RIN+ and RIN-
SER/DES SUPPLY CURRENT *DIGITAL, PLL, AND ANALOG VDDS
62
55
90
RT = 100Ω
WORST CASE pattern
(Figure 4)
VDDn = 1.89 V
f = 50 MHz
Default
Serializer (Tx)
Total Supply Current Mode
(includes load current)
IDDT
mA
RT = 100Ω
RANDOM pattern
Registers
VDDIO = 1.89 V
PCLK = 50 MHz
Default
RT = 100Ω WORST CASE
pattern (Figure 4)
2
7
5
Serializer (Tx)
VDDIO Supply Current
(includes load current)
Registers
IDDIOT
mA
µA
VDDIO = 3.6 V
PCLK = 50 MHz
Default
15
Registers
IDDTZ
VDD = 1.89 V
VDDIO = 1.89 V
VDDIO = 3.6 V
370
55
775
125
135
Serializer (Tx) Supply Current PDB = 0V; All other
Power-down LVCMOS Inputs = 0V
IDDIOTZ
65
9
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Symbol
Parameter
Conditions
Min
Typ
Max
Units
VDDn = 1.89V
CL = 8pF
WORST CASE Pattern
PCLK = 50 MHz
SSCG[3:0] =
ON
60
96
Deserializer (Rx)
VDDn Supply Current
(includes load current)
Default
Registers
(Figure 4)
IDDR
mA
VDDn = 1.89V
CL = 8pF
RANDOM Pattern
PCLK = 50 MHz
Default
Registers
53
21
IDDIOR
Deserializer (Rx)
VDDIO Supply Current
(includes load current)
VDDIO = 1.89 V
CL = 8pF
WORST CASE Pattern
(Figure 4)
PCLK = 50 MHz
Default
Registers
32
83
mA
µA
VDDIO = 3.6 V
CL = 8pF
WORST CASE Pattern
(Figure 4)
PCLK = 50 MHz
Default
Registers
49
PDB = 0V; All other
LVCMOS Inputs = 0V
VDDn = 1.89 V
VDDIO = 1.89 V
VDDIO = 3.6 V
42
8
400
40
IDDRZ
Deserializer (Rx) Supply
Current Power-down
IDDIORZ
350
800
Recommended Serializer Timing for PCLK
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
tTCP
tTCIH
Parameter
Conditions
10 MHz – 50 MHz
(Note 11)
Min
20
Typ
Max
Units
ns
Transmit Clock Period
T
100
Transmit Clock Input High
Time
0.4T
0.5T
0.6T
ns
tTCIL
Transmit Clock Input Low
Time
0.4T
0.5
0.5T
25
0.6T
3
ns
tCLKT
tOSC
PCLK Input Transition Time
ns
Internal oscillator clock
source
MHz
Serializer Switching Characteristics
Symbol
tLHT
Parameter
Conditions
Min
Typ
Max
Units
CML Low-to-High
Transition Time
RL = 100Ω (Figure 5)
150
150
330
330
ps
tHLT
CML High-to-Low
Transition Time
RL = 100Ω
(Figure 5)
ps
tDIS
tDIH
tPLD
Data Input Setup to PCLK
Data Input Hold from PCLK
Serializer PLL Lock Time
2.0
2.0
ns
ns
Serializer Data Inputs (Figure 9)
RL = 100Ω
1
2
ms
RT = 100Ω
f = 10-50 MHz
Reg Address 0x03h b[0] (TRFB = 1)
(Figure 11)
6.386T + 6.386T +
tSD
Serializer Delay
6.386T + 5
ns
12
19.7
tJIND
Serializer Output
Deterministic Jitter
Serializer output intrinsic deterministic
jitter . Measured (cycle-cycle) with
PRBS-7 test pattern PCLK = 50 MHz
0.13
0.04
UI
UI
tJINR
Serializer Output Random Serializer output intrinsic random jitter
Jitter
(cycle-cycle). Alternating-1,0 pattern.
PCLK = 50 MHz
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10
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Serializer output peak-to-peak jitter
includes deterministic jitter, random
jitter, and jitter transfer from serializer
input. Measured (cycle-cycle) with
PRBS-7 test pattern.
Peak-to-peak Serializer
Output Jitter
tJINT
0.396
UI
PCLK = 50MHz
Serializer Jitter Transfer
Function -3 dB Bandwidth
PCLK = 50 MHz Default Registers
PCLK = 50 MHz Default Registers
PCLK = 50 MHz Default Registers
λSTXBW
δSTX
1.90
MHz
dB
Serializer Jitter Transfer
Function (Peaking
0.944
Serializer Jitter Transfer
Function (Peaking
Frequency)
δSTXf
500
kHz
Deserializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
tRCP
Parameter
Receiver Output Clock Period
PCLK Duty Cycle
Conditions
tRCP = tTCP
Pin/Freq.
PCLK
Min
Typ
T
Max
100
55
Units
20
45
ns
%
tPDC
PCLK
50
2.0
LVCMOS Low-to-High Transition VDDIO: 1.71 V to 1.89 V
Time
1.3
2.8
tCLH
tCHL
tCLH
or 3.0 V to 3.6 V,
CL = 8pF (lumped load)
Default Registers
( ) (Note 10)
Deserializer PCLK
Output
ns
ns
1.3
2.0
2.8
LVCMOS High-to-Low Transition
Time
LVCMOS Low-to-High Transition VDDIO: 1.71 V to 1.89 V
Time
1.6
1.6
2.4
2.4
3.3
3.3
or 3.0 V to 3.6 V,
CL = 8pF (lumped load)
Default Registers
Deserializer Data
Outputs
LVCMOS High-to-Low Transition
Time
tCHL
tROS
tROH
(Figure 13) (Note 10)
VDDIO: 1.71 V to 1.89 V
or 3.0 V to 3.6 V, CL =
8pF (lumped load)
ROUT Setup Data to PCLK
ROUT Hold Data to PCLK
0.38
0.5
Deserializer Data
Outputs
T
0.38T
0.5T
Default Registers
Default Registers
Register 0x03h b[0]
(RRFB = 1)
4.571T + 4.571T + 4.571T
tDD
Deserializer Delay
10 MHz - 50 MHz
ns
8
12
+ 16
Figure 14
tDDLT
tRJIT
(Note 5)
10 MHz - 50 MHz
50 MHz
10
Deserializer Data Lock Time
Receiver Input Jitter Tolerance
ms
UI
(Note 13, Note 14)
0.53
300
PCLK
SSCG[3:0] = OFF
(Note 6, Note 11)
10 MHz
550
250
ps
tDCJ
Deserializer Clock Jitter
Deserializer Period Jitter
50 MHz
120
PCLK
SSCG[3:0] = OFF
(Note 7, Note 11)
10 MHz
50 MHz
425
320
600
480
tDPJ
ps
ps
PCLK
SSCG[3:0] = OFF
(Note 8, Note 11)
10 MHz
50 MHz
320
300
500
500
Deserializer Cycle-to-Cycle Clock
Jitter
tDCCJ
Spread Spectrum Clocking
Deviation Frequency
20 MHz - 50 MHz
20 MHz - 50 MHz
±0.5% to
±2.0%
%
fDEV
LVCMOS Output Bus
SSC[3:0] = ON
Figure 16
Spread Spectrum Clocking
Modulation Frequency
9 kHz to
66 kHz
kHz
fMOD
11
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Bi-Directional Control Bus AC Timing Specifications (SCL, SDA) - I2C
Compliant (Figure 3)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
RECOMMENDED INPUT TIMING REQUIREMENTS ()
fSCL
fSCL = 100 kHz
SCL Clock Frequency
SCL Low Period
>0
4.7
4.0
100
kHz
µs
fLOW
fHIGH
SCL High Period
µs
Hold time for a start or a repeated start
condition
tHD:STA
tSU:STA
4.0
4.7
µs
µs
Set Up time for a start or a repeated
start condition
tHD:DAT
tSU:DAT
tSU:STO
tr
Data Hold Time
0
3.45
µs
ns
µs
ns
ns
pF
Data Set Up Time
250
4.0
Set Up Time for STOP Condition,
SCL & SDA Rise Time
SCL & SDA Fall Time
Capacitive load for bus
1000
300
tf
Cb
400
SWITCHING CHARACTERISTICS ()
Serializer MODE = 0 – R/W Register
0x05 = 0x40'h
100
100
fSCL
SCL Clock Frequency
SCL Low Period
kHz
μs
Deserializer MODE = 0 – READ
Register 0x06 b[6:4] = 0x00'h
Serializer MODE = 0 – R/W Register
0x05 = 0x40'h
tLOW
4.7
4.0
Deserializer MODE = 0 – READ
Register 0x06 b[6:4] = 0x00'h
Serializer MODE = 0 – R/W Register
0x05 = 0x40'h
tHIGH
SCL High Period
μs
Deserializer MODE = 0 – READ
Register 0x06 b[6:4] = 0x00'h
Hold time for a start or a repeated start Serializer MODE = 0 Register 0x05
tHD:STA
4.0
4.7
μs
μs
condition
= 0x40'h
Set Up time for a start or a repeated
start condition
Serializer MODE = 0 Register 0x05
= 0x40'h
tSU:STA
tHD:DAT
tSU:DAT
tSU:STO
tf
Data Hold Time
0
3.45
300
μs
μs
μs
μs
Data Set Up Time
250
4.0
Set Up Time for STOP Condition
SCL & SDA Fall Time
Serializer M/S = 0
Bus free time between a stop and start Serializer M/S = 0
condition
tBUF
4.7
µs
Serializer
1
tTIMEOUT
NACK Time out
Deserializer
ms
25
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12
30125136
FIGURE 3. Serial Control Bus Timing
Bi-Directional Control Bus DC Characteristics (SCL, SDA) - I2C Compliant
Symbol
Parameter
Conditions
Min
Typ
Max
Units
VIH
VIL
Input High Level
SDA and SCL
0.7 x
VDDIO
VDDIO
V
Input Low Level Voltage
Input Hysteresis
SDA and SCL
0.3 x
VDDIO
GND
V
VHY
IOZ
>50
±1
mV
µA
TRI-STATE® Output
Current
PDB = 0V VOUT = 0V or VDD
SDA or SCL, Vin = VDDIO or GND
-20
-20
+20
+20
IIN
Input Current
±1
<5
µA
pF
CIN
VOL
Input Pin Capacitance
Low Level Output Voltage SCL and SDA VDDIO = 3.0V IOL = 1.5
mA
0.36
0.36
V
V
SCL and SDA VDDIO = 1.71V IOL = 1
mA
Note 1: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability
and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in
the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional; the device
should not be operated beyond such conditions.
Note 2: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified
or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed.
Note 3: Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground except VOD, ΔVOD,
VTH and VTL which are differential voltages.
Note 4: Typical values represent most likely parametric norms at 1.8V or 3.3V, TA = +25°C, and at the Recommended Operation Conditions at the time of product
characterization and are not guaranteed.
Note 5: tPLD and tDDLT is the time required by the serializer and deserializer to obtain lock when exiting power-down state with an active PCLK.
Note 6: tDCJ is the maximum amount of jitter measured over 30,000 samples based on Time Interval Error (TIE).
Note 7: tDPJ is the maximum amount the period is allowed to deviate measured over 30,000 samples.
Note 8: tDCCJ is the maximum amount of jitter between adjacent clock cycles measured over 30,000 samples.
Note 9: Supply noise testing was done with minimum capacitors (as shown on Figures 35, 36) on the PCB. A sinusoidal signal is AC coupled to the VDDn (1.8V)
supply with amplitude = 25 mVp-p measured at the device VDDn pins. Bit error rate testing of input to the Ser and output of the Des with 10 meter cable shows
no error when the noise frequency on the Ser is less than 1 MHz. The Des on the other hand shows no error when the noise frequency is less than 750 kHz.
Note 10: Specification is guaranteed by design and is not tested in production.
Note 11: Specification is guaranteed by characterization and is not tested in production.
Note 12: Recommended Input Timing Requirements are input specifications and not tested in production.
Note 13: UI – Unit Interval is equivalent to one ideal serialized data bit width. The UI scales with PCLK frequency.
Note 14: tRJIT max (0.61UI) is limited by instrumentation and actual tRJIT of in-band jitter at low frequency (<2 MHz) is greater 1 UI.
13
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AC Timing Diagrams and Test Circuits
30125152
FIGURE 4. “Worst Case” Test Pattern
30125146
30125147
FIGURE 5. Serializer CML Output Load and Transition Times
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14
30125148
30125130
FIGURE 6. Serializer VOD DC Diagram
30125134
FIGURE 7. Low-Voltage Differential VTH/VTL Definition Diagram
30125116
FIGURE 8. Serializer Input Clock Transition Times
15
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30125149
FIGURE 9. Serializer Setup/Hold Times
30125132
FIGURE 10. Serializer Data Lock Time
30125150
FIGURE 11. Serializer Delay
30125113
FIGURE 12. Deserializer Data Lock Time
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16
30125114
FIGURE 13. Deserializer LVCMOS Output Load and Transition Times
30125111
FIGURE 14. Deserializer Delay
30125131
FIGURE 15. Deserializer Output Setup/Hold Times
30125135
FIGURE 16. Spread Spectrum Clock Output Profile
17
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30125162
FIGURE 17. Typical Serializer Jitter Transfer Function Curve at 43 MHz
30125159
FIGURE 18. Typical Deserializer Input Jitter Tolerance Curve at 43 MHz
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18
TABLE 1. DS92LX2121 Control Registers
Addr
(Hex)
Name
Bits Field
R/W
RW
RW
Default Description
7-bit address of Serializer; 0x58h
(1011_000X) default
7:1 DEVICE ID
0x58
I2C Device ID
0
0: Device ID is from CAD
1: Register I2C Device ID overrides CAD
0
SER ID
0
0
7:3 RESERVED
Reserved.
Standby mode control. Retains control register data.
Supported only when M/S = 0
2
STANDBY
RW
0
0: Enabled. Low-current Standby mode with wake-up
capability. Suspends all clocks and functions.
1: Disabled. Standby and wake-up disabled
1
2
Reset
DIGITAL
RESET0
0
1: Digital Reset, retained register value
1
0
RW
RW
self clear
0
1: Digital Reset, retains all register values
DIGITAL RESET1
self clear
Reserved
Reserved
7:0 RESERVED
7:6 RESERVED
0x20'h Reserved.
11'b
Reserved.
Auto VDDIO detect
Allows manual setting of VDDIO by register.
0: Disable
1: Enable (auto detect mode)
VDDIO Control
VDDIO Mode
5
4
VDDIO CONTOL
RW
1
VDDIO voltage set
Only used when VDDIOCONTROL = 0
0: 1.8V
1: 3.3V
I2C Pass-Through Mode
0: Disabled
1: Enabled
VDDIO MODE
RW
RW
1
I2C Pass-
Through
I2C PASS-
THROUGH
3
2
1
0
3
Reserved
RESERVED
Reserved.
Switch over to internal 25 MHz oscillator clock in the
absence of PCLK
0: disable
1: enable
PCLK_AUTO
1
PCLK_AUTO
RW
RW
1
Pixel Clock Edge Select:
0: Parallel Interface Data is strobed on the Falling Clock
Edge.
TRFB
0
TRFB
1
1: Parallel Interface Data is strobed on the Rising Clock
Edge.
4
5
Reserved
7:0 RESERVED
0x80'h Reserved.
I2C SCL frequency is determined by the following: fSCL
= 6.25 MHz / Register value (in decimal) 0x40'h = ~100
kHz SCL (default)
I2C Bus Rate
I2C BUS RATE
7:0
RW
0x40'h
Note: Register values <0x32'h are NOT supported.
Deserializer Device ID = 0x60
(1100_000X) default
7:1 DES DEV ID
RW
RW
0x60'h
6
7
DES ID
0
RESERVED
7:1 SLAVE DEV ID
RESERVED
0
0
0
0
Reserved.
Slave Device ID. Sets remote slave I2C address.
Slave ID
0
Reserved.
Reserved.
8
9
A
Reserved
Reserved
Reserved
7:0 RESERVED
7:0 RESERVED
7:0 RESERVED
0x01'h Reserved.
Reserved.
0
19
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Addr
(Hex)
Name
Bits Field
R/W
Default Description
B
Reserved
Reserved
7:0 RESERVED
7:3 RESERVED
0
0
Reserved.
Reserved.
1: Valid PCLK detected
0: Valid PCLK not detected
PCLK Detect
2
1
0
PCLK DETECT
RESERVED
R
R
0
C
Reserved
Reserved.
Cable Link
Detect Status
0: Cable link not detected
1: Cable link detected
LINK DETECT
0
D
E
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
7:0 RESERVED
7:0 RESERVED
7:0 RESERVED
7:0 RESERVED
7:0 RESERVED
7:0 RESERVED
GPCR[7]
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
0: LOW
F
10
11
12
GPCR[6]
1: HIGH
GPCR[5]
GPCR[4]
7:0
General Purpose
Control Reg
13
RW
0
GPCR[3]
GPCR[2]
GPCR[1]
GPCR[0]
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20
TABLE 2. DS92LX2122 Control Registers
Addr
(Hex)
Name
Bits
Field
R/W
RW
RW
Default
0x60h
0
Description
7-bit address of Deserializer;
0x60h
(1100_000X) default
7:1 DEVICE ID
I2C Device ID
0
0: Device ID is from CAD
1: Register I2C Device ID overrides CAD
0
DES ID
7:3 RESERVED
Reserved
Remote Wake-up Select
1: Enable. Generate remote wakeup signal automatically
wake-up the Serializer in Standby mode
0: Disable. Puts the Serializer in Standby mode
2
REM_WAKEUP
RW
0
1
Reset
1: Resets the device to default register values. Does not
affect device I2C Bus or Device ID
0 self
clear
1
0
DIGITALRESET0
DIGITALRESET1
RW
RW
0 self
clear
1: Digital Reset, retained register value
Reserved
7:6 RESERVED
0
Reserved.
1: Output PCLK or internal 25 MHz Oscillator clock
0: Only PCLK when valid PCLK present
Auto Clock
5
AUTO_CLOCK
RW
RW
0
Output Sleep State Select
0: Outputs = LOW , when LOCK = L
1: Outputs = TRI-STATE®, when LOCK = L
OSS Select
4
OSS_SEL
0
SSCG Select
0000: Normal Operation, SSCG OFF
0001: fmod (KHz) PCLK/2168, fdev ±0.50%
0010: fmod (KHz) PCLK/2168, fdev ±1.00%
0011: fmod (KHz) PCLK/2168, fdev ±1.50%
0100: fmod (KHz) PCLK/2168, fdev ±2.00%
0101: fmod (KHz) PCLK/1300, fdev ±0.50%
0110: fmod (KHz) PCLK/1300, fdev ±1.00%
0111: fmod (KHz) PCLK/1300, fdev ±1.50%
1000: fmod (KHz) PCLK/1300, fdev ±2.00%
1001: fmod (KHz) PCLK/868, fdev ±0.50%
1010: fmod (KHz) PCLK/868, fdev ±1.00%
1011: fmod (KHz) PCLK/868, fdev ±1.50%
1100: fmod (KHz) PCLK/868, fdev ±2.00%
1101: fmod (KHz) PCLK/650, fdev ±0.50%
1110: fmod (KHz) PCLK/650, fdev ±1.00%
1111: fmod (KHz) PCLK/650, fdev +/-1.50%
2
SSCG
3:0 SSCG
0
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Addr
(Hex)
Name
Bits
Field
R/W
Default
Description
Reserved
7:6 RESERVED
11'b
Reserved.
Auto voltage control
0: Disable
1: Enable (auto detect mode)
VDDIO
5
VDDIO Control
RW
RW
1
0
1
CONTROL
VDDIO voltage set
Only used when VDDIOCONTROL = 0
VDDIO Mode
4
3
VDDIO MODE
0: 1.8V
1: 3.3V
I2C Pass-Through Mode
0: Pass-Through Enabled
1: Pass-Through Disabled
I2C PASS-
THROUGH
I2C Pass-Through
3
RW
RW
0: Disable
1: Enable
Auto ACK
Reserved
2
1
AUTO ACK
RESERVED
0
0
Reserved.
Pixel Clock Edge Select
0: Parallel Interface Data is strobed on the Falling Clock
RRFB
0
RRFB
RW
RW
1
Edge
1: Parallel Interface Data is strobed on the Rising Clock
Edge.
EQ Gain
00'h = ~0.0 dB
01'h = ~4.5 dB
03'h = ~6.5 dB
07'h = ~7.5 dB
0F'h = ~8.0 dB
1F'h = ~11.0 dB
3F'h = ~12.5 dB
FF'h = ~14.0 dB
4
5
EQ Control
7:0 EQ
0
0
Reserved
Reserved
7:0 RESERVED
Reserved.
Reserved.
7
RESERVED
Prescales the SCL clock line when reading data byte
from a slave device (MODE = 0)
000 : ~100 kHz SCL (default)
001 : ~125 kHz SCL
101 : ~11 kHz SCL
110 : ~33 kHz SCL
SCL Prescale
Remote NACK
6:4 SCL_PRESCALE
RW
RW
0
1
111 : ~50 kHz SCL
Other values are NOT supported.
Remote NACK Timer Enable In slave mode (MODE = 1)
if bit is set the I2C core will automatically timeout when
no acknowledge condition was detected.
1: Enable
REM_NACK_TIM
6
3
ER
0: Disable
Remote NACK Timeout
000: 2.0 ms
001: 5.2 ms
010: 8.6 ms
REM_NACK_TIM
Remote NACK
2:0
ER
RW
111'b
011: 11.8 ms
100: 14.4 ms
101: 18.4 ms
110: 21.6 ms
111: 25.0 ms
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22
Addr
(Hex)
Name
Bits
Field
R/W
Default
Description
Serializer Device ID = 0x58
(1011_000X) default
Reserved
7:1 SER DEV ID
RW
0x58h
7
SER ID
0
RESERVED
7:1 ID[0] INDEX
RESERVED
7:1 ID[1] INDEX
RESERVED
7:1 ID[2] INDEX
RESERVED
7:1 ID[3] INDEX
RESERVED
7:1 ID[4] INDEX
RESERVED
7:1 ID[5] INDEX
RESERVED
7:1 ID[6] INDEX
RESERVED
7:1 ID[7] INDEX
RESERVED
7:1 ID[0] MATCH
RESERVED
7:1 ID[1] MATCH
RESERVED
7:1 ID[2] MATCH
RESERVED
7:1 ID[3] MATCH
RESERVED
7:1 ID[4] MATCH
RESERVED
7:1 ID[5] MATCH
RESERVED
7:1 ID[6] MATCH
RESERVED
7:1 ID[7] MATCH
RESERVED
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ID[0] Index
RW
Target slave Device ID slv_id1 [7:1]
Reserved.
8
9
0
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Target slave Device ID slv_id1 [7:1]
Reserved.
ID[1] Index
ID[2] Index
ID[3] Index
ID[4] Index
ID[5] Index
ID[6] Index
ID[7] Index
ID[0] Match
ID[1] Match
ID[2] Match
ID[3] Match
ID[4] Match
ID[5] Match
ID[6] Match
ID[7] Match
0
Target slave Device ID slv_id2 [7:1]
Reserved.
A
0
Target slave Device ID slv_id3 [7:1]
Reserved.
B
0
Target slave Device ID slv_id4 [7:1]
Reserved.
C
0
Target slave Device ID slv_id5 [7:1]
Reserved.
D
0
Target slave Device ID slv_id6 [7:1]
Reserved.
E
0
Target slave Device ID slv_id7 [7:1]
Reserved.
F
0
Alias to match Device ID slv_id0 [7:1]
Reserved.
10
11
12
13
14
15
16
17
0
Alias to match Device ID slv_id1 [7:1]
Reserved.
0
Alias to match Device ID slv_id2 [7:1]
Reserved.
0
Alias to match Device ID slv_id3 [7:1]
Reserved.
0
Alias to match Device ID slv_id4 [7:1]
Reserved.
0
Alias to match Device ID slv_id5 [7:1]
Reserved
0
Alias to match Device ID slv_id6 [7:1]
Reserved.
0
Alias to match Device ID slv_id [7:1]
Reserved.
0
18
19
1A
1B
Reserved
Reserved
Reserved
Reserved
Reserved
7:0 RESERVED
7:0 RESERVED
7:0 RESERVED
7:0 RESERVED
7:2 RESERVED
Reserved.
0x01'h Reserved.
0
0
0
Reserved.
Reserved.
Signal Detect
Status
0: Active signal not detected
1: Active signal detected
1
0
R
R
0
0
1C
0: CDR/PLL Unlocked
1: CDR/PLL Locked
LOCK Pin Status
1D
1E
1F
20
21
Reserved
Reserved
Reserved
Reserved
Reserved
7:0 RESERVED
7:0 RESERVED
7:0 RESERVED
7:0 RESERVED
7:0 RESERVED
0x17'h Reserved.
0x07'h Reserved.
0x01'h Reserved.
0x01'h Reserved.
0x01'h Reserved.
23
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Addr
(Hex)
Name
Bits
Field
R/W
Default
Description
22
Reserved
7:0 RESERVED
0x01'h Reserved.
GPCR[7]
GPCR[6]
GPCR[5]
0: LOW
1: HIGH
General Purpose
Control Reg
GPCR[4]
GPCR[3]
23
7:00
RW
0
GPCR[2]
GPCR[1]
GPCR[0]
Reserved
BIST
7:1 RESERVED
0
0
0
0
0
Reserved.
0
BIST_EN
BIST Enable
0: Normal operation
1: Bist Enable
24
25
26
RW
R
BIST_ERR
7:0 BIST_ERR
Bist Error Counter
11: Enable remote wake up mode
00: Normal operation mode
Other values are NOT supported.
REM_WAKEUP_
EN
7:6
RW
RW
Remote Wake
Enable
5:0 RESERVED
Reserved
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24
DISPLAY APPLICATION
Functional Description
The DS92LX2121 / DS92LX2122 chipset is intended for in-
terface between a host (graphics processor, FPGA, etc.) and
a Display. It supports a 21 bit parallel video bus for 18-bit color
depth (RGB666) display format. In a RGB666 configuration,
18 color bits (R [5:0], G[5:0], B[5:0]), Pixel Clock (PCLK) and
three control bits (VS, HS and DE) are supported across the
serial link. The DS92LX2121 Serializer accepts a 21-bit par-
allel data bus along with a bi-directional control bus. The
parallel data and bi-directional control channel information is
converted into a single differential link. The integrated bi-di-
rectional control channel bus supports I2C compatible oper-
ation for controlling auxiliary data transport to and from host
processor and display module. The DS92LX2122 Deserializ-
er extracts the clock/control information from the incoming
data stream and reconstructs the 21-bit data with control
channel data.
The DS92LX2121 / DS92LX2122 Channel Link III chipset is
intended for camera applications. The Serializer/ Deserializer
chipset operates from a 10 MHz to 50 MHz pixel clock fre-
quency. The DS92LX2121 transforms a 21-bit wide parallel
LVCMOS data bus along with a bi-directional back channel
control bus into a single high-speed differential pair. The high
speed serial bit stream contains an embedded clock and DC-
balance information which enhances signal quality to support
AC coupling. The DS92LX2122 receives the single serial data
stream and converts it back into a 21-bit wide parallel data
bus together with the back channel data bus.
The control channel function of the DS92LX2121
/
DS92LX2122 provides bi-directional communication between
the image sensor and Electronic Control Unit (ECU). The in-
tegrated back channel transfers data bi-directionally over the
same differential pair used for video data interface. This in-
terface offers advantages over other chipsets by eliminating
the need for additional wires for programming and control.
The back channel bus is controlled via an I2C port. The bi-
directional back channel offers asymmetrical communication
and is not dependent on video blanking intervals.
SERIAL FRAME FORMAT
The DS92LX2121 / DS92LX2122 chipset will transmit and
receive a pixel of data in the following format:
30125161
FIGURE 19. Serial Bitstream for 28-bit Symbol
The High Speed Forward Channel is a 28-bit symbol com-
posed of 21 bits of data containing video data & control
information transmitted from Serializer to Deserializer. CLK1
and CLK0 represent the embedded clock in the serial stream.
CLK1 is always HIGH and CLK0 is always LOW. This data
payload is optimized for signal transmission over an AC cou-
pled link. Data is randomized, balanced and scrambled.
current sources are required on the SCL and SDA busses to
pull them high when they are not being driven low. A logic zero
is transmitted by driving the output low. A logic high is trans-
mitted by releasing the output and allowing it to be pulled-up
externally. The appropriate pull-up resistor values will depend
upon the total bus capacitance and operating speed. The
DS92LX2121 / DS92LX2122 I2C bus data rate supports up to
100 kbps according to I2C specification.
The bi-directional control channel data is transferred along
with the high-speed forward data over the same serial link.
This architecture provides a full duplex low speed forward
channel across the serial link together with a high speed for-
ward channel without the dependence of the video blanking
phase.
To start any data transfer, the DS92LX2121 / DS92LX2122
must be configured in the proper I2C mode. Each device can
function as an I2C slave proxy or master proxy depending on
the mode determined by M/S pin. The Ser/Des interface acts
as a virtual bridge between the host device and the remote
device. When the M/S pin is set to HIGH, the device is treated
as a slave proxy; and acts as a slave on behalf of the remote
slave. When addressing a remote peripheral or Serializer/
Deserializer (not wired directly to the host device), the slave
proxy will forward any byte transactions sent by the host con-
troller to the target device. When M/S pin is set to LOW, the
device will function as a master proxy device, and acts as a
master on behalf of the I2C master controller. Note that the
devices must have complementary settings for the M/S con-
figuration. For example, if the Serializer M/S pin is set to HIGH
then the Deserializer M/S pin must be set to LOW and vice-
versa.
DESCRIPTION OF BI-DIRECTIONAL CONTROL BUS AND
I2C MODES
The I2C compatible interface allows programming of the
DS92LX2121, DS92LX2122, or an external remote device
(such as a display) through the bi-directional control channel.
Register
programming
transactions
to/from
the
DS92LX2121 / DS92LX2122 chipset are employed through
the clock (SCL) and data (SDA) lines. These two signals have
open drain I/Os and both lines must be pulled-up to VDDIO by
external resistor. Figure 3 shows the timing relationships of
the clock (SCL) and data (SDA) signals. Pull-up resistors or
25
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30125160
FIGURE 20. Write Byte
30125110
FIGURE 21. Read Byte
30125141
FIGURE 22. Basic Operation
30125142
FIGURE 23. START and STOP Conditions
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26
30125143
FIGURE 24. Serial Control Bus Connection
SLAVE CLOCK STRETCHING
CAD PIN ADDRESS DECODER
In order to communicate and synchronize with remote de-
vices on the I2C bus through the bi-directional control channel,
slave clock stretching must be supported by the I2C master
controller/host device. The chipset utilizes bus clock stretch-
ing (holding the SCL line low) during data transmission; where
the I2C slave pulls the SCL line low on the 9th clock of every
I2C data transfer (before the ACK signal). The slave device
will not control the clock and only stretches it until the remote
peripheral has responded; which is typically in the order of 12
μs (typical).
The CAD pin is used to decode and set the physical slave
address of the Serializer/Deserializer (I2C only) to allow up to
six devices on the bus using only a single pin. The pin sets
one of six possible addresses for each Serializer/Deserializer
device. The pin must be pulled to VDD (1.8V, NOT VDDIO))
with a 10 kΩ resistor and a pull down resistor (RID) of the
recommended value to set the physical device address. The
recommended maximum resistor tolerance is 0.1% worst
case (0.2% total tolerance).
TABLE 3. DS92LX2121 RID Resistor Values
CAD Values - DS92LX2121 Ser
Address 7'b
Address 8'b 0 appended (WRITE)
Resistor RID kΩ
0
7b' 101 1000 (h'58)
8b' 1011 0000 (h'B0)
GND
2.0k
4.7k
7b' 101 1001 (h'59)
7b' 101 1010 (h'5A)
7b' 101 1011 (h'5B)
7b' 101 1100 (h'5C)
7b' 101 1110 (h'5E)
8b' 1011 0010 (h'B2)
8b' 1011 0100 (h'B4)
8b' 1011 0110 (h'B6)
8b' 1011 1000 (h'B8)
8b' 1011 1100 (h'BC)
8.2k
12.1k
39.0k
TABLE 4. DS92LX2122 RID Resistor Values
CAD Values - DS92LX2122 Des
Address 7'b
Address 8'b 0 appended (WRITE)
Resistor RID kΩ
0
7b' 110 0000 (h'60)
8b' 1100 0000 (h'C0)
GND
2.0k
4.7k
7b' 110 0001 (h'61)
7b' 110 0010 (h'62)
7b' 110 0011 (h'62)
7b' 110 0100 (h'62)
7b' 110 0110 (h'66)
8b' 1100 0010 (h'C2)
8b' 1100 0100 (h'C4)
8b' 1101 0110 (h'C6)
8b' 1101 1000 (h'C8)
8b' 1100 1100 (h'CC)
8.2k
12.1k
39.0k
27
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CAMERA MODE OPERATION
LOW. Before initiating any I2C commands, the Serializer
needs to be programmed with the target slave device address
and Serializer device address. DES_DEV_ID Register 0x06h
sets the Deserializer device address and SLAVE_DEV_ID
register 0x7h sets the remote target slave address. If the I2C
slave address matches any of registers values, the I2C slave
will acknowledge the transaction allowing read or write to tar-
get device. Note: In Display mode operation, registers
0x08h~0x17h on Deserializer must be reset to 0x00.
In Camera mode, I2C transactions originate from the Deseri-
alizer from the host controller. The I2C slave core in the
Deserializer will detect if a transaction is intended for the Se-
rializer or a slave at the Serializer. Commands are sent over
the bi-directional control channel to initiate the transactions.
The Serializer will receive the command and generate an I2C
transaction on its local I2C bus. At the same time, the Serial-
izer will capture the response on the I2C bus and return the
response as a command on the forward channel link. The
Deserializer parses the response and passes the appropriate
response to the Deserializer I2C bus.
PROGRAMMABLE CONTROLLER
An integrated I2C slave controller is embedded in each of the
DS92LX2121 Serializer and DS92LX2122 Deserializer. It
must be used to access and program the extra features em-
bedded within the configuration registers. Refer to Table 1
and Table 2 for details of control registers.
To configure the devices for camera mode operation, set the
Serializer M/S pin to LOW and the Deserializer M/S pin to
HIGH. Before initiating any I2C commands, the Deserializer
needs to be programmed with the target slave device ad-
dresses and Serializer device address. SER_DEV_ID Regis-
ter 0x07h sets the Serializer device address and
I2C PASS THROUGH
I2C pass-through provides an alternative means to indepen-
dently address slave devices. The mode enables or disables
I2C bidirectional control channel communication to the remote
I2C bus. This option is used to determine whether or not an
I2C instruction is to be transferred over to the remote I2C de-
vice. When enabled, the I2C bus traffic will continue to pass
through and will be received by I2C devices downstream. If
disabled, I2C commands will be excluded to the remote I2C
device. The pass through function also provides access and
communication to only specific devices on the remote bus.
The feature is effective for both Camera mode and Display
mode.
SLAVE_x_MATCH/SLAVE_x_INDEX
registers
0x08h~0x17h set the remote target slave addresses. The
slave address match registers must also be set. In slave mode
the address register is compared with the address byte sent
by the I2C master. If the addresses are equal to any of reg-
isters values, the I2C slave will acknowledge the transaction
to the I2C master allowing reads or writes to target device.
DISPLAY MODE OPERATION
In Display mode, I2C transactions originate from the controller
attached to the Serializer. The I2C slave core in the Serializer
will detect if a transaction targets (local) registers within the
Serializer or the (remote) registers within the Deserializer or
a remote slave connected to the I2C master interface of the
Deserializer. Commands are sent over the forward channel
link to initiate the transactions. The Deserializer will receive
the command and generate an I2C transaction on its local
I2C bus. At the same time, the Deserializer will capture the
response on the I2C bus and return the response as a com-
mand on the bi-directional control channel. The Serializer
parses the response and passes the appropriate response to
the Serializer I2C bus.
The physical device ID of the I2C slave in the Serializer is
determined by the analog voltage on the CAD pin input. It can
be reprogrammed by using the SER_DEV_ID register and
setting the bit . The device ID of the logical I2C slave in the
Deserializer is determined by programming the DES ID in the
Serializer. The state of the CAD pin input on the Deserializer
is used to set the device ID. The I2C transactions between
Ser/ Des will be bridged between the host to the remote slave.
SYNCHRONIZING MULTIPLE LINKS
For applications requiring synchronization across multiple
links, it is recommended to utilize the General Purpose Input/
Output (GPI/GPO) pins to transmit control signals to synchro-
nize slave peripherals together. To synchronize the periph-
erals properly, the system controller needs to provide a sync
signal output. Note this form of synchronization timing rela-
tionship has a non-deterministic latency. After the control data
is reconstructed from the bi-directional control channel, there
will be a time variation of the GPI/GPO signals arriving at the
different target devices (between the parallel links). The max-
imum latency delta (t1) of the GPI/GPO data transmitted
across multiple links is 25 μs.
Note: The user must verify that the timing variations between
the different links are within their system and timing specifi-
cations.
The maximum time (t1) between the rising edge of GPI/GPO
(i.e. sync signal) arriving at Camera A and Camera B is 25
μs.
To configure the devices for display mode operation, set the
Serializer M/S pin to HIGH and the Deserializer M/S pin to
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28
30125154
FIGURE 25. GPIO Delta Latency
GENERAL PURPOSE I/O (GPIO)
BIST duration test. A LOW on this pin at the conclusion of this
test indicates that one or more payloads were detected with
errors.
The DS92LX2121 / DS92LX2122 has up to 4 GPO and 4 GPI
on the Serializer and Deserializer respectively. The GPI/GPO
maximum switching rate is up to 66 kHz for communication
between Deserializer GPI to Serializer GPO.
The BIST duration is defined by the width of BISTEN. BIST
starts when BISTEN goes HIGH. BIST ends when BISTEN
goes LOW. PASS flag will go HIGH when no errors detected
after BIST Duration completes. Any errors detected after the
BIST Duration are not included in PASS logic.
AT-SPEED BIST (BISTEN, PASS)
An optional AT SPEED Built in Self Test (BIST) feature sup-
ports at speed testing of the high-speed serial and the back-
channel link. Control pins allow the system to initiate the test
and set the duration. A HIGH on PASS pin indicates that all
payloads received during the test were error free during the
The following diagram shows how to perform system AT
SPEED BIST:
29
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30125145
FIGURE 26. AT-SPEED BIST System Flow Diagram
Step 1: Place the Deserializer in BIST Mode.
serializer by setting the BISTEN pin High. The DS92LX2122
GPIO[1:0] pins are used to select the PCLK frequency of the
on-chip oscillator for the BIST test on high speed data path.
Serializer and Deserializer power supply must be supplied.
Set the Serializer M/S pin to LOW and the Deserializer M/S
pin to HIGH. Enable the AT SPEED BIST mode on the De-
Oscillator Frequency Select
Oscillator Range min (MHz) typ (MHz) max (MHz)
External PCLK 10 50
Freq Control
00
01
10
11
Internal
Internal
Internal
50
25
12.5
The Deserializer GPIO[1:0] set to 00 will bypass the on-chip
oscillator and an external oscillator to Serializer PCLK input
is required. This allows the user to operate BIST under dif-
ferent frequencies other than the predefined ranges.
The Serializer will start transfer of an internally generated
PRBS data pattern through the high speed serial link. This
pattern traverses across the interconnecting link to the De-
serializer. Check the status of the PASS pin; a HIGH indicates
a pass, a LOW indicates a fail. A fail will stay LOW for ½ a
clock cycle. If two or more bits fail in a row the PASS pin will
toggle ½ clock cycle HIGH and ½ clock cycle low. The user
can use the PASS pin to count the number of fails on the high
speed link. In addition, there is a defined SER and DES reg-
ister that will keep track of the accumulated error count. The
Serializer DS92LX2121 GPIO[0] pin will be assigned as a
PASS flag error indicator for the back-channel link.
Step 2: Enable AT SPEED BIST by placing the Serializer into
BIST mode.
Deserializer will communicate through the back-channel to
configure Serializer into BIST mode. Once the BIST mode is
set, the Serializer will initiate BIST transmission to the Dese-
rializer.
Wait 10 ms for Deserializer to acquire lock and then monitor
the LOCK pin transition from LOW to HIGH. At this point, AT
SPEED BIST is operational and the BIST process has begun.
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30125164
FIGURE 27. BIST Timing Diagram
Step 3: Stop at SPEED BIST by turning off BIST mode in the
TEN width and thus the Bit Error Rate is determined by how
Deserializer to determine Pass/Fail.
long the system holds BISTEN HIGH.
To end BIST, the system must pull BISTEN pin of the Dese-
rializer LOW. The BIST duration is fully defined by the BIS-
30125105
FIGURE 28. BIST BER Calculation
For instance, if BISTEN is held HIGH for 1 second and the
PCLK is running at 43 MHz with 16 bpp, then the Bit Error
Rate is no better than 1.46E-9.
LVCMOS VDDIO OPTION
1.8V or 3.3V SER Inputs and DES Outputs are user config-
urable to provide compatibility with 1.8V and 3.3V system
interfaces.
Step 4: Place system in Normal Operating Mode by disabling
BIST at the Serializer.
REMOTE WAKE UP (Camera Mode)
Once Step 3 is complete, AT SPEED BIST is over and the
Deserializer is out of BIST mode. To fully return to Normal
mode, apply Normal input data into the Serializer.
After initial power up, the SER is in a low-power Standby
mode. The DES (controlled by the host ) 'Remote Wakeup'
register allows the DES side to generate a signal across the
link to remotely wakeup the SER. Once the SER detects the
wakeup signal, the SER switches from Standby mode to ac-
tive mode. In active mode, the SER locks onto PCLK input (if
present), otherwise the on-chip oscillator is used as the input
clock source. Note the host controller should monitor the DES
Any PASS result will remain unless it is changed by a new
BIST session or cleared by asserting and releasing PDB. The
default state of PASS after a PDB toggle is HIGH.
It is important to note that AT SPEED BIST will only determine
if there is an issue on the link that is not related to the clock
and data recovery of the link (whose status is flagged with
LOCK pin).
31
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LOCK pin and confirm LOCK = H before performing any I2C
communication across the link.
a capacitor on the PDB pin is needed to ensure PDB arrives
after all the VDD have settled to the recommended operating
voltage. When PDB pin is pulled to VDDIO, it is recommended
to use a 10 kΩ pull-up and a 22 uF cap to GND to delay the
PDB input signal.
For Remote Wakeup to function properly:
•
The chipset needs to be configured in Camera mode:
Serializer M/S = 0 and Deserializer M/S = 1
•
•
The SER expects remote wake up by default at power on.
SIGNAL QUALITY ENHANCERS
Configure the control channel driver of the DES to be in
remote wake up mode by setting DES register 0x26 to
0xC0.
Perform remote wake up on SER by setting DES register
0x01 b[2] to 1.
Des - Receiver Input Equalization (EQ)
The receiver inputs provided input equalization filter in order
to compensate for loss from the media. The level of equal-
ization is controlled via register setting.
•
•
Return the control channel driver of the DES to the normal
operation mode by setting DES register 0x26 to 0.
EMI REDUCTION
Des - Receiver Staggered Output
The SER can also be put into standby mode by programming
the DES remote wake up control register 0x01 b[2]
REM_WAKEUP to 0.
The Receiver staggered outputs allows for outputs to switch
in a random distribution of transitions within a defined window.
Outputs transitions are distributed randomly. This minimizes
the number of outputs switching simultaneously and helps to
reduce supply noise. In addition it spreads the noise spectrum
out reducing overall EMI.
POWERDOWN
The SER has a PDB input pin to ENABLE or Powerdown the
device. The modes can be controlled by the host and is used
to disable the Link to save power when the remote device is
not operational. An auto mode is also available. In this mode,
the PDB pin is tied High and the SER switches over to an
internal oscillator when the PCLK stops or not present. When
a PCLK starts again, the SER will then lock to the valid input
PCLK and transmits the data to the DES. In powerdown
mode, the high-speed driver outputs are static (HIGH).
Des Spread Spectrum Clocking Compatibilty
The DS92LX2122 parallel data and clock outputs have pro-
grammable SSCG ranges from 70 kHz and +-2% (4% total)
from 20 MHz to 50 MHz. The modulation rate and modulation
frequency variation of output spread is controlled through the
SSC control registers.
The DES has a PDB input pin to ENABLE or Powerdown the
device. This pin can be controlled by the system and is used
to disable the DES to save power. An auto mode is also avail-
able. In this mode, the PDB pin is tied High and the DES will
enter powerdown when the serial stream stops. When the
serial stream starts up again, the DES will lock to the input
stream and assert the LOCK pin and output valid data. In
powerdown mode, the Data and PCLK outputs are set by the
OSS_SEL control register.
PIXEL CLOCK EDGE SELECT (TRFB/RRFB)
The TRFB/RRFB selects which edge of the Pixel Clock is
used. For the SER, this register determines the edge that the
data is latched on. If TRFB register is 1, data is latched on the
Rising edge of the PCLK. If TRFB register is 0, data is latched
on the Falling edge of the PCLK. For the DES, this register
determines the edge that the data is strobed on. If RRFB reg-
ister is 1, data is strobed on the Rising edge of the PCLK. If
RRFB register is 0, data is strobed on the Falling edge of the
PCLK.
POWER UP REQUIREMENTS AND PDB PIN
The VDD (VDDn and VDDIO) supply ramp should be faster
than 1.5 ms with a monotonic rise. If slower then 1.5 ms then
30125151
FIGURE 29. Programmable PCLK Strobe Select
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32
nal AC coupling capacitors must be placed in series in the
Channel Link III signal path as illustrated in Figure 34.
Applications Information
AC COUPLING
The SER/DES supports only AC-coupled interconnects
through an integrated DC balanced decoding scheme. Exter-
30125138
FIGURE 30. AC-Coupled Application
For high-speed Channel Link III transmissions, the smallest
available package should be used for the AC coupling ca-
pacitor. This will help minimize degradation of signal quality
due to package parasitics. The I/O’s require a 0.1 μF AC cou-
pling capacitors to the line.
TYPICAL APPLICATION CONNECTION
Figure 31 shows a typical connection of the DS92LX2121
Serializer.
33
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30125155
FIGURE 31. DS92LX2121 Typical Connection Diagram
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34
Figure 32 shows a typical connection of the DS92LX2122
Deserializer.
30125156
FIGURE 32. DS92LX2122 Typical Connection Diagram
35
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TRANSMISSION MEDIA
ends of the capacitor. Connecting power or ground pins to an
external bypass capacitor will increase the inductance of the
path.
The Ser/Des chipset is intended to be used over a wide variety
of balanced cables depending on distance and signal quality
requirements. The Ser/Des employ internal termination pro-
viding a clean signaling environment. The interconnect for
Channel Link III interface should present a differential
impedance of 100 Ohms. Use of cables and connectors that
have matched differential impedance will minimize
impedance discontinuities. Shielded or un-shielded cables
may be used depending upon the noise environment and ap-
plication requirements. The chipset's optimum cable drive
performance is achieved at 43 MHz at 10 meters length. The
maximum signaling rate increases as the cable length de-
creases. Therefore, the chipset supports 50 MHz at shorter
distances. Other cable parameters that may limit the cable's
performance boundaries are: cable attenuation, near-end
crosstalk and pair-to-pair skew.
A small body size X7R chip capacitor, such as 0603, is rec-
ommended for external bypass. Its small body size reduces
the parasitic inductance of the capacitor. The user must pay
attention to the resonance frequency of these external bypass
capacitors, usually in the range of 20-30 MHz. To provide ef-
fective bypassing, multiple capacitors are often used to
achieve low impedance between the supply rails over the fre-
quency of interest. At high frequency, it is also a common
practice to use two vias from power and ground pins to the
planes, reducing the impedance at high frequency.
Some devices provide separate power for different portions
of the circuit. This is done to isolate switching noise effects
between different sections of the circuit. Separate planes on
the PCB are typically not required. Pin Description tables typ-
ically provide guidance on which circuit blocks are connected
to which power pin pairs. In some cases, an external filter
many be used to provide clean power to sensitive circuits
such as PLLs.
For obtaining optimal performance the system should use:
•
•
Shielded Twisted Pair (STP) cable
100Ω differential impedance and 24 AWG (or lower AWG)
cable
Use at least a four layer board with a power and ground plane.
Locate LVCMOS signals away from the differential lines to
prevent coupling from the LVCMOS lines to the differential
lines. Closely-coupled differential lines of 100 Ohms are typ-
ically recommended for differential interconnect. The closely
coupled lines help to ensure that coupled noise will appear as
common-mode and thus is rejected by the receivers. The
tightly coupled lines will also radiate less.
•
•
Low skew, impedance matched
Terminate unused conductors
PCB LAYOUT AND POWER SYSTEM CONSIDERATIONS
Circuit board layout and stack-up for the Ser/Des devices
should be designed to provide low-noise power feed to the
device. Good layout practice will also separate high frequency
or high-level inputs and outputs to minimize unwanted stray
noise pickup, feedback and interference. Power system per-
formance may be greatly improved by using thin dielectrics (2
to 4 mils) for power / ground sandwiches. This arrangement
provides plane capacitance for the PCB power system with
low-inductance parasitics, which has proven especially effec-
tive at high frequencies, and makes the value and placement
of external bypass capacitors less critical. External bypass
capacitors should include both RF ceramic and tantalum elec-
trolytic types. RF capacitors may use values in the range of
0.01 uF to 0.1 uF. Tantalum capacitors may be in the 2.2 uF
to 10 uF range. Voltage rating of the tantalum capacitors
should be at least 5X the power supply voltage being used.
Information on the LLP style package is provided in National
Application Note: AN-1187.
INTERCONNECT GUIDELINES
See AN-1108 and AN-905 for full details.
•
•
Use 100Ω coupled differential pairs
Use the S/2S/3S rule in spacings
S = space between the pair
2S = space between pairs
3S = space to LVCMOS signal
—
—
—
•
•
Minimize the number of Vias
Use differential connectors when operating above
500Mbps line speed
Surface mount capacitors are recommended due to their
smaller parasitics. When using multiple capacitors per supply
pin, locate the smaller value closer to the pin. A large bulk
capacitor is recommend at the point of power entry. This is
typically in the 50uF to 100uF range and will smooth low fre-
quency switching noise. It is recommended to connect power
and ground pins directly to the power and ground planes with
bypass capacitors connected to the plane with via on both
•
•
Maintain balance of the traces
Minimize skew within the pair
Additional general guidance can be found in the LVDS
Owner’s Manual - available in PDF format from the National
web site at: www.national.com/lvds
www.national.com
36
Physical Dimensions inches (millimeters) unless otherwise noted
DS92LX2121 Serializer
NS Package Number SQA40A
DS92LX2122 Deserializer
NS Package Number SQA48A
37
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