EPC1064VTC32 [ROCHESTER]

64KX1 CONFIGURATION MEMORY, PQFP32, PLASTIC, TQFP-32;


型号：	EPC1064VTC32
厂家：	Rochester Electronics
描述：	64KX1 CONFIGURATION MEMORY, PQFP32, PLASTIC, TQFP-32 内存集成电路
文件：	总40页 (文件大小：1289K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Configuration Devices for

SRAM-Based LUT Devices

February 2002, ver. 12.1

DataSheet

■

Serial device family for configuring APEX^TMII, APEX 20K (including

APEX 20K, APEX 20KC, and APEX 20KE), Mercury^TM, ACEX^®1K,

and FLEX^®(FLEX 6000, FLEX 10KE, and FLEX 10KA) devices

Easy-to-use 4-pin interface to APEX II, APEX 20K, Mercury, ACEX,

and FLEX devices

Features

■

Low current during configuration and near-zero standby current

5.0-V and 3.3-V operation

Software design support with the Altera^®Quartus^®II and

MAX+PLUS^®II development systems for Windows-based PCs as

well as Sun SPARCstation, and HP 9000 Series 700/800

Programming support with Altera’s Master Programming Unit

(MPU) and programming hardware from Data I/O,

BP Microsystems, and other manufacturers

■

Available in compact plastic packages (see Figures 1 and 2)

–

8-pin plastic dual in-line package (PDIP)

20-pin plastic J-lead chip carrier (PLCC) package

32-pin plastic thin quad flat pack (TQFP) package

100-pin plastic thin quad flat pack (TQPF) package

88-pin Ultra FineLine BGA^TMpackage

■

EPC2 device has reprogrammable Flash configuration memory

–

5.0-V and 3.3-V in-system programmability (ISP) through the

built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG)

interface

–

Built-in JTAG boundary-scan test (BST) circuitry compliant with

IEEE Std. 1149.1

ISP circuitry is compatible with IEEE Std. 1532 for EPC2

configuration device

Supports programming through Serial Vector Format Files

(.svf), Jam^TMStandard Test and Programming Language

(STAPL) Files (.jam), Jam STAPL Byte-Code Files (.jbc), and the

MAX+PLUS II software via the MasterBlaster^TM

ByteBlasterMV^TM, or BitBlaster^TMdownload cable

– nINIT_CONFpin allows a JTAG instruction to initiate device

configuration

–

Can be programmed with Programmer Object Files (.pof) for

EPC1 and EPC1441 devices

Available in 20-pin PLCC and 32-pin TQFP packages

Altera Corporation

DS-EPROM-12.1

Configuration Devices for SRAM-based LUT Devices Data Sheet

EPC4, EPC8, and EPC16 configuration devices have reprogrammable

■

Flash configuration memory with density up to 16,000,000 or

32,000,000 bits with compression feature in these devices.

For detailed information on configuration devices, refer to the Enhanced

Configuration Devices (EPC4, EPC8, & EPC16) Data Sheet.

Figure 1. EPC1, EPC1441, EPC1213, EPC1064, & EPC1064V Package Pin-Out Diagrams

Note (1)

32 31 30 29 28 27 26 25

N.C.

VCC

N.C.

DCLK

N.C.

20 19

DCLK

N.C.

VCC

N.C.

DATA

DCLK

VCC

N.C.

VCC

nCASC(2)

GND

N.C.

nCS

N.C.

10 11 12 13 14 15 16

10 11 12 13

2()

32-Pin TQFP

20-Pin PLCC

8-Pin PDIP

EPC1441

EPC1064

EPC1064V

EPC1

EPC1441

EPC1213

EPC1064

EPC1064V

EPC1441

EPC1213

EPC1064

EPC1064V

Notes to Figure 1:

(1) EPC1, EPC1441, EPC1213, and EPC1064 devices are one-time programmable devices. ISP programming is not

available in these devices because they do not have JTAG pins.

(2) The nCASCpin is available on EPC1 and EPC1213 devices. On the EPC1064, EPC1064V, and EPC1441 devices, it is

a reserved pin and should not be connected.

Altera Corporation

Configuration Devices for SRAM-Based LUT Devices Data Sheet

Figure 2. EPC2 Package Pin-Out Diagrams

32 31 30 29 28 27 26 25

N.C.

DCLK

VCCSEL

N.C.

VPP

N.C.

20 19

DCLK

VCCSEL

N.C.

VPP

N.C.

VPPSEL

N.C.

10 11 12 13 14 15

10 11 12 13

32-Pin TQFP

20-Pin PLCC

With SRAM-based devices, configuration data must be reloaded each

time the system initializes, or when new configuration data is needed.

Altera configuration devices store configuration data for SRAM-based

APEX II, APEX 20K, Mercury, ACEX, and FLEX devices. Table 1 lists

Altera configuration devices.

Functional

Description

Table 1. Configuration Devices

Device

Description

EPC16

16,000,000 × 1 bit with 3.3-V operation

EPC8

8,000,000 × 1 bit with 3.3-V operation

EPC4

4,000,000 × 1-bit device with 3.3-V operation

1,695,680 × 1-bit device with 5.0-V or 3.3-V operation

1,046,496 × 1-bit device with 5.0-V or 3.3-V operation

440,800 × 1-bit device with 5.0-V or 3.3-V operation

212,942 × 1-bit device with 5.0-V operation

65,536 × 1-bit device with 5.0-V operation

65,536 × 1-bit device with 3.3-V operation

EPC2

EPC1

EPC1441

EPC1213

EPC1064

EPC1064V

Altera Corporation

Configuration Devices for SRAM-based LUT Devices Data Sheet

Table 2 lists the configuration device used with each APEX II, APEX 20K,

Mercury, ACEX 1K, and FLEX device.

Table 2. Configuration Devices Used for Each APEX II, APEX 20K, Mercury, ACEX & FLEX Device

(Part 1 of 2)

Family

Device

Data Size EPC1064 EPC1213 EPC1441 EPC1 EPC2 EPC4 EPC8 EPC16

(bits)

EPC1064V

APEX II

EP2A15

4,714,000

6,276,000

9,612,000

17,390,000

1,297,000

4,383,000

1,964,000

3,901,000

5,564,000

8,938,000

347,000

(1.5 V)

EP2A25

EP2A40

EP2A70

EP1M120

EP1M350

Mercury

(1.8 V)

APEX 20KC EP20K200C

(1.8 V)

EP20K400C

EP20K600C

EP20K1000C

APEX 20KE EP20K30E

(2.5 V)

EP20K60E

641,000

EP20K100E

EP20K160E

EP20K200E

EP20K300E

EP20K400E

EP20K600E

EP20K1000E

1,009,000

1,523,000

1,964,000

2,733,000

3,901,000

5,564,000

8,938,000

EP20K1500E 12,011,000

APEX 20K

(2.5 V)

EP20K100

EP20K200

EP20K400

EP1K10

985,000

1,950,000

3,878,000

178,000

ACEX 1K

(2.5 V)

EP1K30

470,000

EP1K50

785,000

EP1K100

1,337,000

Altera Corporation

Configuration Devices for SRAM-Based LUT Devices Data Sheet

Table 2. Configuration Devices Used for Each APEX II, APEX 20K, Mercury, ACEX & FLEX Device

(Part 2 of 2)

Family

Device

Data Size EPC1064 EPC1213 EPC1441 EPC1 EPC2 EPC4 EPC8 EPC16

(bits)

EPC1064V

FLEX 10KE EPF10K30E

470,000

785,000

(2.5 V)

EPF10K50E

EPF10K50S

EPF10K100B 1,2000,000

EPF10K100E

EPF10K130E

EPF10K200E

EPF10K200S

1,336,000

1,840,000

2,757,000

120,000

402,000

621,000

1,200,000

1,582,000

3,292,000

118,000

231,000

376,000

498,000

621,000

893,000

1,200,000

260,000

FLEX 10KA EPF10K10A

(3.3 V)

EPF10K30A

EPF10K50V

EPF10K100A

EPF10K130V

EPF10K250A

EPF10K10

EPF10K20

EPF10K30

EPF10K40

EPF10K50

EPF10K70

EPF10K100

EPF6010A

FLEX 10K

(5.0 V)

FLEX

6000/A

(3.3 V)

EPF6016

(5.0 V) /

EPF6016A

EPF6024A

398,000

40,000

FLEX

EPF8282A /

EPF8282AV

(3.3 V)

8000A

(5.0 V)

EPF8452A

EPF8636A

EPF8820A

EPF81188A

EPF1500A

64,000

96,000

128,000

192,000

250,000

Altera Corporation

Configuration Devices for SRAM-based LUT Devices Data Sheet

Figure 3 shows the configuration device block diagram.

Figure 3. Configuration Device Block Diagram

(1)

PLD (except FLEX 8000) Configuration Using an EPC2, EPC1, or EPC1441

DCLK

Address

Counter

CLK

ENA

Oscillator

nRESET

Oscillator

Control

Address

Decode

Logic

nCS

nCASC (2)

Error

Detection

Circuitry

EPROM

Array

OE(3)

DATA

Shift

DATA

FLEX 8000 Device Configuration Using an EPC1, EPC1441, EPC1213, EPC1064, or EPC1064V

Address

Counter

CLK

ENA

DCLK

nRESET

Address

Decode

Logic

nCASC (2)

nCS

EPROM

Array

DATA

Shift

DATA

Notes to Figure 3:

(1) Do not use EPC2 devices to configure FLEX 6000 devices.

(2) The EPC1441, EPC1064, and EPC1064V devices do not support data cascading. The EPC2, EPC1, and EPC1213

devices support data cascading.

(3) The OEpin is a bidirectional open-drain pin.

Altera Corporation

Configuration Devices for SRAM-Based LUT Devices Data Sheet

The control signals for configuration devices—nCS, OE, and DCLK—

interface directly with APEX II, APEX 20K, Mercury, ACEX 1K, and FLEX

device control signals. All APEX II, APEX 20K, Mercury, ACEX 1K, and

FLEX devices can be configured by a configuration device without

requiring an external intelligent controller.

Device

Configuration

The configuration device’s OEand nCSpins control the tri-state buffer on

the DATAoutput pin, and enable the address counter (and the oscillator in

EPC4, EPC 8, EPC16, EPC2, EPC1, and EPC1441 devices). When OEis

driven low, the configuration device resets the address counter and tri-

states its DATApin. The nCSpin controls the output of the configuration

device. If nCSis held high after the OEreset pulse, the counter is disabled

and the DATAoutput pin is tri-stated. When nCSis driven low, the counter

and DATAoutput pin are enabled. When OEis driven low again, the

address counter is reset and the DATAoutput pin is tri-stated, regardless

of the state of nCS.

The EPC4, EPC8, EPC16, EPC2, EPC1, and EPC1441 devices

determine the operation mode and whether the APEX 20K,

Mercury, ACEX 1K, FLEX 10K, FLEX 8000, or FLEX 6000

protocols should be used when OEis driven high.

When the configuration device has driven out all of its data and has

driven nCASClow, the device tri-states the DATApin to avoid contention

with other configuration devices.

The EPC2 device allows the user to initiate configuration of the PLD via

an additional pin, nINIT_CONF, that can be tied to the nCONFIGpin of the

PLD(s) to be configured. A JTAG instruction causes the EPC4, EPC8,

EPC16, and EPC2 device to drive nINIT_CONFlow, which in turn pulls

nCONFIGlow. The EPC4, EPC8, EPC16, and EPC2 device then drives

nINIT_CONFhigh to start configuration. When the JTAG state machine

exits this state, nINIT_CONFreleases nCONFIGand configuration is

initiated.

An EPC4, EPC8, EPC16, and EPC2 device can be programmed

with a POF generated for an EPC1 or EPC1441 device, however,

an EPC2 device cannot configure FLEX 6000 or FLEX 8000

devices. An EPC1 device can be programmed using a POF

generated for an EPC1441 device.

Altera Corporation

Configuration Devices for SRAM-based LUT Devices Data Sheet

APEX II, APEX 20K, Mercury, ACEX 1K, FLEX 10K & FLEX 6000

Device Configuration

APEX 20K, Mercury, ACEX 1K, and FLEX devices can be configured with

EPC4, EPC8, EPC16, EPC2, EPC1, or EPC1441 devices. FLEX 6000 devices

can be configured with EPC1 or EPC1441 devices. APEX II devices can be

configured with EPC2, EPC4, EPC8, and EPC16 devices. The EPC4, EPC8,

EPC16, EPC2, EPC1, or EPC1441 device stores configuration data in its

EPROM array and serially clocks data out with an internal oscillator. The

OE, nCS, and DCLKpins supply the control signals for the address counter

and the output tri-state buffer. The configuration device sends a serial

bitstream of configuration data to its DATApin, which is routed to the

DATA0or DATAinput pin on the LUT-based PLD device. Figure 4 shows

an LUT-based PLD configured with a single EPC2, EPC1, or EPC1441

device.

Altera Corporation

Configuration Devices for SRAM-Based LUT Devices Data Sheet

Figure 4. ACEX 1K, APEX 20K, APEX II, FLEX 10K, FLEX 6000, or Mercury Device Configured with an EPC2,

EPC1, or EPC1441 Configuration Device

Note (1)

APEX II, ACEX 1K, Mercury, APEX 20KC,

APEX 20K & FLEX 10K Devices

Configuration

Device

(2)

LUT-Based PLD (3)

DCLK

DATA

DCLK

DATA0

nCS

nINIT_CONF (4)

nSTATUS

CONF_DONE

nCONFIG

nCEO

(5)

MSEL0

nCE

MSEL1

GND

(6)

CCINT

APEX 20KE Devices

Configuration

Device

(2)

APEX 20KE PLD (7)

DCLK

DATA

DCLK

DATA0

nCS

nINIT_CONF (4)

nSTATUS

CONF_DONE

nCONFIG

(8)

(5)

nCEO

MSEL0

MSEL1

nCE

GND

Notes to Figure 4:

(1) Do not use EPC2 devices to configure FLEX 6000 devices.

(2) The pull-up resistor should be connected to the same supply voltage as the configuration device. All pull-up

resistors are 1 kΩ. APEX 20KE pull up resistors are 10 kΩ. The OE, nCS, and nINIT_CONFpins on EPC2, EPC4,

EPC8, and EPC16 devices have internal, user-configurable 1-kΩ pull-up resistors. If internal pull-up resistors are

used, external pull-up resistors should not be used on these pins. The Quartus II software uses the internal pull-up

resistors by default. To turn off the internal pull-up resistors, check the Disable nCS and OE pull-ups on configuration

device option when generating programming files.

(3) The diagram shows an APEX II, APEX 20K, Mercury, ACEX 1K, and FLEX device, which has MSEL0and MSEL1

tied to ground. For FLEX 6000 devices, MSELis tied to ground, and the DATA0pin is named DATA. EPC4, EPC8,

EPC16, and EPC2 configuration devices cannot be used with FLEX 6000 devices. All other connections are the same

for APEX II, APEX 20K, Mercury, ACEX 1K, and FLEX devices.

(4) The nINIT_CONFpin is only available on EPC2, EPC4, EPC8, and EPC16 devices and has an internal pull up of 1 kΩ

that is always active. If nINIT_CONFis not available or not used, nCONFIGmust be pulled to V_CCeither directly or

through a 1-kΩ resistor.

(5) The nCEOpin is left unconnected.

(6) To ensure successful configuration between APEX 20KE and configuration devices in all possible power-up

sequences, pull up nCONFIGto V_CCINT

(7) This diagram is for APEX 20KE devices only.

(8) To isolate the 1.8-V and 3.3-V power supplies when configuration APEX 20KE devices, add a diode between the

APEX 20KE device’s nCONFIGpin and the configuration device’s nINIT_CONFpin. Select a diode with a threshold

voltage (V_T) less than or equal to 0.7 V. The diode will make the nINIT_CONFpin an open-drain pin; the pin will

only be able to drive low or tri-state.

Altera Corporation

Configuration Devices for SRAM-based LUT Devices Data Sheet

Table 3 describes EPC2, EPC1, and EPC1441 pin functions during

APEX II, APEX 20K, Mercury, ACEX 1K, and FLEX device configuration.

For information on EPC4, EPC8, and EPC16 devices, refer to Enhanced

Configuration Devices (EPC4, EPC8, & EPC16) Data Sheet.

Table 3. EPC2, EPC1, & EPC1441 Pin Functions During APEX II, APEX 20K, Mercury, ACEX 1K, FLEX 10K

& FLEX 6000 Configuration (Part 1 of 3)

Notes (1), (2)

Pin Name

Pin Number

Type

Description

8-Pin

20-Pin 32-Pin

PDIP (3) PLCC TQFP (4)

DATA

Output Serial data output. The DATApin is tri-stated before

configuration when the nCSpin is high, and after the

configuration device finishes sending its configuration

data. This operation is independent of the device’s

position in the cascade chain.

DCLK

I/O

DCLKis a clock output when configuring with a single

configuration device or when the configuration device is

the first device in a configuration device chain. DCLKis

a clock input for subsequent configuration devices in a

configuration device chain. Rising edges on DCLK

increment the internal address counter and present the

next bit of data to the DATApin. The counter is

incremented only if the OEinput is held high, the nCS

input is held low, and all configuration data has not

been transferred to the target device. When configuring

with the first EPC2 or EPC1 device in a configuration

device chain or with a single EPC1441 device, the

DCLKpin drives low after configuration is complete or

when OEis low.

OE(5)

Open- Output enable (active high) and reset (active low). A

Drain

I/O

low logic level resets the address counter. A high logic

level enables DATAand permits the address counter to

count. If this pin is low (reset) during configuration, the

internal oscillator becomes inactive and DCLKdrives

low. See “Error Detection Circuitry” on page 23.

nCS(5)

Input

Chip select input (active low). A low input allows DCLK

to increment the address counter and enables DATAto

drive out. If the EPC1 or EPC2 is reset with nCSlow, the

device initializes as the first device in a configuration

chain. If the EPC1 or EPC2 device is reset with nCS

high, the device initializes as the subsequent device in

the chain.

Altera Corporation

Configuration Devices for SRAM-Based LUT Devices Data Sheet

Table 3. EPC2, EPC1, & EPC1441 Pin Functions During APEX II, APEX 20K, Mercury, ACEX 1K, FLEX 10K

& FLEX 6000 Configuration (Part 2 of 3)

Notes (1), (2)

Pin Name

Pin Number

Type

Description

8-Pin

20-Pin 32-Pin

PDIP (3) PLCC TQFP (4)

nCASC(6)

Output Cascade select output (active low). This output goes

low when the address counter has reached its

maximum value. In a chain of EPC1 or EPC2 devices,

the nCASCpin of one device is connected to the nCSpin

of the next device, which permits DCLKto clock data

from the next EPC1 or EPC2 device in the chain.

nINIT_CONF

–

Open- Allows the INIT_CONF JTAG instruction to initiate

(5), (7)

Drain

configuration. This pin is connected to the nCONFIGpin

Output of the LUT device to initiate configuration from the

EPC2 via a JTAG instruction. If multiple EPC2 devices

are used to configure an ACEX, APEX, FLEX or

Mercury device, only the first EPC2 has its

nINIT_CONFpin tied to the device’s nCONFIGpin.

TDI(7)

–

Input

JTAG data input pin. Connect this pin to V_CCif the

JTAG circuitry is not used.

TDO(7)

Output JTAG data output pin. Do not connect this pin if the

JTAG circuitry is not used.

TMS(7)

Input

JTAG mode select pin. Connect this pin to V_CCif the

JTAG circuitry is not used.

TCK(7)

JTAG clock pin. Connect this pin to ground if the JTAG

circuitry is not used.

VCCSEL (7)

Mode select for V_CCsupply. VCCSELmust be

connected to ground if the device uses a 5.0-V power

supply (i.e., V_CC= 5.0 V). VCCSELmust be connected

to V_CCif the device uses a 3.3-V power supply (i.e.,

V_CC= 3.3 V).

VPPSEL (7)

VPP (7)

–

Input

Mode select for VPP. VPPSELmust be connected to

ground if VPPuses a 5.0-V power supply

(i.e., VPP= 5.0 V). VPPSELmust be connected to V_CC

if VPPuses a 3.3-V power supply (i.e, VPP= 3.3 V).

Power Programming power pin. For the EPC2 device, this pin

is normally tied to V_CC. If the EPC2 V_CCis 3.3 V, VPP

can be tied to 5.0 V to improve in-system programming

times. For EPC1 and EPC1441 devices, VPPmust be

tied to V_CC

Altera Corporation

Configuration Devices for SRAM-based LUT Devices Data Sheet

Table 3. EPC2, EPC1, & EPC1441 Pin Functions During APEX II, APEX 20K, Mercury, ACEX 1K, FLEX 10K

& FLEX 6000 Configuration (Part 3 of 3)

Notes (1), (2)

Pin Name

Pin Number

Type

Description

8-Pin

20-Pin 32-Pin

PDIP (3) PLCC TQFP (4)

VCC

GND

7, 8

Power Power pin.

Ground Ground pin. A 0.2-µF decoupling capacitor must be

placed between the VCCand GNDpins.

Notes to Table 3:

(1) Do not use EPC2 devices to configure FLEX 6000 devices.

(2) Pin-out information for EPC8 and EPC16 configuration devices, please refer to each respective data sheet.

(3) This package is available for EPC1 and EPC1441 devices only.

(4) This package is available for EPC2 and EPC1441 devices only.

(5) The OE, nCS, and nINIT_CONFpins on EPC2 devices have internal, user-configurable 1-kΩ pull-up resistors. If

internal pull-up resistors are used, external pull-up resistors should not be used on these pins.

(6) The EPC1441 device does not support data cascading. EPC2 and EPC1 devices support data cascading.

(7) This pin applies to the EPC2 device only.

APEX II, APEX 20K, Merucry, ACEX 1K, FLEX 10K & FLEX 6000

Device Configuration with Multiple EPC2 or EPC1 Configuration

Devices

When configuration data for APEX II, APEX 20K, Mercury, ACEX 1K,

and FLEX devices exceeds the capacity of a single EPC2 or EPC1

configuration device, multiple EPC2 or EPC1 devices can be cascaded

together. If multiple EPC2 or EPC1 devices are required, the nCASCand

nCSpins provide handshaking between the devices.

EPC8 and EPC16 configuration devices cannot be cascaded

together. The EPC1441 device does not support data cascading.

Altera Corporation

Configuration Devices for SRAM-Based LUT Devices Data Sheet

When configuring APEX II, APEX 20K, Mercury, ACEX 1K, and

FLEX 10K devices with cascaded EPC2 or EPC1 devices, the position of

the EPC2 or EPC1 device in the chain determines its operation. Similarly,

when configuring FLEX 6000 devices with cascaded EPC1 devices, the

position of the EPC1 device in the chain determines its operation. When

the first or master device in a configuration device chain is powered-up or

reset and the nCSpin is driven low, the master device controls

configuration. The master device supplies all clock pulses to one or more

LUT-based PLDs and to any subsequent slave devices during

configuration. The master EPC2 or EPC1 device also provides the first

stream of data to the LUT-based PLD during multi-device configuration.

After the master EPC2 or EPC1 device finishes sending configuration

data, the master EPC2 or EPC1 device drives its nCASCpin low, which

drives the nCSpin of the first slave EPC2 or EPC1 device low. This action

causes the slave EPC2 or EPC1 device to send configuration data to the

LUT-based PLDs.

The master EPC2 or EPC1 device clocks all subsequent slave devices until

configuration is complete. Once all configuration data is transferred and

the nCSpin on the master EPC2 or EPC1 device is driven high by the LUT-

based PLD’s CONF_DONEpin, the master EPC2 or EPC1 device clocks 16

additional cycles to initialize the LUT-based PLD(s). The master EPC2 or

EPC1 device then goes into zero-power (idle) state. If nCSon the master

EPC2 or EPC1 device is driven high before all configuration data is

transferred, or if nCSis not driven high after all configuration data is

transferred, the master EPC2 or EPC1 device drives the APEX 20K,

Mercury, ACEX 1K, and FLEX device’s nSTATUSpin low, indicating a

configuration error.

Configuration automatically restarts if the project is compiled with the

Auto-Restart Configuration on Frame Error option turned on in the

MAX+PLUS II software’s Global Project Device Options dialog box

(Assign menu).

Figure 5 shows an APEX II, APEX 20K, Mercury, ACEX 1K, FLEX 10K, or

FLEX 6000 device configured with two EPC2 or EPC1 devices. Additional

EPC2 or EPC1 devices can be added by connecting nCASCto nCSof the

subsequent slave EPC2 or EPC1 device in the chain and connecting DCLK,

DATA, and OEin parallel.

A mixture of APEX 20K, Mercury, ACEX 1K, FLEX 10K, and

FLEX 6000 devices can be configured in the same chain. A

mixture of FLEX 10K, FLEX 10KA, FLEX 10KE, and 5.0-V and

3.3-V FLEX 6000 devices can be configured in the same chain. See

“Configuration Chain with Multiple Voltage Levels” on page 25.

Altera Corporation

Configuration Devices for SRAM-based LUT Devices Data Sheet

Figure 5. APEX II, APEX 20K, Mercury, ACEX 1K, FLEX 10K, or FLEX 6000 Device Configured with Two EPC2

or EPC1 Configuration Devices

Note (1)

(2, 3)

Configuration

Device 1

Configuration

Device 2

(2, 3)

LUT-Based PLD (4)

DCLK

DATA0

nSTATUS

CONF_DONE

nCONFIG

DCLK

DATA

nCS

nINIT_CONF

DCLK

DATA

nCS

nCASC(5)

(6)

MSEL0

nCE

MSEL1

GND

Notes to Figure 5:

(1) Do not use EPC2 devices to configure FLEX 6000 devices.

(2) The pull-up resistor should be connected to the same supply voltage as the configuration device.

(3) All pull-up resistors are 1 kΩ (APEX 20KE pull-resistors are 10 kΩ). The OEand nCSpins on EPC2 devices have

internal, user-configurable 1-kΩ pull-up resistors. If internal pull-up resistors are used, external pull-up resistors

should not be used on these pins.

(4) The diagram shows an APEX II, APEX 20K, Mercury, ACEX 1K, and FLEX device, which has MSEL0and MSEL1

tied to ground. For FLEX 6000 devices, MSELis tied to ground, and the DATA0pin is named DATA. EPC8, EPC16,

and EPC2 devices cannot be used with FLEX 6000 devices. All other connections are the same for FLEX 6000

devices. The Quartus II software uses the internal pull-up resistors by default. To turn off the internal pull-up

resistors, check the Disable nCS and OE pull-ups on configuration device option when generating programming files.

(5) EPC4, EPC8, and EPC16 devices cannot be cascaded.

(6) The nINIT_CONFpin is only available on EPC2 devices and has an internal pull up of 1 kΩ that is always active. If

nINIT_CONFis not available or not used, nCONFIGmust be pulled to V_CCeither directly or through a 1-kΩ resistor.

Altera Corporation

Configuration Devices for SRAM-Based LUT Devices Data Sheet

Figure 6 shows two APEX II, APEX 20K, Mercury, ACEX 1K, and FLEX

devices configured with two EPC2 or EPC1 devices.

Figure 6. Two ACEX 1K, APEX 20K, APEX II, FLEX 10K, FLEX 6000, or Mercury Devices Configured with Two

EPC2 or EPC1 Configuration Devices

Note (1)

APEX II, ACEX 1K, Mercury, APEX 20KC,

APEX 20K, FLEX 10K, & FLEX 6000 Devices

(2)

Configuration

Device 1

Configuration

Device 2

LUT-Based PLD (3)

DCLK

LUT-Based PLD (3)

DCLK

DATA

nCS nCASC (4)

nINIT_CONF (5)

DCLK

DATA0

nSTATUS

MSEL0

MSEL1

MSEL0

DCLK

DATA0

DATA

nCS

MSEL1

nSTATUS

CONF_DONE

nCONFIG

CONF_DONE

nCONFIG

GND

nCEO

nCE

GND

APEX 20KE Devices

(6)

CCINT

(2)

Configuration

Device 1

Configuration

Device 2

APEX 20KE PLD (7)

DCLK

DATA

nCS nCASC (4)

nINIT_CONF (5)

DCLK

DATA0

nSTATUS

MSEL0

MSEL1

DCLK

DATA0

nSTATUS

MSEL1

DATA

nCS

CONF_DONE

nCONFIG

CONF_DONE

nCONFIG

GND

(8)

nCEO

nCE

GND

Altera Corporation

Configuration Devices for SRAM-based LUT Devices Data Sheet

Notes to Figure 6:

(1) Do not use EPC2 devices to configure FLEX 6000 devices.

(2) The pull-up resistor should be connected to the same supply voltage as the configuration device. All pull-up

resistors are 1 kΩ (APEX 20KE pull-resistors are 10 kΩ). The OEand nCSpins on EPC2 devices have internal, user-

configurable 1-kΩ pull-up resistors. If internal pull-up resistors are used, external pull-up resistors should not be

used on these pins. The Quartus II software uses the internal pull-up resistors by default. To turn off the internal

pull-up resistors, check the Disable nCS and OE pull-ups on configuration device option when generating programming

files.

(3) The diagram shows an APEX II, APEX 20K, Mercury, ACEX 1K, or FLEX 10K device, which has MSEL0and MSEL1

tied to ground. For FLEX 6000 devices, MSELis tied to ground, and the DATA0pin is named DATA. EPC2 cannot be

used with FLEX 6000 devices. All other connections are the same for FLEX 6000 devices.

(4) EPC4, EPC8, and EPC16 devices cannot be cascaded.

(5) The nINIT_CONFpin is only available on EPC2 devices and has an internal pull up of 1 kΩ that is always active. If

nINIT_CONFis not available or not used, nCONFIGmust be pulled to V_CCeither directly or through a 1-kΩ resistor.

(6) To ensure successful configuration between APEX 20KE and configuration devices in all possible power-up

sequences, pull up nCONFIGto V_CCINT

(7) This diagram is for APEX 20KE devices only.

(8) To isolate the 1.8-V and 3.3-V power supplies when configuration APEX 20KE devices, add a diode between the

APEX 20KE device’s nCONFIGpin and the configuration device’s nINIT_CONFpin. Select a diode with a threshold

voltage (V_T) less than or queal to 0.7 V. The diode will make the nINIT_CONFpin an open-drain pin; the pin will

only be able to drive low or tri-state.

For more information on APEX 20K, ACEX 1K, FLEX 10K, or FLEX 6000

device configuration, see Application Note 116 (Configuring ACEX 1K,

APEX 20K, FLEX 10K & FLEX 6000 Devices).

Figure 7 shows the timing waveform for the configuration device scheme.

Figure 7. Configuration Device Scheme Timing Waveform

nINIT_CONF or VCC/nCONFIG

t_POR

OE/nSTATUS

nCS/CONF_DONE

t_CH

t_DSU

t_CL

DCLK

DATA

t_OEZX

t_DH

D₂

D₀

t_CO

Tri-State

D₁

D₃

D_n

(1)

User I/O

User Mode

Tri-State

INIT_DONE

(2)

Notes to Figure 7:

(1) The configuration devivce will drive DATA low after configuration.

(2) APEX II and APEX 20K devices (except EP2A70 devices) enter user mode 40 clock cycles after CONF_DONEgoes

high. EP2A70 devices enter user mode 72 clock cycles after CONF_DONEgoes high. FLEX 10K and FLEX 6000 devices

enter user mode 10 clock cycles after CONF_DONEgoes high. Mercury devices enter user mode 136 clock cycles after

CONF_DONEgoes high.

Altera Corporation

Configuration Devices for SRAM-Based LUT Devices Data Sheet

Table 4 defines the APEX 20K, FLEX 10K, and FLEX 6000 timing

parameters when using EPC2 devices at 3.3 V.

Table 4. APEX 20K, FLEX 10K & FLEX 6000 Timing Parameters using EPC2

Devices at 3.3 V

Note (1)

Symbol

Parameter

Min

Max

Units

t_POR

t_OEZX

t_CH

POR delay (2)

200

OEhigh to DATAoutput enabled

DCLKhigh time

100

t_CL

DCLKlow time

t_DSU

Data setup time before rising edge on

DCLK

t_DH

Data hold time after rising edge on DCLK

DCLKto DATAout

t_CO

t_OEW

OElow pulse width to guarantee counter

reset

100

f_CLK

DCLKfrequency

12.5

MHz

Notes to Table 4:

(1) For more information regarding EPC4, EPC8, or EPC16 configuration device timing

parameters, see the Enhanced Configuration Device (EPC4, EPC8 & EPC16) Data Sheet.

(2) The configuration device imposes a POR delay upon initial power-up to allow the

voltage supply to stabilize. Subsequent reconfigurations do not incur this delay.

Altera Corporation

Configuration Devices for SRAM-based LUT Devices Data Sheet

Table 5 defines the APEX 20K, FLEX 10K, and FLEX 6000 timing

parameters when using EPC1 and EPC1441 devices at 3.3 V.

Table 5. APEX 20K, FLEX 10K & FLEX 6000 Timing Parameters using EPC1 &

EPC1441 Devices at 3.3 V

Note (1)

Symbol

Parameter

Min

Max

Units

t_POR

t_OEZX

t_CH

POR delay (2)

200

OEhigh to DATAoutput enabled

DCLKhigh time

250

t_CL

DCLKlow time

t_DSU

Data setup time before rising edge on

DCLK

t_DH

Data hold time after rising edge on DCLK

DCLKto DATAout

t_CO

t_OEW

OElow pulse width to guarantee counter

reset

100

f_CLK

DCLKfrequency

MHz

Notes to Table 5:

(1) For more information regarding EPC4, EPC8, or EPC16 configuration device timing

parameters, see the Enhanced Configuration Device (EPC4, EPC8 & EPC16) Data Sheet.

(2) The configuration device imposes a POR delay upon initial power-up to allow the

voltage supply to stabilize. Subsequent reconfigurations do not incur this delay.

Altera Corporation

Configuration Devices for SRAM-Based LUT Devices Data Sheet

Table 6 defines the APEX 20K, FLEX 10K, and FLEX 6000 timing

parameters when using EPC2, EPC1, and EPC1441 devices at 5.0 V.

Table 6. APEX 20K, FLEX 10K & FLEX 6000 Timing Parameters using EPC2,

EPC1 & EPC1441 Devices at 5.0 V

Notes (1), (2)

Symbol

t_POR

t_OEZX

t_CH

Parameter

Min

Max

Units

POR delay (3)

200

OEhigh to DATAoutput enabled

DCLKhigh time

t_CL

DCLKlow time

t_DSU

Data setup time before rising edge on

DCLK

t_DH

Data hold time after rising edge on DCLK

DCLKto DATAout

t_CO

t_OEW

OElow pulse width to guarantee counter

reset

100

6.7

f_CLK

DCLKfrequency

16.7

MHz

Notes to Table 6:

(1) Do not use EPC16, EPC8, EPC4, or EPC2 devices to configure FLEX 6000 devices.

(2) For more information regarding EPC4, EPC8, or EPC16 configuration device timing

parameters, see the Enhanced Configuration Device (EPC4, EPC8 & EPC16) Data Sheet.

(3) The configuration device imposes a POR delay upon initial power-up to allow the

voltage supply to stabilize. Subsequent reconfigurations do not incur this delay.

FLEX 8000 Device Configuration

FLEX 8000 devices differ from ACEX 1K, APEX 20K, APEX II, FLEX 10K,

and FLEX 6000 devices in that they have internal oscillators that can

provide a DCLKsignal to the configuration device. The configuration

device sends configuration data out as a serial bitstream on the DATA

output pin. This data is routed into the FLEX 8000 device via the DATA0

input pin. The EPC1, EPC1441, EPC1213, EPC1064, and EPC1064V

configuration devices support this type of configuration.

Altera Corporation

Configuration Devices for SRAM-based LUT Devices Data Sheet

EPC1 and EPC1441 devices can replace the EPC1213, EPC1064, and

EPC1064V configuration devices. The EPC1 or EPC1441 device

automatically emulates the EPC1213, EPC1064, or EPC1064V when it is

programmed with the appropriate POF. When the EPC1 or EPC1441

device is programmed with an EPC1213, EPC1064, or EPC1064V POF, the

FLEX 8000 device drives the EPC1 or EPC1441 device’s OEpin high and

clocks the EPC1 or EPC1441 device. One EPC1 device can store more

configuration data than the EPC1064, EPC1064V, EPC1213, or EPC1441

device. Therefore, designers can use one type of configuration device for

all FLEX devices. In addition, a single EPC1 or EPC1441 device can

configure any FLEX 8000 device.

For multi-device configuration of FLEX 8000 devices, the nCASCand nCS

pins provide handshaking between multiple configuration devices,

allowing several cascaded EPC1 or EPC1213 devices to serially configure

multiple FLEX 8000 devices. The EPC1441, EPC1064, and EPC1064V do

not support data cascading. Figure 8 shows a FLEX 8000 device

configured with a single EPC1, EPC1441, EPC1213, EPC1064, or

EPC1064V configuration device.

Figure 8. FLEX 8000 Device Configured with an EPC1, EPC1441, EPC1213,

EPC1064, or EPC1064V Configuration Device

VCC(1)

VCC (1)

(2)

Configuration

Device

FLEX 8000 Device

nS/P

MSEL1

MSEL0

CONF_DONE

nSTATUS

DCLK

nCS

DCLK

"0"

DATA

DATA0

nCONFIG

Notes to Figure 8:

(1) The pull-up resistor should be connected to the same supply voltage as the

configuration device.

(2) All pull-up resistors are 1 kΩ.

Figure 9 shows three FLEX 8000 devices configured with two EPC1 or

EPC1213 configuration devices.

Altera Corporation

Configuration Devices for SRAM-Based LUT Devices Data Sheet

Figure 9. FLEX 8000 Multi-Device Configuration with Two EPC1 or EPC1213 Configuration Devices

VCC

VCC (1)

(1)

(2)

VCC

(1)

Configuration

Device 2

Configuration

Device 1

(2)

FLEX 8000 Device 1

nS/P

MSEL1

MSEL0

CONF_DONE

nSTATUS

DCLK

nCASC

DATA

"0"

DATA

nCS

DCLK

DATA0

nCONFIG

VCC (1)

(2)

FLEX 8000 Device 2

nS/P

MSEL1

MSEL0

CONF_DONE

nSTATUS

"0"

"1"

"0"

DCLK

DATA0

nCONFIG

VCC (1)

(2)

FLEX 8000 Device 3

nS/P

MSEL1

MSEL0

CONF_DONE

nSTATUS

"0"

"1"

"0"

DCLK

DATA0

nCONFIG

Notes to Figure 9:

(1) The pull-resistor should be connected to the same supply voltage as the confiuration device.

(2) All pull-up resistors are 1 kΩ.

Altera Corporation

Configuration Devices for SRAM-based LUT Devices Data Sheet

Table 7 describes the pin functions of all configuration devices during

FLEX 8000 device configuration.

Table 7. Configuration Device Pin Functions During FLEX 8000 Device Configuration

Pin Name

Pin Number

Type

Description

8-Pin

20-Pin 32-Pin

PDIP (1) PLCC TQFP (2)

DATA

Output

Input

Serial data output. The DATApin is tri-stated before

configuration when the nCSpin is high and after the

configuration device finishes sending its configuration

data. This operation is independent of the device’s

position in the cascade chain.

DCLK

DCLKis a clock input when using EPC1, EPC1213,

EPC1064, and EPC1064V configuration devices. Rising

edges on DCLKincrement the internal address counter

and present the next bit of data to the DATApin. The

counter is incremented only if the OEinput is held high,

the nCSinput is held low, and all configuration data has

not been transferred to the target device.

Open-

Drain

I/O

Output enable (active high) and reset (active low). A low

logic level resets the address counter. A high logic level

enables DATAand permits the address counter to count.

nCS(3)

Input

Chip-select input (active low). A low input allows DCLKto

increment the address counter and enables DATA.

nCASC

Output Cascade-select output (active low). This output goes low

when the address counter has reached its maximum

value. The nCASCoutput is usually connected to the nCS

input of the next device in a configuration chain, so the

next DCLKclocks data out of the next device.

VCC

GND

7, 8

Power Power pin.

Ground Ground pin. A 0.2-µF decoupling capacitor must be

placed between the VCCand GNDpins.

Notes: to Table 7

(1) This package is available for EPC1, EPC1441, EPC1213, EPC1064, and EPC1064V devices only.

(2) This package is available for EPC1441, EPC1064, and EPC1064V devices only.

(3) The EPC1441, EPC1064, and EPC1064V devices do not support data cascading. The EPC1 and EPC1213 devices

support data cascading for FLEX 8000 devices.

For more information on FLEX 8000 device configuration, see the

following documents:

■

Application Note 33 (Configuring FLEX 8000 Devices)

Application Note 38 (Configuring Multiple FLEX 8000 Devices)

Altera Corporation

Configuration Devices for SRAM-Based LUT Devices Data Sheet

This section describes Power-On Reset (POR) delay, error detection, and

3.3-V and 5.0-V operation of Altera configuration devices.

Power &

Operation

Power-On Reset

During initial power-up, a POR delay occurs to permit voltage levels to

stabilize. When configuring an APEX II, APEX 20K, Mercury, ACEX 1K,

FLEX 10K, or FLEX 6000 device with an EPC4, EPC8, EPC16, EPC2, EPC1,

or EPC1441 device, the POR delay occurs inside the configuration device,

and the POR delay is a maximum of 200 ms. When configuring a

FLEX 8000 device with an EPC1213, EPC1064, or EPC1064V device, the

POR delay occurs inside the FLEX 8000 device, and the POR delay is

typically 100 ms, with a maximum of 200 ms.

Error Detection Circuitry

The EPC4, EPC8, EPC16, EPC2, EPC1, and EPC1441 configuration devices

have built-in error detection circuitry for configuring APEX II, APEX 20K,

Mercury, ACEX 1K, FLEX 10K, or FLEX 6000 devices only.

Built-in error-detection circuitry uses the nCSpin of the configuration

device, which monitors the CONF_DONEpin on the APEX II, APEX 20K,

Mercury, ACEX 1K, FLEX 10K, or FLEX 6000 device. An error condition

occurs if the CONF_DONEpin does not go high after all the configuration

data has been sent, or if the CONF_DONEpin goes high before the

configuration device has completed sending configuration data. When an

error condition occurs, the configuration device drives its OEpin low,

which drives the APEX II, APEX 20K, Mercury, ACEX 1K, FLEX 10K, or

FLEX 6000 device’s nSTATUSpin low, indicating an error. After an error,

configuration automatically restarts if the Auto-Restart Configuration on

Frame Error option is turned on in the Global Project Device Options

dialog box (Assign menu) in the MAX+PLUS II software. For APEX 20K,

APEX II, and Mercury devices, the Quartus II software provides a similar

option.

In addition, if the APEX II, APEX 20K, Mercury, ACEX 1K, FLEX 10K, or

FLEX 6000 device detects a cyclic redundancy code (CRC) error in the

received data, it may also flag the error by driving nSTATUSlow. This low

signal on nSTATUSresets the configuration device, allowing

reconfiguration. CRC checking is performed when configuring all

APEX II, APEX 20K, Mercury, ACEX 1K, FLEX 10K, or FLEX 6000

devices.

Altera Corporation

Configuration Devices for SRAM-based LUT Devices Data Sheet

3.3-V or 5.0-V Operation

EPC2, EPC1, and EPC1441 devices can configure 5.0-V, 3.3-V, or 2.5-V

devices. For each configuration device, an option must be set for 5.0-V or

3.3-V operation (EPC4, EPC8, and EPC16 devices are 3.3 V). For EPC1 and

EPC1441 configuration devices, the Use Low-Voltage Configuration EPROM

option in the Global Project Device Options dialog box (Assign menu) in

the MAX+PLUS II software sets this parameter. (For APEX 20K, APEX II,

and Mercury devices, the Quartus II software provides a similar option.)

For EPC2 devices, this option is set externally by the VCCSELpin. In

addition, the EPC2 device has an externally controlled option, set by the

VPPSELpin, to adjust the programming voltage to 5.0 V or 3.3 V.

The functions of the VCCSELand VPPSELpins are described below.

■ VCCSELpin—For EPC2 configuration devices, 5.0-V or 3.3-V

operation is controlled by the VCCSELoption pin. The device

functions in 5.0-V mode when VCCSELis connected to GND; the

device functions in 3.3-V mode when VCCSELis connected to V

■ VPPSELpin—The EPC2 VPPprogramming power pin is normally

tied to V . For EPC2 devices operating with a 3.3-V supply, it is

possible to improve EPC2 in-system programming times by

providing VPPwith a 5.0-V supply. For all other devices, VPPmust be

tied to V . The EPC2 device’s VPPSELpin must be set in accordance

with the EPC2 VPPpin. If the VPPpin is supplied by a 5.0-V supply,

VPPSELmust be connected to GND; if the VPPpin is supplied by a

3.3-V power supply, VPPSELmust be connected to V

Table 8 describes the relationship between the V and V voltage levels

and the required logic level for VCCSELand VPPSEL(i.e., high or low

logic level).

Table 8. VCCSEL & VPPSEL Pin Functions on the EPC2

Voltage Level V Voltage Level VCCSEL Pin Logic VPPSEL Pin Logic

(V)

Level

3.3

5.0

3.3

5.0

High

Low

High

Low

Altera Corporation

Configuration Devices for SRAM-Based LUT Devices Data Sheet

For EPC1 and EPC1441 configuration devices, 3.3-V or 5.0-V operation is

controlled by a programming bit in the POF. The programming bit value

is determined by the core supply voltage of the targeted device during

design compilation with the MAX+PLUS II software. For example, EPC1

devices are programmed automatically to operate in 3.3-V mode when

configuring FLEX 10KA devices, which have a V voltage of 3.3 V. In this

example, the EPC1 device’s VCCpin is connected to a 3.3-V power supply.

Designers may choose to set the configuration device for low voltage

when using the MultiVolt^TMfeature, which allows an ACEX, APEX,

APEX II, FLEX, or Mercury device to bridge between systems operating

with different voltages. When compiling for 3.3-V FLEX 6000 devices, set

the configuration device for low-voltage operation. To set the EPC1 and

EPC1441 configuration devices for low-voltage operation, turn on the

Low-Voltage I/O option in the Global Project Device Options dialog box

(Assign menu) in the MAX+PLUS II software.

Configuration Chain with Multiple Voltage Levels

An EPC2 or EPC1 device can configure a device chain with multiple

voltage levels. All 3.3-V and 2.5-V ACEX, APEX, APEX II, FLEX, and

Mercury devices can be driven by higher-voltage signals.

When configuring a mixed-voltage device chain, the APEX II, APEX 20K,

Mercury, ACEX 1K, or FLEX devices’ VCCINTand VCCIOpins may be

connected to 2.5 V, 3.3 V, or 5.0 V, depending upon the device. The

configuration device may be powered at 3.3 V or 5.0 V. If an EPC1,

EPC1441, EPC1213, EPC1064, or EPC1064V configuration device is

powered at 3.3 V, the nSTATUSand CONF_DONEpull-up resistors must be

connected to 3.3 V. If these configuration devices are powered at 5.0 V, the

nSTATUSand CONF_DONEpull-up resistors must be connected to 3.3 V or

5.0 V.

Altera Corporation

Configuration Devices for SRAM-based LUT Devices Data Sheet

At 3.3-V operation, all EPC2 inputs are 5.0-V tolerant, except DATA, DCLK,

and nCASC. The DATA, DCLK, and nCEOpins are used only to interface

between the EPC2 configuration device and the APEX II, APEX 20K,

Mercury, ACEX 1K, or FLEX 10K device it is configuring. The voltage

tolerances of all EPC2 pins at 5.0 V and 3.3 V are listed in Table 9.

Table 9. EPC2 Input & Bidirectional Pin Voltage Tolerance

5.0-V Operation

3.3-V Operation

5.0-V

Tolerant

3.3-V

Tolerant

5.0-V

Tolerant

3.3-V

Tolerant

DATA

DCLK

nCASC

nCS

VCCSEL

VPPSEL

nINIT_CONF

TDI

TMS

TCK

For more information on APEX II, APEX 20K, Mercury, ACEX 1K,

FLEX 10K, or FLEX 6000 devices, see the following documents:

■

ACEX 1K Programmable Logic Device Family Data Sheet

APEX 20K Programmable Logic Device Family Data Sheet

APEX II Programmable Logic Device Family Data Sheet

FLEX 10K Embedded Programmable Logic Family Data Sheet

FLEX 10KE Embedded Programmable Logic Family Data Sheet

FLEX 8000 Programmable Logic Device Family Data Sheet

FLEX 6000 Programmable Logic Device Family Data Sheet

Mercury Programmable Logic Device Family Data Sheet

Altera Corporation

Configuration Devices for SRAM-Based LUT Devices Data Sheet

The Quartus II and MAX+PLUS II development systems provide

programming support for Altera configuration devices. The Quartus II

and MAX+PLUS II software automatically generates a POF to program

each configuration device in a project. In a multi-device project, the

software can combine the programming files for multiple ACEX, APEX,

APEX II, FLEX, or Mercury devices into one or more configuration

devices. The software allows you to select the appropriate configuration

device to most efficiently store the data for each APEX II, APEX 20K,

Mercury, ACEX 1K, or FLEX device. Moreover, when compiling for

ACEX 1K, FLEX 10KA, FLEX 10KE, or Mercury devices, the

Programming

&Configuration

File Support

MAX+PLUS II software automatically defaults to generate the EPC1 or

EPC1441 POF with the programming bit set for 3.3-V operation.

All Altera configuration devices are programmable using Altera

programming hardware in conjunction with the Quartus II or

MAX+PLUS II software. In addition, many manufacturers offer

programming hardware that supports other Altera configuration devices.

EPC4, EPC8, EPC16, and EPC2 configuration devices can be programmed

in-system through its industry-standard 4-pin JTAG interface. ISP

capability in the EPC2, EPC4, EPC8, and EPC16 devices provides ease in

prototyping and updating APEX II, APEX 20K, Mercury, ACEX 1K, or

FLEX device functionality. The EPC8 and EPC16 devices can be

programmed in-system via test equipment using SVF Files, Jam STAPL

Files (.jam), or Jam STAPL Byte-Code Files (.jbc), embedded processors

using the Jam programming and test language, and the MAX+PLUS II or

Quartus II software via the MasterBlaster or ByteBlasterMV download

cables. When programming multiple EPC2 devices in a JTAG chain, the

Quartus II and MAX+PLUS II software and other programming methods

employ concurrent programming to simultaneously program multiple

devices and reduce programming time. EPC2, EPC4, EPC8, and EPC16

devices can be programmed and erased up to 100 times.

After programming an EPC2, EPC4, EPC8, or EPC16 device in-system,

APEX II, APEX 20K, Mercury, ACEX 1K, or FLEX device configuration

can be initiated by including the EPC2 JTAG configuration instruction.

See Table 10 on page 28.

For more information on programming and configuration support, see the

following documents:

■

Altera Programming Hardware Data Sheet

Programming Hardware Manufacturers

MasterBlaster Serial/USB Communications Cable Data Sheet

ByteBlasterMV Parallel Port Download Cable Data Sheet

ByteBlaster Parallel Port Download Cable Data Sheet

BitBlaster Serial Download Cable Data Sheet

Altera Corporation

Configuration Devices for SRAM-based LUT Devices Data Sheet

The EPC2 provides JTAG BST circuitry that complies with the IEEE Std.

IEEE Std.

1149.1-1990 specification. JTAG boundary-scan testing can be performed

before or after configuration, but not during configuration. The EPC2

device supports the JTAG instructions shown in Table 10.

1149.1 (JTAG)

Boundary-Scan

Testing

The ISP circuitry in EPC2, EPC4, EPC8, and EPC16 devices is compatible

with tools that support the IEEE Std. 1532. The IEEE Std. 1532 is a standard

developed to allow concurrent ISP between multiple PLD vendors.

For EPC4, EPC8, and EPC16 JTAG instruction, refer to the Enhanced

Configuration Devices (EPC4, EPC8, & EPC16) Data Sheet.

Table 10. EPC2 JTAG Instructions

JTAG Instruction

Description

SAMPLE/PRELOAD

Allows a snapshot of a signal at the device pins to be captured and examined during

normal device operation, and permits an initial data pattern output at the device pins.

EXTEST

Allows the external circuitry and board-level interconnections to be tested by forcing a

test pattern at the output pins and capturing results at the input pins.

BYPASS

Places the 1-bit bypass register between the TDIand TDOpins, which allows the BST

data to pass synchronously through a selected device to adjacent devices during

normal device operation.

IDCODE

Selects the device IDCODE register and places it between TDIand TDO, allowing the

device IDCODE to be serially shifted out of TDO. The device IDCODE for the EPC2

configuration device is shown below:

0000 0001000000000010 00001101110 1

USERCODE

Selects the USERCODE register and places it between TDIand TDO, allowing the

USERCODE to be serially shifted out of TDO. The 32-bit USERCODE is a

programmable user-defined pattern.

ISP Instructions

These instructions are used when programming an EPC2 device via JTAG ports with

a MasterBlaster, ByteBlaster MV, ByteBlaster, or BitBlaster download cable, or using

a Jam STAPL File (.jam), Jam STAPL Byte-Code File (.jbc), or SVF File via an

embedded processor.

INIT_CONF

This function allows the user to initiate the APEX or FLEX configuration process by

tying nINIT_CONFto the APEX or FLEX device(s) nCONFIGpin(s). After this

instruction is updated, the nINIT_CONFpin is driven low. When the Initiate

Configuration instruction is cleared, nINIT_CONFis released, which starts the APEX

or FLEX device configuration. This instruction is used by the MAX+PLUS II software,

Jam STAPL Files, and JBC Files.

For more information, see Application Note 39 (IEEE 1149.1 (JTAG)

Boundary-Scan Testing in Altera Devices).

Figure 10 shows the timing requirements for the JTAG signals.

Altera Corporation

Configuration Devices for SRAM-Based LUT Devices Data Sheet

Figure 10. EPC2 JTAG Waveforms

TMS

TDI

t_JCP

t_JCH

t_JCL

t_JPH

t_JPSU

TCK

TDO

t_JPZX

t_JPXZ

t_JPCO

t_JSSU

t_JSH

Signal

to Be

Captured

t_JSZX

t_JSCO

t_JSXZ

Signal

to Be

Driven

Table 11 shows the timing parameters and values for configuration

devices.

Table 11. JTAG Timing Parameters & Values

Symbol

Parameter

Min Max Unit

t_JCP

TCKclock period

100

t_JCH

TCKclock high time

TCKclock low time

JTAG port setup time

JTAG port hold time

t_JCL

t_JPSU

t_JPH

t_JPCO

t_JPZX

t_JPXZ

t_JSSU

t_JSH

JTAG port clock to output

JTAG port high impedance to valid output

JTAG port valid output to high impedance

Capture register setup time

Capture register hold time

t_JSCO

t_JSZX

t_JSXZ

Update register clock to output

Update register high-impedance to valid output

Update register valid output to high impedance

Tables 12 through 19 provide information on absolute maximum ratings,

recommended operating conditions, DC operating conditions, and

capacitance for configuration devices.

Operating

Conditions

Altera Corporation

Configuration Devices for SRAM-based LUT Devices Data Sheet

For EPC4, EPC8, and EPC16 device operating conditions, refer to the

Enhanced Configuration Devices (EPC4, EPC8, & EPC16) Data Sheet.

Table 12. Absolute Maximum Ratings

Note (1)

Symbol

Parameter

Conditions

Min

Max

Unit

V_CC

V_I

Supply voltage

With respect to ground (2)

–2.0

7.0

DC input voltage

I_MAX

I_OUT

P_D

DC V_CCor ground current

DC output current, per pin

Power dissipation

° C

–25

250

150

135

T_STG

T_AMB

T_J

Storage temperature

Ambient temperature

Junction temperature

No bias

–65

Under bias

Table 13. Recommended Operating Conditions

Symbol

Parameter

Conditions

Min

Max

Unit

V_CC

Supply voltage for 5.0-V operation

Supply voltage for 3.3-V operation

Input voltage

(3), (4)

4.75 (4.50) 5.25 (5.50)

3.0 (3.0)

–0.3

3.6 (3.6)

V_I

With respect to ground

V_CC+ 0.3

(5)

V_O

T_A

Output voltage

V_CC

Operating temperature

For commercial use

For industrial use

° C

–40

t_R

t_F

Input rise time

Input fall time

Table 14. DC Operating Conditions

Symbol

Parameter

Conditions

Min

Max

Unit

V_IH

High-level input voltage

2.0

V_CC+ 0.3

(5)

V_IL

Low-level input voltage

5.0-V mode high-level TTL output voltage I_OH= –4 mA DC (6)

–0.3

2.4

0.8

V_OH

3.3-V mode high-level CMOS output

voltage

I_OH= –0.1 mA DC (6)

V_CC– 0.2

V_OL

I_I

Low-level output voltage

Input leakage current

I_OL= 4 mA DC (6)

V_I= V_CCor ground

V_O= V_CCor ground

0.4

–10

µA

I_OZ

Tri-state output off-state current

Altera Corporation

Configuration Devices for SRAM-Based LUT Devices Data Sheet

Table 15. EPC1213, EPC1064 & EPC1064V Device I Supply Current Values

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

I_CC0

I_CC1

V_CCsupply current (standby)

100

200

µA

V_CCsupply current

(during configuration)

Table 16. EPC2 Device I Supply Current Values

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

I_CC0

I_CC1

V_CCsupply current (standby)

V_CC= 5.0 V or 3.3 V

100

µA

V_CCsupply current (during configuration) V_CC= 5.0 V or 3.3 V

Table 17. EPC1 Device I Supply Current Values

Symbol

Parameter

Conditions

Typ

Max

Unit

I_CC0

I_CC1

V_CCsupply current (standby)

100

µA

V_CCsupply current (during configuration) V_CC= 5.0 V

V_CC= 3.3 V

16.5

Table 18. EPC1441 Device I Supply Current Values

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

I_CC0

I_CC1

V_CCsupply current (standby)

µA

V_CCsupply current (during configuration) V_CC= 5.0 V

V_CCsupply current (during configuration) V_CC= 3.3 V

Table 19. Capacitance

Note (7)

Symbol

Parameter

Conditions

Min

Max

Unit

C_IN

Input pin capacitance

Output pin capacitance

V_IN= 0 V, f = 1.0 MHz

V_OUT= 0 V, f = 1.0 MHz

C_OUT

Notes to Tables 12 − 19:

(1) See the Operating Requirements for Altera Devices Data Sheet.

(2) The minimum DC input is –0.3 V. During transitions, the inputs may undershoot to –2.0 V or overshoot to 7.0 V for

input currents less than 100 mA and periods shorter than 20 ns under no-load conditions.

(3) Numbers in parentheses are for industrial-temperature-range devices.

(4) Maximum V_CCrise time is 100 ms.

(5) Certain EPC2 pins may be driven to 5.75 V when operated with a 3.3-V V_CC. See Table 9 on page 26.

(6) The I_OHparameter refers to high-level TTL or CMOS output current; the I_OLparameter refers to low-level TTL or

CMOS output current.

(7) Capacitance is sample-tested only.

Altera Corporation

Configuration Devices for SRAM-based LUT Devices Data Sheet

Tables 20 through 24 show the device configuration parameters for

APEX II, APEX 20K, Mercury, ACEX 1K, or FLEX devices.

Table 20. ACEX 1K, FLEX 10K & FLEX 6000 Device Configuration Parameters Using EPC2 Devices at 5.0-V

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

t_CE

OEhigh to first clock delay

OEhigh to data output enabled

DCLKto data out delay

200

t_OEZX

t_CO

t_MCH

DCLKhigh time for the first device in the

configuration chain

t_MCL

DCLKlow time for the first device in the

configuration chain

f_CK

Clock frequency

6.7

16.7

MHz

t_SCH

DCLKhigh time for subsequent devices

DCLKlow time for subsequent devices

CLKrising edge to nCASC

t_SCL

t_CASC

t_CCA

f_CDOE

t_OEC

t_NRCAS

t_NRR

nCSto nCASCcascade delay

CLKto data enable/disable

OElow to CLKdisable delay

OElow (reset) to nCASCdelay

OElow time (reset) minimum

100

Table 21. ACEX 1K, APEX 20K, APEX II, FLEX 10K & Mercury Device Configuration Parameters Using EPC2

Devices at 3.3-V

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

t_CE

OEhigh to first clock delay

OEhigh to data output enabled

DCLKto data out delay

300

t_OEZX

t_CO

t_MCH

DCLKhigh time for the first device in the

configuration chain

100

t_MCL

DCLKlow time for the first device in the

100

configuration chain

f_CK

Clock frequency

7.7

12.5

MHz

t_SCH

DCLKhigh time for subsequent devices

DCLKlow time for subsequent devices

CLKrising edge to nCASC

t_SCL

t_CASC

t_CCA

f_CDOE

t_OEC

t_NRCAS

t_NRR

nCSto nCASCcascade delay

CLKto data enable/disable

OElow to CLKdisable delay

OElow (reset) to nCASCdelay

OElow time (reset) minimum

100

Altera Corporation

Configuration Devices for SRAM-Based LUT Devices Data Sheet

Table 22. ACEX 1K, FLEX 10K & FLEX 6000 Device Configuration Parameters Using EPC1 &

EPC1441 Devices at 5.0-V

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

t_CE

OEhigh to first clock delay

OEhigh to data output enabled

DCLKto data out delay

200

t_OEZX

t_CO

t_MCH

DCLKhigh time for the first device in the

configuration chain

t_MCL

DCLKlow time for the first device in the

configuration chain

f_CK

Clock frequency

6.7

16.7

MHz

t_SCH

DCLKhigh time for subsequent devices

DCLKlow time for subsequent devices

CLKrising edge to nCASC

t_SCL

t_CASC

t_CCA

f_CDOE

t_OEC

t_NRCAS

t_NRR

nCSto nCASCcascade delay

CLKto data enable/disable

OElow to CLKdisable delay

OElow (reset) to nCASCdelay

OElow time (reset) minimum

100

Table 23. ACEX 1K, FLEX 10K & FLEX 6000 Device Configuration Parameters Using EPC1 &

EPC1441 Devices at 3.3-V

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

t_CE

OEhigh to first clock delay

OEhigh to data output enabled

DCLKto data out delay

300

t_OEZX

t_CO

t_MCH

DCLKhigh time for the first device in the

configuration chain

125

250

t_MCL

DCLKlow time for the first device in the

configuration chain

250

f_CK

Clock frequency

MHz

t_SCH

DCLKhigh time for subsequent devices

DCLKlow time for subsequent devices

CLKrising edge to nCASC

t_SCL

t_CASC

t_CCA

f_CDOE

t_OEC

t_NRCAS

t_NRR

nCSto nCASCcascade delay

CLKto data enable/disable

OElow to CLKdisable delay

OElow (reset) to nCASCdelay

OElow time (reset) minimum

100

Altera Corporation

Configuration Devices for SRAM-based LUT Devices Data Sheet

Table 24. FLEX 8000 Device Configuration Parameters Using EPC1, EPC1441, EPC1213, EPC1064 &

EPC1064V Devices

Symbol

Parameter

Conditions

EPC1064V EPC1064 EPC1

EPC1213 EPC1441

Unit

Min Max Min Max Min Max

t_OEZX

t_CSZX

t_CSXZ

t_CSS

t_CSH

t_DSU

t_DH

OEhigh to DATAoutput enabled

nCSlow to DATAoutput enabled

nCShigh to DATAoutput disabled

nCSlow setup time to first DCLKrising edge

nCSlow hold time after DCLKrising edge

Data setup time before rising edge on DCLK

Data hold time after rising edge on DCLK

DCLKto DATAout delay

MHz

150

100

t_CO

100

t_CK

Clock period

240

160

100

f_CK

Clock frequency

t_CL

DCLKlow time

120

t_CH

DCLKhigh time

t_XZ

OElow or nCShigh to DATAoutput disabled

OEpulse width to guarantee counter reset

Last DCLK+ 1 to nCASClow delay

Last DCLK+ 1 to DATAtri-state delay

nCShigh to nCASChigh delay

t_OEW

t_CASC

t_CKXZ

t_CEOUT

150

100

150

100

The information contained in the Configuration Devices for SRAM-Based

LUT Devices Data Sheet version 12.1 supersedes information published in

pervious versions. The following changes were made to the Configuration

Devices for SRAM-Based LUT Devices Data Sheet version 12.1:

Revision

History

■

Updated Table 2.

Updated notes to Figures 4, 5, and 6.

Added APEX 20KE device diagrams to Figures 4 and 6.

Altera Corporation

Configuration Devices for SRAM-Based LUT Devices Data Sheet

Notes:

Altera Corporation

Configuration Devices for SRAM-Based LUT Devices Data Sheet

101 Innovation Drive

San Jose, CA 95134

(408) 544-7000

http://www.altera.com

Applications Hotline:

(800) 800-EPLD

Customer Marketing:

(408) 544-7104

Literature Services:

lit_req@altera.com

stylized Altera logo, specific device designations, and all other words and logos that are identified as

trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera

Corporation in the U.S. and other countries. All other product or service names are the property of their

respective holders. Altera products are protected under numerous U.S. and foreign patents and pending

applications, mask work rights, and copyrights. Altera warrants performance of its semiconductor products

to current specifications in accordance with Altera’s standard warranty, but reserves the right to make changes

to any products and services at any time without notice. Altera assumes no responsibility or

liability arising out of the application or use of any information, product, or service described

herein except as expressly agreed to in writing by Altera Corporation. Altera customers are

advised to obtain the latest version of device specifications before relying on any published

information and before placing orders for products or services.

Altera Corporation

Advanced Help

Results for: EPC

33 part numbers found and 4 obsolete part numbers found

Configuration Device Family

Configuration Device Datasheet

Part Number Format

Configuration Device Literature

Buying Altera Devices

Part Number

Device

Pins & Package Temperature Speeds Options

EPC1LC20

EPC1

Pinout is in

datasheet

20 pin PLCC

8 pin PDIP

Commercial

( 0 to 85°C)

None

EPC1LI20

EPC1PC8

EPC1PI8

EPC1

Pinout is in

datasheet

Industrial

( -40 to 100°C)

EPC1

Pinout is in

datasheet

Commercial

( 0 to 85°C)

EPC1

Pinout is in

datasheet

8 pin PDIP

Industrial

( -40 to 100°C)

EPC2LC20

EPC2LI20

EPC2TC32

EPC2TI32

EPC2

Pinout is in

datasheet

20 pin PLCC

32 pin TQFP

Commercial

( 0 to 85°C)

EPC2

Pinout is in

datasheet

Industrial

( -40 to 100°C)

EPC2

Pinout is in

datasheet

Commercial

( 0 to 85°C)

EPC2

Pinout is in

datasheet

Industrial

( -40 to 100°C)

EPC1064VLC20 EPC1064V 20 pin PLCC

Commercial

( 0 to 85°C)

Pinout is in

datasheet

EPC1064VPC8 EPC1064V 8 pin PDIP

Commercial

( 0 to 85°C)

Pinout is in

datasheet

EPC1064VTC32 EPC1064V 32 pin TQFP

Commercial

( 0 to 85°C)

Pinout is in

datasheet

EPC1064LC20

EPC1064LI20

EPC1064 20 pin PLCC

Pinout is in

datasheet

Commercial

( 0 to 85°C)

EPC1064 20 pin PLCC

Pinout is in

datasheet

Industrial

( -40 to 100°C)

EPC1064PC8

EPC1064PI8

EPC1064TC32

EPC1213LC20

EPC1213LI20

EPC1213PC8

EPC1213PI8

EPC1441LC20

EPC1441LI20

EPC1441PC8

EPC1441PI8

EPC1441TC32

EPC1441TI32

EPC1064 8 pin PDIP

Pinout is in

datasheet

Commercial

( 0 to 85°C)

None

EPC1064 8 pin PDIP

Pinout is in

datasheet

Industrial

( -40 to 100°C)

EPC1064 32 pin TQFP

Pinout is in

datasheet

Commercial

( 0 to 85°C)

EPC1213 20 pin PLCC

Pinout is in

datasheet

Commercial

( 0 to 85°C)

EPC1213 20 pin PLCC

Pinout is in

datasheet

Industrial

( -40 to 100°C)

EPC1213 8 pin PDIP

Pinout is in

datasheet

Commercial

( 0 to 85°C)

EPC1213 8 pin PDIP

Pinout is in

datasheet

Industrial

( -40 to 100°C)

EPC1441 20 pin PLCC

Pinout is in

datasheet

Commercial

( 0 to 85°C)

EPC1441 20 pin PLCC

Pinout is in

datasheet

Industrial

( -40 to 100°C)

EPC1441 8 pin PDIP

Pinout is in

datasheet

Commercial

( 0 to 85°C)

EPC1441 8 pin PDIP

Pinout is in

datasheet

Industrial

( -40 to 100°C)

EPC1441 32 pin TQFP

Pinout is in

datasheet

Commercial

( 0 to 85°C)

EPC1441 32 pin TQFP

Pinout is in

datasheet

Industrial

( -40 to 100°C)

Enhanced Configuration Device Family

Enhanced Configuration Device Datasheet Configuration Device Literature

Part Number Format Buying Altera Devices

Part Number Device Pins & Package Temperature Speeds Options

EPC4QC100

EPC4QI100

EPC8QC100

EPC4 100 pin PQFP

Pinout

Commercial

( 0 to 85°C)

None

EPC4 100 pin PQFP

Pinout

Industrial

( -40 to 100°C)

EPC8 100 pin PQFP

Pinout

Commercial

( 0 to 85°C)

EPC8QI100

EPC8 100 pin PQFP

Pinout

Industrial

( -40 to 100°C)

None

EPC16QC100 EPC16 100 pin PQFP

Pinout

Commercial

( 0 to 85°C)

EPC16QI100 EPC16 100 pin PQFP

Pinout

Industrial

( -40 to 100°C)

EPC16UC88 EPC16 88 pin UBGA

Pinout

Commercial

( 0 to 85°C)

Your search for EPC found 4 obsolete part numbers.

Obsolete Part Numbers

Part Number Format

Buying Altera Devices

Last Order

Date

Last Ship

Date

Part Number

Replacement

Notes

EP22V10EPC-10

6/28/96

10/31/96

9/30/96

12/31/96

No direct

replacement

PDN 9516

EP22V10EPC-15

No direct

replacement

PDN 9516

EPC1213DM883B

(5962-9474501MPA)

No direct

replacement

"PDN 9513

PDN 9517"

EPC1213DM8

10/31/96

12/31/96

No direct

replacement

"PDN 9513

PDN 9517 "

EPC

webmaster@altera.com

Advanced Help

Please Give Us Feedback

EPC1064VTC32 [ROCHESTER]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E