ISL6235CA-T [ROCHESTER]
SWITCHING CONTROLLER, 345 kHz SWITCHING FREQ-MAX, PDSO24, PLASTIC, SSOP-24;型号: | ISL6235CA-T |
厂家: | Rochester Electronics |
描述: | SWITCHING CONTROLLER, 345 kHz SWITCHING FREQ-MAX, PDSO24, PLASTIC, SSOP-24 开关 光电二极管 |
文件: | 总15页 (文件大小:1121K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
ISL6235
TM
J une 2001
FN9029
Advanced Triple PWM Only Mode and
Dual Linear Power Controller for Portable
Applications
Features
• PWM Only Mode for Reduced Noise at Light Loads
• Provides Five Regulated Voltages
- +5V ALWAYS
- +3.3V ALWAYS
- +5V Main
The ISL6235 provides a highly integrated power control and
protection solution for five output voltages required in high-
performance notebook PC applications. The IC integrates
three fixed frequency pulse-width-modulation (PWM)
controllers and two linear regulators along with monitoring
and protection circuitry into a single 24 lead SSOP package.
- +3.3V Main
- +12V
• High Efficiency Over Wide Line and Load Range
- Synchronous Buck Converters on Main Outputs
The two PWM controllers that regulate the system main 5V
and 3.3V voltages are implemented with synchronous-
rectified buck converters. Synchronous rectification insures
high efficiency over a wide range of input voltage and load
variation. Efficiency is further enhanced by using the lower
• No Current-Sense Resistor Required
- Uses MOSFET’s r
DS(ON)
- Optional Current-Sense Resistor for More Precision
• Operates Directly From Battery 5.6 to 24V Input
• Input Undervoltage Lock-Out (UVLO)
MOSFET’s r
as the current sense element. Input
DS(ON)
voltage feed-forward ramp modulation, current-mode
control, and internal feed-back compensation provide fast
and stable handling of input voltage load transients
encountered in advanced portable computer chip sets.
• Excellent Dynamic Response
- Voltage Feed-Forward and Current-Mode Control
The third PWM controller is a boost converter that regulates
a resistor selectable output voltage of nominally 12V.
• Monitors Output Voltages
• Synchronous Converters Operate Out of Phase
Two internal linear regulators provide +5V ALWAYS and
+3.3V ALWAYS low current outputs required by the
notebook system controller.
• Separate Shut-Down Pins for Advanced Configuration and
Power Interface (ACPI) Compatibility
• 300kHz Fixed Switching Frequency on Main Outputs
• Thermal Shut-Down Protection
Ordering Information
TEMP.
PKG.
NO.
o
PART NUMBER RANGE ( C)
PACKAGE
Applications
ISL6235CA
-10 to 85
24 Ld SSOP
M24.15
•
Mobile PCs
IPM6220EVAL1
Evaluation Board
• Hand-Held Portable Instruments
• LCD PCs
Pinout
ISL6235 (SSOP)
• Cable Modems
• DSL Modems
TOP VIEW
VBATT
1
2
3
4
5
6
7
8
9
24 BOOT1
23 UGATE1
22 PHASE1
21 ISEN1
• Set Top Box
3.3V ALWAYS
BOOT2
Related Literature
• Application Note AN9915 (IPM6220)
UGATE2
PHASE2
5V ALWAYS
LGATE2
PGND2
20 LGATE1
19 PGND1
18 VSEN1
17 SDWN1
16 GATE3
15 VSEN3
14 GND
ISEN2
VSEN2 10
SDWN2 11
PGOOD 12
13 SDWNALL
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2001, All Rights Reserved
1
Block Diagram
VBATT
BOOT1
GND
VSEN3
GATE3
UVFLT
GATE LOGIC 1
HI
HGDR1
UGATE1
PHASE1
SHUTOFF
CLK
200ns
BOOST
CONTROLLER
POWER-ON
RESET (POR)
RAMP 2
RAMP 1
CLK1
CLK2
CLK1
POR
DEADTIME
PWM ON
VCC
REF
LGDR1
OVP1
LGATE1
PGND1
BOOT2
UGATE2
PHASE2
LO
GATE LOGIC 2
HI
HGDR2
VSEN1
SHUTOFF
OC COMP1
-
PWM
LATCH 1
DEADTIME
PWM ON
OC LOGIC1
VCC
VCC
EA1
-
LGATE2
PGND2
LGDR2
OVP2
-
Q
D
R
LO
REF
Q
<
VOLT-
SECOND
CLAMP
VSEN2
∑
-
R1 = 20K
OC COMP2
ISEN1
-
PWM
LATCH 2
OC
LOGIC2
-
VCC
2.8V
EA2
-
LGATE1
VBATT
LDO1
VSEN1
LGATE1
-
D Q
R
Q
REF
>
VOLT-
SECOND
CLAMP
∑
-
SDWN
POR
SDWN1
SDWN2
R1 = 20K
REFERENCE
ISEN2
AND
SDWN
REF
VCC
-
SOFT START
LDO2
UVFLT
OVP1
OUTPUT
VOLTAGE
SDWNALL
LGATE2
2.5V
LGATE2
MONITOR
OVP2
3.3V-ALWAYS
5V-ALWAYS
PGOOD
ISL6235
Simplified Power Sys tem Diagram
VBATT
VBATT
Q1
5V MAIN
3.3V ALWAYS
LINEAR
CONTROLLER
PWM1
CONTROLLER
Q2
5V ALWAYS
LINEAR
CONTROLLER
PGOOD
VOLTAGE,
ISL6235
12V BOOST
CURRENT
MONITORS
VBATT
Q1
3.3V MAIN
PWM3
PWM2
CONTROLLER
CONTROLLER
Q2
Typical Application
+V
BATT
PROCESSOR
5V MAIN
SDWN1
SDWN2
V
CORE
µP CORE
3.3V MAIN
V
I/O
5V ALWAYS
3.3V ALWAYS
12V
I/O
ISL6235
IPM6210
VID CODE
V
CLOCK
PGOOD
PGOOD
C8051
CLOCK
RESET
SDWN
PCM
CIA
ENABLE
SDWNALL
ON/OFF
3
ISL6235
I
Absolute Maximum Ratings
Thermal Information
o
Input Voltage, VBATT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +27.0V
Phase, ISEN and SDWNALL Pins. . . . . . . . . . .GND -0.3V to +27.0V
Boot and UGATE Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +33.0V
BOOT1, 2 with Respect to PHASE1, 2 . . . . . . . . . . . . . . . . . . . +6.5V
All Other Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6.5V
Thermal Resistance (Typical, Note 1)
θ
( C/W)
JA
SSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .
110
o
Maximum Junction Temperature (Plastic Package) . . . . . . . .150 C
o
o
Maximum Storage Temperature Range . . . . . . . . . -65 C to 150 C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300 C
o
(SSOP - Lead Tips Only)
Operating Conditions
Input Voltage, VBATT . . . . . . . . . . . . . . . . . . . . . . . . +5.6V to +24.0V
o
o
Ambient Temperature Range. . . . . . . . . . . . . . . . . . . . -10 C to85 C
o
o
Junction Temperature Range. . . . . . . . . . . . . . . . . . -10 C to 125 C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θ is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
JA
Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. Refer to Block and Simplified Power System
Diagrams, and Typical Application Schematic
PARAMETER
Input Quiescent Current
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
I
SDWN1 = SDWN2 = 5V, SDWNALL = Vin,
-
1.4
2.0
mA
CC
Outputs open circuited
Stand-by Current
I
SDWN1 = SDWN2 = 0V, SDWNALL = Vin,
-
300
-
µA
CCSB
Outputs open circuited
Shut-down Current
I
SDWNALL = 0V
Rising VBATT
-
4.3
-
<1.0
4.7
-
5.1
-
µA
V
CCSN
Input Undervoltage Lock Out
Input Undervoltage Lock Out
OSCILLATOR
UVLO
UVLO
VBATT, Hysteresis
300
mV
PWM1,2 Oscillator Frequency
REFERENCE AND SOFT START
Internal Reference Voltage
Reference Voltage Accuracy
F
V
255
300
345
kHz
c1,2
REF
-
-1.0
-
2.472
-
+1.0
-
V
%
-
SDWN1,SDWN2 Output Current During
Start-up
I
5
µA
SS
PWM1 CONVERTER, 5V Main
Output Voltage
V
-
-2
5.0
0.5
75
-
V
%
%
µA
%
%
OUT1
Line and Load Regulation
Undervoltage Shut-Down Level
Current Limit Threshold
Overvoltage Threshold
Maximum Duty Cycle
0.0 < IVOUT1 < 5.0A; 5.6V < VBATT < 22.0V
2µs delay, % Feedback Voltage at VSNS1 Pin
Current from ISNS1 Pin Through RSNS1
2µs delay, % Feedback Voltage at VSNS1 Pin
SDWN1>4.0V
+2
80
180
120
-
V
70
90
110
-
UV1
I
135
115
94
OC2
V
OVP1
DC
MAX
PWM2 CONVERTER, 3.3V Main
Output Voltage
VOUT2
-
-2
3.3
0.5
75
-
V
%
%
µA
%
%
Line and Load Regulation
Undervoltage Shut-Down Level
Current Limit Threshold
Overvoltage Threshold
Maximum Duty Cycle
0.0 < IVOUT2 < 5.0A; 5.6V<VBATT< 24.0V
2µs delay, % Feedback Voltage at VSNS2 Pin
Current from ISNS2 Pin Through RSNS2
2µs Delay, % Feedback Voltage at VSNS2 Pin
SDWN2 > 4.0V
+2
80
180
120
-
V
70
90
110
-
UV2
I
135
115
94
OC2
V
OVP2
DC
MAX
4
ISL6235
Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. Refer to Block and Simplified Power System
Diagrams, and Typical Application Schematic (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Internal Resistance to GND on VSNS2 Pin
R
-
66K
-
Ω
VSNS2
PWM1 and PWM2 CONTROLLER GATE DRIVERS
Upper Drive Pull-Up Resistance
Upper Drive Pull-Down Resistance
Lower Drive Pull-Up Resistance
Lower Drive Pull-Down Resistance
PWM 3 CONVERTER
R
R
-
-
-
-
5
4
6
5
12
10
9
Ω
Ω
Ω
Ω
2UGPUP
2UGPDN
R
2LGPUP
2LGPDN
R
8
12V Feedback Regulation Voltage
VSEN3
-
-
2.472
0.1
-
V
12V Feedback Regulation Voltage Input
Current
I
1.0
µA
VSEN3
Line and Load Regulation
Undervoltage Shut-Down Level
Overvoltage Threshold
0.0 < IVOUT3 < 120mA, 4.9V < 5VMain < 5.1V
2µs Delay, % Feedback Voltage at VSNS3 Pin
2µs Delay, % Feedback Voltage at VSNS3 Pin
-2
70
-
-
+2
80
%
%
V
75
UV3
V
115
100
33
120
115
-
%
OVP3
PWM3 Oscillator Frequency
Maximum Duty Cycle
F
85
-
kHz
%
c3
PWM 3 CONTROLLER GATE DRIVERS
Pull-Up Resistance
R3GPUP
R3GPDN
-
-
8
8
12
12
Ω
Ω
Pull-Down Resistance
5V AND 3.3V ALWAYS
Linear Regulator Accuracy
PWM1, 5V Output OFF (SDWN1 = 0V);
5.6V < VBATT < 22V; 0 < Iload < 50mA
-2.0
-3.3
0.5
1.0
+2.0
+2.0
%
%
5V ALWAYS Output Voltage Regulation
PWM1, 5V output ON (SDWN1 = 5V);
0 < Iload < 50mA
Maximum Output Current
Current Limit
Combined 5V ALWAYS and 3.3V ALWAYS
Combined 5V ALWAYS and 3.3V ALWAYS
50
-
-
-
-
-
mA
mA
%
100
180
75
5V ALWAYS Undervoltage Shut-Down
-
-
Bypass Switch r
PWM1, 5V output ON (SDWN1 = 5V)
1.3
Ω
DS(ON)
POWER GOOD AND CONTROL FUNCTIONS
Power Good Threshold for PWM1 and
PWM2 Output Voltages
-14
-12
-10
%
PGOOD Leakage Current
PGOOD Voltage Low
I
VPULLUP = 5.0V
IPGOOD = -4mA
-
-
-
-
-
-
-
-
-
-
1.0
µA
V
PGLKG
V
0.2
10
0.5
PGOOD
PGOOD Minimum Pulse Width
SDWN1, 2- Low (Off)
T
-
-
-
-
-
-
-
µs
V
PGmin
0.8
4.3
2.4
40
SDWN1, 2, - High (On)
SDWNALL - High (On)
V
V
SDWNALL - Low (Off)
SDWNALL
mV
o
Over-Temperature Shutdown
Over-Temperature Hysteresis
150
25
C
o
C
5
ISL6235
Functional Pin Des criptions
controllers. The PGOOD, overvoltage protection (OVP) and
VBATT (Pin 1)
undervoltage shutdown circuits use these signals to
determine output voltage status and/or to initiate
undervoltage shut down. The VSEN1 input is also switched
internally to the 5V ALWAYS output if the +5V Main output is
enabled.
Supplies all the power necessary to operate the chip. The IC
starts to operate when the voltage on this pin exceeds 4.7V
and stops operating when the voltage on this pin drops
below approximately 4.5V. Also provides battery voltage to
the oscillator for feed-forward rejection to input voltage
variations.
SDWNALL (Pin 13)
This pin provides enable/disable function for all outputs. The
chip is completely disabled when this pin is pulled to ground.
When this pin is pulled high, the 5V ALWAYS and 3.3
ALWAYS outputs are on and the other outputs are enabled.
The state of 5V Main and 3.3V Main outputs depend on the
voltage on SDWN1 and SDWN2 respectively. See Table 1.
3.3V ALWAYS (Pin 2)
Output of 3.3V ALWAYS linear regulator.
5V ALWAYS (Pin 6)
Output of 5V ALWAYS linear regulator or the +5V Main
output. If the +5V Main output is enabled, it is switched
internally from the VSEN1 pin to the 5V ALWAYS output.
This improves efficiency and reduces the power dissipation
in the controller.
SDWN1 (Pin 17)
This pin provides enable/disable function and soft-start for
the PWM1, 5V Main, output. The output is enabled when this
pin is high and SDWNALL is also high. The 5V output is held
off when the pin is pulled to the ground.
BOOT1, BOOT2 (Pins 24 and 3)
Power is supplied to the upper MOSFET drivers of PWM1
and PWM2 converters via the BOOT pins. Connect these
pins to the respective junctions of bootstrap capacitors with
the cathodes of the bootstrap diodes. Anodes of the
bootstrap diodes are connected to pin 6, 5V ALWAYS.
SDWN2 (Pin 11)
This pin provides enable/disable function and soft-start for
PWM2, 3.3V Main, output. The output is enabled when this
pin is high and SDWNALL is also high. The 3.3V output is
held off when the pin is pulled to the ground.
UGATE1, UGATE2 (Pins 23 and 4)
These pins provide the gate drive for the upper MOSFETs.
Connect UGATE pins to the respective PWM converter’s
upper MOSFET gate.
VSEN3 (Pin 15)
This input pin is the voltage feedback signal for PWM3, the
boost controller. The boost controller regulates this point to a
voltage divided level of 2.472 VDC. The PGOOD,
overvoltage protection (OVP) and undervoltage shutdown
circuits use this signal to determine output-voltage status
and/or to initiate undervoltage shut down.
PHASE1, PHASE2 (Pins 22 and 5)
The phase nodes are the junctions of the upper MOSFET
sources, output filter inductors, and lower MOSFET drains.
Connect the PHASE pins directly to the respective PWM
converter’s lower MOSFET drain.
This pin can also be used to independently disable the
PWM3 controller. Connect this pin to 5V ALWAYS if the
boost converter is not populated in your design.
ISEN1, ISEN2 (Pins 21 and 9)
These pins are used to monitor the voltage drop across the
lower MOSFETs for current feedback and current-limit
protection. For more precise current detection, these inputs
can be connected to optional current sense resistors placed
in series with the sources of the lower MOSFETs.
GATE3 (Pin 16)
This pin drives the gate of the boost MOSFET.
PGOOD (Pin 12)
PGOOD is an open drain output used to indicate the status of
the PWM converters’ output voltages. This pin is pulled low
when any of the outputs except PWM3 (12V) is not within -10%
of respective nominal voltages, or when PWM3 (12V) is not
within its undervoltage and overvoltage thresholds.
LGATE1, LGATE 2 (Pins 20 and 7)
These pins provide the gate drive for the lower MOSFETs.
Connect the lower MOSFET gate of each converter to the
corresponding pin.
PGND1, PGND2 (Pins 19 and 8)
GND (Pin 14)
These are the lower MOSFET gate drive return connection
for PWM1 and PWM2 converters, respectively. Tie each
lower MOSFET source directly to the corresponding pin.
Signal ground for the IC. All voltage levels are measured
with respect to this pin.
VSEN1, VSEN2 (Pins 18, 10)
These pins are connected to the main outputs and provide
the voltage feedback signal for the respective PWM
6
ISL6235
General Des cription
V
= 10.8V
IN
I
(2A/DIV.)
The ISL6235 addresses the system electronics power needs
of modern notebook and LCD PCs that require a fixed
frequency, PWM mode only, controller. The ISL6235 is
similar to the IPM6220A but without the Hysteretic mode of
operation. The IC integrates control circuits for two
L3.3V
5A
3.3V PHASE (10V/DIV.)
synchronous buck converters for 5V Main and 3.3V Main
buses, two linear regulators for 3.3V ALWAYS and 5V
ALWAYS, and a flexible boost converter, nominally 12V.
0 A, V
5A
I
(2A/DIV.)
L5V
The two synchronous converters operate out of phase to
substantially reduce the input-current ripple, minimizing input
filter requirements, minimizing battery heating and
prolonging battery life.
0 A, V
5V PHASE (10V/DIV.)
1µs/DIV.
The 12V boost controller uses a 100kHz clock derived from
the main clock. This controller uses leading edge modulation
with the maximum duty cycle limited to 33%.
FIGURE 1. OUT OF PHASE OPERATION
Current Sens ing and Current Limit Protection
The chip has three input control lines SDWN1, SDWN2 and
SDWNALL. These are provided for Advanced Configuration
and Power Interface (ACPI) compatibility. They turn on and
off all outputs, as well as provide independent control of the
3.3V Main and +5V Main outputs.
Both PWM converters use the lower MOSFET on-state
resistance, r
, as the current-sensing element. This
DS(ON)
technique eliminates the need for a current sense resistor
and the associated power losses. If more accurate current
protection is desired, current sense resistors may be used in
series with the lower MOSFETs’ source.
To maximize efficiency for the 5V Main and 3.3V Main outputs,
the current-sense technique is based on the lower MOSFET
To set the current limit, place a resistor, RSNS, between the
ISEN inputs and the drain of the lower MOSFET (or optional
current sense resistor). The required value of the RSNS
resistor is determined from the following equation:
r
DS(ON).
3.3V Main and 5V Main Architecture
These main outputs are generated from the unregulated
battery input by two independent synchronous buck
converters. The IC integrates all the components required
for output voltage setpoint and feedback compensation,
significantly reducing the number of external components,
saving board space and parts cost.
Rcs
135µA
Vo
Iocdc + ---------------------------------------- – 100
(EQ. 1)
-----------------
RSNS =
L × 2 × 300kHz
where Iocdc is the desired DC overcurrent limit; Rcs is either
the r of the lower MOSFET, or the value of the optional
DS(ON)
current-sense resistor, Vo is the output voltage and L is the
output inductor. Also, the value of Rcs should be specified
for the expected maximum operating temperature.
The buck PWM controllers employ a 300kHz fixed frequency
current-mode control scheme with input voltage feed-
forward ramp programming for better rejection of input
voltage variations.
The sensed voltage, and the resulting current out of the
ISEN pin through RSNS, is used for current feedback and
current limit protection. This is compared with an internal
current limit threshold. When a sampled value of the output
current is determined to be above the current limit
threshold, the PWM drive is terminated and a counter is
initiated. This limits the inductor current build-up and
essentially switches the converter into current-limit mode. If
an overcurrent is detected between 26µs to 53µs later, an
overcurrent shutdown is initiated. If during the 26µs to 53µs
period, an overcurrent is not detected, the counter is reset
and sampling continues as normal.
Figure 1 shows the out-of-phase operation for the 3.3V Main
and 5V Main outputs. The phase node is the junction of the
upper MOSFET, lower MOSFET and the output inductor.
The phase node is high when the upper MOSFET is
conducting and the inductor current rises accordingly. When
the phase node is low, the lower MOSFET is conducting and
the inductor current is ramping down as shown.
This current limit scheme has proven to be very robust in
applications like portable computers where fast inductor
current build-up is common due to a large difference
between input and output voltages and a low value of the
inductor.
7
ISL6235
Figure 2 shows the soft-start initiated by the SDWNALL pin
Gate Control Logic
being pulled high with the Vbatt input at 10.8V and the
resulting 3.3V Main and 5V Main outputs.
The gate control logic translates generated PWM control
signals into the MOSFET gate drive signals providing
necessary amplification, level shifting and shoot-through
protection. Also, it has functions that help optimize the IC
performance over a wide range of operational conditions.
Since MOSFET switching time can vary dramatically from
type to type and with the input voltage, the gate control logic
provides adaptive dead time by monitoring the gate-to-
source voltages of both upper and lower MOSFETs. The
lower MOSFET is not turned on until the gate-to-source
voltage of the upper MOSFET has decreased to less than
approximately 1 volt. Similarly, the upper MOSFET is not
turned on until the gate-to-source voltage of the lower
MOSFET has decreased to less than approximately 1 volt.
This allows a wide variety of upper and lower MOSFETs to
be used without a concern for simultaneous conduction, or
shoot-through.
V
= 10.8V
IN
SDWNALL,10V/DIV.
SDWN2, 2V/DIV.
3.3V
, 2V/DIV.
OUT
0V
0V
SDWN1, 2V/DIV.
5V
, 2V/DIV.
OUT
T0 T1
T2
T3
T4
3.3V Main and 5V Main Soft Start, Sequencing and
Stand-by
4ms/DIV.
FIGURE 2. SOFT START ON 3.3V AND 5V OUTPUTS
See Table 1 for the output voltage control algorithm. The 5V
Main and 3.3V Main converters are enabled if SDWN1 and
SDWN2 are high and SDWNALL is also high. The stand-by
mode is defined as a condition when SDWN1 and SDWN2
are low and the PWM converters are disabled but
SDWNALL is high (3.3V ALWAYS and 5V ALWAYS outputs
are enabled). In this power saving mode, only the low power
micro-controller and keyboard may be powered.
While the SDWNALL pin is held low, prior to T0, all outputs
are off. Pulling SDWNALL high enables the 3.3V ALWAYS
and 5V ALWAYS outputs. With the 3.3V Main and 5V Main
outputs enabled, at T1, the internal 5mA current sources
start charging the soft start capacitors on the SDWN1 and
SDWN2 pins. At T2 the outputs begin to rise and because
they both have the same value of soft-start capacitors,
0.022mF, they both reach regulation at the same time, T3.
The soft-start capacitors continue to charge and are
completely charged at T4.
TABLE 1. OUTPUT VOLTAGE CONTROL
3VAND5V
SDWNALL SDWN1 SDWN2 ALWAYS 5V MAIN 3V MAIN
0
1
1
1
1
X
0
1
0
1
X
0
0
1
1
OFF
ON
ON
ON
ON
OFF
OFF
ON
OFF
OFF
OFF
ON
12V Converter Architecture
The 12V boost converter generates its output voltage from
the 5V Main output. An external MOSFET, inductor, diode
and capacitor are required to complete the circuit. The
output signal is fed back to the controller via an external
resistive divider. The boost controller can be disabled by
connecting the VSEN3 pin to 5V ALWAYS.
OFF
ON
ON
Soft start of the 3.3V Main and 5V Main converters is
accomplished by means of capacitors connected from pins
SDWN1 and SDWN2 to ground. In conjunction with 5µA
internal current sources, they provide a controlled rise of the
3.3V Main and 5V Main output voltages. The value of the
soft-start capacitors can be calculated from the following
expression.
The control circuit for the 12V converter consists of a 3:1
frequency divider which drives a ramp generator and resets a
PWM latch as shown in Figure 3. The width of the CLK/3
pulses is equal to the period of the main clock, limiting the
duty cycle to 33%. The output of a non-inverting error
amplifier is compared with the rising ramp voltage. When the
ramp voltage becomes higher than the error signal, the PWM
comparator sets the latch and the output of the gate driver is
pulled high providing leading edge, voltage mode PWM. The
falling edge of the CLK/3 pulses resets the latch and pulls the
output of the gate driver low.
5µA × Tss
(EQ. 2)
Css = ----------------------------
3.5V
Where T is the desired soft-start time.
ss
By varying the values of the soft-start capacitors, it is possible
to provide sequencing of the main outputs at start-up.
8
ISL6235
controller or other peripherals. The combined current
VSEN3
GATE3
PWM
capability of these outputs is 50mA. When the 5V Main
output is greater than it’s undervoltage level, it is switched to
the 5V ALWAYS output via an internal 1.3Ω MOSFET
switch. Simultaneously, the 5V ALWAYS linear regulator is
disabled to prevent excessive power dissipation.
PWM
COMPARATOR
LATCH 3
EA3
-
-
Q
S
R
REF
RAMP
Q
CLK/3
DIVIDER
CLK
RAMP
GENERATOR
The rise time of the 5V ALWAYS is determined by the value
of the output capacitance on the 5V and 3.3V ALWAYS
outputs. The internal regulator is current limited to about
180mA, so the start up time is approximately:
3:1
CLK/3
CLK
5V
180mA
t
(EQ. 4)
-------------------
×
t = C
OUT
CLK/3
t
t
Where C
OUT
3.3V ALWAYS outputs.
is the sum of the capacitances on the 5V and
RAMP
VEA3
Power Good Status
GATE3
t
The ISL6235 monitors all the output voltages except for the
3.3V ALWAYS. A single power-good signal, PGOOD, is
issued when soft-start is completed and all monitored
outputs are within 10% of their respective set points. After
the soft-start sequence is completed, undervoltage
protection latches the chip off when any of the monitored
outputs drop below 75% of its set point.
FIGURE 3. 12V BOOST OPERATION
The 33% maximum duty cycle of the converter guarantees
discontinuous inductor current and unconditional stability
over all operating conditions.
The boost converter with the limited duty cycle and
discontinuous inductor current can deliver to the load a
limited amount of power before the output voltage starts to
drop. When the duty cycle has reached Dmax, the control
loop is operating open circuit and the output voltage varies
with the output load resistance, Ro, as given by:
A ‘soft-crowbar’ function is implemented for an overvoltage
on the 3.3V Main or 5V Main outputs. If the output voltage
goes above 115% of their nominal output level, the upper
MOSFET is turned off and the lower MOSFET is turned on.
This ‘soft-crowbar’ condition will be maintained until the
output voltage returns to the regulation window and then
normal operation will continue.
Ro
(EQ. 3)
Vo= Vin × Dmax ------------------
2(LxF)
This ‘soft-crowbar’ and monitoring of the output, prevents the
output voltage from ringing negative as the inductor current
flows in the ‘reverse’ direction through the lower MOSFET
and output capacitors.
Where Vin is the 5V Main voltage, Dmax = 0.33, L is the
value of the boost inductor, L3, and F = 100kHz. This
provides automatic output current limiting. When the
maximum duty cycle has been reached and for a given
inductor, a further reduction in Ro by one-half will pull the
output voltage down to 0.707 of nominal and cause an
undervoltage condition.
Over-Temperature Protection
The IC incorporates an over-temperature protection circuit
that shuts all the outputs down when the die temperature
o
exceeds 150 C. Normal operation is automatically restored
o
when the die temperature cools to 125 C.
The 12V converter starts to operate at the same time as the
5V Main converter. The rising voltage on the 5V Main output
and the 33% duty cycle limit provides a similar soft-start, as
the 5V Main, for the 12V output.
Component Selection Guidelines
Output Capacitor Selection
The output capacitors for each output have unique
requirements. In general, the output capacitors should be
selected to meet the dynamic regulation requirements
including ripple voltage and load transients.
3V ALWAYS, 5V ALWAYS Linear
Regulators
The 3.3V ALWAYS and 5V ALWAYS outputs are derived
from the battery voltage and are the first voltages available
in the notebook when power on is initiated. The 5V ALWAYS
output is generated directly from the battery voltage by a
linear regulator. It is used to power the system micro-
controller and to internally power the chip and the gate
drivers. The 3.3V ALWAYS output is generated from the 5V
ALWAYS output and may be used to power the keyboard
3.3V Main and 5V Main PWM Output Capacitors
Selection of the output capacitors is also dependent on the
output inductor so some inductor analysis is required to
select the output capacitors.
9
ISL6235
One of the parameters limiting the converter’s response to a
side of the internal zero and still contribute to increased
load transient is the time required for the inductor current to
slew to it’s new level. Given a sufficiently fast control loop
design, the ISL6235 will provide either 0% or 94% duty cycle
in response to a load transient. The response time is the
time interval required to slew the inductor current from an
initial current value to the load current level. During this
interval the difference between the inductor current and the
transient current level must be supplied by the output
capacitor(s). Minimizing the response time can minimize the
output capacitance required. Also, if the load transient rise
time is slower than the inductor response time, as in a hard
drive or CD drive, this reduces the requirement on the output
capacitor.
phase margin of the control loop. Therefore:
1
C
= -------------------------------------------
(EQ. 7)
OUT
2 × π × ESR × f
Z
In conclusion, the output capacitors must meet three criteria:
1. They must have sufficient bulk capacitance to sustain the
output voltage during a load transient while the output
inductor current is slewing to the value of the load
transient
2. The ESR must be sufficiently low to meet the desired
output voltage ripple due to the output inductor current,
and
3. The ESR zero should be placed, in a rather large range,
to provide additional phase margin.
The maximum capacitor value required to provide the full,
rising step, transient load current during the response time of
the inductor is:
3.3V ALWAYS and 5V ALWAYS Output Capacitors
The output capacitors for the linear regulators insure stability
and provide dynamic load current. The 3.3V ALWAYS and
the 5V ALWAYS linear regulators should have, as a
minimum, 10µF capacitors on their outputs.
L
× I
I
O
TRAN
TRAN
--------------------------------------------- --------------------
C
=
×
(EQ. 5)
OUT
(V – V
) × 2 DV
OUT
IN
OUT
Where: C
OUT
is the output capacitor(s) required, L is the
O
3.3V Main and 5V Main PWM Output Inductor
Selection
output inductor, I
is the transient load current step, V
TRAN
is the input voltage, V
IN
is
is output voltage, and ∆V
OUT
OUT
The PWM converters require output inductors. The output
inductor is selected to meet the output voltage ripple
requirements. The inductor value determines the converter’s
ripple current and the ripple voltage is a function of the ripple
current and output capacitor(s) ESR. The ripple voltage
expression is given in the capacitor selection section and the
ripple current is approximated by the following equation:
the drop in output voltage allowed during the load transient.
High frequency capacitors initially supply the transient
current and slow the load rate-of-change seen by the bulk
capacitors. The bulk filter capacitor values are generally
determined by the ESR (Equivalent Series Resistance) and
voltage rating requirements as well as actual capacitance
requirements. The output voltage ripple is due to the
inductor ripple current and the ESR of the output capacitors
as defined by:
V
– V
V
OUT
IN
OUT
(EQ. 8)
------------------------------- ---------------
∆I
=
×
L
F
× L
V
IN
S
(EQ. 6)
V
= ∆I × ESR
L
Input Capacitor Selection
RIPPLE
The important parameters for the bulk input capacitor(s) are
the voltage rating and the RMS current rating. For reliable
operation, select bulk input capacitors with voltage and
current ratings above the maximum input voltage and largest
RMS current required by the circuit. The capacitor voltage
rating should be at least 1.25 times greater than the
maximum input voltage and 1.5 times is a conservative
guideline.
where, ∆I is calculated in the Inductor Selection section.
L
High frequency decoupling capacitors should be placed as
close to the power pins of the load as physically possible. Be
careful not to add inductance in the circuit board wiring that
could cancel the usefulness of these low inductance
components. Consult with the manufacturer of the load
circuitry for specific decoupling requirements.
The ac RMS input current varies with load as shown in
Figure 4. Depending on the specifics of the input power and
it’s impedance, most (or all) of this current is supplied by the
input capacitor(s). Figure 4 also shows the advantage of
having the PWM converters operating out of phase. If the
converters were operating in phase, the combined RMS
current would be the algebraic sum, which is a much larger
value as shown. The combined out-of-phase current is the
square root of the sum of the square of the individual
reflected currents and is significantly less than the combined
in-phase current.
Use only specialized low-ESR capacitors intended for
switching-regulator applications, at 300kHz, for the bulk
capacitors. In most cases, multiple electrolytic capacitors of
small case size perform better than a single large case
capacitor.
The stability requirement on the selection of the output
capacitor is that the ‘ESR zero’, f , be between 1.2kHz and
Z
30kHz. This range is set by an internal, single compensation
zero at 6kHz. The ESR zero can be a factor of five on either
10
ISL6235
The maximum value of the boost capacitor, Comax that will
5
4.5
4
charge to 9V in the soft start time, T , is shown below,
SS
where L is the value of the boost inductor.
Tss
IN-PHASE
OUT-OF-PHASE
5V
3.5
3
---------
(EQ. 11)
Comax =
× 0.115µF
L
2.5
2
The output capacitor ESR and the boost inductor ripple
current determines the output voltage ripple. The ripple
voltage is given by:
1.5
1
3.3V
0.5
0
(EQ. 12)
V
= ∆I × ESR
L
RIPPLE
0
1
2
3
4
5
3.3V AND 5V LOAD CURRENT
and the maximum ripple current, ∆I is given by:
INPUT CAPACITANCE RMS CURRENT AT VIN = 10.8V
L,
5V
L
(EQ. 13)
-------
FIGURE 4. INPUT RMS CURRENT VS LOAD
∆I
=
× 3.3µ
L
Use a mix of input bypass capacitors to control the voltage
ripple across the MOSFETs. Use ceramic capacitors for the
high frequency decoupling and bulk capacitors to supply the
RMS current. Small ceramic capacitors can be placed very
close to the upper MOSFET to suppress the voltage induced
in the parasitic circuit impedances.
where L is the boost inductor calculated above, 5V is the
boost input voltage and 3.3µ is the maximum on time for the
boost MOSFET.
MOSFET Cons iderations
The logic level MOSFETs are chosen for optimum efficiency
given the potentially wide input voltage range and output
power requirements. Two N-channel MOSFETs are used in
each of the synchronous-rectified buck converters for the
PWM1 and PWM2 outputs. These MOSFETs should be
For board designs that allow through-hole components, the
Sanyo OS-CON
series offer low ESR and good
TM
temperature performance.
For surface mount designs, solid tantalum capacitors can be
used, but caution must be exercised with regard to the
capacitor surge current rating. These capacitors must be
capable of handling the surge-current at power-up. The TPS
series available from AVX is surge current tested.
selected based upon r
and thermal management considerations.
, gate supply requirements,
DS(ON)
The power dissipation includes two loss components;
conduction loss and switching loss. These losses are
distributed between the upper and lower MOSFETs
according to duty cycle (see the following equations). The
conduction losses are the main component of power
dissipation for the lower MOSFETs. Only the upper
MOSFET has significant switching losses, since the lower
device turns on and off into near zero voltage.
2
+12V Boos t Converter Inductor Selection
The inductor value is chosen to provide the required output
power to the load.
2
2
Vinmin × Dmax × Ro
(EQ. 9)
Lmax= ----------------------------------------------------------------
2
2 × Vo × F
I
× r
× V
I
× V × t
× F
SW S
O
DS(ON)
OUT
O
IN
P
= ------------------------------------------------------------ + ----------------------------------------------------
UPPER
V
2
where, V
inmin
is the minimum input voltage, 4.9V; D
=
max
IN
(EQ. 14)
1/3, the maximum duty cycle; R is the minimum load
2
o
I
× r
× (V – V
)
OUT
O
DS(ON)
IN
resistance; V is the nominal output voltage and F is the
o
switching frequency, 100kHz.
P
= --------------------------------------------------------------------------------
LOWER
V
IN
Or, for L in uH, the maximum output current is nominally:
The equations assume linear voltage-current transitions and
do not model power loss due to the reverse-recovery of the
lower MOSFET’s body diode. The gate-charge losses are
dissipated by the ISL6235 and do not heat the MOSFETs.
However, a large gate-charge increases the switching time,
13.88
L × Vo
Imax= ----------------
(EQ. 10)
+12V Boos t Converter Output Capacitor Selection
t
which increases the upper MOSFET switching losses.
SW
The total capacitance on the 12V output should be chosen
appropriately, so that the output voltage will be higher than
the undervoltage limit (9V) when the 5V Main soft-start time
has elapsed. This will avoid triggering of the 12V
undervoltage protection.
Ensure that both MOSFETs are within their maximum
junction temperature at high ambient temperature by
calculating the temperature rise according to package
thermal-resistance specifications.
11
ISL6235
Layout Cons iderations
Small Components Signal Layout Cons iderations
MOSFETs switch very fast and efficiently. The speed with
which the current transitions from one device to another
causes voltage spikes across the interconnecting impedances
and parasitic circuit elements. The voltage spikes can
degrade efficiency, radiate noise into the circuit, and lead to
device overvoltage stress. Careful component layout and
printed circuit design minimizes the voltage spikes in the
converter. Consider, as an example, the turn-off transition of
one of the upper PWM MOSFETs. Prior to turn-off, the upper
MOSFET is carrying the full load current. During the turn-off,
current stops flowing in the upper MOSFET and is picked up
by the lower MOSFET. Any inductance in the switched current
path generates a voltage spike during the switching interval.
Careful component selection, tight layout of the critical
components, and short, wide circuit traces minimize the
magnitude of voltage spikes. See the Application Note for the
evaluation board component placement and the printed circuit
board layout details.
1. The VSNS1 and VSNS2 inputs should be bypassed with
a 1.0µF capacitor close to their respective IC pins.
2. A ‘T’ filter consisting of a ‘split’ RSNS and a small, 100pF,
capacitor as shown in Figure 5, may be helpful in
reducing noise coupling into the ISEN input. For example,
if the calculated value of RSNS1 is 2.2KΩ, dividing it as
shown with a 100pF capacitor provides filtering without
changing the current limit set point. For any calculated
value of RSNS, keep the value of the R9 portion to
approximately 200Ω, and the remainder of the
resistance in the R19 position. The 200Ω resistor and
100pF capacitor provide effective filtering for noise
above 8MHz.
This filter configuration may be helpful on both the 3.3V and
5V Main outputs.
RSNS = R19 + R9
R19
2K
R9
200
ISEN1
FROM PHASE
NODE
C12
There are two sets of critical components in a DC-DC
converter using an ISL6235 controller. The switching power
components are the most critical because they switch large
amounts of energy, and as such, they tend to generate
equally large amounts of noise. The critical small signal
components are those connected to sensitive nodes or
those supplying critical bias currents.
100pF
FIGURE 5. NOISE FILTER FOR ISEN1 INPUT
3. The bypass capacitors for VBATT and the soft-start
capacitors, C
and C should be located close to
SS1
SS2
their connecting pins on the control IC. Minimize any
leakage current paths from SDWN1 and SDWN2 nodes,
since the internal current source is only 5mA.
Power Components Layout Cons iderations
The power components and the controller IC should be
placed first. Locate the input capacitors, especially the high-
frequency ceramic decoupling capacitors, close to the power
MOSFETs. Locate the output inductor and output capacitors
between the MOSFETs and the load. Locate the PWM
controller close to the MOSFETs.
4. Refer to the Application Note for a recommended
component placement and interconnections.
Figure 6 shows an application circuit of a power supply for a
notebook PC microprocessor system. The power supply
provides +5V ALWAYS, +3.3V ALWAYS, +5.0V, +3.3V, and
12V from +5.6-22V
battery voltage. For detailed
DC
Insure the current paths from the input capacitors to the
MOSFETs, to the output inductors and output capacitors are
as short as possible with maximum allowable trace widths.
information on the circuit, including a Bill of Materials and
circuit board description, see Application Note AN9915. Also
see Intersil’s web site (www.intersil.com) for the latest
information.
A multi-layer printed circuit board is recommended. Dedicate
one solid layer for a ground plane and make all critical
component ground connections with vias to this layer.
Dedicate another solid layer as a power plane and break this
plane into smaller islands of common voltage levels. The
power plane should support the input power and output power
nodes. Use copper filled polygons on the top and bottom
circuit layers for the phase nodes, but do not unnecessarily
oversize these particular islands. Since the phase nodes are
subjected to very high dV/dt voltages, the stray capacitor
formed between these islands and the surrounding circuitry
will tend to couple switching noise. Use the remaining printed
circuit layers for small signal wiring. The wiring traces from the
control IC to the MOSFET gate and source should be sized to
carry 2A peak currents.
12
ISL6235
+5.6-22V
IN
C4
C3, 6, 10
56µF
3x1µF
GND
D2
BAT54WT1
VBATT
1
+3.3V ALWAYS
BOOT1
(50mA)
3.3V ALWAYS
5V ALWAYS
24
2
6
+
C2
C9
10µF
Q3
0.15µF
UGATE1
PHASE1
+5V ALWAYS
(50mA)
23
22
HUF76112SK8
L4
R9, 19
+
L2
ISEN1
C1
2.7µH
21
D1
BAT54WT1
+5V
(5A)
100µF
2.2K
8.2µH
ISL6235
BOOT2
+
3
C21, 32
2x330µF
LGATE1
PGND1
Q5
20
Q2
L3
HUF76112SK8
HUF76112SK8
6.8µH
C7
+
19
UGATE2
PHASE2
0.15µF
4
5
C36
22µF
+3.3V
(5A)
L1
R10, 11
2.2K
VSEN1
GATE3
ISEN2
D3
18
16
9
8.2µH
+
Q5
HUF76112SK8
C24, 33
+
R14
97.6K
C22
LGATE2
PGND2
2x47µF
Q4
7
8
330µF
HUF76112SK8
R13
24.9K
VSEN3
VSEN2
SDWN2
15
10
11
SDWN1
17
C16
C17
0.022µF
0.022µF
SDWNALL
PGOOD
12
13
14
GND
FIGURE 6. APPLICATIONS CIRCUIT
13
ISL6235
Shrink Small Outline Plas tic Packages (SSOP)
M24.15
N
24 LEAD THIN SHRINK NARROW BODY SMALL OUTLINE
PLASTIC PACKAGE
INDEX
AREA
0.25(0.010)
M
B M
H
E
INCHES
MIN
MILLIMETERS
GAUGE
PLANE
-B-
SYMBOL
MAX
0.069
0.010
0.061
0.012
0.010
0.344
0.157
MIN
1.35
0.10
-
MAX
1.75
0.25
1.54
0.30
0.25
8.74
3.98
NOTES
A
A1
A2
B
0.053
0.004
-
-
1
2
3
-
L
-
0.25
0.010
SEATING PLANE
A
0.008
0.007
0.337
0.150
0.20
0.18
8.55
3.81
9
-A-
o
D
h x 45
C
D
E
-
3
-C-
α
4
A2
e
A1
e
0.025 BSC
0.635 BSC
-
C
B
0.10(0.004)
H
h
0.228
0.0099
0.016
0.244
0.0196
0.050
5.80
0.26
0.41
6.19
0.49
1.27
-
0.17(0.007) M
C
A M B S
5
L
6
NOTES:
N
α
24
24
7
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2
of Publication Number 95.
o
o
o
o
0
8
0
8
-
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
Rev. 0 12/00
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.25mm (0.010 inch)
per side.
5. The chamfer on the body is optional. If it is not present, a visual in-
dex feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “B” does not include dambar protrusion. Allowable dam-
bar protrusion shall be 0.10mm (0.004 inch) total in excess of “B”
dimension at maximum material condition.
10. Controlling dimension: INCHES. Converted millimeter dimensions
are not necessarily exact.
All Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at website www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice.
Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. How-
ever, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use.
No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site www.intersil.com
14
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