ISL8483IB [ROCHESTER]
LINE TRANSCEIVER, PDSO8, PLASTIC, MS-012AA, SOIC-8;
| 型号： | ISL8483IB |
| 厂家： | 
Rochester Electronics |
| 描述： | LINE TRANSCEIVER, PDSO8, PLASTIC, MS-012AA, SOIC-8 驱动 光电二极管 接口集成电路 驱动器 |
| 文件： | 总17页 (文件大小：1257K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISL8483, ISL8485, ISL8488,
ISL8489, ISL8490, ISL8491
®
Data Sheet
February 28, 2006
FN6046.8
5V, Low Power, High Speed or Slew Rate
Limited, RS-485/RS-422 Trans ceivers
Features
• Specified for 10% Tolerance Supplies
The Intersil RS-485/RS-422 devices are BiCMOS 5V
powered, single transceivers that meet both the RS-485 and
RS-422 standards for balanced communication. Unlike
competitive devices, this Intersil family is specified for 10%
tolerance supplies (4.5V to 5.5V).
• Class 3 ESD Protection (HBM) on all Pins. . . . . . . . >7kV
• High Data Rates. . . . . . . . . . . . . . . . . . . . . . up to 5Mbps
• Slew Rate Limited Versions for Error Free Data
Transmission at 250kbps (ISL8483, ISL8488, ISL8489)
The ISL8483, ISL8488, and ISL8489 utilize slew rate limited
drivers which reduce EMI, and minimize reflections from
improperly terminated transmission lines, or unterminated
stubs in multidrop and multipoint applications.
• Single Unit Load Allows up to 32 Devices on the Bus
• 1nA Low Current Shutdown Mode (ISL8483)
• Low Quiescent Current:
- 160µA (ISL8483, ISL8488, ISL8489)
- 500µA (ISL8485, ISL8490, ISL8491)
Data rates up to 5Mbps are achievable by using the
ISL8485, ISL8490, or ISL8491, which feature higher slew
rates.
• -7V to +12V Common Mode Input Voltage Range
• Three State Rx and Tx Outputs (Except ISL8488,
ISL8490)
All devices present a “single unit load” to the RS-485 bus,
which allows up to 32 transceivers on the network.
• 30ns Propagation Delays, 5ns Skew (ISL8485, ISL8490,
ISL8491)
Receiver (Rx) inputs feature a “fail-safe if open” design,
which ensures a logic high Rx output if Rx inputs are
floating.
• Full Duplex and Half Duplex Pinouts
Driver (Tx) outputs are short circuit protected, even for
voltages exceeding the power supply voltage. Additionally,
on-chip thermal shutdown circuitry disables the Tx outputs to
prevent damage if power dissipation becomes excessive.
• Operate from a Single +5V Supply (10% Tolerance)
• Current Limiting and Thermal Shutdown for driver
Overload Protection
• Pb-Free Plus Anneal Available (RoHS Compliant)
The ISL8488 - 91 are configured for full duplex (separate Rx
input and Tx output pins) applications. The ISL8488 and
ISL8490 are offered in space saving 8 lead packages for
applications not requiring Rx and Tx output disable functions
(e.g., point-to-point). Half duplex configurations (ISL8483,
ISL8485) multiplex the Rx inputs and Tx outputs to allow
transceivers with Rx and Tx disable functions in 8 lead
packages.
Applications
• Factory Automation
• Security Networks
• Building Environmental Control Systems
• Industrial/Process Control Networks
• Level Translators (e.g., RS-232 to RS-422)
• RS-232 “Extension Cords”
TABLE 1. SUMMARY OF FEATURES
NO. OF DEVICES DATARATE SLEW-RATE RECEIVER/
PART
NUMBER
HALF/FULL
DUPLEX
QUIESCENT LOW POWER
PIN
ALLOWED ON BUS
(Mbps)
0.25
5
LIMITED?
DRIVER ENABLE?
I
(µA) SHUTDOWN? COUNT
CC
160
ISL8483
ISL8485
ISL8488
ISL8489
ISL8490
ISL8491
Half
Half
Full
Full
Full
Full
32
32
32
32
32
32
Yes
Yes
Yes
No
Yes
No
No
No
No
No
8
8
No
500
160
160
500
500
0.25
0.25
5
Yes
8
Yes
Yes
No
14
8
No
5
No
Yes
14
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003, 2005, 2006. All Rights Reserved.
All other trademarks mentioned are the property of their respective owners.
ISL8483, ISL8485, ISL8488, ISL8489, ISL8490, ISL8491
Ordering Information
PART NUMBER
PART MARKING
TEMP. RANGE (°C)
PACKAGE
8 Ld PDIP* (Pb-free)
8 Ld SOIC
PKG. DWG. #
E8.3
ISL8483CPZ (Note)
ISL8483CPZ
-40 to 85
ISL8483IB
8483IB
-40 to 85
M8.15
M8.15
M8.15
M8.15
E8.3
ISL8483IBZ (Note)
ISL8483IB-T
8483IBZ
8483IB
-40 to 85
8 Ld SOIC (Pb-free)
8 Ld SOIC Tape and Reel
ISL8483IBZ-T (Note)
ISL8483IP
8483IBZ
ISL8483IP
ISL8483IPZ
8485CB
8 Ld SOIC Tape and Reel (Pb-free)
-40 to 85
-40 to 85
8 Ld PDIP
ISL8483IPZ (Note)
ISL8485CB
8 Ld PDIP* (Pb-free)
8 Ld SOIC
E8.3
0 to 70
M8.15
M8.15
M8.15
M8.15
E8.3
ISL8485CBZ (Note)
ISL8485CB-T
8485CBZ
8485CB
0 to 70
8 Ld SOIC(Pb-free)
8 Ld SOIC Tape and Reel
ISL8485CBZ-T (Note)
ISL8485CP
8485CBZ
ISL8485CP
ISL8485CPZ
8485IB
8 Ld SOIC Tape and Reel (Pb-free)
0 to 70
0 to 70
8 Ld PDIP
ISL8485CPZ (Note)
ISL8485IB
8 Ld PDIP* (Pb-free)
8 Ld SOIC
E8.3
-40 to 85
M8.15
M8.15
M8.15
M8.15
E8.3
ISL8485IBZ (Note)
ISL8485IB-T
8485IBZ
8485IB
-40 to 85
8 Ld SOIC (Pb-free)
8 Ld SOIC Tape and Reel
ISL8485IBZ-T (Note)
ISL8485IP
8485IBZ
ISL8485IP
ISL8485IPZ
8488IB
8 Ld SOIC Tape and Reel (Pb-free)
-40 to 85
-40 to 85
8 Ld PDIP
ISL8485IPZ (Note)
ISL8488IB
8 Ld PDIP* (Pb-free)
8 Ld SOIC
E8.3
-40 to 85
M8.15
M8.15
M8.15
M8.15
E8.3
ISL8488IBZ (Note)
ISL8488IB-T
8488IBZ
8488IB
-40 to 85
8 Ld SOIC (Pb-free)
8 Ld SOIC Tape and Reel
ISL8488IBZ-T (Note)
ISL8488IP
8488IBZ
ISL8488IP
ISL8488IPZ
ISL8489IB
ISL8489IB
ISL8489IP
8490IB
8 Ld SOIC Tape and Reel (Pb-free)
-40 to 85
-40 to 85
8 Ld PDIP
ISL8488IPZ (Note)
ISL8489IB
8 Ld PDIP* (Pb-free)
14 Ld SOIC
E8.3
-40 to 85
M14.15
M14.15
E14.3
M8.15
M8.15
M8.15
M8.15
E8.3
ISL8489IB-T
14 Ld SOIC Tape and Reel
-40 to 85
ISL8489IP
14 Ld PDIP
ISL8490IB
-40 to 85
8 Ld SOIC
ISL8490IBZ (Note)
ISL8490IB-T
8490IBZ
8490IB
-40 to 85
8 Ld SOIC (Pb-free)
8 Ld SOIC Tape and Reel
ISL8490IBZ-T (Note)
ISL8490IP
8490IBZ
ISL8490IP
ISL8491IB
8491IBZ
ISL8491IB
8491IBZ
ISL8491IP
8 Ld SOIC Tape and Reel (Pb-free)
-40 to 85
-40 to 85
8 Ld PDIP
ISL8491IB
14 Ld SOIC
M14.15
M14.15
M14.15
M14.15
E14.3
ISL8491IBZ (Note)
ISL8491IB-T
-40 to 85
14 Ld SOIC (Pb-free)
14 Ld SOIC Tape and Reel
ISL8491IBZ-T (Note)
ISL8491IP
14 Ld SOIC Tape and Reel (Pb-free)
-40 to 85 14 Ld PDIP
*Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
FN6046.8
2
February 28, 2006
ISL8483, ISL8485, ISL8488, ISL8489, ISL8490, ISL8491
Pinouts
ISL8483, ISL8485 (PDIP, SOIC)
ISL8488, ISL8490 (PDIP, SOIC)
ISL8489, ISL8491 (PDIP, SOIC)
TOP VIEW
TOP VIEW
TOP VIEW
NC
RO
1
2
3
4
5
6
7
14 V
CC
V
1
2
3
4
8
7
6
5
A
B
Z
RO
RE
DE
DI
1
2
3
4
8
7
6
5
V
CC
CC
R
D
R
13 NC
12 A
11 B
10 Z
RO
DI
B/Z
R
D
RE
A/Y
GND
DE
D
GND
Y
DI
GND
GND
9
8
Y
NC
Truth Tables
RECEIVING
INPUTS
TRANSMITTING
OUTPUT
INPUTS
OUTPUTS
RE
DE
DE
A-B
RO
RE
X
DE
1
DI
1
Z
0
Y
Half Duplex Full Duplex
1
0
0
0
0
1
1
0
0
0
0
1
X
X
X
0
≥ +0.2V
≤ -0.2V
1
0
X
1
0
1
0
0
X
X
High-Z
High-Z *
High-Z
Inputs Open
1
1
0
High-Z *
X
X
High-Z *
High-Z
*Shutdown Mode for ISL8483 (see Note 7)
1
*Shutdown Mode for ISL8483 (see Note 7)
Pin Des criptions
PIN
FUNCTION
RO
RE
DE
DI
Receiver output: If A > B by at least 0.2V, RO is high; If A < B by 0.2V or more, RO is low; RO = High if A and B are unconnected (floating).
Receiver output enable. RO is enabled when RE is low; RO is high impedance when RE is high.
Driver output enable. The driver outputs, Y and Z, are enabled by bringing DE high. They are high impedance when DE is low.
Driver input. A low on DI forces output Y low and output Z high. Similarly, a high on DI forces output Y high and output Z low.
GND
A/Y
B/Z
A
Ground connection.
Noninverting receiver input and noninverting driver output. Pin is an input (A) if DE = 0; pin is an output (Y) if DE = 1.
Inverting receiver input and inverting driver output. Pin is an input (B) if DE = 0; pin is an output (Z) if DE = 1.
Noninverting receiver input.
Inverting receiver input.
B
Y
Noninverting driver output.
Inverting driver output.
Z
V
System power supply input (4.5V to 5.5V).
No Connection.
CC
NC
FN6046.8
3
February 28, 2006
ISL8483, ISL8485, ISL8488, ISL8489, ISL8490, ISL8491
Typical Operating Circuits
ISL8483, ISL8485
ISL8488, ISL8490
ISL8489, ISL8491
+5V
+5V
+
+
0.1µF
0.1µF
8
8
V
CC
V
CC
RO
1
2
4
DI
R
D
RE
DE
R
T
R
3
2
T
7
6
B/Z
A/Y
DE
RE
7
6
B/Z
A/Y
3
4
DI
1
RO
R
D
GND
GND
5
5
+5V
+5V
+
+
0.1µF
0.1µF
1
1
V
CC
V
CC
R
A
B
8
7
Y
Z
T
5
6
2
3
RO
DI
3
2
DI
R
D
R
6
5
Z
Y
T
B
A
7
8
RO
R
D
GND
GND
4
4
+5V
+5V
+
+
0.1µF
0.1µF
14
14
V
CC
V
CC
R
A
B
12
11
Y
Z
T
9
DI
2
5
RO
R
D
10
3
4
RE
DE
4
3
DE
RE
R
10
9
Z
Y
T
B
A
11
12
RO
5
DI
2
R
D
GND
6, 7
GND
6, 7
FN6046.8
4
February 28, 2006
ISL8483, ISL8485, ISL8488, ISL8489, ISL8490, ISL8491
Absolute Maximum Ratings
Thermal Information
V
to Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V
Thermal Resistance (Typical, Note 1)
θJA (°C/W)
CC
Input Voltages
DI, DE, RE . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to (V
Input/Output Voltages
A, B, Y, Z . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -8V to +12.5V
RO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to (V
Short Circuit Duration
Y, Z. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous
ESD Rating
HBM (Per MIL-STD-883, Method 3015.7) . . . . . . . . . . . . . . >7kV
8 Ld SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . .
8 Ld PDIP Package* . . . . . . . . . . . . . . . . . . . . . . . .
14 Ld SOIC Package . . . . . . . . . . . . . . . . . . . . . . . .
14 Ld PDIP Package . . . . . . . . . . . . . . . . . . . . . . . .
Moisture Sensitivity (see Technical Brief TB363)
All Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Level 1
Maximum Junction Temperature (Plastic Package) . . . . . . . 150°C
Maximum Storage Temperature Range . . . . . . . . . .-65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300°C
(SOIC - Lead Tips Only)
170
140
120
100
+0.5V)
CC
+0.5V)
CC
*Pb-free PDIPs can be used for through hole wave solder processing
only. They are not intended for use in Reflow solder processing
applications.
Operating Conditions
Temperature Range
ISL84XXCX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
ISL84XXIX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to 85°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θ is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
JA
Electrical Specifications Test Conditions: V = 4.5V to 5.5V; Unless Otherwise Specified.
CC
Typicals are at V
= 5V, T = 25°C, Note 2
CC
A
TEMP
(°C)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX UNITS
DC CHARACTERISTICS
Driver Differential V
(no load)
V
V
Full
Full
Full
Full
-
2
-
3
V
V
V
V
V
OUT
OUT
OD1
OD2
CC
-
Driver Differential V
(with load)
R = 50Ω (RS-422), Figure 1
R = 27Ω (RS-485), Figure 1
R = 27Ω or 50Ω, Figure 1
1.5
-
2.3
0.01
5
Change in Magnitude of Driver
Differential V for
∆V
0.2
OD
OUT
Complementary Output States
Driver Common-Mode V
V
R = 27Ω or 50Ω, Figure 1
R = 27Ω or 50Ω, Figure 1
Full
Full
-
-
-
3
V
V
OUT
Change in Magnitude of Driver
Common-Mode V for
OC
∆V
0.01
0.2
OC
OUT
Complementary Output States
Logic Input High Voltage
Logic Input Low Voltage
Logic Input Current
V
DE, DI, RE
Full
Full
Full
Full
Full
Full
Full
Full
2
-
-
-
-
-
-
-
-
-
-
0.8
2
V
V
IH
V
DE, DI, RE
IL
I
DE, DI, RE (ISL8483)
DI (ISL8485 - ISL8491)
DE, RE (ISL8485, ISL8489, ISL8491)
-2
-2
-25
-
µA
µA
µA
mA
mA
V
IN1
IN1
IN1
IN2
I
I
I
2
25
1
Input Current (A, B), Note 10
DE = 0V, V
4.5 to 5.5V
= 0V or
V
V
= 12V
= -7V
CC
IN
IN
-
-0.8
0.2
Receiver Differential Threshold
Voltage
V
-7V ≤ V
≤ 12V
CM
-0.2
TH
Receiver Input Hysteresis
∆V
V
= 0V
CM
25
-
3.5
-
70
-
-
-
mV
V
TH
Receiver Output High Voltage
Receiver Output Low Voltage
V
I
I
= -4mA, V = 200mV
ID
Full
Full
Full
OH
O
O
V
= -4mA, V = 200mV
ID
-
0.4
±1
V
OL
Three-State (high impedance)
Receiver Output Current
I
0.4V ≤ V ≤ 2.4V
-
-
µA
OZR
O
FN6046.8
5
February 28, 2006
ISL8483, ISL8485, ISL8488, ISL8489, ISL8490, ISL8491
Electrical Specifications Test Conditions: V = 4.5V to 5.5V; Unless Otherwise Specified.
CC
Typicals are at V
= 5V, T = 25°C, Note 2 (Continued)
CC
A
TEMP
(°C)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
-
MAX UNITS
Receiver Input Resistance
No-Load Supply Current, Note 3
R
-7V ≤ V
≤ 12V
CM
Full
Full
Full
Full
Full
Full
Full
Full
Full
12
-
-
kΩ
µA
µA
µA
µA
µA
µA
nA
mA
IN
I
ISL8488, ISL8489, DE, DI, RE = 0V or V
ISL8490, ISL8491, DE, DI, RE = 0V or V
160
500
700
500
470
160
1
250
565
900
565
650
250
50
CC
CC
CC
-
ISL8485, DI, RE = 0V or DE = V
-
CC
V
CC
DE = 0V
-
ISL8483, DI, RE = 0V or DE = V
-
CC
V
CC
DE = 0V
-
Shutdown Supply Current
Driver Short-Circuit Current,
I
ISL8483, DE = 0V, RE = V , DI = 0V or V
CC
-
SHDN
CC
I
DE = V , -7V ≤ V or V ≤ 12V, Note 4
35
-
250
OSD1
CC
Y
Z
V
= High or Low
O
Receiver Short-Circuit Current
I
0V ≤ V ≤ V
Full
7
-
85
mA
OSR
O
CC
SWITCHING CHARACTERISTICS (ISL8485, ISL8490, ISL8491)
Driver Input to Output Delay
Driver Output Skew
t
, t
PLH PHL
R
R
R
C
C
C
C
= 54Ω, C = 100pF, Figure 2
Full
Full
Full
Full
Full
Full
Full
Full
25
18
-
30
2
50
10
25
70
70
70
70
150
-
ns
ns
DIFF
DIFF
DIFF
L
t
= 54Ω, C = 100pF, Figure 2
L
SKEW
t , t
Driver Differential Rise or Fall Time
Driver Enable to Output High
Driver Enable to Output Low
Driver Disable from Output High
Driver Disable from Output Low
Receiver Input to Output Delay
= 54Ω, C = 100pF, Figure 2
3
-
11
17
14
19
13
40
5
ns
R
F
L
t
= 100pF, SW = GND, Figure 3
ns
ZH
L
L
L
L
t
= 100pF, SW = V , Figure 3
CC
-
ns
ZL
t
= 15pF, SW = GND, Figure 3
-
ns
HZ
t
= 15pF, SW = V , Figure 3
CC
-
ns
LZ
, t
t
Figure 4
Figure 4
30
-
ns
PLH PHL
Receiver Skew | t
- t
PLH PHL
|
t
ns
SKD
Receiver Enable to Output High
Receiver Enable to Output Low
Receiver Disable from Output High
Receiver Disable from Output Low
Maximum Data Rate
t
C
C
C
C
= 15pF, SW = GND, Figure 5
Full
Full
Full
Full
Full
-
9
50
50
50
50
-
ns
ZH
L
L
L
L
t
= 15pF, SW = V , Figure 5
CC
-
9
ns
ZL
t
= 15pF, SW = GND, Figure 5
-
9
ns
HZ
t
= 15pF, SW = V , Figure 5
CC
-
9
ns
LZ
f
Note 11
5
-
Mbps
MAX
SWITCHING CHARACTERISTICS (ISL8483, ISL8488, ISL8489)
Driver Input to Output Delay
Driver Output Skew
t
, t
PLH PHL
R
R
R
C
C
C
C
= 54Ω, C = 100pF, Figure 2
Full
Full
Full
Full
Full
Full
Full
Full
25
250
-
800
160
800
-
2000
800
2000
2000
2000
3000
3000
2000
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DIFF
DIFF
DIFF
L
t
= 54Ω, C = 100pF, Figure 2
L
SKEW
t , t
Driver Differential Rise or Fall Time
Driver Enable to Output High
Driver Enable to Output Low
Driver Disable from Output High
Driver Disable from Output Low
Receiver Input to Output Delay
= 54Ω, C = 100pF, Figure 2
250
250
250
300
300
250
-
R
F
L
t
= 100pF, SW = GND, Figure 3, Note 5
ZH
L
L
L
L
t
= 100pF, SW = V , Figure 3, Note 5
CC
-
ZL
t
= 15pF, SW = GND, Figure 3
-
HZ
t
= 15pF, SW = V , Figure 3
CC
-
LZ
, t
t
Figure 4
Figure 4
350
25
10
10
10
PLH PHL
Receiver Skew | t
- t
PLH PHL
|
t
SKD
Receiver Enable to Output High
Receiver Enable to Output Low
Receiver Disable from Output High
t
C
C
C
= 15pF, SW = GND, Figure 5, Note 6
Full
Full
Full
-
50
ZH
L
L
L
t
= 15pF, SW = V , Figure 5, Note 6
CC
-
50
ZL
t
= 15pF, SW = GND, Figure 5
-
50
HZ
FN6046.8
6
February 28, 2006
ISL8483, ISL8485, ISL8488, ISL8489, ISL8490, ISL8491
Electrical Specifications Test Conditions: V = 4.5V to 5.5V; Unless Otherwise Specified.
CC
Typicals are at V
= 5V, T = 25°C, Note 2 (Continued)
CC
A
TEMP
(°C)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
-
TYP
10
-
MAX UNITS
Receiver Disable from Output Low
Maximum Data Rate
t
C
= 15pF, SW = V , Figure 5
Full
Full
Full
Full
50
-
ns
kbps
ns
LZ
L CC
f
Note 11
Note 7
250
50
-
MAX
Time to Shutdown (ISL8483 only)
t
200
-
600
2000
SHDN
Driver Enable from Shutdown to
Output High (ISL8483 only)
t
t
C
C
C
C
= 100pF, SW = GND, Figure 3, Notes 7, 8
ns
ZH(SHDN)
L
L
L
L
Driver Enable from Shutdown to
Output Low (ISL8483 only)
t
= 100pF, SW = V , Figure 3, Notes 7, 8
CC
Full
Full
Full
-
-
-
-
-
-
2000
2500
2500
ns
ns
ns
ZL(SHDN)
ZH(SHDN)
Receiver Enable from Shutdown to
Output High (ISL8483 only)
= 15pF, SW = GND, Figure 5, Notes 7, 9
Receiver Enable from Shutdown to
Output Low (ISL8483 only)
t
= 15pF, SW = V , Figure 5, Notes 7, 9
CC
ZL(SHDN)
NOTES:
2. All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground unless
otherwise specified.
3. Supply current specification is valid for loaded drivers when DE = 0V.
4. Applies to peak current. See “Typical Performance Curves” for more information.
5. When testing the ISL8483, keep RE = 0 to prevent the device from entering SHDN.
6. When testing the ISL8483, the RE signal high time must be short enough (typically <200ns) to prevent the device from entering SHDN.
7. The ISL8483 is put into shutdown by bringing RE high and DE low. If the inputs are in this state for less than 50ns, the parts are guaranteed not
to enter shutdown. If the inputs are in this state for at least 600ns, the parts are guaranteed to have entered shutdown. See “Low-Power
Shutdown Mode” section.
8. Keep RE = V , and set the DE signal low time >600ns to ensure that the device enters SHDN.
CC
9. Set the RE signal high time >600ns to ensure that the device enters SHDN.
10. Devices meeting these limits are denoted as “single unit load (1 UL)” transceivers. The RS-485 standard allows up to 32 Unit Loads on the bus.
11. Guaranteed by characterization, but not tested.
Tes t Circuits and Waveforms
R
DE
V
CC
Z
Y
DI
V
D
OD
V
R
OC
FIGURE 1. DRIVER V
AND V
OD
OC
FN6046.8
7
February 28, 2006
ISL8483, ISL8485, ISL8488, ISL8489, ISL8490, ISL8491
Tes t Circuits and Waveforms (Continued)
3V
0V
DI
1.5V
1.5V
PHL
C
= 100pF
= 100pF
L
t
t
PLH
DE
DI
V
CC
V
OH
Z
Y
50%
50%
50%
50%
OUT (Y)
R
DIFF
D
V
OL
C
L
t
t
PLH
PHL
SIGNAL
GENERATOR
V
OH
OUT (Z)
V
OL
+V
OD
90%
10%
90%
10%
t
DIFF OUT (Y - Z)
-V
OD
t
R
F
SKEW = |t
(Y or Z) - t
(Z or Y)|
PHL
PLH
FIGURE 2B. MEASUREMENT POINTS
FIGURE 2. DRIVER PROPAGATION DELAY AND DIFFERENTIAL TRANSITION TIMES
FIGURE 2A. TEST CIRCUIT
DE
DI
Z
Y
500Ω
3V
V
CC
DE
D
1.5V
1.5V
HZ
GND
NOTE 7
SW
SIGNAL
GENERATOR
0V
C
L
t
, t
ZH ZH(SHDN)
NOTE 7
t
OUTPUT HIGH
2.3V
V
OH
V
- 0.5V
OH
(SHDN) for ISL8483 only
OUT (Y, Z)
PARAMETER OUTPUT
RE
X
DI
SW
GND
C
L
(pF)
0V
t
Y/Z
Y/Z
Y/Z
Y/Z
Y/Z
Y/Z
1/0
0/1
1/0
0/1
1/0
0/1
15
15
HZ
t
, t
t
ZL ZL(SHDN)
LZ
t
X
V
LZ
CC
GND
NOTE 7
V
CC
t
0 (Note 5)
0 (Note 5)
1 (Note 8)
1 (Note 8)
100
100
100
100
ZH
OUT (Y, Z)
2.3V
t
V
ZL
CC
GND
V
+ 0.5V
V
OL
OL
t
OUTPUT LOW
ZH(SHDN)
t
V
CC
ZL(SHDN)
FIGURE 3A. TEST CIRCUIT
FIGURE 3B. MEASUREMENT POINTS
FIGURE 3. DRIVER ENABLE AND DISABLE TIMES (EXCLUDING ISL8488, ISL8490)
RE
3V
0V
15pF
A
1.5V
1.5V
PHL
B
A
+1.5V
RO
R
t
t
PLH
V
CC
SIGNAL
GENERATOR
50%
50%
RO
0V
FIGURE 4B. MEASUREMENT POINTS
FIGURE 4. RECEIVER PROPAGATION DELAY
FIGURE 4A. TEST CIRCUIT
FN6046.8
February 28, 2006
8
ISL8483, ISL8485, ISL8488, ISL8489, ISL8490, ISL8491
Tes t Circuits and Waveforms (Continued)
RE
NOTE 7
B
1kΩ
3V
0V
V
CC
RO
R
RE
1.5V
1.5V
HZ
GND
SW
SIGNAL
A
GENERATOR
15pF
t
, t
ZH ZH(SHDN)
NOTE 7
t
OUTPUT HIGH
V
OH
- 0.5V
V
OH
(SHDN) for ISL8483 only.
PARAMETER
RO
1.5V
0V
DE
0
A
SW
t
+1.5V
-1.5V
+1.5V
-1.5V
+1.5V
-1.5V
GND
HZ
t
, t
t
ZL ZL(SHDN)
LZ
t
0
V
NOTE 7
LZ
CC
V
CC
OL
t
(Note 6)
(Note 6)
0
GND
ZH
RO
1.5V
V
+ 0.5V
V
t
0
V
OL
ZL
CC
OUTPUT LOW
t
(Note 9)
(Note 9)
0
GND
ZH(SHDN)
t
0
V
CC
ZL(SHDN)
FIGURE 5B. MEASUREMENT POINTS
FIGURE 5A. TEST CIRCUIT
FIGURE 5. RECEIVER ENABLE AND DISABLE TIMES (EXCLUDING ISL8488, ISL8490)
Receivers easily meet the data rates supported by the
corresponding driver.
Application Information
RS-485 and RS-422 are differential (balanced) data
transmission standards for use in long haul or noisy
environments. RS-422 is a subset of RS-485, so RS-485
transceivers are also RS-422 compliant. RS-422 is a point-
to-multipoint (multidrop) standard, which allows only one
driver and up to 10 (assuming one unit load devices)
receivers on each bus. RS-485 is a true multipoint standard,
which allows up to 32 one unit load devices (any
combination of drivers and receivers) on each bus. To allow
for multipoint operation, the RS-485 spec requires that
drivers must handle bus contention without sustaining any
damage.
ISL8483/85/89/91 receiver outputs are three-statable via the
active low RE input.
Driver Features
The RS-485/422 driver is a differential output device that
delivers at least 1.5Vacross a 54Ω load (RS-485), and at
least 2V across a 100Ω load (RS-422). The drivers feature
low propagation delay skew to maximize bit width, and to
minimize EMI.
Drivers of the ISL8483/85/89/91 are three-statable via the
active high DE input.
The ISL8483/88/89 driver outputs are slew rate limited to
minimize EMI, and to minimize reflections in unterminated or
improperly terminated networks. Data rate on these slew
rate limited versions is a maximum of 250kbps. Outputs of
ISL8485/90/91 drivers are not limited, so faster output
transition times allow data rates of at least 5Mbps.
Another important advantage of RS-485 is the extended
common mode range (CMR), which specifies that the driver
outputs and receiver inputs withstand signals that range
from +12V to -7V. RS-422 and RS-485 are intended for runs
as long as 4000’, so the wide CMR is necessary to handle
ground potential differences, as well as voltages induced in
the cable by external fields.
Data Rate, Cables , and Terminations
RS-485/422 are intended for network lengths up to 4000’,
but the maximum system data rate decreases as the
transmission length increases. Devices operating at 5Mbps
are limited to lengths less than 100’, while the 250kbps
versions can operate at full data rates with lengths in excess
of 1000’.
Receiver Features
These devices utilize a differential input receiver for maximum
noise immunity and common mode rejection. Input sensitivity
is ±200mV, as required by the RS422 and RS-485
specifications.
Receiver input impedance surpasses the RS-422 spec of
4kΩ, and meets the RS-485 “Unit Load” requirement of
12kΩ minimum.
Twisted pair is the cable of choice for RS-485/422 networks.
Twisted pair cables tend to pick up noise and other
electromagnetically induced voltages as common mode
signals, which are effectively rejected by the differential
receivers in these ICs.
Receiver inputs function with common mode voltages as
great as ±7V outside the power supplies (i.e., +12V and
-7V), making them ideal for long networks where induced
voltages are a realistic concern.
Proper termination is imperative, when using the 5Mbps
devices, to minimize reflections. Short networks using the
250kbps versions need not be terminated, but, terminations
are recommended unless power dissipation is an overriding
concern.
All the receivers include a “fail-safe if open” function that
guarantees a high level receiver output if the receiver inputs
are unconnected (floating).
FN6046.8
9
February 28, 2006
ISL8483, ISL8485, ISL8488, ISL8489, ISL8490, ISL8491
In point-to-point, or point-to-multipoint (single driver on bus)
In the event of a major short circuit condition, ISL84XX
devices also include a thermal shutdown feature that
disables the drivers whenever the die temperature becomes
excessive. This eliminates the power dissipation, allowing
the die to cool. The drivers automatically reenable after the
die temperature drops about 15 degrees. If the contention
persists, the thermal shutdown/reenable cycle repeats until
the fault is cleared. Receivers stay operational during
thermal shutdown.
networks, the main cable should be terminated in its
characteristic impedance (typically 120Ω) at the end farthest
from the driver. In multi-receiver applications, stubs
connecting receivers to the main cable should be kept as
short as possible. Multipoint (multi-driver) systems require
that the main cable be terminated in its characteristic
impedance at both ends. Stubs connecting a transceiver to
the main cable should be kept as short as possible.
Built-In Driver Overload Protection
Low Power Shutdown Mode (ISL8483 Only)
As stated previously, the RS-485 spec requires that drivers
survive worst case bus contentions undamaged. The
ISL84XX devices meet this requirement via driver output
short circuit current limits, and on-chip thermal shutdown
circuitry.
These CMOS transceivers all use a fraction of the power
required by their bipolar counterparts, but the ISL8483
includes a shutdown feature that reduces the already low
quiescent I
to a 1nA trickle. The ISL8483 enters shutdown
CC
whenever the receiver and driver are s imultaneous ly
disabled (RE = V and DE = GND) for a period of at least
CC
The driver output stages incorporate short circuit current
limiting circuitry which ensures that the output current never
exceeds the RS-485 spec, even at the common mode
voltage range extremes. Additionally, these devices utilize a
foldback circuit which reduces the short circuit current, and
thus the power dissipation, whenever the contending voltage
exceeds either supply.
600ns. Disabling both the driver and the receiver for less
than 50ns guarantees that the ISL8483 will not enter
shutdown.
Note that receiver and driver enable times increase when
the ISL8483 enables from shutdown. Refer to Notes 5-8, at
the end of the Electrical Specification table, for more
information.
Typical Performance Curves
V
= 5V, T = 25°C, ISL8483 thru ISL8491; Unless Otherwise Specified
CC A
90
3.6
3.4
3.2
3
80
70
60
50
40
30
R
= 100Ω
DIFF
2.8
2.6
2.4
2.2
2
20
10
0
R
= 54Ω
DIFF
0
1
2
3
4
5
-40
0
50
85
-25
25
75
DIFFERENTIAL OUTPUT VOLTAGE (V)
TEMPERATURE (°C)
FIGURE 6. DRIVER OUTPUT CURRENT vs DIFFERENTIAL
OUTPUT VOLTAGE
FIGURE 7. DRIVER DIFFERENTIAL OUTPUT VOLTAGE vs
TEMPERATURE
FN6046.8
February 28, 2006
10
ISL8483, ISL8485, ISL8488, ISL8489, ISL8490, ISL8491
Typical Performance Curves
V
= 5V, T = 25°C, ISL8483 thru ISL8491; Unless Otherwise Specified (Continued)
CC
A
160
140
120
700
ISL8485, DE = V , RE = X
CC
650
Y OR Z = LOW
600
550
500
450
400
350
100
ISL8485, DE = GND, RE = X,
ISL8490/91, DE = RE = X
80
60
40
20
0
ISL8483, DE = V , RE = X
CC
-20
Y OR Z = HIGH
-40
-60
300
250
200
150
-80
ISL8483, DE = GND, RE = GND; ISL8488/89, DE = RE = X
-100
-120
-40
0
50
85
-25
25
75
-7 -6
-4
-2
0
2
4
6
8
10
12
OUTPUT VOLTAGE (V)
TEMPERATURE (°C)
FIGURE 8. DRIVER OUTPUT CURRENT vs SHORT CIRCUIT
VOLTAGE
FIGURE 9. SUPPLY CURRENT vs TEMPERATURE
400
1200
1100
t
t
PLHY
300
200
100
0
PLHZ
1000
900
800
700
600
500
|t
- t |
PHLY PLHZ
t
PHLY
|t |
- t
PLHY PHLZ
t
PHLZ
|CROSS PT. OF Y↑ & Z↓ - CROSS PT. OF Y↓ & Z↑|
-40
0
50
85
-25
25
75
-40
0
50
85
-25
25
75
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 10. DRIVER PROPAGATION DELAY vs
TEMPERATURE (ISL8483, ISL8488, ISL8489)
FIGURE 11. DRIVER SKEW vs TEMPERATURE
(ISL8483, ISL8488, ISL8489)
3
40
35
2.5
|t
- t |
PHLY PLHZ
t
PHLY
t
PHLZ
30
25
20
2
1.5
1
|t |
- t
t
PLHY PHLZ
PLHZ
t
PLHY
|CROSSING PT. OF Y↑ & Z↓ - CROSSING PT. OF Y↓ & Z↑|
-40
0
50
85
-40
0
50
85
-25
25
75
-25
25
75
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 12. DRIVER PROPAGATION DELAY vs
FIGURE 13. DRIVER SKEW vs TEMPERATURE
(ISL8485, ISL8490, ISL8491)
TEMPERATURE (ISL8485, ISL8490, ISL8491)
FN6046.8
11
February 28, 2006
ISL8483, ISL8485, ISL8488, ISL8489, ISL8490, ISL8491
Typical Performance Curves
V
= 5V, T = 25°C, ISL8483 thru ISL8491; Unless Otherwise Specified (Continued)
A
CC
R
= 54Ω, C = 100pF
L
R
= 54Ω, C = 100pF
DIFF
DIFF
L
5
0
5
0
DI
DI
5
0
5
0
RO
RO
4
3
2
4
B/Z
A/Y
B/Z
3
2
A/Y
1
0
1
0
TIME (400ns/DIV)
TIME (400ns/DIV)
FIGURE 14. DRIVER AND RECEIVER WAVEFORMS,
LOW TO HIGH (ISL8483, ISL8488, ISL8489)
FIGURE 15. DRIVER AND RECEIVER WAVEFORMS,
HIGH TO LOW (ISL8483, ISL8488, ISL8489)
R
= 54Ω, C = 100pF
L
R
= 54Ω, C = 100pF
L
DIFF
DIFF
5
0
5
0
DI
DI
5
0
5
0
RO
RO
4
3
4
B/Z
A/Y
A/Y
B/Z
3
2
1
0
2
1
0
TIME (10ns/DIV)
TIME (10ns/DIV)
FIGURE 17. DRIVER AND RECEIVER WAVEFORMS,
HIGH TO LOW (ISL8485, ISL8490, ISL8491)
FIGURE 16. DRIVER AND RECEIVER WAVEFORMS,
LOW TO HIGH (ISL8485, ISL8490, ISL8491)
Die Characteris tics
SUBSTRATE POTENTIAL (POWERED UP):
GND
TRANSISTOR COUNT:
518
PROCESS:
Si Gate CMOS
FN6046.8
12
February 28, 2006
ISL8483, ISL8485, ISL8488, ISL8489, ISL8490, ISL8491
Dual-In-Line Plas tic Packages (PDIP)
E8.3 (JEDEC MS-001-BA ISSUE D)
N
8 LEAD DUAL-IN-LINE PLASTIC PACKAGE
E1
INDEX
AREA
INCHES
MILLIMETERS
1 2
3
N/2
SYMBOL
MIN
MAX
0.210
-
MIN
-
MAX
5.33
-
NOTES
-B-
A
A1
A2
B
-
4
-A-
D
E
0.015
0.115
0.014
0.045
0.008
0.355
0.005
0.300
0.240
0.39
2.93
0.356
1.15
0.204
9.01
0.13
7.62
6.10
4
BASE
PLANE
0.195
0.022
0.070
0.014
0.400
-
4.95
0.558
1.77
0.355
10.16
-
-
A2
A
-C-
-
SEATING
PLANE
L
C
L
B1
C
8, 10
D1
B1
eA
-
A
A
1
D1
e
D
5
eC
C
B
eB
D1
E
5
0.010 (0.25) M
C
B S
0.325
0.280
8.25
7.11
6
NOTES:
E1
e
5
1. Controlling Dimensions: INCH. In case of conflict between
0.100 BSC
0.300 BSC
2.54 BSC
7.62 BSC
-
English and Metric dimensions, the inch dimensions control.
e
e
6
A
B
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
-
0.430
0.150
-
10.92
3.81
7
3. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication No. 95.
L
0.115
2.93
4
9
4. Dimensions A, A1 and L are measured with the package seated
N
8
8
in JEDEC seating plane gauge GS-3.
Rev. 0 12/93
5. D, D1, and E1 dimensions do not include mold flash or protru-
sions. Mold flash or protrusions shall not exceed 0.010 inch
(0.25mm).
e
6. E and
pendicular to datum
7. e and e are measured at the lead tips with the leads uncon-
are measured with the leads constrained to be per-
A
-C-
.
B
C
strained. e must be zero or greater.
C
8. B1 maximum dimensions do not include dambar protrusions.
Dambar protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3,
E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch
(0.76 - 1.14mm).
FN6046.8
13
February 28, 2006
ISL8483, ISL8485, ISL8488, ISL8489, ISL8490, ISL8491
Dual-In-Line Plas tic Packages (PDIP)
E14.3 (JEDEC MS-001-AA ISSUE D)
N
14 LEAD DUAL-IN-LINE PLASTIC PACKAGE
E1
INCHES
MILLIMETERS
INDEX
AREA
1 2
3
N/2
SYMBOL
MIN
MAX
0.210
-
MIN
-
MAX
5.33
-
NOTES
-B-
A
A1
A2
B
-
4
-A-
0.015
0.115
0.014
0.045
0.008
0.735
0.005
0.300
0.240
0.39
2.93
0.356
1.15
0.204
18.66
0.13
7.62
6.10
4
D
E
0.195
0.022
0.070
0.014
0.775
-
4.95
0.558
1.77
0.355
19.68
-
-
BASE
PLANE
A2
A
-C-
-
SEATING
PLANE
B1
C
8
L
C
L
-
D1
B1
eA
A1
A
D1
e
D
5
eC
C
B
D1
E
5
eB
0.010 (0.25) M
C
B S
0.325
0.280
8.25
7.11
6
NOTES:
E1
e
5
1. Controlling Dimensions: INCH. In case of conflict between English
and Metric dimensions, the inch dimensions control.
0.100 BSC
0.300 BSC
2.54 BSC
7.62 BSC
-
e
e
6
A
B
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
-
0.430
0.150
-
10.92
3.81
7
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication No. 95.
L
0.115
2.93
4
9
4. Dimensions A, A1 and L are measured with the package seated in
N
14
14
JEDEC seating plane gauge GS-3.
Rev. 0 12/93
5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
e
6. E and
dicular to datum
7. e and e are measured at the lead tips with the leads uncon-
are measured with the leads constrained to be perpen-
A
-C-
.
B
C
strained. e must be zero or greater.
C
8. B1maximumdimensionsdonotincludedambarprotrusions. Dambar
protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 -
1.14mm).
FN6046.8
14
February 28, 2006
ISL8483, ISL8485, ISL8488, ISL8489, ISL8490, ISL8491
Small Outline Plastic Packages (SOIC)
M8.15 (JEDEC MS-012-AA ISSUE C)
N
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
INDEX
AREA
0.25(0.010)
M
B M
H
INCHES
MILLIMETERS
E
SYMBOL
MIN
MAX
MIN
1.35
0.10
0.33
0.19
4.80
3.80
MAX
1.75
0.25
0.51
0.25
5.00
4.00
NOTES
-B-
A
A1
B
C
D
E
e
0.0532
0.0040
0.013
0.0688
0.0098
0.020
-
-
1
2
3
L
9
SEATING PLANE
A
0.0075
0.1890
0.1497
0.0098
0.1968
0.1574
-
-A-
3
h x 45°
D
4
-C-
0.050 BSC
1.27 BSC
-
α
H
h
0.2284
0.0099
0.016
0.2440
0.0196
0.050
5.80
0.25
0.40
6.20
0.50
1.27
-
e
A1
C
5
B
0.10(0.004)
L
6
0.25(0.010) M
C
A M B S
N
α
8
8
7
NOTES:
0°
8°
0°
8°
-
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Rev. 1 6/05
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
FN6046.8
15
February 28, 2006
ISL8483, ISL8485, ISL8488, ISL8489, ISL8490, ISL8491
Small Outline Plas tic Packages (SOIC)
M14.15 (JEDEC MS-012-AB ISSUE C)
14 LEAD NARROW BODY SMALL OUTLINE PLASTIC
PACKAGE
N
INDEX
AREA
0.25(0.010)
M
B M
H
E
INCHES
MILLIMETERS
-B-
SYMBOL
MIN
MAX
MIN
1.35
0.10
0.33
0.19
8.55
3.80
MAX
1.75
0.25
0.51
0.25
8.75
4.00
NOTES
A
A1
B
C
D
E
e
0.0532
0.0040
0.013
0.0688
0.0098
0.020
-
1
2
3
L
-
SEATING PLANE
A
9
0.0075
0.3367
0.1497
0.0098
0.3444
0.1574
-
-A-
o
h x 45
D
3
4
-C-
α
0.050 BSC
1.27 BSC
-
e
A1
C
H
h
0.2284
0.0099
0.016
0.2440
0.0196
0.050
5.80
0.25
0.40
6.20
0.50
1.27
-
B
0.10(0.004)
5
0.25(0.010) M
C
A M B S
L
6
N
α
14
14
7
NOTES:
o
o
o
o
0
8
0
8
-
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
Rev. 0 12/93
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension“E”doesnotincludeinterleadflashorprotrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6046.8
16
February 28, 2006
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