MAX5063BASA+T [ROCHESTER]
2 A HALF BRDG BASED MOSFET DRIVER, PDSO8, LEAD FREE, SOIC-8;
| 型号： | MAX5063BASA+T |
| 厂家： | 
Rochester Electronics |
| 描述： | 2 A HALF BRDG BASED MOSFET DRIVER, PDSO8, LEAD FREE, SOIC-8 驱动 信息通信管理 光电二极管 接口集成电路 驱动器 |
| 文件： | 总21页 (文件大小：1086K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-3502; Rev 5; 5/07
125V/2A, High-Speed,
Half-Bridge MOSFET Drivers
General Description
Features
♦ HIP2100/HIP2101 Pin Compatible (MAX5062A/
The MAX5062/MAX5063/MAX5064 high-frequency,
125V half-bridge, n-channel MOSFET drivers drive high-
and low-side MOSFETs in high-voltage applications.
These drivers are independently controlled and their
35ns typical propagation delay, from input to output, are
matched to within 3ns (typ). The high-voltage operation
with very low and matched propagation delay between
drivers, and high source/sink current capabilities in a
thermally enhanced package make these devices suit-
able for the high-power, high-frequency telecom power
converters. The 125V maximum input voltage range pro-
vides plenty of margin over the 100V input transient
requirement of telecom standards. A reliable on-chip
MAX5063A)
♦ Up to 125V Input Operation
♦ 8V to 12.6V V
Input Voltage Range
DD
♦ 2A Peak Source and Sink Current Drive Capability
♦ 35ns Typical Propagation Delay
♦ Guaranteed 8ns Propagation Delay Matching
Between Drivers
♦ Programmable Break-Before-Make Timing
(MAX5064)
♦ Up to 1MHz Combined Switching Frequency while
Driving 100nC Gate Charge (MAX5064)
bootstrap diode connected between V
and BST elimi-
DD
nates the need for an external discrete diode.
♦ Available in CMOS (V
/ 2) or TTL Logic-Level
DD
Inputs with Hysteresis
The MAX5062A/C and the MAX5063A/C offer both nonin-
verting drivers (see the Selector Guide). The
MAX5062B/D and the MAX5063B/D offer a noninverting
high-side driver and an inverting low-side driver. The
MAX5064A/B offer two inputs per driver that can be
either inverting or noninverting. The MAX5062A/B/C/D
♦ Up to 15V Logic Inputs Independent of Input
Voltage
♦ Low 2.5pF Input Capacitance
♦ Instant Turn-Off of Drivers During Fault or PWM
Start-Stop Synchronization (MAX5064)
and the MAX5064A feature CMOS (V
/ 2) logic inputs.
DD
The MAX5063A/B/C/D and the MAX5064B feature TTL
logic inputs. The MAX5064A/B include a break-before-
make adjustment input that sets the dead time between
drivers from 16ns to 95ns. The drivers are available in the
industry-standard 8-pin SO footprint and pin configura-
tion, and a thermally enhanced 8-pin SO and 12-pin
(4mm x 4mm) thin QFN packages. All devices operate
over the -40°C to +125°C automotive temperature range.
♦ Low 200µA Supply Current
♦ Versions Available With Combination of
Noninverting and Inverting Drivers (MAX5062B/D
and MAX5063B/D)
♦ Available in 8-Pin SO, Thermally Enhanced SO,
and 12-Pin Thin QFN Packages
Ordering Information
PIN-
TOP
PKG
Applications
PART
TEMP RANGE
PACKAGE MARK CODE
Telecom Half-Bridge Power Supplies
Two-Switch Forward Converters
Full-Bridge Converters
MAX5062AASA -40°C to +125°C 8 SO
MAX5062BASA -40°C to +125°C 8 SO
MAX5062CASA -40°C to +125°C 8 SO-EP*
MAX5062DASA -40°C to +125°C 8 SO-EP*
*EP = Exposed paddle.
Devices are available in both leaded and lead-free packaging.
Specify lead-free by replacing “-T” with “+T” when ordering.
Ordering Information continued at end of data sheet.
—
—
—
—
S8-5
S8-5
S8E-14
S8E-14
Active-Clamp Forward Converters
Power-Supply Modules
Motor Control
Selector Guide
PART
HIGH-SIDE DRIVER
Noninverting
LOW-SIDE DRIVER
Noninverting
Inverting
LOGIC LEVELS
CMOS (V / 2)
PIN COMPATIBLE
MAX5062AASA
MAX5062BASA
MAX5062CASA
MAX5062DASA
HIP 2100IB
DD
Noninverting
CMOS (V / 2)
—
—
—
DD
Noninverting
Noninverting
Inverting
CMOS (V / 2)
DD
Noninverting
CMOS (V / 2)
DD
Selector Guide continued at end of data sheet.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
125V/2A, High-Speed,
Half-Bridge MOSFET Drivers
ABSOLUTE MAXIMUM RATINGS
(All voltages referenced to GND, unless otherwise noted.)
, IN_H, IN_L, IN_L+, IN_L-, IN_H+, IN_H-........-0.3V to +15V
8-Pin SO with Exposed Pad (derate 19.2mW/°C
above +70°C)* ....................................................1538.5mW
12-Pin Thin QFN (derate 24.4mW/°C
V
DD
DL, BBM .....................................................-0.3V to (V
+ 0.3V)
DD
HS............................................................................-5V to +130V
DH to HS.....................................................-0.3V to (V + 0.3V)
BST to HS ...............................................................-0.3V to +15V
AGND to PGND (MAX5064)..................................-0.3V to +0.3V
dV/dt at HS ........................................................................50V/ns
above +70°C)* ....................................................1951.2mW
Maximum Junction Temperature .....................................+150°C
Operating Temperature Range .........................-40°C to +125°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
DD
Continuous Power Dissipation (T = +70°C)
A
8-Pin SO (derate 5.9mW/°C above +70°C)...............470.6mW
*Per JEDEC 51 standard multilayer board.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
= V
= +8V to +12.6V, V = GND = 0V, BBM = open, T = -40°C to +125°C, unless otherwise noted. Typical values are at
= +12V and T = +25°C.) (Note 1)
DD
BST
HS
A
V
= V
DD
BST A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
POWER SUPPLIES
Operating Supply Voltage
V
(Note 2)
8.0
12.6
140
V
DD
MAX5062_/
MAX5063_
70
IN_H = IN_L = GND
(no switching)
V
Quiescent Supply Current
I
µA
DD
DD
MAX5064_
120
260
V
Operating Supply Current
I
f
= 500kHz, V = +12V
DD
3
mA
µA
mA
V
DD
DDO
SW
BST Quiescent Supply Current
BST Operating Supply Current
I
IN_H = IN_L = GND (no switching)
15
40
3
BST
I
f
= 500kHz, V
V rising
DD
= V
= +12V
BST
BSTO
SW
DD
UVLO (V
to GND)
UVLO
6.5
6.0
7.3
6.9
0.5
8.0
7.8
DD
VDD
UVLO (BST to HS)
UVLO Hysteresis
LOGIC INPUT
UVLO
BST rising
V
BST
V
MAX5062_/MAX5064A,
CMOS (V / 2) version
0.67 x
0.55 x
V
V
Input-Logic High
V
V
V
V
DD
DD
DD
IH_
MAX5063_/MAX5064B, TTL version
2
1.65
MAX5062_/MAX5064A,
CMOS (V / 2) version
DD
0.4 x
0.33 x
V
DD
V
Input-Logic Low
V
DD
IL_
MAX5063_/MAX5064B, TTL version
1.4
0.8
MAX5062_/MAX5064A,
CMOS (V / 2) version
DD
1.6
Logic-Input Hysteresis
V
HYS
MAX5063_/MAX5064B, TTL version
0.25
2
_______________________________________________________________________________________
125V/2A, High-Speed,
Half-Bridge MOSFET Drivers
ELECTRICAL CHARACTERISTICS (continued)
(V
= V
= +8V to +12.6V, V = GND = 0V, BBM = open, T = -40°C to +125°C, unless otherwise noted. Typical values are at
= +12V and T = +25°C.) (Note 1)
DD
BST
HS
A
V
= V
DD
BST A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V
V
V
V
, V
= 0V
IN_H+ IN_L+
= V
for MAX5062B/D, MAX5063B/D
IN_L
DD
Logic-Input Current
Input Resistance
I_IN
-1
0.001
+1
µA
, V
, V
= V
IN_H- IN_L- IN_H DD
= 0V for MAX5062A/C, MAX5063A/C
IN_L
IN_H+, IN_L+ IN_H, to GND
IN_L to V for MAX5062B/D,
DD
MAX5063B/D
R
C
1
MΩ
IN
IN_H-, IN_L-, IN_H, to V
DD
IN_LforMAX5062A/C, MAX5063A/C to GND
Input Capacitance
2.5
pF
IN
HIGH-SIDE GATE DRIVER
HS Maximum Voltage
BST Maximum Voltage
V
125
140
V
V
HS_MAX
V
BST_MAX
T
A
T
A
T
A
T
A
= +25°C
= +125°C
= +25°C
= +125°C
2.5
3.5
2.1
3.2
3.3
4.6
2.8
4.2
Driver Output Resistance
(Sourcing)
V
= 12V, I
= 100mA
= 100mA
DD
DH
R
Ω
Ω
ON_HP
(sourcing)
Driver Output Resistance
(Sinking)
V
DD
(sinking)
= 12V, I
DH
R
ON_HN
DH Reverse Current (Latchup
Protection)
(Note 3)
400
mA
V
Power-Off Pulldown Clamp
Voltage
V
= 0V or floating, I
= 1mA (sinking)
0.94
1.16
BST
DH
Peak Output Current (Sourcing)
Peak Output Current (Sinking)
LOW-SIDE GATE DRIVER
C = 10nF, V
= 0V
2
2
A
A
L
DH
I
DH_PEAK
C = 10nF, V
L
= 12V
DH
T
A
T
A
T
A
T
A
= +25°C
= +125°C
= +25°C
= +125°C
2.5
3.5
2.1
3.2
3.3
4.6
2.8
4.2
Driver Output Resistance
(Sourcing)
V
= 12V, I = 100mA
DD DL
R
R
Ω
Ω
ON_LP
(sourcing)
V = 12V, I = 100mA
DD
Driver Output Resistance
(Sinking)
DL
ON_LN
(sinking)
Reverse Current at DL (Latchup
Protection)
(Note 3)
400
mA
V
Power-Off Pulldown Clamp
Voltage
V
= 0V or floating, I = 1mA (sinking)
0.95
1.16
1.11
DD
DL
Peak Output Current (Sourcing)
Peak Output Current (Sinking)
INTERNAL BOOTSTRAP DIODE
Forward Voltage Drop
I
C = 10nF, V = 0V
L
2
2
A
A
PK_LP
DL
I
C = 10nF, V = 12V
L
PK_LN
DL
V
I
I
= 100mA
0.91
40
V
f
BST
Turn-On and Turn-Off Time
t
= 100mA
ns
R
BST
_______________________________________________________________________________________
3
125V/2A, High-Speed,
Half-Bridge MOSFET Drivers
ELECTRICAL CHARACTERISTICS (continued)
(V
= V
= +8V to +12.6V, V = GND = 0V, BBM = open, T = -40°C to +125°C, unless otherwise noted. Typical values are at
= +12V and T = +25°C.) (Note 1)
DD
BST
HS
A
V
= V
DD
BST A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ns
SWITCHING CHARACTERISTICS FOR HIGH- AND LOW-SIDE DRIVERS (V
= V
= +12V)
DD
BST
C = 1000pF
7
L
Rise Time
Fall Time
t
C = 5000pF
L
33
65
7
R
C = 10,000pF
L
C = 1000pF
L
t
ns
C = 5000pF
L
33
65
30
35
30
35
F
C = 10,000pF
L
CMOS
TTL
55
63
55
63
Figure 1, C = 1000pF
L
Turn-On Propagation Delay Time
Turn-Off Propagation Delay Time
t
ns
ns
D_ON
(Note 3)
CMOS
TTL
Figure 1, C = 1000pF
L
t
D_OFF
(Note 3)
Delay Matching Between
Inverting Input to Output and
Noninverting Input to Output
C = 1000pF, BBM open for MAX5064,
L
Figure 1 (Note 3)
t
t
2
8
8
ns
ns
ns
MATCH1
MATCH2
Delay Matching Between Driver-
Low and Driver-High
C = 1000pF, BBM open for MAX5064,
L
Figure 1 (Note 3)
2
R
BBM
R
BBM
R
BBM
= 10kΩ
16
56
Break-Before-Make Accuracy
(MAX5064 Only)
= 47kΩ (Notes 3, 4)
= 100kΩ
40
72
95
Internal Nonoverlap
1
ns
ns
V
V
= V
= 12V
= 8V
135
170
Minimum Pulse-Width Input Logic
(High or Low) (Note 5)
DD
DD
BST
BST
t
PW-MIN
= V
Note 1: All devices are 100% tested at T = +125°C. Limits over temperature are guaranteed by design.
A
Note 2: Ensure that the V -to-GND or BST-to-HS voltage does not exceed 13.2V.
DD
Note 3: Guaranteed by design, not production tested.
Note 4: Break-before-make time is calculated by t
Note 5: See the Minimum Pulse Width section.
= 8ns x (1 + R
/ 10kΩ).
BBM
BBM
4
_______________________________________________________________________________________
125V/2A, High-Speed,
Half-Bridge MOSFET Drivers
Typical Operating Characteristics
(Typical values are at V
= V
= +12V and T = +25°C, unless otherwise specified.)
DD
BST
A
UNDERVOLTAGE LOCKOUT
V
DD
AND BST UNDERVOLTAGE LOCKOUT
HYSTERESIS vs. TEMPERATURE
(V AND V
RISING) vs. TEMPERATURE
I vs. V
DD DD
DD
BST
MAX5062/3/4 toc03
7.5
7.4
7.3
7.2
7.1
7.0
6.9
6.8
6.7
6.6
6.5
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
MAX5064
IN_L-, IN_H- = V
IN_L+, IN_H+ = GND
DD
UVLO
VDD
BST
2V/div
V
DD
UVLO
HYSTERESIS
VDD
UVLO
HYSTERESIS
BST
UVLO
0V
500µA/div
I
DD
0A
-40 -25 -10
5
20 35 50 65 80 95 110 125
-40 -25 -10
5
20 35 50 65 80 95 110 125
40µs/div
TEMPERATURE (°C)
TEMPERATURE (°C)
I
+ I
vs. V
INTERNAL BST DIODE
(I-V) CHARACTERISTICS
DDO BSTO DD
(f = 250kHz)
SW
200
180
3.0
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
T
= +125°C
= +25°C
= 0°C
A
A
A
A
160
T
140
T
120
T
= -40°C
100
80
60
40
20
0
0
1
2
3
4
5
6
7
8
9
10 11 12 13
0.5
0.6
0.7
0.8
0.9
1.0
1.1
V
(V)
V
DD
- V (V)
BST
DD
V
QUIESCENT CURRENT
DD
BST QUIESCENT CURRENT
vs. BST VOLTAGE
DD
vs. V (NO SWITCHING)
160
140
120
100
80
21
18
15
12
9
V
= V + 1V,
DD
MAX5064
BST
NO SWITCHING
T
= +125°C
A
T
= +25°C, T = 0°C
A
A
T
= +125°C
A
60
T
= -40°C
A
6
40
3
20
T
= -40°C, T = 0°C, T = +25°C
A A
A
0
0
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
V
(V)
V
(V)
DD
BST
_______________________________________________________________________________________
5
125V/2A, High-Speed,
Half-Bridge MOSFET Drivers
Typical Operating Characteristics (continued)
(Typical values are at V
= V
= +12V and T = +25°C, unless otherwise specified.)
DD
BST
A
V
DD
AND BST OPERATING SUPPLY
CURRENT vs. FREQUENCY
DH OR DL OUTPUT LOW VOLTAGE
vs. TEMPERATURE
10
9
8
7
6
5
4
3
2
1
0
0.34
0.32
0.30
0.28
0.26
0.24
0.22
0.20
0.18
0.16
0.14
0.12
0.10
SINKING 100mA
C = 0
L
0
100 200 300 400 500 600 700 800 900 1000
FREQUENCY (kHz)
-40 -25 -10
5
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
DH OR DL RISE TIME
vs. TEMPERATURE (C = 10nF)
PEAK DH AND DL
SOURCE/SINK CURRENT
L
MAX5062/3/4 toc10
120
108
96
84
72
60
48
36
24
12
0
C
= 100nF
L
V
= V = 8V
BST
DD
5V/div
2A/div
DH OR DL
V
= V = 12V
BST
DD
SINK AND SOURCE
CURRENT
-40 -25 -10
5
20 35 50 65 80 95 110 125
1µs/div
TEMPERATURE (°C)
DH OR DL FALL TIME
vs. TEMPERATURE (C = 10nF)
DH OR DL RISE PROPAGATION DELAY
vs. TEMPERATURE
LOAD
120
110
100
90
80
70
60
50
40
30
20
10
0
60
55
50
45
40
35
30
25
20
15
10
5
V
= V = 8V
BST
DD
DH
DL
V
= V = 12V
BST
DD
0
-40 -25 -10
5
20 35 50 65 80 95 110 125
-40 -25 -10
5
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
TEMPERATURE (°C)
6
_______________________________________________________________________________________
125V/2A, High-Speed,
Half-Bridge MOSFET Drivers
Typical Operating Characteristics (continued)
(Typical values are at V
= V
= +12V and T = +25°C, unless otherwise specified.)
BST A
DD
DH OR DL FALL PROPAGATION DELAY
vs. TEMPERATURE
BREAK-BEFORE-MAKE
DEAD TIME vs. R
BBM
60
55
50
45
40
35
30
25
20
15
10
5
250
225
200
175
150
125
100
75
MAX5064
DH
DL
50
25
0
0
170
290
-40 -25 -10
5
20 35 50 65 80 95 110 125
10
50
90 130
210 250
TEMPERATURE (°C)
R
(kΩ)
BBM
BREAK-BEFORE-MAKE DEAD TIME
vs. TEMPERATURE
DELAY MATCHING (DH/DL RISING)
MAX5062/3/4 toc17
120
110
100
90
80
70
60
50
40
30
20
10
0
MAX5064
C
= 0
L
R
= 100kΩ
BBM
INPUT
DH/DL
5V/div
5V/div
R
= 10kΩ
BBM
-40 -25 -10
5
20 35 50 65 80 95 110 125
10ns/div
TEMPERATURE (°C)
DH/DL RESPONSE TO V GLITCH
DELAY MATCHING (DH/DL FALLING)
DD
MAX5062/3/4 toc19
MAX5062/3/4 toc18
C
= 0
L
10V/div
10V/div
DH
DL
INPUT
DH/DL
5V/div
5V/div
V
10V/div
5V/div
DD
INPUT
40µs/div
10ns/div
_______________________________________________________________________________________
7
125V/2A, High-Speed,
Half-Bridge MOSFET Drivers
MAX5062/MAX5063 Pin Description
PIN
NAME
FUNCTION
1
V
Power Input. Bypass to GND with a parallel combination of 0.1µF and 1µF ceramic capacitor.
DD
Boost Flying Capacitor Connection. Connect a 0.1µF ceramic capacitor between BST and HS for the
high-side MOSFET driver supply.
2
BST
3
4
5
DH
HS
High-Side-Gate Driver Output. Driver output for the high-side MOSFET gate.
Source Connection for High-Side MOSFET. Also serves as a return terminal for the high-side driver.
High-Side Noninverting Logic Input
IN_H
Low-Side Noninverting Logic Input (MAX5062A/C, MAX5063A/C). Low-side inverting logic input
(MAX5062B/D, MAX5063B/D).
6
IN_L
7
8
GND
DL
Ground. Use GND as a return path to the DL driver output and IN_H/IN_L inputs.
Low-Side-Gate Driver Output. Drives low-side MOSFET gate.
Exposed Pad. Internally connected to GND. Externally connect the exposed pad to a large ground
plane to aid in heat dissipation (MAX5062C/D, MAX5063C/D only).
—
EP
MAX5064 Pin Description
PIN
NAME
FUNCTION
Boost Flying Capacitor Connection. Connect a 0.1µF ceramic capacitor between BST and HS for the
high-side MOSFET driver supply.
1
BST
2
3
4
DH
HS
High-Side-Gate Driver Output. Drives high-side MOSFET gate.
Source Connection for High-Side MOSFET. Also serves as a return terminal for the high-side driver.
Analog Ground. Return path for low-switching current signals. IN_H/IN_L inputs referenced to
AGND
Break-Before-Make Programming Resistor Connection. Connect a 10kΩ to 100kΩ resistor from BBM
to AGND to program the break-before-make time (t
greater than 200kΩ disables the BBM function and makes t
) from 16ns to 95ns. Resistance values
BBM
5
BBM
= 1ns. Bypass this pin with at least a
BBM
1nF capacitor to AGND.
High-Side Inverting CMOS (V / 2) (MAX5064A), or TTL (MAX5064B) Logic Input. Connect to
DD
AGND when not used.
6
7
IN_H-
IN_H+
IN_L-
High-Side Noninverting CMOS (V / 2) (MAX5064A), or TTL (MAX5064B) Logic Input. Connect to
DD
V
when not used.
DD
Low-Side Inverting CMOS (V / 2) (MAX5064A), or TTL (MAX5064B) Logic Input. Connect to AGND
DD
when not used.
8
Low-Side Noninverting CMOS (V / 2) (MAX5064A), or TTL (MAX5064B) Logic Input. Connect to
DD
9
IN_L+
V
when not used.
DD
Power Ground. Return path for high-switching current signals. Use PGND as a return path for the
low-side driver.
10
PGND
DL
11
12
Low-Side-Gate Driver Output. Drives the low-side MOSFET gate.
V
Power Input. Bypass to PGND with a 0.1µF ceramic in parallel with a 1µF ceramic capacitor.
DD
Exposed Pad. Internally connected to AGND. Externally connect to a large ground plane to aid in
heat dissipation.
—
EP
8
_______________________________________________________________________________________
125V/2A, High-Speed,
Half-Bridge MOSFET Drivers
V
IH
IN_L+
V
IL
90%
10%
DL
t
D_OFF1
t
D_ON1
t
F
t
R
V
IH
IN_L-
V
IL
t
D_OFF2
t
D_ON2
V
IH
IN_H+
V
IL
90%
10%
DH
t
D_OFF3
t
D_ON3
t
F
t
R
V
IH
IN_H-
V
IL
t
t
D_ON4
D_OFF4
t
t
= (t
= (t
- t
) or (t
- t
- t
)
MATCH1
MATCH2
D_ON2 D_ON1
D_OFF2 D_OFF1
- t
) or (t
) or (t
- t
) or (t
- t
)
D_ON3 D_ON1
D_ON4 D_ON2
D_OFF3 D_OFF1
D_OFF4 D_OFF2
Figure 1. Timing Characteristics for Noninverting and Inverting Logic Inputs
propagation delays. The typical propagation delay from
the logic-input signal to the drive output is 35ns with a
matched propagation delay of 3ns typical. Matching
these propagation delays is as important as the
absolute value of the delay itself. The high 125V input
voltage range allows plenty of margin above the 100V
transient specification per telecom standards.
Detailed Description
The MAX5062/MAX5063/MAX5064 are 125V/2A high-
speed, half-bridge MOSFET drivers that operate from a
supply voltage of +8V to +12.6V. The drivers are
intended to drive a high-side switch without any isola-
tion device like an optocoupler or drive transformer.
The high-side driver is controlled by a TTL/CMOS logic
signal referenced to ground. The 2A source and sink
The MAX5064 is available in a thermally enhanced
TQFN package, which can dissipate up to 1.95W (at
+70°C) and allow up to 1MHz switching frequency
while driving 100nC combined gate-charge MOSFETs.
drive capability is achieved by using low R
p-
DS_ON
and n-channel driver output stages. The BiCMOS
process allows extremely fast rise/fall times and low
_______________________________________________________________________________________
9
125V/2A, High-Speed,
Half-Bridge MOSFET Drivers
Undervoltage Lockout
Internal Bootstrap Diode
An internal diode connects from V to BST and is
used in conjunction with a bootstrap capacitor external-
ly connected between BST and HS. The diode charges
Both the high- and low-side drivers feature undervolt-
DD
age lockout (UVLO). The low-side driver’s UVLO
LOW
threshold is referenced to GND and pulls both driver
outputs low when V falls below 6.8V. The high-side
the capacitor from V
when the DL low-side switch is
DD
DD
driver has its own undervoltage lockout threshold
(UVLO ), referenced to HS, and pulls DH low when
BST falls below 6.4V with respect to HS.
on and isolates V
when HS is pulled high as the high-
DD
side driver turns on (see the Typical Operating Circuit).
HIGH
The internal bootstrap diode has a typical forward volt-
age drop of 0.9V and has a 10ns typical turn-off/turn-on
During turn-on, once V rises above its UVLO thresh-
DD
old, DL starts switching and follows the IN_L logic input.
At this time, the bootstrap capacitor is not charged and
time. For lower voltage drops from V
to BST, connect
and BST.
DD
an external Schottky diode between V
DD
the BST-to-HS voltage is below UVLO . For synchro-
BST
Programmable Break-Before-Make
(MAX5064)
nous buck and half-bridge converter topologies, the
bootstrap capacitor can charge up in one cycle and
normal operation begins in a few microseconds after the
Half-bridge and synchronous buck topologies require
that the high- or low-side switch be turned off before
the other switch is turned on to avoid shoot-through
currents. Shoot-through occurs when both high- and
low-side switches are on at the same time. This condi-
tion is caused by the mismatch in the propagation
delay from IN_H/IN_L to DH/DL, driver output imped-
ance, and the MOSFET gate capacitance. Shoot-
through currents increase power dissipation, radiate
EMI, and can be catastrophic, especially with high
input voltages.
BST-to-HS voltage exceeds UVLO . In the two-switch
BST
forward topology, the BST capacitor takes some time (a
few hundred microseconds) to charge and increase its
voltage above UVLO
.
BST
The typical hysteresis for both UVLO thresholds is 0.5V.
The bootstrap capacitor value should be selected care-
fully to avoid unintentional oscillations during turn-on
and turn-off at the DH output. Choose the capacitor
value about 20 times higher than the total gate capaci-
tance of the MOSFET. Use a low-ESR-type X7R dielec-
tric ceramic capacitor at BST (typically a 0.1µF ceramic
is adequate) and a parallel combination of 1µF and
The MAX5064 offers a break-before-make (BBM) fea-
ture that allows the adjustment of the delay from the
input to the output of each driver. The propagation
delay from the rising edges of IN_H and IN_L to the ris-
ing edges of DH and DL, respectively, can be pro-
grammed from 16ns to 95ns. Note that the BBM time
0.1µF ceramic capacitors from V
to GND
DD
(MAX5062_, MAX5063_) or to PGND (MAX5064_). The
high-side MOSFET’s continuous on-time is limited due
to the charge loss from the high-side driver’s quiescent
current. The maximum on-time is dependent on the size
(t
) has a higher percentage error at lower value
BBM
because of the fixed comparator delay in the BBM
of C
, I
(50µA max), and UVLO
.
BST BST
BST
block. The propagation delay mismatch (t
needs to be included when calculating the total t
)
MATCH_
Output Driver
The MAX5062/MAX5063/MAX5064 have low 2.5Ω
p-channel and n-channel devices (totem pole)
BBM
error. The low 8ns (maximum) delay mismatch reduces
the total t variation. Use the following equations to
R
DS_ON
BBM
in the output stage. This allows for a fast turn-on and
turn-off of the high gate-charge switching MOSFETs.
The peak source and sink current is typically 2A.
Propagation delays from the logic inputs to the driver
outputs are matched to within 8ns. The internal p- and
n-channel MOSFETs have a 1ns break-before-make
logic to avoid any cross conduction between them. This
internal break-before-make logic eliminates shoot-
through currents reducing the operating supply current
calculate R
for the required BBM time and
BBM
t
:
BBM_ERROR
t
⎛
⎞
BBM
8ns
R
= 10kΩ ×
−1 for R
< 200kΩ
⎜
⎝
⎟
BBM
BBM
⎠
t
= 0.15 × t
+ t
BBM MATCH_
BBM_ERROR
where t
is in nanoseconds.
BBM
as well as the spikes at V . The DL voltage is approxi-
DD
The voltage at BBM is regulated to 1.3V. The BBM circuit
adjusts t depending on the current drawn by R
mately equal to V
and the DH-to-HS voltage, a diode
.
BBM
DD
BBM
drop below V , when they are in a high state and to
Bypass BBM to AGND with a 1nF or smaller ceramic
capacitor (C ) to avoid any effect of ground bounce
DD
zero when in a low state. The driver R
is lower at
DS_ON
BBM
higher V . Lower R
means higher source and
caused during switching. The charging time of C
DD
DS_ON
BBM
sink currents and faster switching speeds.
does not affect t
at turn-on because the BBM voltage
BBM
is stabilized before the UVLO clears the device turn-on.
10 ______________________________________________________________________________________
125V/2A, High-Speed,
Half-Bridge MOSFET Drivers
Topologies like the two-switch forward converter, where
both high- and low-side switches are turned on and off
simultaneously, can have the BBM function disabled by
shoot-through in the absence of external BBM delay
during the narrow pulse at low duty cycle (see Figure 2).
At high duty cycle (close to 100%) the DH minimum low
leaving BBM unconnected. When disabled, t
cally 1ns.
is typi-
BBM
pulse width (t
) must be higher than the DL
DMIN-DH-L
minimum low pulse width (t
) to avoid overlap
DMIN-DL-L
and shoot-through (see Figure 3). In the case of
MAX5062/MAX5063/MAX5064, there is a possibility of
about 40ns overlap if an external BBM delay is not pro-
vided. We recommend adding external delay in the INH
path so that the minimum low pulse width seen at INH
Driver Logic Inputs (IN_H, IN_L, IN_H+,
IN_H-, IN_L+, IN_L-)
The MAX5062_/MAX5064A are CMOS (V
/ 2) logic-
DD
input drivers while the MAX5063_/MAX5064B have TTL-
compatible logic inputs. The logic-input signals are
independent of V . For example, the IC can be pow-
DD
is always longer than t
. See the Electrical
PW-MIN
Characteristics table for the typical values of t
.
PW-MIN
ered by a 10V supply while the logic inputs are provid-
ed from a 12V CMOS logic. Also, the logic inputs are
protected against voltage spikes up to 15V, regardless
V
DD
V
IN
of the V
voltage. The TTL and CMOS logic inputs
DD
A)
have 400mV and 1.6V hysteresis, respectively, to avoid
double pulsing during transition. The logic inputs are
high-impedance pins and should not be left floating.
The low 2.5pF input capacitance reduces loading and
increases switching speed. The noninverting inputs are
pulled down to GND and the inverting inputs are pulled
PWM
IN
INH
INL
DH
V
OUT
N
N
up to V
internally using a 1MΩ resistor. The PWM
DD
HS
DL
output from the controller must assume a proper state
while powering up the device. With the logic inputs
floating, the DH and DL outputs pull low as V
up above the UVLO threshold.
rises
DD
The MAX5064_ has two logic inputs per driver, which
provide greater flexibility in controlling the MOSFET.
Use IN_H+/IN_L+ for noninverting logic and IN_H-/
IN_L- for inverting logic operation. Connect
MAX5062B/MAX5062D/MAX5063B/MAX5063D/MAX5064
B)
PWM
IN
IN_H+/IN_L+ to V
and IN_H-/IN_L- to GND if not
DD
used. Alternatively, the unused input can be used as an
ON/OFF function. Use IN_+ for active-low and IN_- for
active-high shutdown logic.
t
DMIN-DH-H
Table 1. MAX5064_ Truth Table
DH
IN_H+/IN_L+
IN_H-/IN_L-
DH/DL
Low
Low
Low
Low
High
Low
High
Low
High
Low
High
High
BUILT-IN
DEAD TIME
Minimum Pulse Width
The MAX5062/MAX5063/MAX5064 uses a single-shot
level shifter architecture to achieve low propagation
delay. Typical level shifter architecture causes a mini-
mum (high or low) pulse width (t ) at the output that
DMIN
DL
may be higher than the logic-input pulse width. For
MAX5062/MAX5063/MAX5064 devices, the DH mini-
t
DMIN-DL-L
mum high pulse width (t
) is lower than the DL
DMIN-DL-L
DMIN-DH-H
minimum low pulse width (t
Figure 2. Minimum Pulse-Width Behavior for Narrow Duty-
Cycle Input (On-Time < t
) to avoid any
)
PW-MIN
______________________________________________________________________________________ 11
125V/2A, High-Speed,
Half-Bridge MOSFET Drivers
V
DD
V
IN
A)
C)
PWM
IN
EXTERNAL
BBM DELAY
PWM
IN
INH
INL
DH
V
OUT
N
N
HS
DL
EXTERNAL
BBM DELAY
t
DMIN-DH-L
DH
MAX5062B/MAX5062D/MAX5063B/MAX5063D/MAX5064
V
DD
V
IN
B)
POTENTIAL
OVERLAP TIME
EXTERNAL
BBM DELAY
PWM
IN
INH
INL
DH
V
OUT
N
N
HS
DL
DL
t
DMIN-DL-H
MAX5062A/MAX5062C/MAX5063A/MAX5063C/MAX5064
Figure 3. Minimum Pulse-Width Behavior for High Duty-Cycle Input (Off-Time < t
)
PW-MIN
series inductance. Place the external MOSFET as close
as possible to the MAX5062/MAX5063/MAX5064 to fur-
ther minimize board inductance and AC path resis-
tance. For the MAX5064_ the low-power logic ground
(AGND) is separated from the high-power driver return
(PGND). Apply the logic-input signal between IN_ to
AGND and connect the load (MOSFET gate) between
DL and PGND.
Applications Information
Supply Bypassing and Grounding
Pay extra attention to bypassing and grounding the
MAX5062/MAX5063/MAX5064. Peak supply and output
currents may exceed 4A when both drivers are driving
large external capacitive loads in-phase. Supply drops
and ground shifts create forms of negative feedback for
inverters and may degrade the delay and transition
times. Ground shifts due to insufficient device ground-
ing may also disturb other circuits sharing the same AC
Power Dissipation
Power dissipation in the MAX5062/MAX5063/MAX5064
is primarily due to power loss in the internal boost
diode and the nMOS and pMOS FETS.
ground return path. Any series inductance in the V
,
DD
DH, DL, and/or GND paths can cause oscillations due
to the very high di/dt when switching the MAX5062/
MAX5063/MAX5064 with any capacitive load. Place
one or more 0.1µF ceramic capacitors in parallel as
For capacitive loads, the total power dissipation for the
device is:
2
⎛
⎞
P = C × V
× f
+ I
(
⎠
+ I
× V
close to the device as possible to bypass V
to GND
)
DD
D
L
DD
SW
DDO
BSTO DD
⎝
(MAX5062/MAX5063) or PGND (MAX5064). Use a
ground plane to minimize ground return resistance and
12 ______________________________________________________________________________________
125V/2A, High-Speed,
Half-Bridge MOSFET Drivers
where C is the combined capacitive load at DH and
from V
to GND or BST to HS can damage the
DD
L
DL. V
is the supply voltage and f
is the switching
SW
device. Place one or more low ESL 0.1µF decou-
pling ceramic capacitors from V to GND
DD
frequency of the converter. P includes the power dis-
D
DD
sipated in the internal bootstrap diode. The internal
(MAX5062/MAX5063) or to PGND (MAX5064), and
from BST to HS as close as possible to the part. The
ceramic decoupling capacitors should be at least
20 times the gate capacitance being driven.
power dissipation reduces by P
, if an external
DIODE
bootstrap Schottky diode is used. The power dissipa-
tion in the internal boost diode (when driving a capaci-
tive load) will be the charge through the diode per
switching period multiplied by the maximum diode for-
• There are two AC current loops formed between the
device and the gate of the MOSFET being driven.
The MOSFET looks like a large capacitance from gate
to source when the gate is being pulled low. The
active current loop is from the MOSFET driver output
(DL or DH) to the MOSFET gate, to the MOSFET
source, and to the return terminal of the MOSFET dri-
ver (either GND or HS). When the gate of the MOS-
FET is being pulled high, the active current loop is
from the MOSFET driver output, (DL or DH), to the
MOSFET gate, to the MOSFET source, to the return
terminal of the drivers decoupling capacitor, to the
positive terminal of the decoupling capacitor, and to
the supply connection of the MOSFET driver. The
decoupling capacitor will be either the flying capaci-
tor connected between BST and HS or the decou-
ward voltage drop (V = 1V).
f
P
= C × V − 1 × f
× V
(
)
DIODE
DH
DD
SW f
The total power dissipation when using the internal
boost diode will be P and, when using an external
D
Schottky diode, will be P - P
. The total power
DIODE
D
dissipated in the device must be kept below the maxi-
mum of 1.951W for the 12-pin TQFN package, 1.5W for
the 8-pin SO with exposed pad, and 0.471W for the
regular 8-pin SO package at T = +70°C ambient.
A
Layout Information
The MAX5062/MAX5063/MAX5064 drivers source and
sink large currents to create very fast rise and fall
edges at the gates of the switching MOSFETs. The high
di/dt can cause unacceptable ringing if the trace
lengths and impedances are not well controlled. Use
the following PC board layout guidelines when design-
ing with the MAX5062/MAX5063/MAX5064:
pling capacitor for V . Care must be taken to
DD
minimize the physical distance and the impedance of
these AC current paths.
• Solder the exposed pad of the TQFN (MAX5064) or
SO (MAX5062C/D and MAX5063C/D) package to a
large copper plane to achieve the rated power dissi-
pation. Connect AGND and PGND at one point near
• It is important that the V
voltage (with respect to
DD
ground) or BST voltage (with respect to HS) does
not exceed 13.2V. Voltage spikes higher than 13.2V
V
DD
’s decoupling capacitor return.
______________________________________________________________________________________ 13
125V/2A, High-Speed,
Half-Bridge MOSFET Drivers
Typical Application Circuits
V
= 8V TO 12.6V
V = 0 TO 125V
IN
DD
V
DD
BST
DH
N
N
MAX5062A/
MAX5063A
IN_H
IN_L
PWM
CONTROLLER
HS
DL
V
OUT
GND
PIN FOR PIN REPLACEMENT FOR THE HIP2100/HIP2101
Figure 4. MAX5062 Half-Bridge Conversion
V
DD
= 8V TO 12.6V
V
IN
= 0 TO 125V
C
BST
V
DD
BST
N
N
DH
MAX5064
IN_H+
PWM
V
OUT
HS
DL
IN_L-
BBM
AGND PGND
R
C
BBM
BBM
Figure 5. Synchronous Buck Converter
14 ______________________________________________________________________________________
125V/2A, High-Speed,
Half-Bridge MOSFET Drivers
Typical Application Circuits (continued)
V
DD
= 8V TO 12.6V
V
IN
= 0 TO 125V
C
BST
V
DD
BST
N
DH
HS
MAX5064
IN_H+
IN_L+
BBM
V
OUT
PWM
DL
N
AGND PGND
Figure 6. Two-Switch Forward Conversion
V
= 8V TO 12.6V
V
= 0 TO 125V
DD
IN
C
BST
V
DD
BST
DH
N
N
PWM
MAX5064_
IN_H+
HS
DL
IN_L-
BBM
V
OUT
AGND
PGND
R
BBM
C
BBM
Figure 7. MAX5064 Half-Bridge Converter
______________________________________________________________________________________ 15
125V/2A, High-Speed,
Half-Bridge MOSFET Drivers
Functional Diagrams
MAX5062A
MAX5062C
MAX5062B/
MAX5062D
MAX5063A/
MAX5063C
V
DD
/2 CMOS
V
DD
/2 CMOS
TTL
BST
BST
BST
2
3
2
3
2
3
IN_H
IN_L
IN_H
IN_L
IN_H
IN_L
DH
HS
DH
HS
DH
HS
5
6
5
6
5
6
4
1
4
1
4
1
V
V
V
DD
DD
DD
DL
DL
DL
8
8
8
GND
GND
GND
7
7
7
SO/SO-EP
SO/SO-EP
SO/SO-EP
MAX5063B/
MAX5064A
MAX5064B
MAX5063D
TTL
V
DD
/2 CMOS
TTL
BST
BST
BST
2
3
1
2
1
2
IN_H+
IN_H+
7
7
IN_H
IN_L
DH
HS
DH
HS
DH
HS
5
6
IN_H-
BBM
IN_H-
BBM
6
5
6
5
4
1
3
3
V
V
V
DD
DD
DD
12
12
IN_L+
IN_L+
9
9
DL
DL
DL
8
11
11
IN_L-
AGND
IN_L-
AGND
8
4
8
4
GND
PGND
PGND
7
10
10
SO/SO-EP
THIN QFN
THIN QFN
Pin Configurations
TOP VIEW
IN_L+ IN_L- IN_H+
9
8
7
V
1
2
3
4
8
DL
V
1
8
7
6
5
DL
DD
DD
PGND 10
DL 11
6
5
4
IN_H-
BBM
BST
DH
HS
7
6
5
GND
IN_L
IN_H
BST
2
3
4
GND
IN_L
IN_H
MAX5062A/B
MAX5063A/B
MAX5062C/D
MAX5063C/D
MAX5064A/
MAX5064B
DH
HS
V
DD
12
AGND
1
2
3
SO
SO-EP
BST
DH
HS
THIN QFN
16 ______________________________________________________________________________________
125V/2A, High-Speed,
Half-Bridge MOSFET Drivers
Typical Operating Circuit
V
IN
= 125V
V
DD
8V TO 12.6V
MAX5064A/
MAX5064B
BST
PWM IN
IN_H+
IN_H-
C
C
BST
DH
HS
V
OUT
V
DD
IN_L+
DD
DL
V
IN_L-
BBM
DD
PGND
AGND
C
BBM
R
BBM
Selector Guide (continued)
PART
HIGH-SIDE DRIVER
Noninverting
LOW-SIDE DRIVER
Noninverting
Inverting
LOGIC LEVELS
PIN COMPATIBLE
MAX5063AASA
MAX5063BASA
MAX5063CASA
MAX5063DASA
TTL
TTL
TTL
TTL
HIP2101IB
Noninverting
—
—
—
Noninverting
Noninverting
Inverting
Noninverting
Both Inverting and
Noninverting
Both Inverting and
Noninverting
MAX5064AATC
MAX5064BATC
CMOS (V / 2)
DD
—
—
Both Inverting and
Noninverting
Both Inverting and
Noninverting
TTL
Ordering Information (continued)
Chip Information
TRANSISTOR COUNT: 790
PROCESS: HV BiCMOS
TEMP PIN-
TOP
PKG
PART
RANGE PACKAGE MARK
CODE
-40°C to
+125°C
MAX5063AASA
MAX5063BASA
MAX5063CASA
MAX5063DASA
MAX5064AATC
MAX5064BATC
8 SO
—
—
S8-5
S8-5
-40°C to
+125°C
8 SO
-40°C to
+125°C
8 SO-EP*
8 SO-EP*
12 TQFN
12 TQFN
—
S8E-14
S8E-14
T1244-4
T1244-4
-40°C to
+125°C
—
-40°C to
+125°C
AAEF
AAEG
-40°C to
+125°C
*EP = Exposed paddle.
Devices are available in both leaded and lead-free packaging.
Specify lead-free by replacing “-T” with “+T” when ordering.
______________________________________________________________________________________ 17
125V/2A, High-Speed,
Half-Bridge MOSFET Drivers
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
PACKAGE OUTLINE
8L SOIC, .150" EXPOSED PAD
1
21-0111
C
1
18 ______________________________________________________________________________________
125V/2A, High-Speed,
Half-Bridge MOSFET Drivers
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
______________________________________________________________________________________ 19
125V/2A, High-Speed,
Half-Bridge MOSFET Drivers
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
Revision History
Pages changed at Rev 5: 1, 2, 4, 5, 11–15, 19, 20
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
20 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2007 Maxim Integrated Products
is a registered trademark of Maxim Integrated Products, Inc.
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MAXIM
MAX5065|MAX5067
Dual-Phase. +0.6V to +3.3V Output Parallelable. Average-Current-Mode Controllers
MAXIM
MAX5066
Configurable, Single-/Dual-Output, Synchronous Buck Controller for High-Current Applications
MAXIM
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