MAX5812PEUT-T [ROCHESTER]
SERIAL INPUT LOADING, 4us SETTLING TIME, 12-BIT DAC, PDSO6, MINIATURE, SOT-23, 6 PIN;
| 型号： | MAX5812PEUT-T |
| 厂家： | 
Rochester Electronics |
| 描述： | SERIAL INPUT LOADING, 4us SETTLING TIME, 12-BIT DAC, PDSO6, MINIATURE, SOT-23, 6 PIN 输入元件 信息通信管理 光电二极管 转换器 |
| 文件： | 总16页 (文件大小：1018K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-2340; Rev 0; 1/02
12-Bit Low-Power, 2-Wire, Serial
Voltage-Output DAC
General Description
Features
The MAX5812 is a single, 12-bit voltage-output, digital-to-
analog converter (DAC) with an I2C™-compatible 2-wire
interface that operates at clock rates up to 400kHz. The
device operates from a single 2.7V to 5.5V supply and
o Ultra-Low Supply Current
100µA at V
130µA at V
= 3.6V
= 5.5V
DD
DD
o 300nA Low-Power Power-Down Mode
o Single 2.7V to 5.5V Supply Voltage
draws only 100µA at V
= 3.6V. A low-power power-
DD
down mode decreases current consumption to less than
1µA. The MAX5812 features three software-selectable
power-down output impedances: 100kΩ, 1kΩ, and high
impedance. Other features include an internal precision
o Fast 400kHz I2C-Compatible 2-Wire Serial
Interface
®
Rail-to-Rail output buffer and a power-on reset circuit
o Schmitt-Trigger Inputs for Direct Interfacing to
that powers up the DAC in the 100kΩ power-down mode.
Optocouplers
The MAX5812 features a double-buffered I2C-compatible
serial interface that allows multiple devices to share a sin-
gle bus. All logic inputs are CMOS-logic compatible and
buffered with Schmitt triggers, allowing direct interfacing
to optocoupled and transformer-isolated interfaces. The
MAX5812 minimizes digital noise feedthrough by discon-
necting the clock (SCL) signal from the rest of the device
when an address mismatch is detected.
o Rail-to-Rail Output Buffer Amplifier
o Three Software-Selectable Power-Down Output
Impedances
100kΩ, 1kΩ, and High Impedance
o Read-Back Mode for Bus and Data Checking
o Power-On Reset to Zero
The MAX5812 is specified over the extended temperature
range of -40°C to +85°C and is available in a space-sav-
ing 6-pin SOT23 package. Refer to the MAX5811 for the
10-bit version.
o Miniature 6-Pin SOT23 Package
Ordering Information
PIN-
PACKAGE
TOP
MARK
Applications
PART
TEMP RANGE
Digital Gain and Offset Adjustments
Programmable Voltage and Current Sources
Programmable Attenuation
MAX5812LEUT
MAX5812MEUT
MAX5812NEUT
MAX5812PEUT
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
6 SOT23
6 SOT23
6 SOT23
6 SOT23
AAYT
AAYV
AAYX
AAYZ
VCO/Varactor Diode Control
Selector Guide appears at end of data sheet.
Functional Diagram appears at end of data sheet.
Rail-to-Rail is a registered trademark of Nippon Motorola, Ltd.
I2C is a trademark of Philips Corporation.
Low-Cost Instrumentation
Battery-Operated Equipment
Typical Operating Circuit
Pin Configuration
V
DD
TOP VIEW
V
DD
µC
SCL
SDA
R
R
P
P
R
S
1
2
3
6
5
4
V
OUT
ADD
SCL
DD
SCL
SDA
V
DD
R
S
MAX5812
MAX5812
GND
SDA
OUT
MAX5812
R
S
SCL
SDA
V
DD
R
S
SOT23
OUT
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
12-Bit Low-Power, 2-Wire, Serial
Voltage-Output DAC
ABSOLUTE MAXIMUM RATINGS
DD
OUT, ADD to GND........................................-0.3V to V
Maximum Current Into Any Pin ...........................................50mA
V
, SCL, SDA to GND............................................-0.3V to +6V
Operating Temperature Range ...........................-40°C to +85°C
Maximum Junction Temperature .....................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
+ 0.3V
DD
Continuous Power Dissipation (T = +70°C)
A
6-Pin SOT23 (derate 9.1mW above +70°C).................727mW
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
V
= +2.7V to +5.5V, GND = 0, R = 5kΩ, C = 200pF, T = T
to T
, unless otherwise noted. Typical values are at
MAX
DD
L
L
A
MIN
= +5V, T = +25°C.) (Note 1)
A
DD
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
STATIC ACCURACY (Note 2)
Resolution
N
12
Bits
LSB
Integral Nonlinearity
Differential Nonlinearity
Zero-Code Error
INL
(Note 3)
2
16
1
DNL
ZCE
Guaranteed monotonic (Note 3)
LSB
Code = 000 hex, V
Code = FFF hex
= 2.7V
6
2.3
40
mV
ppm/oC
DD
Zero-Code Error Tempco
Gain Error
GE
-0.8
0.26
-3
%FS
ppm/oC
Gain-Error Tempco
DAC OUTPUT
Output Voltage Range
DC Output Impedance
No load (Note 4)
Code = 800 hex
0
V
V
DD
1.2
42.2
15.1
8
Ω
V
V
V
V
= 5V, V
= 3V, V
= 5V
= full scale (short to GND)
= full scale (short to GND)
DD
DD
DD
DD
OUT
OUT
Short-Circuit Current
Wake-Up Time
mA
µs
= 3V
8
Power-down mode = high impedance,
DAC Output Leakage Current
0.1
1
µA
V
= 5.5V, V
= V
or GND
DD
OUT
DD
DIGITAL INPUTS (SCL, SDA)
Input High Voltage
✕
V
0.7
V
V
V
IH
DD
✕
Input Low Voltage
V
0.3
V
DD
IL
✕
Input Hysteresis
0.05
V
V
DD
Input Leakage Current
Input Capacitance
Digital inputs = 0 or V
0.1
6
1
µA
pF
DD
DD
DIGITAL OUTPUT (SDA)
Output Logic Low Voltage
Three-State Leakage Current
Three-State Output Capacitance
DYNAMIC PERFORMANCE
Voltage-Output Slew Rate
V
I
= 3mA
SINK
0.4
1
V
OL
I
Digital inputs = 0 or V
0.1
6
µA
pF
L
SR
0.5
4
V/µs
µs
To 1/2LSB code 400 hex to C00 hex or
C00 hex to 400 hex (Note 5)
Voltage-Output Settling Time
12
2
_______________________________________________________________________________________
12-Bit Low-Power, 2-Wire, Serial
Voltage-Output DAC
ELECTRICAL CHARACTERISTICS (continued)
(V
V
= +2.7V to +5.5V, GND = 0, R = 5kΩ, C = 200pF, T = T
to T
, unless otherwise noted. Typical values are at
MAX
DD
L
L
A
MIN
= +5V, T = +25°C.) (Note 1)
A
DD
PARAMETER
SYMBOL
CONDITIONS
Code = 000 hex, digital inputs from 0 to V
MIN
TYP
MAX
UNITS
Digital Feedthrough
0.2
nV-s
DD
Major carry transition, code = 7FF hex to 800
hex and 800 hex to 7FF hex
Digital-to-Analog Glitch Impulse
12
nV-s
POWER SUPPLIES
Supply Voltage Range
V
2.7
5.5
170
190
1
V
DD
All digital inputs at 0 or V
All digital inputs at 0 or V
= 3.6V
= 5.5V
100
130
0.3
DD
DD
Supply Current with No Load
µA
µA
Power-Down Supply Current
All digital inputs at 0 or V = 5.5V
DD
TIMING CHARACTERISTICS (Figure 1)
Serial Clock Frequency
f
0
400
kHz
µs
SCL
Bus Free Time Between STOP
and START Conditions
t
1.3
BUF
START Condition Hold Time
SCL Pulse Width Low
SCL Pulse Width High
Repeated START Setup Time
Data Hold Time
t
0.6
1.3
0.6
0.6
0
µs
µs
µs
µs
µs
ns
HD, STA
t
LOW
t
HIGH
t
SU, STA
t
0.9
HD, DAT
Data Setup Time
t
100
SU, DAT
SDA and SCL Receiving
Rise Time
t
(Note 5)
(Note 5)
(Note 5)
0
300
300
250
ns
ns
ns
r
SDA and SCL Receiving
Fall Time
t
t
0
f
20 +
0.1C
SDA Transmitting Fall Time
f
b
STOP Condition Setup Time
Bus Capacitance
t
0.6
µs
SU-STO
C
(Note 5)
400
50
.
pF
b
Maximum Duration of
Suppressed Pulse Widths
t
0
ns
SP
Note 1: All devices are 100% production tested at T = +25°C and are guaranteed by design for T = T
to T
MAX
A
A
MIN
Note 2: Static specifications are tested with the output unloaded.
Note 3: Linearity is guaranteed from codes 115 to 3981.
Note 4: Offset and gain error limit the FSR.
Note 5: Guaranteed by design. Not production tested.
_______________________________________________________________________________________
3
12-Bit Low-Power, 2-Wire, Serial
Voltage-Output DAC
Typical Operating Characteristics
(V
= +5V, R = 5kΩ, T = +25°C.)
L A
DD
INTEGRAL NONLINEARITY
vs. INPUT CODE
INTEGRAL NONLINEARITY
vs. SUPPLY VOLTAGE
INTEGRAL NONLINEARITY
vs. TEMPERATURE
4
5
4
3
2
1
0
5
4
3
2
1
0
3
2
1
0
-1
-2
-3
-4
0
1024
2048
3072
4096
2.7
3.4
4.1
4.8
5.5
-40
-40
2.7
-15
10
35
60
85
85
5.5
INPUT CODE
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
DIFFERENTIAL NONLINEARITY
vs. INPUT CODE
DIFFERENTIAL NONLINEARITY
vs. TEMPERATURE
DIFFERENTIAL NONLINEARITY
vs. SUPPLY VOLTAGE
1.00
0.75
0.50
0.25
0
0
0
-0.25
-0.50
-0.25
-0.50
-0.75
-1.00
-0.25
-0.50
-0.75
-1.00
-0.75
-1.00
0
1024
2048
3072
4096
2.7
3.4
4.1
4.8
5.5
-15
10
35
60
INPUT CODE
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
GAIN ERROR
vs. SUPPLY VOLTAGE
ZERO-CODE ERROR
vs. TEMPERATURE
ZERO-CODE ERROR
vs. SUPPLY VOLTAGE
-2.0
-1.6
-1.2
-0.8
-0.4
0
10
8
10
8
6
6
4
4
2
2
NO LOAD
4.8
NO LOAD
NO LOAD
60
0
0
3.4
4.1
2.7
3.4
4.1
4.8
5.5
-40
-15
10
35
85
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
4
_______________________________________________________________________________________
12-Bit Low-Power, 2-Wire, Serial
Voltage-Output DAC
Typical Operating Characteristics (continued)
(V
= +5V, R = 5kΩ, T = +25°C.)
L A
DD
DAC OUTPUT VOLTAGE
vs. OUTPUT SOURCE CURRENT (NOTE 6)
DAC OUTPUT VOLTAGE
vs. OUTPUT SINK CURRENT (NOTE 6)
GAIN ERROR vs. TEMPERATURE
6
5
4
3
2
1
0
-2.0
2.5
2.0
1.5
1.0
0.5
0
-1.6
-1.2
-0.8
-0.4
0
CODE = 400 hex
NO LOAD
CODE = FFF hex
0
2
4
6
8
10
-40
-15
10
35
60
85
4096
5.5
0
2
4
6
8
10
OUTPUT SOURCE CURRENT (mA)
TEMPERATURE (°C)
OUTPUT SINK CURRENT (mA)
SUPPLY CURRENT
vs. INPUT CODE
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
SUPPLY CURRENT
vs. TEMPERATURE
120
100
80
60
40
20
0
100
95
90
85
80
100
90
80
70
60
50
NO LOAD
CODE = FFF hex
CODE = FFF hex
NO LOAD
NO LOAD
819
0
1638
2457
3276
-40
-15
10
35
60
85
2.7
3.4
4.1
4.8
5.5
INPUT CODE
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
POWER-DOWN SUPPLY CURRENT
vs. SUPPLY VOLTAGE
EXITING SHUTDOWN
POWER-UP GLITCH
MAX5812 toc18
MAX5812 toc17
500
400
300
200
100
0
5V
V
DD
T
A
= -40°C
T
A
= +25°C
OUT
500mV/div
0
10mV/div
OUT
T
= +85°C
A
Z
= HIGH IMPEDANCE
OUT
NO LOAD
2µs/div
100µs/div
2.7
3.4
4.1
4.8
C
= 200pF
CODE = 800 hex
LOAD
SUPPLY VOLTAGE (V)
Note 6: The ability to drive loads less than 5kΩ is not implied.
_______________________________________________________________________________________
5
12-Bit Low-Power, 2-Wire, Serial
Voltage-Output DAC
Typical Operating Characteristics (continued)
(V
= +5V, R = 5kΩ, T = +25°C.)
L A
DD
MAJOR CARRY TRANSITION
(POSITIVE)
MAJOR CARRY TRANSITION
(NEGATIVE)
SETTLING TIME
(POSITIVE)
MAX5812 toc19
MAX5812 toc20
MAX5812 toc21
OUT
5mV/div
OUT
5mV/div
OUT
500mV/div
2µs/div
CODE = 7FF hex TO 800 hex
2µs/div
CODE = 7FF hex TO 800 hex
2µs/div
C
L
= 200pF
C
L
= 200pF
C
LOAD
= 200pF
CODE = 400 hex to C00 hex
LOAD
R = 5kΩ
LOAD
R = 5kΩ
SETTLING TIME
(NEGATIVE)
DIGITAL FEEDTHROUGH
MAX5812 toc23
MAX5812 toc22
2V/div
SCL
OUT
500mV/div
2mV/div
OUT
40µs/div
2µs/div
C = 200pF
LOAD
SCL
CODE = 000 hex
C
LOAD
= 200pF
CODE = C00 hex to 400 hex
f
= 12kHz
6
_______________________________________________________________________________________
12-Bit Low-Power, 2-Wire, Serial
Voltage-Output DAC
Pin Description
PIN
1
NAME
FUNCTION
V
Power Supply and DAC Reference Input
DD
2
GND
SDA
SCL
ADD
OUT
Ground
3
Bidirectional Serial Data I/O
4
Serial Clock Line
5
Address Select. A logic high sets the address LSB to 1; a logic low sets the address LSB to 0.
Analog Output
6
swings rail-to-rail and is capable of driving 5kΩ in paral-
lel with 200pF. The output settles to 0.5LSB within 4µs.
Detailed Description
The MAX5812 is a 12-bit, voltage-output DAC with an
I2C/SMBus-compatible 2-wire interface. The device con-
sists of a serial interface, power-down circuitry, input
and DAC registers, a 12-bit resistor string DAC, unity-
gain output buffer, and output resistor network. The seri-
al interface decodes the address and control bits,
routing the data to either the input or DAC register. Data
can be directly written to the DAC register immediately
updating the device output, or can be written to the
input register without changing the DAC output. Both
registers retain data as long as the device is powered.
Power-On Reset
The MAX5812 features an internal power-on-reset
(POR) circuit that initializes the device upon power-up.
The DAC registers are set to zero-scale and the device
is powered down with the output buffer disabled and
the output pulled to GND through the 100kΩ termina-
tion resistor. Following power-up, a wake-up command
must be initiated before conversions are performed.
Power-Down Modes
The MAX5812 has three software-controlled, low-
power, power-down modes. All three modes disable
the output buffer and disconnect the DAC resistor
DAC Operation
The MAX5812 uses a segmented resistor string DAC
architecture, which saves power in the overall system
and guarantees output monotonicity. The MAX5812’s
input coding is straight binary with the output voltage
given by the following equation:
string from V , reducing supply current draw to
DD
300nA. In power-down mode 0, the device output is
high impedance. In power-down mode 1, the device
output is internally pulled to GND by a 1kΩ termination
resistor. In power-down mode 2, the device output is
internally pulled to GND by a 100kΩ termination resis-
tor. Table 1 shows the power-down mode command
words.
V
× (D)
N
REF
2
V
=
OUT
where N = 12(bits), and D = the decimal value of the
input code (0 to 4095).
Upon wake-up, the DAC output is restored to its previ-
ous value. Data is retained in the input and DAC regis-
ters during power-down mode.
Output Buffer
The MAX5812 analog output is buffered by a precision
unity-gain follower that slews 0.5V/µs. The buffer output
Digital Interface
The MAX5812 features an I2C/SMBus-compatible
2-wire interface consisting of a serial data line (SDA)
Table 1. Power-Down Command Bits
POWER-DOWN
COMMAND BITS
MODE/FUNCTION
PD1
PD0
0
0
1
1
0
1
0
1
Power-up device. DAC output restored to previous value.
Power-down mode 0. Powers down device with output floating.
Power-down mode 1. Powers down device with output terminated with 1kΩ to GND.
Power-down mode 2. Powers down device with output terminated with 100kΩ to GND.
_______________________________________________________________________________________
7
12-Bit Low-Power, 2-Wire, Serial
Voltage-Output DAC
SDA
t
SU, STA
t
BUF
t
SU, DAT
t
HD, STA
t
t
SP
SU, STO
t
LOW
t
HD, DAT
SCL
t
HIGH
t
HD, STA
t
t
R
F
START CONDITION
REPEATED START CONDITION
STOP
CONDITION
START
CONDITION
Figure 1. Two-Wire Serial lnterface Timing Diagram
S
Sr
P
and a serial clock line (SCL). The MAX5812 is SMBus
compatible within the range of V
= 2.7V to 3.6V. SDA
DD
SCL
SDA
and SCL facilitate bidirectional communication between
the MAX5812 and the master at rates up to 400kHz.
Figure 1 shows the 2-wire interface timing diagram. The
MAX5812 is a transmit/receive slave-only device, rely-
ing upon a master to generate a clock signal. The mas-
ter, typically a microcontroller, initiates data transfer on
the bus and generates SCL to permit that transfer.
A master device communicates to the MAX5812 by
transmitting the proper address followed by command
and/or data words. Each transmit sequence is framed
Figure 2. START/STOP Conditions
by a START (S) or REPEATED START (S ) condition and
r
a STOP (P) condition. Each word transmitted over the
bus is 8 bits long and is always followed by an
acknowledge clock pulse.
SCL
SDA
The MAX5812 SDA and SCL drivers are open-drain out-
puts, requiring a pullup resistor (500Ω or greater) to
generate a logic high voltage (see the Typical Operating
STOP
START
LEGAL STOP CONDITION
Circuit). Series resistors R are optional. These series
S
resistors protect the input stages of the MAX5812 from
high-voltage spikes on the bus lines and minimize
crosstalk and undershoot of the bus signals.
SCL
SDA
Bit Transfer
One data bit is transferred during each SCL clock
cycle. The data on SDA must remain stable during the
high period of the SCL clock pulse. Changes in SDA
while the SCL is high are control signals (see the
START and STOP Conditions section). SDA and SCL
idle high when the I2C bus is not busy.
ILLEGAL
START
STOP
ILLEGAL EARLY STOP CONDITION
Figure 3. Early STOP condition
START and STOP Conditions
When the serial interface is inactive, SDA and SCL idle
high. A master device initiates communication by issu-
ing a START condition. A START condition is a high-to-
8
_______________________________________________________________________________________
12-Bit Low-Power, 2-Wire, Serial
Voltage-Output DAC
low transition on SDA with SCL high. A STOP condition
2
Table 2. MAX5812 I C Slave Addresses
is a low-to-high transition on SDA while SCL is high
(Figure 2). A START condition from the master signals
the beginning of a transmission to the MAX5812. The
master terminates transmission by issuing a not
acknowledge followed by a STOP condition (see the
Acknowledge Bit section). The STOP condition frees the
DEVICE ADDRESS
PART
V
ADD
(A ...A )
6
0
MAX5812L
MAX5812L
MAX5812M
MAX5812M
MAX5812N
MAX5812N
MAX5812P
MAX5812P
GND
0010 000
0010 001
0010 010
0010 011
0110 100
0110 101
1010 100
1010 101
V
DD
bus. If a repeated START condition (S ) is generated
r
GND
instead of a STOP condition, the bus remains active.
When a STOP condition or incorrect address is detect-
ed, the MAX5812 internally disconnects SCL from the
serial interface until the next START condition, minimiz-
ing digital noise and feedthrough.
V
DD
GND
V
DD
GND
V
DD
Early STOP Conditions
The MAX5812 recognizes a STOP condition at any point
during transmission except when a STOP condition
occurs in the same high pulse as a START condition
(Figure 3). This condition is not a legal I2C format, at
least one clock pulse must separate any START and
STOP conditions.
S
A6
A5
A4
A3
A2
A1
A0
R/W
Figure 4. Slave Address Byte Definition
Repeated START Conditions
A repeated start (S ) condition might indicate a change
r
of data direction on the bus. Such a change occurs
when a command word is required to initiate a read
C3
C2
C1
C0
D11
D10
D9
D8
operation. S also can be used when the bus master is
r
writing to several I2C devices and does not want to
relinquish control of the bus. The MAX5812 serial inter-
face supports continuous write operations with or with-
Figure 5. Command Byte Definition
value bit-by-bit, allowing the interface to power-down
immediately when an incorrect address is detected.
The LSB of the address word is the Read/Write (R/W)
bit. R/W indicates whether the master is writing to or
reading from the MAX5812 (R/W = 0 selects the write
condition, R/W = 1 selects the read condition). After
receiving the proper address, the MAX5812 issues an
ACK by pulling SDA low for one clock cycle.
out an S condition separating them. Continuous read
r
operations require S conditions because of the change
r
in direction of data flow.
Acknowledge Bit (ACK)
The acknowledge bit (ACK) is the ninth bit attached to
any 8-bit data word. ACK is always generated by the
receiving device. The MAX5812 generates an ACK
when receiving an address or data by pulling SDA low
during the ninth clock period. When transmitting data,
the MAX5812 waits for the receiving device to generate
an ACK. Monitoring ACK allows detection of unsuc-
cessful data transfers. An unsuccessful data transfer
occurs if a receiving device is busy or if a system fault
has occurred. In the event of an unsuccessful data
transfer, the bus master should reattempt communica-
tion at a later time.
The MAX5812 has eight factory/user-programmed
addresses (Table 2). Address bits A6 through A1 are
preset; A0 is controlled by ADD. Connecting ADD to
GND sets A0 = 0. Connecting ADD to V
This feature allows up to eight MAX5812s to share a bus.
sets A0 = 1.
DD
Write Data Format
In write mode (R/W = 0), data that follows the address
byte controls the MAX5812 (Figure 5). Bits C3–C0 con-
figure the MAX5812 (Table 3). Bits D11–D0 are DAC
data. Input and DAC registers update on the falling
edge of SCL during the acknowledge bit. Should the
write cycle be prematurely aborted, data will not be
updated and the write cycle must be repeated. Figure
6 shows two example write data sequences.
Slave Address
A bus master initiates communication with a slave
device by issuing a START condition followed by the
7-bit slave address (Figure 4). When idle, the MAX5812
waits for a START condition followed by its slave
address. The serial interface compares each address
_______________________________________________________________________________________
9
12-Bit Low-Power, 2-Wire, Serial
Voltage-Output DAC
Table 3. Command Byte Definitions
SERIAL DATA INPUT
FUNCTION
C3
C2
C1
C0
D11/PD1* D10/PD0*
D9–D8
Load DAC with a new data from the following data byte
and update DAC output simultaneously as soon as data
is available from the serial bus. The DAC and input
registers are updated with the new data.
DAC
DATA
DAC
DATA
DAC
DATA
1
1
0
0
DAC
DATA
DAC
DATA
DAC
DATA
Load input register with the data from the following data
byte. DAC output remains unchanged.
1
1
1
1
1
1
0
1
1
1
0
1
DAC
DATA
DAC
DATA
DAC
DATA
Load input register with data from the following data byte.
Update DAC output to the previously stored data.
Update DAC output from input register. The device will
ignore any new data.
X
X
XX
Read data request. Data bits are ignored. The contents of
the DAC register are available on the bus.
1
0
0
0
1
1
X
X
X
X
X
X
X
0
0
X
0
1
XX
XX
XX
Powers up device.
Power-down mode 0. Powers down device with output
floating.
Power-down mode 1. Powers down device with output
terminated with 1kΩ to GND.
0
0
1
1
X
X
X
X
1
1
0
1
XX
XX
Power-down mode 2. Powers down device with output
terminated with 100kΩ to GND.
*When C3 = 0 and C2 = 1, data bits D11 and D10 write to the power-down registers (PD1 and PD0).
X = Don’t care.
MSB
S
LSB
R/W
MSB
C3
LSB
D8
A6
A5
A4
D6
A4
A3
D5
A3
A2
D4
A2
A1
D3
A1
A0
ACK
C2
C1
C0
D11
D10
D9
ACK
MSB
D7
LSB
D0
D2
D1
ACK
P
EXAMPLE WRITE DATA SEQUENCE
MSB
S
LSB
R/W
MSB
C3
LSB
X
A6
A5
A0
ACK
C2
X
X
PD1
PD0
X
ACK
P
EXAMPLE WRITE TO POWER-DOWN REGISTER SEQUENCE
Figure 6. Example Write Command Sequences
10 ______________________________________________________________________________________
12-Bit Low-Power, 2-Wire, Serial
Voltage-Output DAC
MSB
A6
LSB
MSB
C3
LSB
X
R/W
= 0
S
A4
A3
A2
A1
A0
C2
X
X
X
X
ACK
A5
X
ACK
DATA BYTES GENERATED BY MASTER DEVICE
MSB
A6
LSB
MSB
X
LSB
D8
R/W
= 1
ACK
Sr
A4
A3
A2
A1
A0
ACK
X
PD0
D11
D10
D9
A5
PD1
ACK GENERATED BY
MASTER DEVICE
DATA BYTES GENERATED BY MAX5812
LSB
MSB
D7
D6
D5
D4
D3
D2
D1
D0
ACK
P
Figure 7. Example Read Word Data Sequence
patible only with the 7-bit I2C addressing protocol. Ten-
bit address formats are not supported.
IN
OUT
V
DD
Digital Feedthrough Suppression
When the MAX5812 detects an address mismatch, the
serial interface disconnects the SCL signal from the
core circuitry. This minimizes digital feedthrough
caused by the SCL signal on a static output. The serial
interface reconnects the SCL signal when a valid
START condition is detected.
OUT
MAX6030/
MAX5812
MAX6050
GND
GND
Figure 8. Powering the MAX5812 from An External Reference
Applications Information
Read Data Format
In read mode (R/W = 1), the MAX5812 writes the con-
tents of the DAC register to the bus. The direction of
data flow reverses after the address acknowledge by
the MAX5812. The device transmits the first byte of
data, waits for the master to acknowledge, and then
transmits the second byte. Figure 7 shows an example-
read data sequence.
Powering the Device From an
External Reference
The MAX5812 uses the V
as the DAC voltage refer-
DD
ence. Any power-supply noise is directly coupled to the
device output. The circuit in Figure 8 uses a precision
voltage reference to power the MAX5812, isolating the
device from any power-supply noise. Powering the
MAX5812 in such a manner greatly improves overall
performance, especially in noisy systems. The
MAX6030 (3V, 75ppm/°C) or the MAX6050 (5V,
75ppm/°C) precision voltage references are ideal
choices because of the low power requirements of the
MAX5812.
2
I C Compatibility
The MAX5812 is compatible with existing I2C systems.
SCL and SDA are high-impedance inputs; SDA has an
open drain that pulls the data line low during the ninth
clock pulse. The Typical Operating Circuit shows a typ-
ical I2C application. The communication protocol sup-
ports standard I2C 8-bit communications. The general
call address is ignored. The MAX5812 address is com-
Digital Inputs and Interface Logic
The MAX5812 2-wire digital interface is I2C and SMBus-
compatible. The two digital inputs (SCL and SDA) load
______________________________________________________________________________________ 11
12-Bit Low-Power, 2-Wire, Serial
Voltage-Output DAC
Functional Diagram
V
DD
INPUT
REGISTER
MUX AND DAC
REGISTER
12-BIT
DAC
OUT
RESISTOR
NETWORK
SERIAL
INTERFACE
POWER-DOWN
CIRCUITRY
MAX5812
SDA ADD SCL
GND
the digital input serially into the DAC. Schmitt-trigger
buffered inputs allow slow transition interfaces such as
optocouplers to interface directly to the device. The
digital inputs are compatible with CMOS logic levels.
Chip Information
TRANSISTOR COUNT: 7172
PROCESS: BiCMOS
Power-Supply Bypassing and
Ground Management
Careful PC board layout is important for optimal system
performance. Keep analog and digital signals separate
to reduce noise injection and digital feedthrough. Use a
ground plane to ensure that the ground return from
GND to the power supply ground is short and low
impedance. Bypass V
with a 0.1µF capacitor to
DD
ground as close to the device as possible.
Selector Guide
PART
ADDRESS
0010 00X
0010 01X
0110 10X
1010 10X
MAX5812LEUT
MAX5812MEUT
MAX5812NEUT
MAX5812PEUT
12 ______________________________________________________________________________________
12-Bit Low-Power, 2-Wire, Serial
Voltage-Output DAC
Package Information
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 13
© 2002 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
ENG LIS H • ? ? ? ? • ? ? ? • ? ?
WH AT' S N EW
PRO DU CT S
S OL UT IO NS
D ESIGN
A PPNOTES
SU PPORT
B U Y
CO MPA N Y
M EMB ERS
M a x i m > P r o d u c t s > D i g i t a l - t o - A n a l o g C o n v e r t e r s A u t o m o t i v e
M A X 5 8 1 2
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Q u i c k V i e w
T e c h n i c a l D o c u m e n t s
O r d e r i n g I n f o
M o r e I n f o r m a t i o n
A l l
O r d e r i n g I n f o r m a t i o n
N o t e s :
1 . O t h e r o p t i o n s a n d l i n k s f o r p u r c h a s i n g p a r t s a r e l i s t e d a t : h t t p : / / w w w . m a x i m - i c . c o m / s a l e s .
2 . D i d n ' t F i n d W h a t Y o u N e e d ? A s k o u r a p p l i c a t i o n s e n g i n e e r s . E x p e r t a s s i s t a n c e i n f i n d i n g p a r t s , u s u a l l y w i t h i n o n e
b u s i n e s s d a y .
3 . P a r t n u m b e r s u f f i x e s : T o r T & R = t a p e a n d r e e l ; + = R o H S / l e a d - f r e e ; # = R o H S / l e a d - e x e m p t . M o r e : S e e F u l l D a t a
S h e e t o r P a r t N a m i n g C o n v e n t i o n s .
4 . * S o m e p a c k a g e s h a v e v a r i a t i o n s , l i s t e d o n t h e d r a w i n g . " P k g C o d e / V a r i a t i o n " t e l l s w h i c h v a r i a t i o n t h e p r o d u c t u s e s .
D e v i c e s : 1 - 1 0 o f 1 0
M A X 5 8 1 2
F r e e
B uy
T e m p
R o H S/ L e a d - F r e e ?
M a t e r i a l s A n a l y s i s
P
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S O T - 2 3 ; 6 p i n ; 9 m m
D w g : 2 1 - 0 0 5 8 I ( P D F )
- 4 0 C t o + 8 5 C R o H S / L e a d - F r e e : R o H S Q u a l i f i e
M a t e r i a l s A n a l y s i s
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M A X 5 8 1 2 M E U T # G 1 6
M A X 5 8 1 2 P E U T
S O T - 2 3 ; 6 p i n ; 9 m m
D w g : 2 1 - 0 0 5 8 I ( P D F )
U s e p k g c o d e / v a r i a t i o n : U 6 F H - 6 *
- 4 0 C t o + 8 5 C R o H S / L e a d - F r e e : R o H S Q u a l i f i e
M a t e r i a l s A n a l y s i s
S O T - 2 3 ; 6 p i n ; 9 m m
D w g : 2 1 - 0 0 5 8 I ( P D F )
- 4 0 C t o + 8 5 C R o H S / L e a d - F r e e : N o
M a t e r i a l s A n a l y s i s
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D w g : 2 1 - 0 0 5 8 I ( P D F )
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M a t e r i a l s A n a l y s i s
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M A X 5 8 1 2 M E U T
M A X 5 8 1 2 L E U T
S O T - 2 3 ; 6 p i n ; 9 m m
D w g : 2 1 - 0 0 5 8 I ( P D F )
U s e p k g c o d e / v a r i a t i o n : U 6 F - 6 *
- 4 0 C t o + 8 5 C R o H S / L e a d - F r e e : N o
M a t e r i a l s A n a l y s i s
S O T - 2 3 ; 6 p i n ; 9 m m
D w g : 2 1 - 0 0 5 8 I ( P D F )
- 4 0 C t o + 8 5 C R o H S / L e a d - F r e e : N o
M a t e r i a l s A n a l y s i s
U s e p k g c o d e / v a r i a t i o n : U 6 F - 6 *
M A X 5 8 1 2 P E U T - T
M A X 5 8 1 2 N E U T - T
M A X 5 8 1 2 M E U T - T
M A X 5 8 1 2 L E U T - T
S O T - 2 3 ; 6 p i n ; 9 m m
D w g : 2 1 - 0 0 5 8 I ( P D F )
U s e p k g c o d e / v a r i a t i o n : U 6 F - 6 *
- 4 0 C t o + 8 5 C R o H S / L e a d - F r e e : N o
M a t e r i a l s A n a l y s i s
S O T - 2 3 ; 6 p i n ; 9 m m
D w g : 2 1 - 0 0 5 8 I ( P D F )
U s e p k g c o d e / v a r i a t i o n : U 6 F - 6 *
- 4 0 C t o + 8 5 C R o H S / L e a d - F r e e : N o
M a t e r i a l s A n a l y s i s
S O T - 2 3 ; 6 p i n ; 9 m m
D w g : 2 1 - 0 0 5 8 I ( P D F )
U s e p k g c o d e / v a r i a t i o n : U 6 F - 6 *
- 4 0 C t o + 8 5 C R o H S / L e a d - F r e e : N o
M a t e r i a l s A n a l y s i s
S O T - 2 3 ; 6 p i n ; 9 m m
D w g : 2 1 - 0 0 5 8 I ( P D F )
- 4 0 C t o + 8 5 C R o H S / L e a d - F r e e : N o
M a t e r i a l s A n a l y s i s
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N e x t D a y P r o d u c t S e l e c t i o n A s s i s t a n c e f r o m A p p l i c a t i o n s E n g i n e e r s
P a r a m e t r i c S e a r c h
A p p l i c a t i o n s H e l p
Q u i c k V i e w
T e c h n i c a l D o c u m e n t s
O r d e r i n g I n f o
M o r e I n f o r m a t i o n
D e s c r i p t i o n
D a t a S h e e t
A p p l i c a t i o n N o t e s
D e s i g n G u i d e s
E n g i n e e r i n g J o u r n a l s
R e l i a b i l i t y R e p o r t s
S o f t w a r e / M o d e l s
E v a l u a t i o n K i t s
P r i c e a n d A v a i l a b i l i t y
S a m p l e s
B u y O n l i n e
P a c k a g e I n f o r m a t i o n
L e a d - F r e e I n f o r m a t i o n
R e l a t e d P r o d u c t s
N o t e s a n d C o m m e n t s
E v a l u a t i o n K i t s
K e y F e a t u r e s
A p p l i c a t i o n s / U s e s
K e y S p e c i f i c a t i o n s
D i a g r a m
D o c u m e n t R e f . : 1 9 - 2 3 4 0 ; R e v 0 ; 2 0 0 2 - 0 2 - 2 2
T h i s p a g e l a s t m o d i f i e d : 2 0 0 7 - 0 7 - 3 0
C O N T A C T U S : S E N D U S A N E M A I L
C o p y r i g h t 2 0 0 7 b y M a x i m I n t e g r a t e d P r o d u c t s , D a l l a s S e m i c o n d u c t o r • L e g a l N o t i c e s • P r i v a c y P o l i c y
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