MAX8709ETI [ROCHESTER]
VACUUM FLUOR DISPLAY DRIVER, QCC28, 5 X 5 MM, 0.80 MM HEIGHT, MO220WHHD-1, TQFN-28;
| 型号： | MAX8709ETI |
| 厂家： | 
Rochester Electronics |
| 描述： | VACUUM FLUOR DISPLAY DRIVER, QCC28, 5 X 5 MM, 0.80 MM HEIGHT, MO220WHHD-1, TQFN-28 驱动 信息通信管理 接口集成电路 |
| 文件： | 总25页 (文件大小：1645K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-3177; Rev 1; 3/05
High-Efficiency CCFL Backlight
Controller with SMBus Interface
General Description
Features
♦ Synchronized to Resonant Frequency
The MAX8709/MAX8709A integrated backlight controller
are optimized to drive cold-cathode fluorescent lamps
(CCFLs) using a resonant full-bridge inverter architecture.
The resonant operation maximizes striking capability and
provides near-sinusoidal waveforms over the entire input
range to improve CCFL lifetime. The controller operates
over a wide input voltage range of 4.6V to 28V with high
power-to-light efficiency. The device also includes safety
features that effectively protect against many single-point
fault conditions including lamp-out and short-circuit faults.
Longer Lamp Life
Guaranteed Striking Capability
High Power-to-Light Efficiency
♦ Wide Input Voltage Range (4.6V to 28V)
♦ Feed Forward for Excellent Line Rejection
♦ SMBus Dimming Control Interface
♦ 10:1 Dimming Range
The MAX8709/MAX8709A achieve 10:1 dimming range
by “chopping” the lamp current on and off using a digital
pulse-width-modulation (DPWM) method. The minimum
DPWM duty cycle of the MAX8709 is 9.375% and the
minumum duty cycle of the MAX8709A is 12.5%. The
brightness is controlled with a 2-wire SMBus™-compati-
ble interface. The device directly drives the four external
N-channel power MOSFETs of the full-bridge inverter. An
internal 5.3V linear regulator powers the MOSFET dri-
vers, the DPWM oscillator, and most of the internal cir-
cuitry. The MAX8709/MAX8709A are available in a
space-saving 28-pin thin QFN package and operates
over a -40°C to +85°C temperature range.
♦ Guaranteed 200Hz to 220Hz DPWM Frequency
♦ Secondary Voltage Limit Reduces Transformer
Stress
♦ Adjustable Lamp-Out Protection with 1s Timer
♦ Secondary Current Limit Protects Against High-
Voltage Short Circuits to Ground
♦ Small 5mm x 5mm Thin QFN Package
Ordering Information
PART
TEMP RANGE PIN-PACKAGE
Applications
MAX8709ETI
MAX8709AETI
-40°C to +85°C 28 Thin QFN 5mm x 5mm
-40°C to +85°C 28 Thin QFN 5mm x 5mm
Notebook Computer Displays
LCD TVs
LCD Monitors
SMBus is a trademark of Intel Corp.
Automotive Displays
Pin Configuration appears at end of data sheet.
Minimal Operating Circuit
V
IN
BATT
GND
V
V
CC
DD
BST2
LOT
REF
BST1
GH1
MAX8709/
MAX8709A
LX1
LX2
GL1
ILIM
CCV
CCI
PGND
GL2
GH2
VFB
SUS
SDA
SCL
ISEC
IFB
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
High-Efficiency CCFL Backlight
Controller with SMBus Interface
ABSOLUTE MAXIMUM RATINGS
BATT to GND..........................................................-0.3V to +30V
BST1, BST2 to GND ...............................................-0.3V to +36V
BST1 to LX1, BST2 to LX2........................................-0.3V to +6V
IFB, ISEC, VFB to GND................................................-6V to +6V
SDA, SCL, SUS to GND............................................-0.3V to +6V
PGND to GND .......................................................-0.3V to +0.3V
GH1 to LX1 ..............................................-0.3V to (V
GH2 to LX2 ..............................................-0.3V to (V
+ 0.3V)
+ 0.3V)
Continuous Power Dissipation (T = +70°C)
BST1
BST2
A
28-Pin Thin QFN (derate 20.84mW/°C above +70°C) ..1667mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
V
, V
to GND .....................................................-0.3V to +6V
CC DD
REF, ILIM to GND.......................................-0.3V to (V + 0.3V)
CC
DD
GL1, GL2 to GND.......................................-0.3V to (V + 0.3V)
CCI, CCV, LOT to GND ............................................-0.3V to +6V
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1. V
= 12V, V
= V
, V
REF CC
= V
V
= 5.3V, T = 0°C to +85°C. Typical values are at T = +25°C,
BATT
LOT
DD, SUS
A
A
unless otherwise noted.)
PARAMETER
CONDITIONS
= V
MIN
4.6
TYP
MAX
5.5
28.0
3
UNITS
V
V
= V
= V
CC
CC
DD
DD
BATT
V
Input Voltage Range
V
BATT
= open
5.5
V
V
= 28V
1.5
BATT
BATT
V
V
V
V
V
Quiescent Current
V
= 5.5V
mA
µA
V
BATT
BATT
SUS
= V
= 5V
3
CC
Quiescent Current, Shutdown
SUS = GND
= 5.5V, 6V < V
6
20
V
0 < I
< 28V,
BATT
SUS
Output Voltage, Normal Operation
Output Voltage, Shutdown
5.0
3.5
5.35
4.6
5.5
CC
CC
CC
< 20mA
LOAD
SUS = GND, no load
5.5
4.5
V
V
V
rising (leaving lockout)
CC
CC
Undervoltage-Lockout Threshold
V
falling (entering lockout)
4.0
V
V
V
Undervoltage-Lockout Hysteresis
Power-On Reset (POR) Threshold
POR Hysteresis
200
1.75
50
mV
V
CC
CC
CC
Rising edge
0.90
1.96
2.70
mV
V
REF Output Voltage, Normal Operation
GH1, GH2, GL1, GL2 On-Resistance
GH1, GH2, GL1, GL2 Output Current
BST1, BST2 Leakage Current
Input Resonant Frequency
4.5V < V
< 5.5V, I
= 40µA
2.00
9
2.04
18
CC
LOAD
I
= 100mA, V
= V = 5.3V
DD
Ω
TEST
CC
0.5
A
V
_ = 12V, V _ = 7V
5
µA
kHz
ns
µs
BST
LX
Guaranteed by design
25
180
18
300
380
38
Minimum Off-Time
280
28
Maximum Off-Time
Current-Limit Threshold
LX1 - GND, LX2 - GND (Fixed)
ILIM = V
180
200
220
mV
mV
mV
CC
V
V
= 0.5V
= 2.0V
80
100
400
120
430
ILIM
ILIM
Current-Limit Threshold
LX1 - GND, LX2 - GND (Adjustable)
370
Minimum Current Threshold
LX1 - GND, LX2 - GND
6
2
_______________________________________________________________________________________
High-Efficiency CCFL Backlight
Controller with SMBus Interface
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1. V
= 12V, V
= V
, V
REF CC
= V
V
= 5.3V, T = 0°C to +85°C. Typical values are at T = +25°C,
BATT
LOT
DD, SUS A A
unless otherwise noted.)
PARAMETER
CONDITIONS
MIN
0.5
-2
TYP
MAX
UNITS
V
LOT Input Voltage Range
LOT Input Bias Current
IFB Input Voltage Range
IFB Regulation Point
V
REF
+2
+1.7
420
+2
µA
V
-1.7
380
-2
400
mV
µA
mV
µS
MΩ
V
IFB Input Bias Current
IFB Lamp-Out Threshold
V
= 0.4V
IFB
LOT = REF
1V < V < 2.5V
500
600
100
20
700
IFB to CCI Transconductance
CCI Output Impedance
ISEC Input Voltage Range
ISEC Regulation Threshold
ISEC Input Bias Current
VFB Input Voltage Range
VFB Input Bias Current
CCI
-2
1.20
-2
+2
1.30
+2
1.25
V
V
V
= 1.25V
= 0.5V
µA
V
ISEC
-2
+2
-0.5
490
+0.5
530
µA
mV
µS
mV
MΩ
VFB
VFB Regulation Point
510
40
VFB to CCV Transconductance
1V < V
< 2.7V
CCV
VFB Zero-Voltage Crossing Threshold
CCV Output Impedance
-10
+10
20
MAX8709
200
204
1.14
210
210
1.22
220
216
1.30
0.8
Digital PWM Chopping Frequency
Hz
MAX8709A
Lamp-Out Detection Timeout Timer
SDA, SCL, SUS Input Low Voltage
SDA, SCL, SUS Input High Voltage
SDA, SCL, SUS Input Hysteresis
SDA, SCL, SUS Input Bias Current
SDA Output Low Sink Current
SCL Serial Clock High Period
SCL Serial Clock Low Period
Start-Condition Setup Time
V
< 0.1V (Note 1)
s
V
IFB
2.1
V
300
mV
µA
mA
µs
µs
µs
µs
-1
4
+1
V
= 0.4V
SDA
HIGH
LOW
T
T
4
4.7
4.7
4
t
t
SU:STA
HD:STA
Start-Condition Hold Time
SDA Valid to SCL Rising-Edge Setup Time,
Slave Clocking-In Data
t
t
250
0
ns
ns
ns
SU:DAT
HD:DAT
SCL Falling Edge to SDA Transition
SCL Falling Edge to SDA Valid,
Reading Out Data
T
700
DV
_______________________________________________________________________________________
3
High-Efficiency CCFL Backlight
Controller with SMBus Interface
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1. V
= 12V, V
= V
, V
REF CC
= V
V
= 5.3V, T = -40°C to +85°C. Typical values are at T = +25°C,
BATT
LOT
DD, SUS A A
unless otherwise noted.) (Note 2)
PARAMETER
CONDITIONS
MIN
4.6
TYP
MAX
5.5
28.0
3
UNITS
V
V
= V
= V
= V
BATT
CC
CC
DD
DD
V
Input Voltage Range
Quiescent Current
V
BATT
= open
5.5
V
V
= 28V
BATT
BATT
V
V
V
V
V
V
V
= 5.5V
mA
µA
V
BATT
BATT
SUS
= V
= 5V
3
CC
Quiescent Current, Shutdown
SUS = GND
= 5.5V, 6V < V
20
V
0 < I
< 28V,
BATT
SUS
Output Voltage, Normal Operation
Output Voltage, Shutdown
5.0
3.5
5.5
CC
CC
CC
CC
< 20mA
LOAD
SUS = GND, no load
5.5
4.5
V
V
V
rising (leaving lockout)
CC
CC
Undervoltage-Lockout Threshold
V
falling (entering lockout)
4.0
Power-On Reset (POR) Threshold
Rising edge
4.5V < V < 5.5V, I
0.90
1.95
2.70
2.05
18
V
V
REF Output Voltage, Normal Operation
GH1, GH2, GL1, GL2 On-Resistance
BST1, BST2 Leakage Current
Input Resonant Frequency
Minimum Off-Time
= 40µA
LOAD
CC
I
= 100mA, V
= V = 5.3V
DD
Ω
TEST
CC
V
_ = 12V, V _ = 7V
5
µA
kHz
ns
µs
BST
LX
Guaranteed by design
25
180
18
300
380
38
Maximum Off-Time
Current-Limit Threshold
LX1 - GND, LX2 - GND (Fixed)
ILIM = V
180
220
mV
mV
CC
V
V
= 0.5V
= 2.0V
80
370
250
0.5
-2
120
430
450
ILIM
ILIM
Current-Limit Threshold
LX1 - GND, LX2 - GND (Adjustable)
Current-Limit Leading-Edge Blanking
LOT Input Voltage Range
LOT Input Bias Current
ns
V
V
REF
+2
+1.7
420
+2
µA
V
IFB Input Voltage Range
IFB Regulation Point
-1.7
380
-2
mV
µA
mV
V
IFB Input Bias Current
V
= 0.4V
IFB
IFB Lamp-Out Threshold
ISEC Input Voltage Range
ISEC Regulation Point
LOT = REF
500
-2
700
+2
1.20
-2
1.30
+2
V
ISEC Input Bias Current
VFB Input Voltage Range
VFB Input Bias Current
V
V
= 1.25V
= 0.5V
µA
V
ISEC
-2
+2
-0.5
490
-10
200
204
+0.5
530
+10
220
216
µA
mV
mV
VFB
VFB Regulation Point
VFB Zero-Voltage Crossing Threshold
MAX8709
Digital PWM Chopping Frequency
Hz
MAX8709A
4
_______________________________________________________________________________________
High-Efficiency CCFL Backlight
Controller with SMBus Interface
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1. V
= 12V, V
= V
, V
REF CC
= V
V
= 5.3V, T = -40°C to +85°C. Typical values are at T = +25°C,
BATT
LOT
DD, SUS A A
unless otherwise noted.) (Note 2)
PARAMETER
Lamp-Out Detection Timeout Timer
SDA, SCL, SUS Input Low Voltage
SDA, SCL, SUS Input High Voltage
SDA, SCL, SUS Input Bias Current
SDA Output Low Sink Current
SCL Serial Clock High Period
SCL Serial Clock Low Period
Start-Condition Setup Time
CONDITIONS
< 0.1V (Note 1)
MIN
TYP
MAX
1.30
0.8
UNITS
s
V
1.14
IFB
V
2.1
-1
4
V
+1
µA
mA
µs
V
= 0.4V
SDA
HIGH
LOW
T
T
4
4.7
4.7
4
µs
t
t
µs
SU:STA
HD:STA
Start-Condition Hold Time
µs
SDA Valid to SCL Rising-Edge Setup Time,
Slave Clocking-In Data
t
250
0
ns
ns
SU:DAT
HD:DAT
SCL Falling Edge to SDA Transition
t
Note 1: Corresponds to 256 DPWM cycles.
Note 2: Specifications to -40°C are guaranteed by design based on final characterization results.
Typical Operating Characteristics
(Circuit of Figure 1. V
= 12V, V
= V
, V
REF CC
= V
V
= 5.3V, T = +25°C, unless otherwise noted.)
BATT
LOT
DD, SUS A
LOW INPUT-VOLTAGE
OPERATION (V = 8V)
HIGH INPUT-VOLTAGE
OPERATION (V = 20V)
LINE-TRANSIENT RESPONSE
BATT
BATT
MAX8709 toc01
MAX8709 toc03
MAX8709 toc02
0V
0V
A
B
0V
0V
A
B
A
B
C
8V
0V
0V
0V
C
D
C
D
0V
0V
0V
0V
D
10µs/div
40µs/div
10µs/div
A: V , 2V/div
IFB
A: V
B: V , 2V/div
C: V , 2V/div
VFB
D: V , 10V/div
, 5V/div
A: V , 2V/div
BATT
IFB
IFB
B: V , 2V/div
B: V , 2V/div
VFB
VFB
C: V , 10V/div
LX1
C: V , 10V/div
LX1
D: V , 10V/div
D: V , 10V/div
LX2
LX1
LX2
_______________________________________________________________________________________
5
High-Efficiency CCFL Backlight
Controller with SMBus Interface
Typical Operating Characteristics (continued)
(Circuit of Figure 1. V
= 12V, V
= V
, V
REF CC
= V
V
= 5.3V, T = +25°C, unless otherwise noted.)
BATT
LOT
DD, SUS A
DPWM OPERATION (50%)
DPWM OPERATION (10%)
STARTUP
MAX8709 toc06
MAX8709 toc05
MAX8709 toc04
A
B
A
B
A
B
0V
0V
1.2V
0V
1.2V
0V
C
D
0V
0V
C
0V
C
0V
1ms/div
2ms/div
1ms/div
A: V , 200mV/div
A: V , 5V/div
SUS
CCV
A: V , 200mV/div
CCV
B: V , 1V/div
B: V , 2V/div
IFB
IFB
B: V , 1V/div
C: V , 1V/div
VFB
IFB
C: V , 2V/div
VFB
C: V , 1V/div
VFB
D: V , 10V/div
LX1
LAMP-OUT VOLTAGE
LIMITING AND TIMEOUT
DPWM SOFT-STOP
DPWM SOFT-START
MAX8709 toc08
MAX8709 toc07
MAX8709 toc09
CCI
CCI
A
0V
1.2V
CCV
CCV
A
B
A
B
0V
0V
0V
B
0V
0V
200ms/div
40µs/div
40µs/div
A: V , 1V/div
B: V , 1V/div
IFB
VFB
A: V , 1V/div
A: V , 1V/div
IFB
IFB
B: V , 1V/div
B: V , 1V/div
VFB
VFB
6
_______________________________________________________________________________________
High-Efficiency CCFL Backlight
Controller with SMBus Interface
Typical Operating Characteristics (continued)
(Circuit of Figure 1. V
= 12V, V
= V
, V
REF CC
= V
V
= 5.3V, T = +25°C, unless otherwise noted.)
BATT
LOT
DD, SUS A
SWITCHING FREQUENCY
vs. INPUT VOLTAGE
ELECTRICAL EFFICIENCY
vs. INPUT VOLTAGE
DPWM FREQUENCY
vs. INPUT VOLTAGE
100
90
80
70
60
50
62
58
54
50
46
220
215
210
205
200
7
10
13
16
19
22
25
7
10
13
16
19
22
25
7
10
13
16
19
22
25
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
NORMALIZED BRIGHTNESS
vs. BRIGHTNESS CODE
NORMALIZED RMS LAMP CURRENT
vs. INPUT VOLTAGE
REF LOAD REGULATION
100
80
60
40
20
0
0.8
0.6
0.4
0.2
0
0.10
0.05
0
-0.05
-0.10
-0.15
-0.2
-0.4
-0.6
-0.8
0
4
8
12 16 20 24 28 32
BRIGHTNESS CODE
7
10
13
16
19
22
25
0
20
40
60
80
100
INPUT VOLTAGE (V)
REF LOAD CURRENT (µA)
REF OUTPUT vs. TEMPERATURE
V
CC
LOAD REGULATION
NORMALIZED V LINE REGULATION
CC
0.05
0
0
0.2
0
V
= 5.3V
CC
-0.3
-0.6
-0.9
-1.2
-1.5
-0.05
-0.10
-0.15
-0.20
-0.25
-0.2
-0.4
-0.6
-0.8
-1.0
-40 -20
0
20
40
60
80 100
0
4
8
12
16
20
5
10
15
20
25
EXTERNAL LOAD CURRENT (mA)
TEMPERATURE (°C)
INPUT VOLTAGE (V)
_______________________________________________________________________________________
7
High-Efficiency CCFL Backlight
Controller with SMBus Interface
Pin Description
PIN
NAME
FUNCTION
Current-Limit Threshold Adjustment. Connect a resistive voltage-divider between REF or V
and GND.
CC
1
ILIM
The current-limit threshold measured between LX_ and GND is 1/5th the voltage forced at ILIM. The ILIM
adjustment range is 0 to 3V. Connect ILIM to V to select the default current-limit threshold of 0.2V.
CC
2V Reference Output. Bypass REF to GND with a 0.1µF ceramic capacitor. REF is discharged to GND
during shutdown.
2
3
4
5
REF
LOT
Lamp-Out Threshold Adjustment. The lamp-out threshold is 30% of the voltage at LOT. The LOT
adjustment range is from 0.5V to V
.
REF
Analog Ground. The ground return for V , REF, and other analog circuitry. Connect GND to PGND
CC
under the IC at the IC’s backside exposed metal pad.
GND
ISEC
Secondary Current-Limit Sense Input. The secondary current limit controls the transformer secondary
current even if the IFB sense resistor is shorted. See the Secondary Current Limit (ISEC) section.
6
SDA
SCL
SUS
N.C.
SMBus Serial Data Input
7
SMBus Serial Clock Input
8
SMBus Suspend Input
9, 10, 11, 23
No Connection. Not internally connected.
Gate-Driver Supply Input. Connect V
0.1µF capacitor to PGND.
to V , the output of the linear regulator. Bypass V
with a
DD
CC
DD
12
V
DD
13
14
15
16
PGND
GL2
Power Ground. Gate-driver current flows through this pin.
Low-Side MOSFET NL2 Gate-Driver Output
Low-Side MOSFET NL1 Gate-Driver Output
High-Side MOSFET NH1 Gate-Driver Output
GL1
GH1
Switching Node Connection. LX1 is the internal gate driver’s (GH1’s) source connection for the high-side
MOSFET NH1. LX1 is also the sense input to the current comparators.
17
18
19
LX1
Driver Bootstrap Input for High-Side MOSFET NH1. Connect BST1 through a diode to V
0.1µF capacitor to LX1 (Figure 1).
and through a
DD
BST1
BST2
Driver Bootstrap Input for High-Side MOSFET NH2. Connect BST2 through a diode to V
0.1µF capacitor to LX2 (Figure 1).
and through a
DD
Switching Node Connection. LX2 is the internal gate driver’s (GH2’s) source connection for the high-side
MOSFET NH2. LX2 is also the sense input to the current comparators.
20
21
LX2
GH2
High-Side MOSFET NH2 Gate-Driver Output
Lamp Output Feedback Sense Input. The average value on VFB is regulated during startup and open-
lamp conditions to 0.5V by controlling the on-time of high-side switches. A capacitive voltage-divider
between the CCFL lamp output and GND is sensed to set the maximum average lamp output voltage.
22
24
VFB
IFB
Lamp Current-Sense Input. The voltage on IFB is used to regulate the lamp current. If the IFB input falls
below 30% of the LOT voltage for 1.22s, then the MAX8709/MAX8709A activate the lamp-out fault latch.
Current-Loop Compensation Pin. CCI is the output of the current-loop transconductance amplifier (GMI)
that regulates the CCFL current. The CCI voltage controls the time interval during which the full bridge
applies the input voltage (BATT) to the transformer primary. Connect CCI to GND through a 0.1µF
capacitor. CCI is internally discharged to GND in shutdown.
25
CCI
8
_______________________________________________________________________________________
High-Efficiency CCFL Backlight
Controller with SMBus Interface
Pin Description (continued)
PIN
NAME
FUNCTION
Voltage-Loop Compensation Pin. CCV is the output of the voltage-loop transconductance amplifier (GMV)
that regulates the maximum average secondary transformer voltage. The CCV voltage controls the time
interval during which the full bridge applies the input voltage (BATT) to the transformer primary. The CCV
capacitor also sets the rise time and fall time of the lamp current in DPWM. Connect CCV to GND with a
6.8nF capacitor. CCV is internally discharged to GND in shutdown.
26
CCV
MAX8709/MAX8709A Supply Input. Input to the internal 5.3V linear regulator (V ) that provides power to
CC
the device. Bypass BATT to GND with a 0.1µF capacitor.
27
28
BATT
5.3V Linear-Regulator Output. V
is the supply voltage for the MAX8709/MAX8709A. Bypass V
to
CC
CC
V
CC
GND with a 0.47µF ceramic capacitor. V
can also be connected to BATT if V
< 5.5V.
CC
BATT
V
IN
7V TO 24V
C1
4.7µF
25V
BATT
V
V
CC
C8
0.1µF
C7
0.47µF
DD
GND
LOT
D1
BST2
BST1
GH1
REF
C9
0.1µF
R4
NH1 NH2
MAX8709/
MAX8709A
C2
1µF
C6
0.1µF
100kΩ
T1
1:93
CCFL
LX1
LX2
GL1
ILIM
C5
0.1µF
R5
100kΩ
NL1 NL2
C3
15pF
3kV
CCV
CCI
C10
0.01µF
PGND
GL2
GH2
VFB
ISEC
IFB
C11
0.1µF
SMBSUS
SMBDATA
SMBCLK
SUS
SDA
SCL
R1
150Ω
1%
C4
22nF
R2
2kΩ
R3
40.2Ω
1%
Figure 1. Typical Operating Circuit of the MAX8709/MAX8709A
_______________________________________________________________________________________
9
High-Efficiency CCFL Backlight
Controller with SMBus Interface
Figure 2. MAX8709/MAX8709A Functional Diagram
10 ______________________________________________________________________________________
High-Efficiency CCFL Backlight
Controller with SMBus Interface
Table 1. Component List
DESIGNATION
DESCRIPTION
DESIGNATION
DESCRIPTION
0.47µF 10%, 10V X5R
4.7µF 20%, 25V X5R
ceramic capacitor (0603)
Taiyo Yuden LMK107BJ474KA
TDK C1608X5R1A474K
ceramic capacitor (1210)
Murata GRM32RR61E475K
Taiyo Yuden TMK325BJ475MN
TDK C3225X7R1E475M
C7
C1
Dual silicon switching diode,
common anode (SOT-323)
Central Semiconductor CMSD2836
Diodes Incorporated BAW56W
1µF 10%, 25V X7R
D1
ceramic capacitor (1206)
Murata GRM31MR71E105K
Taiyo Yuden TMK316BJ105KL
TDK C3216X7R1E105K
C2
C3
C4
30V, 0.095 dual N-channel MOSFETs
(6-pin SOT23)
Fairchild FDC6561AN
NH1/2, NL1/2
15pF 1pF, 3kVhigh-voltage
ceramic capacitor (1808)
Murata GRM42D1X3F150J
TDK C4520C0G3F150F
R1
R2
150Ω 1% resistor (0603)
2kΩ 5% resistor (0603)
39Ω 1% (resistor (0603)
100kΩ 5% resistors (0603)
R3
R4, R5
0.022µF 10%, 16V X7R
ceramic capacitor (0402)
Murata GRP155R71C223K
Taiyo Yuden EMK105BJ223KV
TDK C1005X7R1C223K
CCFL transformer, 1:93 turns ratio
Sumida 5371-400-W1423
TOKO T912MG-1018
T1
Detailed Description
0.1µF 10%, 25V X7R
ceramic capacitors (0603)
Murata GRM188R71E104K
Taiyo Yuden TMK107BJ104KA
TDK C1608X7R1E104K
The MAX8709/MAX8709A control a full-bridge resonant
inverter to convert an unregulated DC input into a near-
sinusoidal AC output for powering CCFLs. The lamp
brightness is adjusted by turning the lamp on and off
with an internal DPWM signal. The duty cycle of the
DPWM signal is set through an SMBus-compatible 2-
wire serial interface. Figure 2 shows the functional dia-
gram of the MAX8709/MAX8709A.
C5, C6, C8, C9
Table 2. Component Suppliers
SUPPLIER
Central Semiconductor
Fairchild Semiconductor
Murata
WEBSITE
www.centralsemi.com
www.fairchildsemi.com
www.murata.com
Resonant Operation
The MAX8709/MAX8709A drive the four N-channel power
MOSFETs that make up the zero-voltage-switching (ZVS)
full-bridge inverter as shown in Figure 3. Assume that
NH1 and NL2 are turned on at the beginning of a switch-
ing cycle as shown in Figure 3(a). The primary current
flows through MOSFET NH1, DC blocking cap C2, the
primary side of transformer T1, and MOSFET NL2. During
this interval, the primary current ramps up until the con-
troller turns off NH1. When NH1 turns off, the primary cur-
rent forward biases the body diode of NL1, which clamps
the LX1 voltage just below ground as shown in Figure
3(b). When the controller turns on NL1, its drain-to-source
voltage is near zero because its forward-biased body
diode clamps the drain. Since NL2 is still on, the primary
current flows through NL1, C2, the primary side of T1,
and NL2. Once the primary current drops to the minimum
Sumida
www.sumida.com
Taiyo Yuden
www.t-yuden.com
TDK
www.components.tdk.com
Typical Operating Circuit
The Typical Operating Circuit of the MAX8709/
MAX8709A (Figure 1) is a complete CCFL backlight
inverter for notebook TFT LCD panels. The circuit works
over an input voltage range of 7V to 24V with an RMS
lamp current of 6mA. The circuit’s maximum RMS
open-lamp voltage is limited to 1600V. Table 1 lists rec-
ommended component options, and Table 2 lists the
component suppliers’ contact information.
current threshold (6mV / R
), the controller turns off
DS(ON)
NL2. The remaining energy in T1 charges up the LX2
______________________________________________________________________________________ 11
High-Efficiency CCFL Backlight
Controller with SMBus Interface
VBATT
VBATT
NH1
ON
NH2
OFF
NH1
OFF
NH2
ON
T1
T1
C2
C2
LX1
LX2
LX1
LX2
NL1
OFF
NL2
ON
NL1
ON
NL2
OFF
(a)
VBATT
(c)
VBATT
NH1
OFF
NH2
OFF
NH1
OFF
NH2
OFF
T1
T1
C2
C2
LX1
LX2
LX1
LX2
NL1
ON
NL2
ON
NL1
ON
NL2
ON
(BODY DIODE TURNS ON FIRST)
(BODY DIODE TURNS ON FIRST)
(b)
(d)
Figure 3. Resonant Operation
node until the body diode of NH2 is forward biased.
NH1 is forward biased. Finally, NH1 losslessly turns on,
beginning a new cycle as shown in Figure 3(a). Note that
switching transitions on all four power MOSFETs occur
under ZVS conditions, which reduce transient power loss-
es and EMI.
When NH2 turns on, it does so with near-zero drain-to-
source voltage. The primary current reverses polarity as
shown in Figure 3(c), beginning a new cycle with the cur-
rent flowing in the opposite direction, with NH2 and NL1
on. The primary current ramps up until the controller turns
off NH2. When NH2 turns off, the primary current forward
biases the body diode of NL2, which clamps the LX2 volt-
age just below ground as shown in Figure 3(d). After the
LX2 node goes low, the controller losslessly turns on NL2.
Once the primary current drops to the minimum current
threshold, the controller turns off NL1. The remaining
energy charges up the LX1 node until the body diode of
The simplified CCFL inverter circuit is shown in Figure
4(a). The full-bridge power stage is simplified and rep-
resented as a square-wave AC source. The resonant
tank circuit can be further simplified to Figure 4(b) by
removing the transformer. C is the primary series
S
capacitor, C’ is the series capacitance reflected to the
S
secondary, C is the secondary parallel capacitor, N is
P
the transformer turns ratio, L is the transformer sec-
12 ______________________________________________________________________________________
High-Efficiency CCFL Backlight
Controller with SMBus Interface
C
S
L
1:N
4
AC
SOURCE
C
P
CCFL
3
2
1
0
R INCREASING
L
(a)
C
S
C' =
S
N2
L
AC
SOURCE
0
20
40
60
80
100
C
P
R
L
FREQUENCY (kHz)
(b)
Figure 4. Equivalent Resonant Tank Circuit
Figure 5. Frequency Response of the Resonant Tank
ondary leakage inductance, and R is an idealized
L
resistance that models the CCFL in normal operation.
the output voltage of the resonant converter keeps
going until the lamp is ionized.
Figure 5 shows the frequency response of the resonant
tank’s voltage gain under different load conditions. The
primary series capacitor is 1µF, the secondary parallel
capacitor is 15pF, the transformer turns ratio is 1:93,
and the secondary leakage inductance is 260mH.
Once the lamp is ionized, the equivalent load resistance
decreases rapidly and the operating point moves toward
the series resonant peak. The series resonant operation
causes the circuit to behave like a current source.
Current and Voltage Control Loops
(CCI, CCV)
Notice there are two peaks, f and f , in the frequency
S
P
response. The first peak, f , is the series resonant peak
S
The MAX8709/MAX8709A use a current loop and a
voltage loop to control the power delivered to the
CCFL. The current loop is the dominant loop in regulat-
ing the lamp current. The voltage loop limits the trans-
former secondary voltage and is active during startup,
the DPWM off-time, and open-lamp fault.
determined by the reflected series capacitor and the
secondary leakage inductance:
1
f
=
S
2π LC'
S
Both the current and the voltage loops use transcon-
ductance error amplifiers for regulation. The AC lamp
current is measured with a sense resistor in series with
the CCFL. The voltage across this resistor is applied to
the IFB input and is internally half-wave rectified. The
current-loop transconductance error amplifier com-
pares the rectified IFB voltage with a 400mV internal
threshold to create an error current. The error current
charges and discharges a capacitor connected
between CCI and ground to generate an error voltage
The second peak, f , is the parallel resonant peak deter-
P
mined by the reflected series capacitor, the parallel
capacitor, and the secondary leakage inductance:
1
f
=
P
C' C
S
P
2π L
C' + C
S
P
These two frequencies set the lower and upper bound-
aries of resonant operation. When the lamp is off, the
operating point of the resonant tank is close to the paral-
lel resonant peak due to the infinite lamp impedance.
The circuit displays the characteristics of a parallel-
loaded resonant converter, acting like a voltage source
to generate the necessary striking voltage. Theoretically,
V
. Similarly, the AC voltage across the transformer
CCI
secondary winding is measured through a capacitive
voltage-divider. The sense voltage is applied to the
VFB input and is internally half-wave rectified. The volt-
______________________________________________________________________________________ 13
High-Efficiency CCFL Backlight
Controller with SMBus Interface
age-loop transconductance error amplifier compares
the rectified VFB voltage with a 500mV internal thresh-
old to create an error current. The error current charges
and discharges a capacitor connected between CCV
controller’s response to input voltage changes is
essentially instantaneous.
To maximize run time, it may be desirable to allow the
circuit to operate in dropout if the backlight’s perfor-
and ground to generate an error voltage V
. The
CCV
mance is not critical. When V
is very low, the con-
BATT
lower of V
and V
takes control and is compared
CCI
CCV
troller loses current regulation and runs at maximum
duty cycle. Under these circumstances, a transient
overvoltage condition could occur when the AC
adapter is suddenly applied to power the circuit. The
feed-forward circuitry minimizes variations in lamp volt-
age due to such input voltage steps. The regulator also
with an internal ramp signal to set the high-side
MOSFET switch on-time (t ).
ON
Lamp Startup
A CCFL is a gas discharge lamp that is normally driven
in the avalanche mode. To start ionization in a nonion-
ized lamp, the applied voltage (striking voltage) must
be increased to the level required for the start of
avalanche. The striking voltage can be several times
the typical operating voltage.
clamps the voltage on V
. These two features togeth-
CCI
er ensure that overvoltage transients do not appear on
the transformer when leaving dropout.
The V
clamp is unique in that it limits V
to the
CCI
CCI
peak voltage of the PWM ramp. As the circuit reaches
dropout, V approaches the PWM ramp’s peak in
Because of the resonant topology, the striking voltage
is guaranteed regardless of the temperature. Before the
lamp is ionized, the lamp impedance is infinite. The
transformer secondary leakage inductance and the
high-voltage parallel capacitor determine the unloaded
resonant frequency. Since the unloaded resonant cir-
cuit has a high Q, it is easy to generate high voltages
across the lamp.
CCI
order to reach maximum t . If V
decreases fur-
BATT
ON
ther, the control loop loses regulation and V
tries to
CCI
rides just above
continues to decrease,
CCI
reach its positive supply rail. The clamp on V
pre-
vents this from happening and V
CCI
the PWM ramp’s peak. If V
BATT
the feed-forward control reduces the amplitude of the
PWM ramp and the clamp pulls V down. When
CCI
Operation during startup differs from the steady-state
V
suddenly steps out of dropout, V
is still low
BATT
CCI
condition described in the Current and Voltage Control
and maintains the drive on the transformer at the old
dropout level. The control loop then slowly corrects and
Loops section. Upon power-up, V
slowly rises,
CCI
increasing the duty cycle, which provides soft-start.
During this time, V is limited to 150mV above V
increases V
to bring the circuit back into regulation.
CCI
.
CCI
CCV
DPWM Dimming Control
Once the secondary voltage reaches the strike voltage,
the lamp current begins to increase. When the lamp
The MAX8709/MAX8709A control the brightness of the
CCFL by “chopping” the lamp current on and off using an
internal DPWM signal. The frequency of the DPWM signal
is 210Hz. The brightness code set through the SMBus
interface determines the duty cycle of the DPWM signal.
A brightness code of 0b00000 corresponds to a 9.375%
DPWM duty cycle for MAX8709, and a 12.5% duty cycle
for MAX8709A. A brightness code of 0b11111 corre-
sponds to a 100% DPWM duty cycle. The duty cycle
changes by 3.125% per step, but codes 0b00000 to
0b00010 all produce 9.375% for MAX8709 as shown in
Figure 6. Codes 0b00000 to 0b00011 all produce 12.5%
for MAX8709A.
current reaches the regulation point, V
CCV
exceeds
CCI
V
and it reaches steady state.
Feed-Forward Control and
Dropout Operation
The MAX8709/MAX8709A are designed to maintain
tight control of the transformer secondary under all
transient conditions including dropout. The feed-for-
ward control instantaneously adjusts the t
time for
ON
changes in input voltage (V
). This feature provides
BATT
immunity to input voltage variations and simplifies loop
compensation over wide input voltage ranges. The
feed-forward control also improves the line regulation
for short DPWM on-times and makes startup transients
less dependent on the input voltage.
In DPWM operation, the CCI and CCV control loops work
together to regulate the lamp current, limit the secondary
voltage, and control the rising and falling of the lamp cur-
rent. During the DPWM off-cycle, the output of the volt-
age-loop error amplifier (CCV) is set to 1.15V and the
current-loop error-amplifier output (CCI) is high imped-
ance. The high-impedance output acts like a sample-
Feed-forward control is implemented by increasing the
PWM’s internal voltage ramp rate for higher V
. This
BATT
has the effect of varying t
as a function of the input
ON
voltage while maintaining about the same signal levels
at V and V . Since the required voltage change
and-hold circuit to keep V
from changing during the
CCI
CCV
CCI
across the compensation capacitors is minimal, the
off-cycles. At the beginning of the DPWM on-cycle, V
CCV
14 ______________________________________________________________________________________
High-Efficiency CCFL Backlight
Controller with SMBus Interface
Lamp-Out Protection
For safety, the MAX8709/MAX8709A monitor the lamp-
current feedback (IFB) to detect faulty or open CCFL
tubes and secondary short circuits in the lamp and IFB
sense resistor. If the voltage on IFB is continuously
below 30% of the LOT voltage for greater than 1.22s
(typ), the MAX8709/MAX8709A latch off the full bridge.
Unlike the normal shutdown mode, the linear-regulator
DPWM SETTINGS
100
90
80
70
60
50
40
output (V ) remains at 5.3V. Toggling SUS or cycling
CC
the input power reactivates the device.
30
20
10
During the 1.22s delay, V
slowly rises, increasing
CCI
t
in an attempt to maintain lamp current regulation.
ON
As V
rises, V
rises with it until the secondary
CCI
CCV
0
voltage reaches its preset limit. At this point, V
CCV
0
4
8
12 16 20 24 28 32
BRIGHTNESS CODE
stops and limits the secondary voltage by limiting t
.
ON
Because V
is limited to 150mV above V
, the volt-
CCV
CCI
Figure 6. DPWM Settings
age control loop is able to quickly limit the secondary
voltage. Without this clamping feature, the transformer
linearly rises, gradually increasing t , which provides
ON
voltage overshoots to dangerous levels because V
takes time to slew down from its supply rail.
CCV
soft-start. Once V
exceeds V
, the current-loop
CCV
CCI
error amplifier takes control and starts to regulate the
Primary Overcurrent Protection (ILIM)
The MAX8709/MAX8709A sense primary current in each
switching cycle. When the regulator turns on the low-side
MOSFET, a comparator monitors the voltage drop from
LX_ to GND. If the voltage exceeds the current-limit
threshold, the regulator turns off the high-side switch at
the opposite side of the primary to prevent the trans-
former primary current from increasing further.
lamp current. In the meantime, V
continues to rise
CCV
and is limited to 150mV above V . At the end of the
CCI
DPWM on-cycle, the CCV capacitor discharges linearly,
gradually decreasing t
and providing soft-stop.
ON
POR and UVLO
The MAX8709/MAX8709A include power-on-reset
(POR) and undervoltage-lockout (UVLO) circuits. The
POR resets all internal registers such as DAC outputs,
fault latches, and all SMBus registers. POR occurs
The current-limit threshold can be adjusted using the
ILIM input. Connect a resistive voltage-divider between
when V
is below 1.5V. The SMBus input logic thresh-
CC
REF or V
and GND with the midpoint connected to
CC
olds are only guaranteed to meet electrical characteris-
ILIM. The current-limit threshold measured between
LX_ and GND is 1/5th the voltage at ILIM. The ILIM
tic limits for V
as low as 3.5V, but the interface
CC
continues to function down to the POR threshold.
adjustment range is 0 to 3V. Connect ILIM to V
select the default current-limit threshold of 0.2V.
to
CC
The UVLO is activated and disables both high-side and
low-side switch drivers when V
is below 4.2V (typ).
CC
Secondary Current Limit (ISEC)
The secondary current limit provides failsafe current
limiting in case a failure, such as a short circuit or leak-
age from the lamp high-voltage terminal to ground, pre-
vents the CCI current control loop from functioning
properly. ISEC monitors the voltage across a sense
resistor placed between the transformer’s low-voltage
secondary terminal and ground. The ISEC voltage is
internally half-wave rectified and continuously com-
pared to the ISEC regulation threshold (1.25V typ). Any
time the ISEC voltage exceeds the threshold, a con-
trolled current is drawn from CCI to reduce the on-time
of the bridge’s high-side switches.
Low-Power Shutdown (SUS)
When the MAX8709/MAX8709A are placed in shut-
down, all functions of the IC are turned off except for
the 5.3V linear regulator that powers all internal regis-
ters and the SMBus interface. The SMBus interface is
accessible in shutdown. In shutdown, the linear-regula-
tor output voltage drops to about 4.5V and the supply
current is 6µA (typ), which is the required power to
maintain all internal register states. While in shutdown,
lamp-out detection and short-circuit detection latches
are reset. The device can be placed into shutdown
either by writing to the shutdown-mode register or
pulling SUS low.
Reference Output (REF)
The reference output is nominally 2V, and can source at
least 40µA (see the Typical Operating Characteristics).
______________________________________________________________________________________ 15
High-Efficiency CCFL Backlight
Controller with SMBus Interface
Write-Byte Format
S
ADDRESS
WR
ACK
COMMAND
ACK
DATA
ACK
P
7 bits
1b
1b
8 bits
1b
8 bits
1b
Slave Address
Command Byte: selects
which register you are
writing to
Data Byte: data goes into the register
set by the command byte
Read-Byte Format
ADDRESS WR ACK
S
COMMAND
ACK
S
ADDRESS
7 bits
RD ACK
1b 1b
DATA
///
P
7 bits
1b
1b
8 bits
1b
8 bits
1b
Slave Address
Command Byte: selects
which register you are
reading from
Slave Address: repeated
due to change in data-
flow direction
Data Byte: reads from
the register set by the
command byte
Send-Byte Format
ADDRESS WR ACK COMMAND ACK
7 bits 1b 1b 8 bits 1b
Receive-Byte Format
S
P
S
ADDRESS
7 bits
RD ACK
1b 1b
DATA
///
1b
P
8 bits
Data Byte: reads data from
the register commanded
by the last read-byte or
write-byte transmission;
also used for SMBus Alert
Response return address
Command Byte: sends command
with no data; usually used for one-
shot command
Slave Address
S = Start condition
P = Stop condition
Shaded = Slave transmission
Ack= Acknowledged = 0
/// = Not acknowledged = 1
WR = Write = 0
RD = Read =1
Figure 7. SMBus Protocols
Bypass REF with a 0.22µF ceramic capacitor connected
between REF and GND.
The MAX8709/MAX8709A are slave-only devices and
respond to the 7-bit address 0b01011000 (i.e., with the
R/W bit clear indicating a write, this corresponds to 0x58).
The MAX8709/MAX8709A have three functional registers:
a 5-bit brightness register (BRIGHT4–BRIGHT0), a 3-bit
shutdown-mode register (SHMD2–SHMDE0), and a 2-bit
status register (STATUS1–STATUS0). In addition, the
device has three identification (ID) registers: an 8-bit chip
ID register, an 8-bit chip revision register, and an 8-bit
manufacturer ID register.
Linear-Regulator Output (V
)
CC
The internal linear regulator steps down the DC input volt-
age to 5.3V (typ). The linear regulator supplies power to
the internal control circuitry of the MAX8709/MAX8709A
and can also be used to power the MOSFET drivers by
connecting V
directly to V . The V
voltage drops
CC
DD
CC
to 4.5V in shutdown.
SMBus Interface (SDA, SCL)
Communication starts with the master signaling the
beginning of a transmission with a START condition,
which is a high-to-low transition on SDA while SCL is
high. When the master has finished communicating with
the slave, the master issues a STOP condition, which is
a low-to-high transition on SDA while SCL is high. The
bus is then free for another transmission. Figures 8 and
9 show the timing diagrams for signals on the 2-wire
interface. The address byte, command byte, and data
byte are transmitted between the START and STOP con-
ditions. The SDA state is allowed to change only while
SCL is low, except for the START and STOP conditions.
Data is transmitted in 8-bit words and is sampled on the
The MAX8709/MAX8709A support an Intel SMBus-com-
patible 2-wire digital interface. SDA is the bidirectional
data line and SCL is the clock line of the 2-wire interface
corresponding respectively to SMBDATA and SMBCLK
lines of the SMBus. SDA and SCL are Schmidt-triggered
inputs that can accommodate slow edges; however, the
rising and falling edges should still be faster than 1µs and
300ns, respectively. The MAX8709/MAX8709A use the
write-byte, read-byte, and receive-byte protocols (Figure
7). The SMBus protocols are documented in System
Management Bus Specification V1.1 and are available at
http://www.SMBus.org/.
16 ______________________________________________________________________________________
High-Efficiency CCFL Backlight
Controller with SMBus Interface
A
B
C
D
E
F
G
H
I
J
K
L
M
t
t
HIGH
LOW
SMBCLK
SMBDATA
t
t
t
t
t
HD:DAT
HD:STA
SU:STA
SU:DAT
HD:DAT
t
t
SU:STO
BUF
A = START CONDITION
F = ACKNOWLEDGE BIT CLOCKED INTO MASTER
G = MSB OF DATA CLOCKED INTO SLAVE
H = LSB OF DATA CLOCKED INTO SLAVE
I = SLAVE PULLS SMBDATA LINE LOW
J = ACKNOWLEDGE CLOCKED INTO MASTER
K = ACKNOWLEDGE CLOCK PULSE
L = STOP CONDITION, DATA EXECUTED BY SLAVE
M = NEW START CONDITION
B = MSB OF ADDRESS CLOCKED INTO SLAVE
C = LSB OF ADDRESS CLOCKED INTO SLAVE
D = R/W BIT CLOCKED INTO SLAVE
E = SLAVE PULLS SMBDATA LINE LOW
Figure 8. SMBus Write Timing
A
B
C
D
E
F
G
H
I
J
K
t
t
HIGH
LOW
SMBCLK
SMBDATA
t
t
t
t
t
t
t
BUF
SU:STA HD:STA
SU:DAT
HD:DAT
SU:DAT
SU:STO
A = START CONDITION
E = SLAVE PULLS SMBDATA LINE LOW
I = ACKNOWLEDGE CLOCK PULSE
J = STOP CONDITION
K = NEW START CONDITION
B = MSB OF ADDRESS CLOCKED INTO SLAVE
C = LSB OF ADDRESS CLOCKED INTO SLAVE
D = R/W BIT CLOCKED INTO SLAVE
F = ACKNOWLEDGE BIT CLOCKED INTO MASTER
G = MSB OF DATA CLOCKED INTO MASTER
H = LSB OF DATA CLOCKED INTO MASTER
Figure 9. SMBus Read Timing
rising edge of SCL. Nine clock cycles are required to
transfer each byte in or out of the MAX8709/MAX8709A
since either the master or the slave acknowledges the
receipt of the correct byte during the ninth clock. If the
MAX8709/MAX8709A receive the correct slave address
followed by R/W = 0, it expects to receive 1 or 2 bytes of
information (depending on the protocol). If the device
detects a START or STOP condition prior to clocking in
the bytes of data, it considers this an error condition and
disregards all of the data.
If the transmission is completed correctly, the registers
are updated immediately after a STOP (or RESTART)
condition. If the MAX8709/MAX8709A receives its cor-
rect slave address followed by R/W = 1, it expects to
clock out the register data selected by the previous com-
mand byte.
SMBus Commands
The MAX8709/MAX8709A registers are accessible
through several different redundant commands (i.e.,
the command byte in the read-byte and write-byte pro-
tocols), which can be used to read or write the bright-
ness, SHMD, status, or ID registers.
Table 3 summarizes the command byte’s register
assignments, as well as each register’s power-on state.
______________________________________________________________________________________ 17
High-Efficiency CCFL Backlight
Controller with SMBus Interface
Table 3. Commands Description
DATA REGISTER BIT ASSIGNMENT
SMBus
PROTOCOL
COMMAND
BYTE*
POR
STATE
BIT 7
(MSB)
BIT 0
(LSB)
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
Read and
Write
0x01
0b0XXX XX01
BRIGHT4
(MSB)
BRIGHT0
(LSB)
0x17
0xF9
0x0C
0x00
0x40
0x40
0x4D
0x0C
0
0
0
1
BRIGHT3 BRIGHT2 BRIGHT1
Read and
Write
0x02
0b0XXX XX10
STATUS1 STATUS0
1
1
SHMD2
SHMD1
SHMD0
0x03
0b0XXX XX11
ChipID7
0
ChipID6
0
ChipID5
0
ChipID4
0
ChipID3
1
ChipID2
1
ChipID1
0
ChipID0
1
Read Only
Read Only
0x04
0b0XXX XX00
ChipRev7 ChipRev6 ChipRev5 ChipRev4 ChipRev3 ChipRev2 ChipRev1 ChipRev0
0
0
0
0
0
0
0
0
Read and
Write
0xAA
0b10XX XXX0
BRIGHT4
(MSB)
BRIGHT0
(LSB)
BRIGHT3 BRIGHT2 BRIGHT1
BRIGHT3 BRIGHT2 BRIGHT1
0
STATUS1 STATUS0
STATUS1 STATUS0
Read and
Write
0XA9
0b10XX XXX1
BRIGHT4
(MSB)
BRIGHT0
(LSB)
0
0xFE
0b11XX XXX0
MfgID7
0
MfgID6
1
MfgID5
0
MfgID4
0
MfgID3
1
MfgID2
1
MfgID1
0
MfgID0
1
Read Only
Read Only
0xFF
0b11XX XXX1
ChipID7
0
ChipID6
0
ChipID5
0
ChipID4
0
ChipID3
1
ChipID2
1
ChipID1
0
ChipID0
1
*The hexadecimal command byte shown is recommended for maximum forward compatibility with future products.
X = Don’t care.
Table 4. SHMD Register Bit Descriptions
POR
STATE
BIT NAME
DESCRIPTION
SHMD2 = 1 forces the lamp off and sets STATUS1. SHMD2 = 0 allows the lamp to operate,
although it may still be shut down by SUS (depending on the state of SHMD1 and SHMD0).
2
1
0
SHMD2
SHMD1
SHMD0
0
When SUS = 0, this bit has no effect. SUS = 1 and SHMD1 = 1 forces the lamp off and sets STATUS1.
SUS = 1 and SHMD1 = 0 allows the lamp to operate, although it may still be shut down by the SHMD2 bit.
0
1
When SUS = 1, this bit has no effect. SUS = 0 and SHMD0 = 1 forces the lamp off and sets STATUS1.
SUS = 0 and SHMD0 = 0 allows the lamp to operate, although it may still be shut down by the SHMD2 bit.
The MAX8709/MAX8709A also support the receive-byte
protocol for quicker data transfers. This protocol
accesses the register configuration pointed to by the
last command byte. Immediately after power-up, the
data byte returned by the receive-byte protocol is the
inverted contents of the brightness register, left justified
(i.e., BRIGHT4 is in the most-significant-bit position of
the data byte) with the 3 remaining bits containing a
one, STATUS1, and STATUS0. This gives the same
result as using the read-word protocol with
0b10XXXXXX (0xAA and 0xA9) command. Use caution
with the shorter protocols in multimaster systems, since
a second master could overwrite the command byte
without informing the first master. During shutdown the
serial interface remains fully functional.
18 ______________________________________________________________________________________
High-Efficiency CCFL Backlight
Controller with SMBus Interface
any given digital PWM period, STATUS0 is set for the
Table 5. SUS and SHMD Register Truth
Table
duration of the following digital PWM period. Note that
the status-register polarity of command bytes 0xA9 and
0xAA are inverted from that of command byte 0x02.
SUS SHMD2 SHMD1 SHMD0
OPERATING MODE
0
0
1
1
X
0
0
0
0
1
X
X
0
1
X
0
1
X
X
X
Operate
ID Registers
The ID registers return information on the manufacturer
chip ID and the chip revision number. The
MAX8709/MAX8709A are the first-generation advanced
CCFL controller and its ChipRev is 0x00. Reading from
MfgID register returns 0x4D, which is the ASCII code for
M (for Maxim). The ChipID register returns 0x0D. Writing
to these registers has no effect.
Shutdown, STATUS1 set
Operate
Shutdown, STATUS1 set
Shutdown, STATUS1 set
X = Don’t care.
Brightness Register [BRIGHT4 – BRIGHT0]
(POR = 0b10111)
Applications Information
The 5-bit brightness register corresponds to the 5-bit
brightness code used in dimming control (See the
Dimming Control section). BRIGHT4 - BRIGHT0 =
0b11111 sets minimum brightness and BRIGHT4 -
BRIGHT0 = 0b00000 sets maximum brightness. Note that
the brightness-register polarity of command bytes 0xA9
and 0xAA are inverted from that of command byte 0x01.
To select the correct component values for the
MAX8709/MAX8709A, several CCFL parameters must be
specified. (Table 7)
MOSFETs
The MAX8709/MAX8709A require four external N-channel
power MOSFETs (NL1, NL2, NH1, and NH2) to form a
full-bridge inverter circuit to drive the transformer primary.
The regulator senses the on-state drain-to-source voltage
of the two low-side MOSFETs NL1 and NL2 to detect the
Shutdown-Mode Register [SHMD2–SHMD0]
(POR = 0b001)
The 3-bit shutdown-mode register configures the oper-
ation of the device when the SUS pin is toggled as
described in Table 4. The shutdown-mode register can
also be used to directly shut off the CCFL regardless of
the state of SUS (Table 5).
transformer primary current, so the R
of NL1 and
DS(ON)
NL2 should be matched. For instance, if dual MOSFETs
are used to form the full bridge, NL1 and NL2 should be
in one package. Select dual logic-level N-channel
MOSFETs with low R
to minimize conduction loss
DS(ON)
for NL1/NL2 and NH1/NH2. The regulator utilizes the
energy stored in the transformer’s primary leakage induc-
tance to softly turn on each of four switches in the full
bridge zero voltage switching (ZVS) occurs when the
external power MOSFETs are turned on when their
respective drain-to-source voltages are near 0V. ZVS
effectively eliminates the instantaneous turn-on loss of
Status Register [STATUS1–STATUS0]
(POR = 0b11)
The status register returns information on fault condi-
tions. If the MAX8709/MAX8709A detect that V
does
IFB
not exceed 30% of V
continuously for 1.22s, the IC
LOT
latches STATUS1 to zero. STATUS1 is reset to 1 by tog-
gling SUS or by toggling the input power.
MOSFETs caused by C
(drain-to-source capaci-
OSS
STATUS0 reports 1 as long as no overcurrent condi-
tions are detected. If an overcurrent condition is detect-
ed in any given digital PWM period, STATUS0 is
cleared for the duration of the following digital PWM
period. If an overcurrent condition is not detected in
tance) and parasitic capacitance discharge, and
improves efficiency and reduces switching-related EMI.
Table 6. Status-Register Bit Descriptions (Read Only, Writes Have No Effect)
POR
STATE
BIT
NAME
DESCRIPTION
STATUS1 = 0 (or STATUS1 = 1) means that a lamp-out condition has been detected. The
STATUS1 bit stays clear even after the lamp-out condition has gone away. The only way to set
STATUS1 is to shut off the lamp by programming the shutdown-mode register or by toggling SUS.
1
STATUS1
1
STATUS0 = 0 (or STATUS0 = 1) means that an overcurrent condition was detected during the
previous digital PWM period. STATUS0 = 1 means that an overcurrent condition was not detected
during the previous digital PWM period.
0
STATUS0
1
______________________________________________________________________________________ 19
High-Efficiency CCFL Backlight
Controller with SMBus Interface
Setting the Lamp Current
The MAX8709/MAX8709A sense the lamp current flow-
ing through a resistor R1 (Figure 1) connected between
the low-voltage terminal of the lamp and ground. The
voltage across R1 is fed to IFB and is internally recti-
fied. The MAX8709/MAX8709A control the desired
lamp current by regulating the average of the half-wave
rectified IFB voltage. To set the RMS lamp current,
determine R1 as follows:
Setting the Secondary Current Limit
The MAX8709/MAX8709A limit the secondary current
even if the IFB sense resistor is shorted or transformer
secondary current finds its way to ground without pass-
ing through R1. ISEC monitors the voltage across the
sense resistor R3 connected between the low-voltage
terminal of the transformer secondary winding and
ground. Determine the value of R3 using the following
equation:
1.25V
π × 400mV
R1=
R3 =
2 × I
2 × I
SEC(RMS)_MAX
LAMP(RMS)
where I
is the desired RMS lamp current and
where I
_
is the desired maximum RMS
LAMP(RMS)
SEC(RMS) MAX
400mV is the typical value of the IFB regulation point
specified in the Electrical Characteristics table. To set
the RMS lamp current to 6mA, the value of R1 should
be 148Ω. The closest standard 1% resistors are 147Ω
and 150Ω. The precise shape of the lamp-current
waveform, which is dependent on lamp parasitics, influ-
ences the actual RMS lamp current. Use a true RMS
current meter to make final adjustments to R1.
transformer secondary current during fault conditions,
and 1.25V is the typical value of the ISEC regulation
point specified in the Electrical Characteristics table.
Transformer Design and Resonant
Component Selection
The transformer is the most important component of the
resonant tank circuit. The first step in designing the
transformer is to determine the transformer turns ratio.
The ratio must be high enough to support the CCFL
operating voltage at the minimum supply voltage. The
transformer turns-ratio N can be calculated as follows:
Setting the Secondary Voltage Limit
The MAX8709/MAX8709A limit the transformer sec-
ondary voltage during lamp striking and lamp-out faults.
The secondary voltage is sensed through the capacitive
voltage-divider formed by C3 and C4 (Figure 1). The
voltage on VFB is proportional to the CCFL voltage. The
selection of the parallel resonant capacitor C3 is
described in the Transformer Design and Resonant
Component Selection section. C3 is usually between
10pF to 22pF. After the value of C3 is determined, select
C4 using the following equation to set the desired maxi-
V
LAMP(RMS)
N=
0.9 × V
IN(MIN)
where V
in normal operation, and V
input voltage.
is the maximum RMS lamp voltage
LAMP(RMS)
is the minimum DC
IN(MIN)
The next step in the design procedure is to determine
the desired operating frequency range. The
MAX8709/MAX8709A are synchronized to the natural
resonant frequency of the resonant tank. The resonant
frequency changes with operating conditions, such as
the input voltage, lamp impedance, etc. Therefore, the
switching frequency varies over a certain range. To
ensure reliable operation, the resonant frequency range
must be within the operating frequency range specified
by the CCFL lamp transformer manufacturers. As dis-
cussed in the Resonant Operation section, the resonant
frequency range is determined by the transformer sec-
ondary leakage inductance L, the primary series DC-
blocking capacitor C2, and the secondary parallel
resonant capacitor C3. Since it is difficult to control the
transformer leakage inductance, the resonant tank
design should be based on the existing secondary
leakage inductance of the selected CCFL transformer.
The leakage inductance values usually have large toler-
ance and significant variations among different batch-
es. It is best to work directly with transformer vendors
mum RMS secondary voltage V
_
:
LAMP(RMS) MAX
2 × V
LAMP(RMS)_MAX
C4 =
-1 ×C3
π × 510mV
where 510mV is the typical value of the VFB regulation
threshold specified in the Electrical Characteristics
table. If C3 is 15pF, C4 needs to be 21.2nF to set the
desired maximum RMS secondary voltage to 1600V.
The closest standard value of C4 is 22nF.
The resistor R2 is used to set the VFB DC bias point to
0V. Choose the value of R2 as follows:
10
R2 =
2π × f
× C4
SW
where f
is the nominal resonant operating frequency.
SW
20 ______________________________________________________________________________________
High-Efficiency CCFL Backlight
Controller with SMBus Interface
Table 7. CCFL Specifications
SPECIFICATION
SYMBOL
UNITS
DESCRIPTION
Although CCFLs typically operate at less than 550V
, a higher voltage (1000V
RMS
RMS
CCFL Minimum
Striking Voltage
(Kick-Off Voltage)
and up) is required initially to start the tube. The strike voltage is typically higher at
cold temperatures and at the end of life of the tube. Resonant operation and the
high Q of the resonant tank generate the required strike voltage of the lamp.
V
V
V
STRIKE
RMS
RMS
Once a CCFL has been struck, the lamp voltage required to maintain light output
CCFL Typical
Operating Voltage
(Lamp Voltage)
falls to approximately 550V
. Short tubes may operate on as little as 250V
RMS
.
RMS
V
LAMP
The operating voltage of the CCFL stays relatively constant, even as the tube’s
brightness is varied.
CCFL Operating
Current
(Lamp Current)
The desired RMS AC current through a CCFL is typically 6mA
allowed through CCFLs. The sense resistor, R1, sets the lamp current.
. DC current is not
RMS
I
mA
RMS
LAMP
CCFL Maximum
Frequency
(Lamp Frequency)
The maximum AC-lamp-current frequency. The circuit should be designed to
operate the lamp below this frequency. The MAX8709/MAX8709A are designed to
operate between 20kHz and 100kHz.
f
kHz
on leakage inductance requirements. The
MAX8709/MAX8709A work best when the secondary
leakage inductance is between 250mH and 350mH.
The series capacitor C2 sets the minimum operating
frequency, which is approximately two times the series
resonant peak frequency. Choose:
Compensation Design
The CCI capacitor sets the speed of the current loop
that is used during startup, maintaining lamp current
regulation, and during transients caused by changing
the input voltage. The typical CCI value is 0.1µF. Larger
values increase the transient-response delays. Smaller
values speed up transient response, but extremely
small values can cause loop instability.
2
N
C2 ≤
2
2
π
× f
× L
MIN
The CCV capacitor sets the speed of the voltage loop
that affects soft-start and soft-stop during DPWM opera-
tion, and voltage loop stability during startup and open-
lamp conditions. The typical CCV capacitor value is
10nF. Use the smallest value of CCV that gives an
acceptable fault transient response and does not cause
excessive ringing at the beginning of a DPWM pulse.
where f
is the minimum operating frequency range.
MIN
The parallel capacitor C3 sets the maximum operating
frequency, which is also the parallel resonant peak fre-
quency. Choose:
C2
C3≥
2
2
2
(4π × f
× L × C2) - N
MAX
The transformer core saturation also needs to be con-
sidered when selecting the operating frequency. The
primary winding should have enough turns to prevent
transformer saturation under all operating conditions.
Use the following expression to calculate the minimum
number of turns (N1) of the primary winding:
D
× V
IN(MAX)
MAX
N1>
B
× S × f
MIN
S
where D
is the maximum duty cycle (approximately
MAX
0.8) of the high-side switches, V
is the maximum
IN(MAX)
DC input voltage, B is the saturation flux density of the
core, and S is the minimal cross-section area of the core.
S
______________________________________________________________________________________ 21
High-Efficiency CCFL Backlight
Controller with SMBus Interface
Larger CCV values reduce transient overshoot but can
reduce light output at low-DPWM duty cycles by increas-
ing the time required to reach the tube strike voltage.
3) Route high-speed switching nodes away from sen-
sitive analog areas (CCI, CCV, REF, V , I , I
,
FB FB SEC
ILIM). Make all pin-strap control input connections
(ILIM, etc.) to analog ground or V rather than
CC
Other Components
The external bootstrap circuits formed by D1 and
C5/C6 in Figure 1 power the high-side MOSFET drivers.
Connect BST1/BST2 through a signal-level silicon
diode to V , and bypass it to LX1/LX2 with a 0.1µF
DD
ceramic capacitor.
power ground or V
.
DD
4) Mount the decoupling capacitor from V
to GND
CC
as close as possible to the IC with dedicated
traces that are not shared with other signal paths.
5) The current-sense paths for LX1 and LX2 to GND
must be made using Kelvin-sense connections to
guarantee the current-limit accuracy. With 8-pin
SO MOSFETs, this is best done by routing power
to the MOSFETs from outside using the top copper
layer, while connecting GND and LX inside (under-
neath) the 8-pin SO package.
Layout Guidelines
Careful PC board layout is critical to achieve stable
operation. The high-voltage section and the switching
section of the circuit require particular attention. The
high-voltage sections of the layout need to be well sep-
arated from the control circuit. Most layouts for single-
lamp notebook displays are constrained to the long
and narrow form factor, so this separation occurs natu-
rally. Follow these guidelines for good PC board layout:
6) Ensure the feedback connections are short and
direct. To the extent possible, IFB, VFB, and ISEC
connections should be far away from the high-volt-
age traces and the transformer.
1) Keep the high-current paths short and wide, espe-
cially at the ground terminals. This is essential for
stable, jitter-free operation, and high efficiency.
7) To the extent possible, high-voltage trace clear-
ance on the transformer’s secondary should be
widely separated. The high-voltage traces should
also be separated from adjacent ground planes to
prevent lossy capacitive coupling.
2) Utilize a star-ground configuration for power and
analog grounds. The power and analog grounds
should be completely isolated—meeting only at the
center of the star. The center should be placed at
the exposed backside pad to the QFN package.
Using separate copper islands for these grounds
may simplify this task. Quiet analog ground is used
for REF, CCV, CCI, and ILIM (if a resistive voltage-
divider is used).
8) The traces to the capacitive voltage-divider on the
transformer’s secondary need to be widely sepa-
rated to prevent arcing. Moving these traces to
opposite sides of the board can be beneficial in
some cases (see Figure 10).
D1
C4
C2
N1
N2
LAMP
R2
T1
C3
HIGH-CURRENT PRIMARY CONNECTION
HIGH-VOLTAGE SECONDARY CONNECTION
NOTE: DUAL MOSFET N2 IS MOUNTED ON THE BOTTOM SIDE OF THE PC BOARD DIRECTLY UNDER N1.
Figure 10. High-Voltage Components Layout Example
22 ______________________________________________________________________________________
High-Efficiency CCFL Backlight
Controller with SMBus Interface
Pin Configuration
Chip Information
TRANSISTOR COUNT: 7116
TOP VIEW
PROCESS: BiCMOS
28
27
26
25
24
23
22
ILIM
REF
1
2
3
4
5
6
7
21 GH2
20
19
LX2
LOT
GND
ISEC
SDA
SCL
BST2
18 BST1
MAX8709ETI
MAX8709AETI
17
16
LX1
GH1
15 GL1
8
9
10 11
12
13 14
THIN QFN
______________________________________________________________________________________ 23
High-Efficiency CCFL Backlight
Controller with SMBus Interface
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
D2
D
b
0.10 M
C A B
C
L
D2/2
D/2
k
L
MARKING
XXXXX
E/2
E2/2
C
(NE-1) X
e
L
E2
E
PIN # 1 I.D.
0.35x45°
DETAIL A
e/2
PIN # 1
I.D.
e
(ND-1) X
e
DETAIL B
e
L
C
C
L
L1
L
L
L
e
e
0.10
C
A
0.08
C
C
A3
A1
PACKAGE OUTLINE,
16, 20, 28, 32, 40L THIN QFN, 5x5x0.8mm
1
21-0140
H
-DRAWING NOT TO SCALE-
2
COMMON DIMENSIONS
20L 5x5 28L 5x5
EXPOSED PAD VARIATIONS
D2 E2
MIN. NOM. MAX. MIN. NOM. MAX. ±0.15
PKG.
SYMBOL MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX.
16L 5x5
32L 5x5
40L 5x5
DOWN
BONDS
ALLOWED
L
PKG.
CODES
A
0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80
T1655-1
T1655-2
3.00 3.10 3.20 3.00 3.10 3.20
3.00 3.10 3.20 3.00 3.10 3.20
NO
**
**
**
**
A1
A3
b
0
0.02 0.05
0.20 REF.
0
0.02 0.05
0.20 REF.
0
0.02 0.05
0.20 REF.
0
0.02 0.05
0.20 REF.
0
0.02 0.05
0.20 REF.
YES
NO
T1655N-1 3.00 3.10 3.20 3.00 3.10 3.20
0.25 0.30 0.35 0.25 0.30 0.35 0.20 0.25 0.30 0.20 0.25 0.30 0.15 0.20 0.25
4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10
4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10
T2055-2
T2055-3
T2055-4
T2055-5
3.00 3.10 3.20 3.00 3.10 3.20
3.00 3.10 3.20 3.00 3.10 3.20
3.00 3.10 3.20 3.00 3.10 3.20
NO
YES
NO
D
E
**
**
e
0.80 BSC.
0.25
0.65 BSC.
0.25
0.50 BSC.
0.25
0.50 BSC.
0.25
0.40 BSC.
YES
3.15 3.25 3.35 3.15 3.25 3.35 0.40
k
-
-
-
-
-
-
-
-
0.25 0.35 0.45
T2855-1
T2855-2
3.15 3.25 3.35 3.15 3.25 3.35
2.60 2.70 2.80 2.60 2.70 2.80
NO
NO
L
**
**
**
**
0.30 0.40 0.50 0.45 0.55 0.65 0.45 0.55 0.65 0.30 0.40 0.50 0.40 0.50 0.60
L1
-
-
-
-
-
-
-
-
-
-
-
-
0.30 0.40 0.50
40
T2855-3
T2855-4
3.15 3.25 3.35 3.15 3.25 3.35
2.60 2.70 2.80 2.60 2.70 2.80
2.60 2.70 2.80 2.60 2.70 2.80
3.15 3.25 3.35 3.15 3.25 3.35
YES
YES
NO
N
ND
NE
16
20
28
32
4
4
5
5
7
7
8
8
10
10
T2855-5
T2855-6
T2855-7
T2855-8
**
**
**
WHHB
WHHC
WHHD-1
WHHD-2
-----
JEDEC
NO
YES
2.80
3.35
3.35
3.20
2.60 2.70
3.15 3.25
2.60 2.70 2.80
3.15 3.25 3.35
3.15 3.25 3.35
3.00 3.10 3.20
0.40
YES
NO
NO
NOTES:
T2855N-1 3.15 3.25
**
**
**
1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES.
3. N IS THE TOTAL NUMBER OF TERMINALS.
T3255-2
T3255-3
T3255-4
3.00 3.10
3.00 3.10 3.20 3.00 3.10 3.20
3.00 3.10 3.20 3.00 3.10 3.20
YES
NO
**
**
**
4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL
CONFORM TO JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE
OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1
IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE.
NO
T3255N-1 3.00 3.10 3.20 3.00 3.10 3.20
T4055-1 3.20 3.30 3.40 3.20 3.30 3.40
YES
**SEE COMMON DIMENSIONS TABLE
5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN
0.25 mm AND 0.30 mm FROM TERMINAL TIP.
6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY.
7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION.
8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS.
9. DRAWING CONFORMS TO JEDEC MO220, EXCEPT EXPOSED PAD DIMENSION FOR T2855-1,
T2855-3, AND T2855-6.
10. WARPAGE SHALL NOT EXCEED 0.10 mm.
11. MARKING IS FOR PACKAGE ORIENTATION REFERENCE ONLY.
12. NUMBER OF LEADS SHOWN ARE FOR REFERENCE ONLY.
13. LEAD CENTERLINES TO BE AT TRUE POSITION AS DEFINED BY BASIC DIMENSION "e", ±0.05.
PACKAGE OUTLINE,
16, 20, 28, 32, 40L THIN QFN, 5x5x0.8mm
2
-DRAWING NOT TO SCALE-
21-0140
H
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
24 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2005 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products, Inc.
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