MC10111L [ROCHESTER]
10K SERIES, DUAL 3-INPUT NOR GATE, CDIP16, CERAMIC, DIP-16;
| 型号： | MC10111L |
| 厂家： | 
Rochester Electronics |
| 描述： | 10K SERIES, DUAL 3-INPUT NOR GATE, CDIP16, CERAMIC, DIP-16 栅 CD 输入元件 输出元件 逻辑集成电路 触发器 |
| 文件： | 总6页 (文件大小：839K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC10111
Dual 3−Input/3−Ouput NOR
Gate
The MC10111 is designed to drive up to three transmission lines
simul− taneously. The multiple outputs of this device also allow the
wire “OR”−ing of several levels of gating for minimization of gate and
package count.
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The ability to control three parallel lines from a single point makes
the MC10111 particularly useful in clock distribution applications
MARKING
DIAGRAMS
where minimum clock skew is desired. Three V pins are provided
CC
and each one should be used.
16
• P = 80 mW typ/gate (No Load)
CDIP−16
L SUFFIX
CASE 620
D
MC10111L
AWLYYWW
• t = 2.4 ns typ (All Outputs Loaded)
pd
• t , t = 2.2 ns typ (20%−80%)
r
f
1
16
LOGIC DIAGRAM
PDIP−16
P SUFFIX
CASE 648
MC10111P
AWLYYWW
2
3
4
5
6
7
1
1
12
13
14
PLCC−20
FN SUFFIX
CASE 775
9
10
11
10111
AWLYYWW
V
V
= PIN 1,15
= PIN 16
= PIN 8
CC1
CC2
V
EE
A
= Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
DIP
PIN ASSIGNMENT
ORDERING INFORMATION
V
A
V
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CC1
CC2
Device
Package
Shipping
V
B
B
B
B
B
B
OUT
OUT
OUT
CC1
OUT
OUT
OUT
IN
MC10111L
CDIP−16
25 Units / Rail
A
A
MC10111P
PDIP−16
PLCC−20
25 Units / Rail
46 Units / Rail
MC10111FN
A
IN
A
IN
A
IN
IN
V
IN
EE
Pin assignment is for Dual−in−Line Package.
For PLCC pin assignment, see the Pin Conversion Tables on page 18
of the ON Semiconductor MECL Data Book (DL122/D).
©
Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
June, 2006 − Rev. 8
MC10111/D
MC10111
ELECTRICAL CHARACTERISTICS
Test Limits
+25°C
Typ
Pin
Under
Test
−30°C
Max
42
+85°C
Min
Min
Max
38
Min
Max
42
Characteristic
Power Supply Drain Current
Input Current
Symbol
Unit
mAdc
μAdc
μAdc
Vdc
I
8
30
E
I
5, 6, 7
5, 6, 7
680
425
425
inH
I
0.5
0.5
0.3
inL
Output Voltage
Output Voltage
Logic 1
Logic 0
V
2
3
4
−1.060
−1.060
−1.060
−0.890
−0.890
−0.890
−0.960
−0.960
−0.960
−0.810
−0.810
−0.810
−0.890
−0.890
−0.890
−0.700
−0.700
−0.700
OH
V
2
3
4
−1.890
−1.890
−1.890
−1.675
−1.675
−1.675
−1.850
−1.850
−1.850
−1.650
−1.650
−1.650
−1.825
−1.825
−1.825
−1.615
−1.615
−1.615
Vdc
Vdc
Vdc
ns
OL
Threshold Voltage Logic 1
Threshold Voltage Logic 0
V
2
3
4
−1.080
−1.080
−1.080
−0.980
−0.980
−0.980
−0.910
−0.910
−0.910
OHA
V
2
3
4
−1.655
−1.655
−1.655
−1.630
−1.630
−1.630
−1.595
−1.595
−1.595
OLA
Switching Times (50Ω Load)
Propagation Delay
t
t
t
t
t
t
2
2
3
3
4
4
1.4
1.4
1.4
1.4
1.4
1.4
3.5
3.5
3.5
3.5
3.5
3.5
1.4
1.4
1.4
1.4
1.4
1.4
2.4
2.4
2.4
2.4
2.4
2.4
3.5
3.5
3.5
3.5
3.5
3.5
1.5
1.5
1.5
1.5
1.5
1.5
3.8
3.8
3.8
3.8
3.8
3.8
5+2−
5−2+
5+3−
5−3+
5+4−
5−4+
Rise Time
Fall Time
(20 to 80%)
(20 to 80%)
t
t
t
2
3
4
1.0
1.0
1.0
3.5
3.5
3.5
1.1
1.1
1.1
2.2
2.2
2.2
3.5
3.5
3.5
1.2
1.2
1.2
3.8
3.8
3.8
2+
3+
4+
t
t
t
2
3
4
1.0
1.0
1.0
3.5
3.5
3.5
1.1
1.1
1.1
2.2
2.2
2.2
3.5
3.5
3.5
1.2
1.2
1.2
3.8
3.8
3.8
2−
3−
4−
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2
MC10111
ELECTRICAL CHARACTERISTICS (continued)
TEST VOLTAGE VALUES (Volts)
@ Test Temperature
V
V
V
V
V
EE
IHmax
ILmin
IHAmin
ILAmax
−30°C
+25°C
+85°C
−0.890
−0.810
−0.700
−1.890
−1.850
−1.825
−1.205
−1.105
−1.035
−1.500
−1.475
−1.440
−5.2
−5.2
−5.2
TEST VOLTAGE APPLIED TO PINS LISTED BELOW
Pin
Under
Test
(V
)
CC
V
V
V
V
V
EE
Gnd
Characteristic
Power Supply Drain Current
Input Current
Symbol
IHmax
ILmin
IHAmin
ILAmax
I
8
8
8
8
1, 15, 16
1, 15, 16
1, 15, 16
E
I
5, 6, 7
5, 6, 7
*
inH
I
*
inL
Output Voltage
Logic 1
Logic 0
Logic 1
Logic 0
V
2
3
4
8
8
8
1, 15, 16
1, 15, 16
1, 15, 16
OH
Output Voltage
V
2
3
4
5
6
7
8
8
8
1, 15, 16
1, 15, 16
1, 15, 16
OL
Threshold Voltage
Threshold Voltage
V
2
3
4
5
6
7
8
8
8
1, 15, 16
1, 15, 16
1, 15, 16
OHA
V
2
3
4
5
6
7
8
8
8
1, 15, 16
1, 15, 16
1, 15, 16
OLA
Switching Times
(50Ω Load)
Pulse In Pulse Out
−3.2 V
+2.0 V
Propagation Delay
t
t
t
t
t
t
2
2
3
3
4
4
5
5
5
5
5
5
2
2
3
3
4
4
8
8
8
8
8
8
1, 15, 16
1, 15, 16
1, 15, 16
1, 15, 16
1, 15, 16
1, 15, 16
5+2−
5−2+
5+3−
5−3+
5+4−
5−4+
Rise Time
Fall Time
(20 to 80%)
(20 to 80%)
t
t
t
2
3
4
5
5
5
2
3
4
8
8
8
1, 15, 16
1, 15, 16
1, 15, 16
2+
3+
4+
t
t
t
2
3
4
5
5
5
2
3
4
8
8
8
1, 15, 16
1, 15, 16
1, 15, 16
2−
3−
4−
* Individually test each input using the pin connections shown.
Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been
established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.
Outputs are terminated through a 50-ohm resistor to −2.0 volts. Test procedures are shown for only one gate. The other gates are tested in the
same manner.
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3
MC10111
PACKAGE DIMENSIONS
PLCC−20
FN SUFFIX
PLASTIC PLCC PACKAGE
CASE 775−02
ISSUE C
S
S
0.007 (0.180) M
T
L−M
N
B
Y BRK
−N−
M
S
S
N
0.007 (0.180)
T
L−M
U
D
D
−L−
−M−
Z
W
20
1
S
S
S
0.010 (0.250)
T
L−M
N
G1
X
V
A
VIEW D−D
M
S
S
S
S
0.007 (0.180)
T
L−M
L−M
N
N
M
S
S
N
H
0.007 (0.180)
T
L−M
Z
0.007 (0.180) M
T
R
K1
K
C
E
M
S
S
N
0.007 (0.180)
T
L−M
F
0.004 (0.100)
VIEW S
G
−T− SEATING
PLANE
J
VIEW S
NOTES:
INCHES
MILLIMETERS
G1
1. DATUMS −L−, −M−, AND −N− DETERMINED
WHERE TOP OF LEAD SHOULDER EXITS PLASTIC
BODY AT MOLD PARTING LINE.
2. DIMENSION G1, TRUE POSITION TO BE
MEASURED AT DATUM −T−, SEATING PLANE.
3. DIMENSIONS R AND U DO NOT INCLUDE MOLD
FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250)
PER SIDE.
DIM MIN
MAX
0.395
0.395
0.180
0.110
0.019
MIN
9.78
9.78
4.20
2.29
0.33
MAX
10.03
10.03
4.57
S
S
S
0.010 (0.250)
T
L−M
N
A
B
C
E
F
0.385
0.385
0.165
0.090
0.013
2.79
0.48
G
H
J
0.050 BSC
1.27 BSC
4. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
5. CONTROLLING DIMENSION: INCH.
0.026
0.020
0.025
0.350
0.350
0.042
0.042
0.042
0.032
−−−
−−−
0.66
0.51
0.64
8.89
8.89
1.07
1.07
1.07
−−−
2
0.81
−−−
−−−
9.04
9.04
1.21
1.21
1.42
0.50
10
K
R
U
V
W
X
Y
Z
6. THE PACKAGE TOP MAY BE SMALLER THAN THE
PACKAGE BOTTOM BY UP TO 0.012 (0.300).
DIMENSIONS R AND U ARE DETERMINED AT THE
OUTERMOST EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS,
GATE BURRS AND INTERLEAD FLASH, BUT
INCLUDING ANY MISMATCH BETWEEN THE TOP
AND BOTTOM OF THE PLASTIC BODY.
7. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H
DIMENSION TO BE GREATER THAN 0.037 (0.940).
THE DAMBAR INTRUSION(S) SHALL NOT CAUSE
THE H DIMENSION TO BE SMALLER THAN 0.025
(0.635).
0.356
0.356
0.048
0.048
0.056
−−− 0.020
10
2
_
_
_
_
G1 0.310
K1 0.040
0.330
−−−
7.88
1.02
8.38
−−−
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4
MC10111
PACKAGE DIMENSIONS
CDIP−16
L SUFFIX
CERAMIC DIP PACKAGE
CASE 620−10
ISSUE T
−A−
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
BODY.
16
1
9
8
−B−
C
L
INCHES
DIM MIN MAX
0.785 19.05
MILLIMETERS
MIN
MAX
19.93
7.49
5.08
0.50
A
B
C
D
E
F
0.750
0.240
0.295
6.10
−−−
0.39
−−− 0.200
0.015 0.020
0.050 BSC
−T−
SEATING
PLANE
K
N
1.27 BSC
0.055
0.065
1.40
1.65
G
H
K
L
0.100 BSC
2.54 BSC
M
E
0.008
0.125
0.015
0.170
0.21
3.18
0.38
4.31
F
J 16 PL
G
0.300 BSC
7.62 BSC
M
S
T B
0.25 (0.010)
M
N
0
0.020
15
0.040
0
_
0.51
15
1.01
D 16 PL
_
_
_
M
S
T A
0.25 (0.010)
PDIP−16
P SUFFIX
PLASTIC DIP PACKAGE
CASE 648−08
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
−A−
ISSUE R
16
1
9
8
B
S
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
INCHES
DIM MIN MAX
MILLIMETERS
MIN
18.80
6.35
3.69
0.39
1.02
MAX
19.55
6.85
4.44
0.53
1.77
F
A
B
C
D
F
0.740
0.250
0.145
0.015
0.040
0.770
0.270
0.175
0.021
0.70
C
L
SEATING
PLANE
−T−
G
H
J
0.100 BSC
0.050 BSC
2.54 BSC
1.27 BSC
K
M
0.008
0.015
0.130
0.305
10
0.21
0.38
3.30
7.74
10
H
J
K
L
0.110
0.295
0
2.80
7.50
0
G
D 16 PL
M
S
_
_
_
_
0.020
0.040
0.51
1.01
M
M
0.25 (0.010)
T A
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to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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MC10111/D
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