MC10H641FNR2G [ROCHESTER]
10H SERIES, LOW SKEW CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC28, LEAD FREE, PLASTIC, LCC-28;
| 型号： | MC10H641FNR2G |
| 厂家： | 
Rochester Electronics |
| 描述： | 10H SERIES, LOW SKEW CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC28, LEAD FREE, PLASTIC, LCC-28 驱动 输出元件 逻辑集成电路 |
| 文件： | 总11页 (文件大小：821K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC10H641, MC100H641
Single Supply PECL to TTL
1:9 Clock Distribution Chip
Description
The MC10H/100H641 is a single supply, low skew translating 1:9
clock driver. Devices in the ON Semiconductor H641 translator series
utilize the PLCC−28 for optimal power pinning, signal flow through
and electrical performance.
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The device features a 24 mA TTL output stage, with AC
performance specified into a 50 pF load capacitance. A latch is
provided on−chip. When LEN is LOW (or left open, in which case it is
pulled LOW by the internal pulldown) the latch is transparent. A
HIGH on the enable pin (EN) forces all outputs LOW. Both the LEN
and EN pins are positive ECL inputs.
PLCC−28
FN SUFFIX
CASE 776
The V output is provided in case the user wants to drive the
BB
device with a single−ended input. For single−ended use, the V
BB
should be connected to the D input and bypassed with a 0.01 mF
capacitor.
The 10H version of the H641 is compatible with positive
MECL 10H™ logic levels. The 100H version is compatible with
positive 100K levels.
MARKING DIAGRAM*
1
Features
• PECL − TTL Version of Popular ECLinPS E111
• Low Skew
MCxxxH641G
AWLYYWW
• Guaranteed Skew Spec
• Latched Input
• Differential ECL Internal Design
xxx
A
WL
YY
WW
G
= 10 or 100
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
• V Output for Single−Ended Use
BB
• Single +5.0 V Supply
• Logic Enable
• Extra Power and Ground Supplies
• Separate ECL and TTL Supply Pins
• Pb−Free Packages are Available*
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
©
Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
November, 2006 − Rev.7
MC10H641/D
MC10H641, MC100H641
GT
25
Q6 VT
24 23
Q7 VT
22 21
Q8
GT
19
Table 1. PIN DESCRIPTION
20
Pins
Function
GT 26
Q5 27
VT 28
18
17
16
15
14
13
12
V
BB
GT, VT
GE, VE
D, D
TTL GND, TTL V
ECL GND, ECL V
Signal Input (Positive ECL)
V Reference Output (Positive ECL)
BB
Signal Outputs (TTL)
CC
CC
D
V
BB
D
Q0 − Q8
EN
LEN
Enable Input (Positive ECL)
Latch Enable Input (Positive ECL)
Q4
1
VE
LEN
GE
EN
VT
Q3
GT
2
3
4
5
6
7
8
9
10
11
GT
Q2 VT
Q1 VT
Q0
GT
Figure 1. Pinout: PLCC−28 (Top View)
TTL Outputs
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
PECL Input
D
D
D
Q
V
BB
LEN
EN
Figure 2. Logic Diagram
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2
MC10H641, MC100H641
Table 2. 10H PECL DC CHARACTERISTICS
0°C
25°C
85°C
Min
Max
Min
Max
Min
Max
Symbol
Characteristic
Input HIGH Current
Condition
Unit
mA
mA
V
I
I
255
175
175
INH
IL
Input LOW Current
0.5
0.5
0.5
V
V
V
Input HIGH Voltage
Input LOW Voltage
Output Reference Voltage
V
V
V
= 5.0 V (Note 1)
= 5.0 V (Note 1)
= 5.0 V (Note 1)
3.83
3.05
3.62
4.16
3.52
3.73
3.87
3.05
3.65
4.19
3.52
3.75
3.94
3.05
3.69
4.28
3.55
3.81
IH
IL
E
E
E
V
V
BB
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification
limit values are applied individually under normal operating conditions and not valid simultaneously.
1. PECL V , V , and V are referenced to VE and will vary 1:1 with the power supply. The levels shown are for VE = 5.0 V.
IH
IL
BB
Table 3. 100H PECL DC CHARACTERISTICS
0°C
25°C
85°C
Min
Max
Min
Max
175
Min
Max
175
Symbol
Characteristic
Input HIGH Current
Condition
Unit
mA
mA
V
I
I
255
INH
INL
Input LOW Current
0.5
0.5
0.5
V
V
V
Input HIGH Voltage
Input LOW Voltage
Output Reference Voltage
V
V
V
= 5.0 V (Note 2)
= 5.0 V (Note 2)
= 5.0 V (Note 2)
3.835 4.120 3.835 4.120 3.835 4.120
3.190 3.525 3.190 3.525 3.190 3.525
IH
IL
E
E
E
V
3.62
3.74
3.62
3.74
3.62
3.74
V
BB
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification
limit values are applied individually under normal operating conditions and not valid simultaneously.
2. PECL V , V , and V are referenced to VE and will vary 1:1 with the power supply. The levels shown are for VE = 5.0 V.
IH
IL
BB
Table 4. DC CHARACTERISTICS (V = V = 5.0 V ± 5%)
T
E
T
A
= 0°C
Typ
T
= + 25°C
T = + 85°C
A
A
Min
Max
Min
Typ
Max
Min
Typ
Max
Symbol
Characteristic
Unit
I
Power Supply Current
PECL
24
30
24
30
24
30
mA
EE
I
I
TTL
24
27
30
35
24
27
30
35
24
27
30
35
mA
mA
CCH
CCL
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification
limit values are applied individually under normal operating conditions and not valid simultaneously.
Table 5. TTL DC CHARACTERISTICS (V = V = 5.0 V ± 5%)
T
E
0°C
25°C
85°C
Characteristic
Output HIGH Voltage
Condition
Min
Max
Min
2.5
Max
Min
2.5
Max
Unit
V
Symbol
V
V
I
= −15 mA
OH
2.5
OH
OL
Output LOW Voltage
I
= 24 mA
0.5
0.5
0.5
V
OL
I
Output Short Circuit Current
V
= 0 V
OUT
−100 −225 −100 −225 −100 −225
mA
OS
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification
limit values are applied individually under normal operating conditions and not valid simultaneously.
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3
MC10H641, MC100H641
Table 6. AC CHARACTERISTICS (V = V = 5.0 V ± 5%)
T
E
T = 0°C
J
T = + 25°C
J
T = + 85°C
J
Symbol
Condition
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max Unit
Characteristic
t
t
Propagation Delay
D to Q
CL = 50 pF (Note 3) 5.00 5.50 6.00 4.86 5.36 5.86 5.08 5.58 6.08
5.36 5.86 6.36 5.27 5.77 6.27 5.43 5.93 6.43
ns
PLH
PHL
t
Device Skew
ps
skew
Part−to−Part CL = 50 pF (Note 4)
Single V CL = 50 pF (Note 5)
Output−to−Output CL = 50 pF (Note 6)
1000
750
350
1000
750
350
1000
750
350
CC
t
t
Propagation Delay
CL = 50 pF
4.9
5.0
6.9
7.0
4.9
4.9
6.9
6.9
5.0
5.0
7.0
7.0
ns
ns
ns
PLH
PHL
LEN to Q
t
t
Propagation Delay
EN to Q
CL = 50 pF
PLH
PHL
t
t
Output Rise/Fall
0.8 V to 2.0 V
CL = 50 pF
1.7
1.6
1.7
1.6
1.7
1.6
r
f
f
t
t
Max Input Frequency
Setup Time
CL = 50 pF (Note 7)
65
65
65
MHz
ns
MAX
S
0.75 0.50
0.75 0.50
0.75 0.50
0.75 0.50
0.75 0.50
0.75 0.50
Hold Time
ns
H
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification
limit values are applied individually under normal operating conditions and not valid simultaneously.
3. Propagation delay measurement guaranteed for junction temperatures. Measurements performed at 50 MHz input frequency.
4. Skew window guaranteed for a single temperature across a V = V = V of 4.75 V to 5.25 V (See Application Note in this data sheet).
CC
T
E
5. Skew window guaranteed for a single temperature and single V = V = V
CC
T
E
6. Output−to−output skew is specified for identical transitions through the device.
7. Frequency at which output levels will meet a 0.8 V to 2.0 V minimum swing.
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4
MC10H641, MC100H641
Determining Skew for a Specific Application
The H641 has been designed to meet the needs of very low
skew clock distribution applications. In order to optimize
the device for this application special considerations are
necessary in the determining of the part−to−part skew
specification limits. Older standard logic devices are
specified with relatively slack limits so that the device can
be guaranteed over a wide range of potential environmental
conditions. This range of conditions represented all of the
potential applications in which the device could be used. The
result was a specification limit that in the vast majority of
cases was extremely conservative and thus did not allow for
an optimum system design. For non−critical skew designs
this practice is acceptable, however as the clock speeds of
systems increase overly conservative specification limits
can kill a design.
The following will discuss how users can use the
information provided in this data sheet to tailor a
part−to−part skew specification limit to their application.
The skew determination process may appear somewhat
tedious and time consuming, however if the utmost in
performance is required this procedure is necessary. For
applications which do not require this level of skew
performance a generic part−to−part skew limit of 2.5 ns can
be used. This limit is good for the entire ambient temperature
P (watts) = I (no load) * V
+
D
CC
CC
V * V * f * C * # Outputs
S
CC
L
where:
V = Output Voltage Swing = 3.0 V
S
f = Output Frequency
C = Load Capacitance
L
I
= I + I
CC
EE CCH
Figure 1 plots the I versus Frequency of the H641 with
CC
no load capacitance on the output. Using this graph and the
information specific to the application a user can determine
the power dissipation of the H641.
5
4
3
2
1
0
range, the guaranteed V
(V , V ) range and the
CC
T E
guaranteed operating frequency range.
0
10
20
30
40
50
60
70
80
Temperature Dependence
FREQUENCY (MHz)
A unique characteristic of the H641 data sheet is that the
AC parameters are specified for a junction temperature
rather than the usual ambient temperature. Because very few
designs will actually utilize the entire commercial
temperature range of a device a tighter propagation delay
window can be established given the smaller temperature
range. Because the junction temperature and not the ambient
temperature is what affects the performance of the device the
parameter limits are specified for junction temperature. In
addition the relationship between the ambient and junction
temperature will vary depending on the frequency, load and
board environment of the application. Since these factors are
all under the control of the user it is impossible to provide
specification limits for every possible application.
Therefore a baseline specification was established for
specific junction temperatures and the information that
follows will allow these to be tailored to specific
applications.
Since the junction temperature of a device is difficult to
measure directly, the first requirement is to be able to
“translate” from ambient to junction temperatures. The
standard method of doing this is to use the power dissipation
of the device and the thermal resistance of the package. For
a TTL output device the power dissipation will be a function
of the load capacitance and the frequency of the output. The
total power dissipation of a device can be described by the
following equation:
Figure 1. ICC versus f (No Load)
Figure 2 illustrates the thermal resistance (in °C/W) for
the PLCC−28 under various air flow conditions. By reading
the thermal resistance from the graph and multiplying by the
power dissipation calculated above the junction temperature
increase above ambient of the device can be calculated.
70
60
50
40
30
0
200
400
600
800
1000
AIRFLOW (LFPM)
Figure 2. jJA versus Air Flow
Finally taking this value for junction temperature and
applying it to Figure 3 allows the user to determine the
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5
MC10H641, MC100H641
propagation delay for the device in question. A more
propagation delay at the typical, minimum and maximum
common use would be to establish an ambient temperature
range for the H641’s in the system and utilize the above
methodology to determine the potential increased skew of
the distribution network. Note that for this information if the
V
CC
.
140
100
60
T
versus Temperature curve were linear the calculations
PD
would not be required. If the curve were linear over all
temperatures a simple temperature coefficient could be
provided.
6.4
20
−20
−60
−100
−140
6.2
6.0
5.8
5.6
5.4
5.2
T
PHL
T
T
PLH
PHL
4.75
4.85
4.95
5.05
VCC (V)
5.15
5.25
T
PLH
Figure 4. DTPD versus VCC
Capacitive Load Dependence
As with V the propagation delay of a TTL output is
CC
intimately tied to variation in the load capacitance. The skew
specifications given in the data sheet, of course, assume
equal loading on all of the outputs. However situations could
arise where this is an impossibility and it may be necessary
to estimate the skew added by asymmetric loading. In
addition the propagation delay numbers are provided only
for 50 pF loads, thus necessitating a method of determining
the propagation delay for alternative loads.
Figure 5 shows the relationship between the two
propagation delays with respect to the capacitive load on the
output. Utilizing this graph and the 50 pF limits the
specification of the H641 can be mapped into a spec for
−30 −10
10
30
50
70
90
110 130
JUNCTION TEMPERATURE (°C)
Figure 3. TPD versus Junction Temperature
VCC Dependence
TTL and CMOS devices show a significant propagation
delay dependence with V . Therefore the V variation in
a system will have a direct impact on the total skew of the
clock distribution network. When calculating the skew
between two devices on a single board it is very likely an
CC
CC
assumption of identical V ’s can be made. In this case the
CC
either a different value load or asymmetric loads.
1.15
number provided in the data sheet for part−to−part skew
would be overly conservative. By using Figure 4 the skew
given in the data sheet can be reduced to represent a smaller
or zero variation in V . The delay variation due to the
specified V
1.10
1.05
CC
variation is ≈ 270 ps. Therefore, the 1 ns
CC
T
PLH
window on the data sheet can be reduced by 270 ps if the
devices in question will always experience the same V
The distribution of the propagation delay ranges given in the
data sheet is actually a composite of three distributions
whose means are separated by the fixed difference in
1.00
0.95
0.90
0.85
0.80
0.75
.
CC
MEASURED
T
PHL
THEORETICAL
0
10 20 30 40 50 60 70 80 90 100
CAPACITIVE LOAD (pF)
Figure 5. TPD versus Load
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6
MC10H641, MC100H641
Rise/Fall Skew Determination
The rise−to−fall skew is defined as simply the difference
always be at the same V ; therefore the propagation delay
window will only be 1 ns − 0.27 ns = 0.73 ns.
Putting all of this information together leads to a skew
between all devices of
0.19 ns + 0.88 ns
(temperature + supply, and inherent device),
while the skew between devices A and B will be only
0.19 ns + 0.73 ns
(temperature + inherent device only).
In both cases, the propagation delays will be centered
CC
between the T
and the T
propagation delays. This
PLH
PHL
skew for the H641 is dependent on the V applied to the
device. Notice from Figure 4 the opposite relationship of
CC
T
versus V between T
and T
. Because of this
PD
CC
PLH
PHL
the rise−to−fall skew will vary depending on V . Since in
CC
all likelihood it will be impossible to establish the exact
value for V , the expected variation range for V should
CC
CC
be used. If this variation will be the ± 5% shown in the data
sheet the rise−to−fall skew could be established by simply
around 5.42 ns, resulting in the following t
windows:
PLH
subtracting the fastest T
from the slowest T
; this
T
= 4.92 ns − 5.99 ns; 1.07 ns window
PLH
PHL
PLH
exercise yields 1.41 ns. If a tighter V range can be realized
Figure 4 can be used to establish the rise−to−fall skew.
(all devices)
CC
T
=
PLH
5.00 ns − 5.92 ns; 0.92 ns window
(devices a & b)
Specification Limit Determination Example
Of course the output−to−output skew will be as shown in
the data sheet since all outputs are equally loaded.
This process may seem cumbersome, however the delay
windows, and thus skew, obtained are significantly better
than the conservative worst case limits provided at the
beginning of this note. For very high performance designs,
this extra information and effort can mean the difference
between going ahead with prototypes or spending valuable
engineering time searching for alternative approaches.
Card 1
The situation pictured in Figure 6 will be analyzed as an
example. The central clock is distributed to two different
cards; on one card a single H641 is used to distribute the
clock while on the second card two H641’s are required to
supply the needed clocks. The data sheet as well as the
graphical information of this section will be used to
calculate the skew between H641a and H641b as well as the
skew between all three of the devices. Only the T
will be
PLH
analyzed, the T
numbers can be found using the same
PHL
technique. The following assumptions will be used:
− All outputs will be loaded with 50 pF
− All outputs will toggle at 30 MHz
H641a
Q0
− The V variation between the two boards is ± 3 %
CC
ECL
TTL
− The temperature variation between the three
devices is ± 15°C around an ambient of 45°C.
− 500 lfpm air flow
Q8
The first task is to calculate the junction temperature for
the devices under these conditions. Using the power
equation yields:
H641b
ECL
Q0
Q8
P = I (no load) * V +
D
CC
CC
TTL
V
* V * f * C * # outputs
S L
CC
=4.3 * 48m A * 5.0 V + 5.0 V * 3.0 V * 30 MHz *
50 pF * 9
=432 mW + 203 mW = 635 mW
Using the thermal resistance graph of Figure 2 yields a
thermal resistance of 41°C/W which yields a junction
temperature of 71°C with a range of 56°C to 86°C. Using the
Card 2
H641c
ECL
Q0
Q8
T
versus Temperature curve of Figure 3 yields a
PD
propagation delay of 5.42 ns and a variation of 0.19 ns.
TTL
Since the design will not experience the full ± 5% V
CC
variation of the data sheet the 1.0 ns window provided will
be unnecessarily conservative. Using the curve of Figure 4
shows a delay variation due to a ± 3% V
variation of
CC
± 0.075 ns. Therefore the 1.0 ns window can be reduced to
1.0 ns − (0.27 ns − 0.15 ns) = 0.88 ns. Since H641a and
H641b are on the same board we will assume that they will
Figure 6. Example Application
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7
MC10H641, MC100H641
ORDERING INFORMATION
Device
†
Package
Shipping
MC10H641FN
PLCC−28
37 Units / Rail
37 Units / Rail
MC10H641FNG
PLCC−28
(Pb−Free)
MC10H641FNR2
PLCC−28
500 / Tape & Reel
500 / Tape & Reel
MC10H641FNR2G
PLCC−28
(Pb−Free)
MC100H641FN
PLCC−28
37 Units / Rail
37 Units / Rail
MC100H641FNG
PLCC−28
(Pb−Free)
MC100H641FNR2
MC100H641FNR2G
PLCC−28
500 / Tape & Reel
500 / Tape & Reel
PLCC−28
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D
AN1406/D
AN1503/D
AN1504/D
AN1568/D
AN1672/D
AND8001/D
AND8002/D
AND8020/D
AND8066/D
AND8090/D
−
−
−
−
−
−
−
−
−
−
−
ECL Clock Distribution Techniques
Designing with PECL (ECL at +5.0 V)
ECLinPSt I/O SPiCE Modeling Kit
Metastability and the ECLinPS Family
Interfacing Between LVDS and ECL
The ECL Translator Guide
Odd Number Counters Design
Marking and Date Codes
Termination of ECL Logic Devices
Interfacing with ECLinPS
AC Characteristics of ECL Devices
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MC10H641, MC100H641
PACKAGE DIMENSIONS
PLCC−28
FN SUFFIX
PLASTIC PLCC PACKAGE
CASE 776−02
ISSUE E
M
S
S
0.007 (0.180)
T
L−M
N
B
Y BRK
D
−N−
M
S
S
N
0.007 (0.180)
T
L−M
U
Z
−M−
−L−
W
D
S
S
S
N
0.010 (0.250)
T
L−M
X
G1
V
28
1
VIEW D−D
M
S
S
S
A
0.007 (0.180)
0.007 (0.180)
T
L−M
L−M
N
M
S
S
N
0.007 (0.180)
T
L−M
H
Z
M
S
T
N
R
K1
C
E
0.004 (0.100)
G
K
SEATING
PLANE
−T−
J
M
S
S
N
0.007 (0.180)
T
L−M
F
VIEW S
G1
S
S
S
N
0.010 (0.250)
T
L−M
VIEW S
NOTES:
INCHES
MILLIMETERS
1. DATUMS −L−, −M−, AND −N− DETERMINED
WHERE TOP OF LEAD SHOULDER EXITS
PLASTIC BODY AT MOLD PARTING LINE.
2. DIMENSION G1, TRUE POSITION TO BE
MEASURED AT DATUM −T−, SEATING PLANE.
3. DIMENSIONS R AND U DO NOT INCLUDE
MOLD FLASH. ALLOWABLE MOLD FLASH IS
0.010 (0.250) PER SIDE.
4. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
5. CONTROLLING DIMENSION: INCH.
6. THE PACKAGE TOP MAY BE SMALLER THAN
THE PACKAGE BOTTOM BY UP TO 0.012
(0.300). DIMENSIONS R AND U ARE
DETERMINED AT THE OUTERMOST
EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FLASH, TIE BAR
BURRS, GATE BURRS AND INTERLEAD
FLASH, BUT INCLUDING ANY MISMATCH
BETWEEN THE TOP AND BOTTOM OF THE
PLASTIC BODY.
DIM MIN
MAX
0.495
0.495
0.180
0.110
0.019
MIN
12.32
12.32
4.20
MAX
12.57
12.57
4.57
A
B
C
E
F
0.485
0.485
0.165
0.090
0.013
2.29
0.33
2.79
0.48
G
H
J
0.050 BSC
1.27 BSC
0.026
0.020
0.025
0.450
0.450
0.042
0.042
0.042
0.032
−−−
−−−
0.66
0.51
0.64
11.43
11.43
1.07
1.07
1.07
−−−
0.81
−−−
K
R
U
V
W
X
Y
Z
−−−
0.456
0.456
0.048
0.048
0.056
11.58
11.58
1.21
1.21
1.42
0.50
10
−−− 0.020
10
2
2
_
_
_
_
G1 0.410
K1 0.040
0.430
−−−
10.42
1.02
10.92
−−−
7. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H
DIMENSION TO BE GREATER THAN 0.037
(0.940). THE DAMBAR INTRUSION(S) SHALL
NOT CAUSE THE H DIMENSION TO BE
SMALLER THAN 0.025 (0.635).
http://onsemi.com
9
MC10H641, MC100H641
ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC).
MECL 10H is a trademark of Motorola, Inc.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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MC10H640/D
相关型号：
MC10H643FN
10H SERIES, LOW SKEW CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC28, PLATIC, LCC-28
ROCHESTER
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