MC68HC705L1B [ROCHESTER]
Microcontroller, 8-Bit, OTPROM, HCMOS, PDIP56, SDIP-56;
| 型号： | MC68HC705L1B |
| 厂家： | 
Rochester Electronics |
| 描述： | Microcontroller, 8-Bit, OTPROM, HCMOS, PDIP56, SDIP-56 可编程只读存储器 微控制器 光电二极管 |
| 文件： | 总102页 (文件大小：632K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC68HC05L1D/H
HC05
MC68HC05L1
MC68HC705L1
TECHNICAL
DATA
!MOTOROLA
GENERAL DESCRIPTION
PIN DESCRIPTION AND INPUT/OUTPUT PORTS
MEMORY AND REGISTERS
1
2
3
RESETS AND INTERRUPTS
4
PROGRAMMABLE TIMER
5
ANALOG TO DIGITAL CONVERTER
LIQUID CRYSTAL DISPLAY DRIVER
CPU CORE AND INSTRUCTION SET
LOW POWER MODES
6
7
8
9
OPERATING MODES
10
11
12
A
ELECTRICAL SPECIFICATIONS
MECHANICAL SPECIFICATIONS
MC68HC705L1
TPG
GENERAL DESCRIPTION
1
2
PIN DESCRIPTION AND INPUT/OUTPUT PORTS
MEMORY AND REGISTERS
RESETS AND INTERRUPTS
PROGRAMMABLE TIMER
3
4
5
ANALOG TO DIGITAL CONVERTER
LIQUID CRYSTAL DISPLAY DRIVER
CPU CORE AND INSTRUCTION SET
LOW POWER MODES
6
7
8
9
OPERATING MODES
10
11
12
A
ELECTRICAL SPECIFICATIONS
MECHANICAL SPECIFICATIONS
MC68HC705L1
TPG
MC68HC05L1
MC68HC705L1
High-density complementary
metal oxide semiconductor
(HCMOS) microcontroller unit
All Trade Marks recognized. This document contains information on new products. Specifications and information herein are
subject to change without notice.
All products are sold on Motorola’s Terms & Conditions of Supply. In ordering a product covered by this document the
Customer agrees to be bound by those Terms & Conditions and nothing contained in this document constitutes or forms part
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Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty,
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The Customer should ensure that it has the most up to date version of the document by contacting its local Motorola office.
This document supersedes any earlier documentation relating to the products referred to herein. The information contained
in this document is current at the date of publication. It may subsequently be updated, revised or withdrawn.
MOTOROLA LTD., 1996
TPG
Conventions
Register and bit mnemonics are defined in the paragraphs describing them.
An overbar is used to designate an active-low signal, eg: RESET.
Unless otherwise stated, blank cells in a register diagram indicate that the bit is
either unused or reserved; shaded cells indicate that the bit is not described in the
following paragraphs; ‘u’ is used to indicate an undefined state (on reset).
TPG
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SECTION 1
SECTION 2
SECTION 3
SECTION 4
SECTION 5
SECTION 6
SECTION 7
SECTION 8
SECTION 9
GENERAL DESCRIPTION
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PIN DESCRIPTIONS AND INPUT/OUTPUT PORTS
MEMORY AND REGISTERS
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RESETS AND INTERRUPTS
PROGRAMMABLE TIMER
ANALOG TO DIGITAL CONVERTER
LIQUID CRYSTAL DISPLAY DRIVER
CPU CORE AND INSTRUCTION SET
LOW POWER MODES
SECTION 10 OPERATING MODES
SECTION 11 ELECTRICAL SPECIFICATIONS
SECTION 12 MECHANICAL SPECIFICATIONS
SECTION A
Comments:
MC68HC705L1
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!MOTOROLA
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TABLE OF CONTENTS
Paragraph
Number
Page
Number
TITLE
1
GENERAL DESCRIPTION
1.1
Features.................................................................................................................1-1
2
PIN DESCRIPTION AND INPUT/OUTPUT PORTS
2.1
2.1.1
2.2
2.2.1
2.2.2
PIN DESCRIPTIONS.............................................................................................2-1
Pin Assignments ..............................................................................................2-3
INPUT/OUTPUT PORTS.......................................................................................2-4
Parallel Ports....................................................................................................2-4
Fixed Ports.......................................................................................................2-4
3
MEMORY AND REGISTERS
3.1
3.2
3.3
Memory Map..........................................................................................................3-1
Input/Output Section..............................................................................................3-1
RAM.......................................................................................................................3-1
4
RESETS AND INTERRUPTS
4.1
RESETS ................................................................................................................4-1
RESET Pin.......................................................................................................4-1
Power-On Reset (POR)....................................................................................4-1
INTERRUPTS........................................................................................................4-3
Hardware Controlled Sequences.....................................................................4-4
Software Interrupt (SWI) ..................................................................................4-4
External Interrupt (IRQ) ...................................................................................4-6
Programmable Timer Interrupt .........................................................................4-6
4.1.1
4.1.2
4.2
4.2.1
4.2.2
4.2.3
4.2.4
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MC68HC05L1
MOTOROLA
i
Paragraph
Number
Page
Number
TITLE
5
PROGRAMMABLE TIMER
5.1
5.1.1
5.2
5.2.1
5.2.2
5.3
5.3.1
5.3.2
5.3.3
5.4
Counter..................................................................................................................5-3
Counter Register and Alternate Counter Register...........................................5-3
Input Capture.........................................................................................................5-4
Input Capture Register 1 (ICR1)......................................................................5-4
Input Capture Register 2 (ICR2)......................................................................5-5
Output Compare....................................................................................................5-5
Output Compare Register 1 (OCR1) ...............................................................5-6
Output Compare Register 2 (OCR2) ...............................................................5-7
Software Force Compare.................................................................................5-7
Timer Control and Status ......................................................................................5-8
Timer Control Register (TCR)..........................................................................5-8
Timer Status Register (TSR) ...........................................................................5-10
Programmable Timer Timing Diagrams.................................................................5-11
5.4.1
5.4.2
5.5
6
ANALOG TO DIGITAL CONVERTER
6.1
6.2
6.3
A/D Converter Operation.......................................................................................6-2
ADC Status/Control Register (ACR)......................................................................6-3
ADC Result Data Register (ADDATA)....................................................................6-4
7
LIQUID CRYSTAL DISPLAY DRIVER
7.1
7.2
7.3
LCD Display RAM..................................................................................................7-2
LCD Operation.......................................................................................................7-2
Timing Signals and LCD Voltage Waveforms ........................................................7-3
8
CPU CORE AND INSTRUCTION SET
8.1
Registers ...............................................................................................................8-1
Accumulator (A)...............................................................................................8-1
Index register (X) .............................................................................................8-2
Program counter (PC)......................................................................................8-2
Stack pointer (SP)............................................................................................8-2
Condition code register (CCR).........................................................................8-2
Instruction set........................................................................................................8-3
Register/memory Instructions..........................................................................8-4
Branch instructions ..........................................................................................8-4
8.1.1
8.1.2
8.1.3
8.1.4
8.1.5
8.2
8.2.1
8.2.2
TPG
MOTOROLA
ii
MC68HC05L1
Paragraph
Number
Page
Number
TITLE
8.2.3
8.2.4
8.2.5
8.2.6
8.3
8.3.1
8.3.2
8.3.3
8.3.4
8.3.5
8.3.6
8.3.7
8.3.8
8.3.9
8.3.10
Bit manipulation instructions ............................................................................8-4
Read/modify/write instructions.........................................................................8-4
Control instructions ..........................................................................................8-4
Tables...............................................................................................................8-4
Addressing modes.................................................................................................8-11
Inherent............................................................................................................8-11
Immediate ........................................................................................................8-11
Direct................................................................................................................8-11
Extended..........................................................................................................8-12
Indexed, no offset.............................................................................................8-12
Indexed, 8-bit offset..........................................................................................8-12
Indexed, 16-bit offset........................................................................................8-12
Relative ............................................................................................................8-13
Bit set/clear ......................................................................................................8-13
Bit test and branch...........................................................................................8-13
9
LOW POWER MODES
9.1
Stop Mode .............................................................................................................9-1
Timer during Stop Mode ..................................................................................9-1
ADC during Stop Mode....................................................................................9-2
Wait Mode..............................................................................................................9-2
9.1.1
9.1.2
9.2
10
OPERATING MODES
10.1 User Mode (Normal Operation) ...........................................................................10-2
10.2 Self-Check Mode .................................................................................................10-2
10.3 Bootstrap Mode ...................................................................................................10-4
10.3.1
10.3.2
10.3.3
EPROM Programming ...................................................................................10-4
Program Control Register (PCR) ...................................................................10-4
EPROM Programming Sequence ..................................................................10-5
11
ELECTRICAL SPECIFICATIONS
11.1 Maximum Ratings................................................................................................11-1
11.2 Thermal Characteristics.......................................................................................11-1
11.3 DC Electrical Characteristics...............................................................................11-2
11.4 LCD Driver DC Electrical Characteristics ............................................................11-4
11.5 A/D Converter Electrical Characteristics .............................................................11-5
11.6 Control Timing .....................................................................................................11-7
TPG
MC68HC05L1
MOTOROLA
iii
Paragraph
Number
Page
Number
TITLE
12
MECHANICAL SPECIFICATIONS
12.1 56-pin SDIP Package ..........................................................................................12-1
12.2 64-pin QFP Package ...........................................................................................12-2
A
MC68HC705L1
A.1
A.2
A.3
A.3.1
A.3.2
A.4
A.4.1
A.4.2
A.5
Features ............................................................................................................... A-1
Memory Map ........................................................................................................ A-1
Modes of Operation.............................................................................................. A-3
User Mode ...................................................................................................... A-3
Bootstrap Mode .............................................................................................. A-3
EPROM Programming.......................................................................................... A-3
Program Control Register (PCR) .................................................................... A-4
EPROM Programming Sequence................................................................... A-4
Pin Assignments................................................................................................... A-6
TPG
MOTOROLA
iv
MC68HC05L1
LIST OF FIGURES
Figure
Number
Page
Number
TITLE
1-1
2-1
2-2
2-3
3-1
4-1
4-2
4-3
4-4
5-1
5-2
5-3
5-4
5-5
6-1
7-1
7-2
7-3
7-4
8-1
8-2
10-1
10-2
10-3
10-4
11-1
12-1
12-2
A-1
A-2
A-3
A-4
MC68HC05L1/MC68HC705L1 Block Diagram.......................................................1-2
Pin Assignments for 56-pin SDIP package.............................................................2-3
Pin Assignment for 64-pin QFP package................................................................2-3
Parallel Port I/O Circuitry........................................................................................2-5
MC68HC05L1/MC68HC705L1 Memory Map.........................................................3-2
Power-On Reset and RESET Timing......................................................................4-2
Interrupt Stacking Order .........................................................................................4-3
Hardware Interrupt Flowchart.................................................................................4-5
External Interrupt Circuit and Timing......................................................................4-7
16-Bit Programmable Timer Block Diagram ...........................................................5-2
Timer State Timing Diagram for Reset ...................................................................5-12
Timer State Timing Diagram for Input Capture.......................................................5-12
Timer State Timing Diagram for Output Compare ..................................................5-13
Timer State Diagram for Timer Overflow ................................................................5-13
A/D Converter Block Diagram.................................................................................6-1
LCD Driver Block Diagram......................................................................................7-1
LCD Voltage Level Divider......................................................................................7-4
LCD Waveform with 3 Backplanes..........................................................................7-5
LCD Waveform with 4 Backplanes..........................................................................7-6
Programming model ...............................................................................................8-1
Stacking order ........................................................................................................8-2
Flowchart of Mode Entering .................................................................................10-1
Self-Check Mode Timing ......................................................................................10-2
MC68HC05L1 Self-Test Circuit.............................................................................10-3
MC68HC705L1 EPROM Programming Circuit.....................................................10-6
LCD Driver Voltage Divider...................................................................................11-4
56-pin SDIP Mechanical Dimensions ...................................................................12-1
64-pin QFP Mechanical Dimensions ....................................................................12-2
MC68HC705L1 Memory Map................................................................................ A-2
MC68HC705L1 EPROM Programming Circuit...................................................... A-5
Pin Assignments for 56-pin SDIP package............................................................ A-6
Pin Assignment for 64-pin QFP package............................................................... A-6
TPG
MC68HC05L1
MOTOROLA
v
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TPG
MOTOROLA
vi
MC68HC05L1
LIST OF TABLES
Table
Number
Page
Number
TITLE
2-1
3-1
4-1
4-2
6-1
6-2
7-1
7-2
7-3
8-1
8-2
8-3
8-4
8-5
8-6
8-7
I/O Pin Functions....................................................................................................2-4
MC68HC05L1/MC68HC705L1 I/O Registers.........................................................3-3
Reset Action on Internal Circuit..............................................................................4-2
Reset/Interrupt Vector Addresses ..........................................................................4-4
A/D Clock Selection................................................................................................6-3
ADC Channel Assignment......................................................................................6-4
LCD RAM Organization..........................................................................................7-2
Multiplex Ratio/Backplane Selection.......................................................................7-3
LCD Prescaler Division Versus Bit Levels ..............................................................7-4
MUL instruction.......................................................................................................8-5
Register/memory instructions.................................................................................8-5
Branch instructions.................................................................................................8-6
Bit manipulation instructions...................................................................................8-6
Read/modify/write instructions ...............................................................................8-7
Control instructions.................................................................................................8-7
Instruction set .........................................................................................................8-8
M68HC05 opcode map...........................................................................................8-10
Mode Selection.....................................................................................................10-2
Self-Check Report................................................................................................10-4
DC Electrical Characteristics for 5V Operation.....................................................11-2
DC Electrical Characteristics for 2.7V Operation..................................................11-3
LCD Driver DC Electrical Characteristics .............................................................11-4
A/D Converter Electrical Characteristics for 5V Operation...................................11-5
A/D Converter Electrical Characteristics for 2.7V Operation................................11-6
Control Timing for 5V Operation...........................................................................11-7
Control Timing for 2.7V Operation........................................................................11-8
MC68HC705L1 Operating Mode Entry Conditions ............................................... A-3
8-8
10-1
10-2
11-1
11-2
11-3
11-4
11-5
11-6
11-7
A-1
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MC68HC05L1
MOTOROLA
vii
THIS PAGE LEFT BLANK INTENTIONALLY
TPG
MOTOROLA
viii
MC68HC05L1
1
1
GENERAL DESCRIPTION
The MC68HC05L1 HCMOS microcontroller is a member of the M68HC05 Family of low-cost
single-chip microcontrollers. This 8-bit microcontroller unit (MCU) contains an on-chip oscillator,
CPU, RAM, ROM, parallel I/O capability with pins programmable as input or output, one 16-bits
programmable timer, liquid crystal display driver circuitry and 6-channel A/D converter.
The MC68HC705L1 is an EPROM version of the MC68HC05L1; it is available in windowed and
OTP 56-pin SDIP and 64-pin QFP packages. All references to the MC68HC05L1 apply equally to
the MC68HC705L1, unless otherwise stated. References specific to the MC68HC705L1 are
italicized in the text, and also, for quick reference, they are summarized in Appendix A.
1.1
Features
•
•
•
•
•
8-bit architecture
Power saving Stop and Wait modes
128 bytes of on-chip RAM (64 bytes for stack)
16x4 bits of on-chip display RAM
4096 bytes of on-chip ROM for MC68HC05L1
5632 bytes of on-chip EPROM for MC68HC705L1
•
•
•
•
•
•
•
17 bidirectional I/O lines, 10 input only lines and 2 output only lines
LCD driver circuitry with a selection of 3x12, 3x16, 4x12, 4x16 segments drive
6-Channel A/D converter
Internal 16-bit free-running counter timer
On-chip crystal oscillator
Self-check mode
Available in 56-pin SDIP and 64-pin QFP packages
TPG
MC68HC05L1
GENERAL DESCRIPTION
MOTOROLA
1-1
1
8
USER ROM/EPROM - 4K/5.5K BYTES
SELF-CHECK/BOOTSTRAP ROM - 480 BYTES
RAM - 128 BYTES
PA0 - PA7
PB0 - PB7
8
7
0
ACCUMULATOR
0
M68HC05
CPU
7
0
PC0/AN0
PC1/AN1
PC2/AN2
PC3/AN3
PC4/AN4
PC5/AN5
PC6/VRH
PC7/VRL
INDEX REGISTER
0
12
0
5
1
0
0
0
1
1
STACK POINTER
8-BIT
ADC
15
4
0
IRQ
PROGRAM COUNTER
0
7
1
1
H
I
N Z C
RESET
CONDITION CODE REGISTER
PD0/TCAP1
PD1/TCAP2
PD2/TCMP1
PD3/TCMP2
16-BIT
TIMER
OSC1
OSC2
OSC
÷ 2
LCD CLOCK
PRESCALER
DISPLAY RAM
16x4-bit
VOLTAGE
GENERATOR
VLCD
PE0
DATA
LATCHES
16
VSEG0
:
VSEG15
SEGMENT
DRIVER
VDD
VSS
4
VBP0
:
VBP3
BACKPLANE
DRIVER
POWER
Figure 1-1 MC68HC05L1/MC68HC705L1 Block Diagram
TPG
MOTOROLA
1-2
GENERAL DESCRIPTION
MC68HC05L1
2
2
PIN DESCRIPTION AND
INPUT/OUTPUT PORTS
This section provides a description of the functional pins and I/O programming of the
MC68HC05L1/MC68HC705L1 microcontroller.
2.1
PIN DESCRIPTIONS
56-pin SDIP
PIN No.
64-pin QFP
PIN No.
PIN NAME
VDD, VSS
DESCRIPTION
Power is supplied to the MCU using these two pins.VDD is power and
VSS is ground.
27, 28
23, 24
In the user mode this pin is an external hardware interrupt IRQ. It is
software programmable to provide two choices of interrupt triggering
sensitivity. These options are:
IRQ/VPP
18
12
1) negative edge-sensitive triggering only, or
2) both negative edge-sensitive and level sensitive triggering.
In bootstrap mode on the MC68HC705L1, this is the EPROM
programming voltage input pin.
The active low RESET input is not required for start-up, but can be
used to reset the MCU internal state and provide an orderly software
start-up procedure.
RESET
45
43
These pins provide connections to the on-chip oscillator. The
maximum crystal frequency is 4.2MHz. OSC1 may be driven by an
external oscillator if an external crystal circuit is not used.
OSC1, OSC2
PA0-PA7
46, 47
19-26
29-36
44, 45
These eight I/O lines comprise port A.The state of any pin is software
programmable. All port A lines are configured as input during power
on or external reset.
13-16, 19-22
25-30, 33, 34
These eight I/O lines comprise port B.The state of any pin is software
programmable. All port B lines are configured as input during power
on or external reset.
PB0-PB7
TPG
MC68HC05L1
PIN DESCRIPTION AND INPUT/OUTPUT PORTS
MOTOROLA
2-1
56-pin SDIP
PIN No.
64-pin QFP
PIN No.
PIN NAME
DESCRIPTION
These eight lines comprise port C.These port lines perform either as
standard input ports or as ADC inputs.
AN0-AN5 are the ADC input channels. VRH and VRL are the ADC
voltage reference inputs.
Port C is configured for ADC use when the ADON bit in the ADC
Status/Control register (bit 5 of address $09) is set.
2
PC0-PC7
37-44
35-42
AN0-AN5
VRH, VRL
37-42
43, 44
35-40
41, 42
These four lines comprise port D. PD0 and PD1 are input only and are
shared with TCAP1 and TCAP2. PD2 and PD3 are output only and
are shared with TCMP1 and TCMP2. TCAPx and TCMPx are
functions of the programmable timer.
PD0-PD3
16, 15, 13, 14
10, 9, 7, 8
TCAP1, TCAP2
TCMP1, TCMP2
16, 15
13, 14
10, 9
7, 8
PD2/TCMP1 is set for TCMP1 when the TE2 bit is “0” in the General
Control register ($0A).
PD3/TCMP2 is set for TCMP2 when the TE1 bit is “0” in the General
Control register ($0A).
Port E consist of only one pin. The state of this pin is software
programmable, and is configured as input during power on or external
reset.
PE0
17
11
These 4 output pins provide the backplane drive signals to the LCD
unit. If a 3x multiplex is selected, VBP3 should be grounded.
VBP0-VBP3
12, 11, 10, 9
6, 5, 4, 3
These 16 output pins provide the segment drive signals to the LCD
unit. If only x12 multiplex is selected, VSEG12-VSEG15 should be
grounded.
1, 2, 62-51,
48, 47
VSEG0-VSEG15
VLCD
8-1, 56-49
48
46
This pin is the input voltage to the LCD driver circuitry.
TPG
MOTOROLA
2-2
PIN DESCRIPTION AND INPUT/OUTPUT PORTS
MC68HC05L1
2.1.1
Pin Assignments
2
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
VSEG7
VSEG6
VSEG5
VSEG4
VSEG3
VSEG2
VSEG1
VSEG0
VBP3
1
VSEG8
VSEG9
VSEG10
VSEG11
VSEG12
VSEG13
VSEG14
VSEG15
VLCD
2
3
4
5
6
7
8
9
VBP2
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
OSC2
VBP1
VBP0
PD2/TCMP1
PD3/TCMP2
PD1/TCAP2
PD0/TCAP1
PE0
OSC1
RESET
PC7/VRL
PC6/VRH
PC5/AN5
PC4/AN4
PC3/AN3
PC2/AN2
PC1/AN1
PC0/AN0
PB7
IRQ/VPP
PA0
PA1
PA2
PA3
PB6
PA4
PB5
PA5
PB4
PA6
PB3
PA7
PB2
VDD
PB1
VSS
PB0
Figure 2-1 Pin Assignments for 56-pin SDIP package
VSEG1
VSEG0
VBP3
1
2
3
48 VSEG14
47 VSEG15
46 VLCD
VBP2
4
45 OSC2
VBP1
5
44 OSC1
VBP0
6
7
8
9
10
11
12
13
14
15
16
43 RESET
42 PC7/VRL
41 PC6/VRH
40 PC5/AN5
39 PC4/AN4
38 PC3/AN3
37 PC2/AN2
36 PC1/AN1
35 PC0/AN0
34 PB7
PD2/TCMP1
PD3/TCMP2
PD1/TCAP2
PD0/TCAP1
PE0
IRQ/VPP
PA0
PA1
PA2
PA3
33 PB6
Figure 2-2 Pin Assignment for 64-pin QFP package
TPG
MC68HC05L1
PIN DESCRIPTION AND INPUT/OUTPUT PORTS
MOTOROLA
2-3
2.2
INPUT/OUTPUT PORTS
Parallel Ports
2
2.2.1
Port A, B, and E may be programmed as an input or an output under software control. The
direction of the pins is determined by the state of corresponding bit in the port data direction
register (DDR). Each 8-bit port has an associated 8-bit data direction register. Any port A, B, or E
pin is configured as an output if its corresponding DDR bit is set to a logic one. A pin is configured
as an input if its corresponding DDR bit is cleared to a logic zero. At power-on or reset, all DDRs
are cleared, which configure all port A, B, and E pins as inputs. The data direction registers are
capable of being written to or read by the processor. Refer to Figure 2-3 and Table 2-1. During the
programmed output state, a read of the data register actually reads the value of the output data
latch and not the I/O pin.
Table 2-1 I/O Pin Functions
R/W
DDR
I/O Pin Function
0
0
1
1
0
1
0
1
The I/O pin is in input mode. Data is written into the output data latch.
Data is written into the output data latch and output to the I/O pin.
The state of the I/O pin is read.
The I/O pin is in an output mode. The output data latch is read.
2.2.2
Fixed Ports
Port C is an 8-bit fixed input port that is shared with 6 analog inputs and 2 voltage references of
the ADC. PC0-PC5 will be configured as 6 analog input when the ADON bit of the ADC Status and
Control register (bit5 of address $09) is set. PC6 and PC7 will be configured as VRH and VRL
correspondingly. At power-on or reset, port C defaults to an input port.
Port D is a four bit port, with PD0 and PD1 are input only, and PD2 and PD3 are output only. PD0
and PD1 are shared with TCAP1 and TCAP2 respectively. PD2 and PD3 are shared with TCMP1
and TCMP2 respectively.
TPG
MOTOROLA
2-4
PIN DESCRIPTION AND INPUT/OUTPUT PORTS
MC68HC05L1
DATA DIRECTION
REGISTER BIT
2
INTERNAL
MC68HC05
CONNECTIONS
LATCHED OUTPUT
DATA BIT
OUTPUT
I/O PIN
INPUT
REGISTER
BIT
INPUT I/O
(a)
7
6
5
4
3
2
1
0
TYPICAL PORT
DDR 7
DDR 6 DDR 5
DDR 4
DDR 3
DDR 2
DDR 1 DDR 0
DATA DIRECTION REGISTER
TYPICAL PORT REGISTER
I/O PORT LINES
Px7
Px6
Px5
Px4
Px3
Px2
Px1
Px0
(b)
VDD
NOTE:
(1) IP = INPUT PROTECTION
(2) LATCH-UP PROTECTION NOT SHOWN
PORT DATA
PORT DDR
P
N
&
PAD
+
IP
INTERNAL LOGIC
(c)
Figure 2-3 Parallel Port I/O Circuitry
TPG
MC68HC05L1
PIN DESCRIPTION AND INPUT/OUTPUT PORTS
MOTOROLA
2-5
2
THIS PAGE LEFT BLANK INTENTIONALLY
TPG
MOTOROLA
2-6
PIN DESCRIPTION AND INPUT/OUTPUT PORTS
MC68HC05L1
3
3
MEMORY AND REGISTERS
This section describes the organization of the on-chip memory.
3.1
Memory Map
The CPU can address 8K-bytes of memory space. The ROM portion of memory holds the
program instructions, fixed data, user-defined vectors, and interrupt service routines. The RAM
portion of memory holds variable data. I/O registers are memory-mapped so that the CPU can
access their locations in the same way that it accesses all other memory locations. Figure 3-1
shows the Memory Map for the MC68HC05L1/MC68HC705L1.
3.2
Input/Output Section
The first 32 addresses of memory space, $0000-$001F, are the I/O section. These are the
addresses of the I/O control registers, status registers, and data registers. Table 3-1 shows these
registers and their respective bits.
3.3
RAM
The 128 addresses from $0080-$00FF are RAM locations.The CPU uses the 64 RAM addresses,
$00C0-$00FF, as the stack. Before processing an interrupt, the CPU uses five bytes of the stack
to save the contents of the CPU registers. During a subroutine call, the CPU uses two bytes of the
stack to store the return address. The stack pointer decrements during pushes and increments
during pulls.
Note:
Be careful when using nested subroutines or multiple interrupt levels. The CPU may
overwrite data in the RAM during a subroutine or during the interrupt stacking
operation. Once the stack pointer passes $00C0, it wraps round back to $00FF.
TPG
MC68HC05L1
MEMORY AND REGISTERS
MOTOROLA
3-1
MC68HC05L1
$0000
0
Port A Data Register
Port B Data Register
$00
$01
$02
$03
$04
$05
$06
$07
$08
$09
$0A
$0B
I/O
32 Bytes
Ports
$001F
$0020
Port C Input Data Register
Port D Data Register
8 Bytes
User ROM
48 Bytes
Port E Data Register
3
Port A Data Direction Register
Port B Data Direction Register
Port E Data Direction Register
ADC Data Register
ADC
2 Bytes
$004F
$0080
Reserved
General Control
1 Bytes
LCD Prescaler
1 Bytes
User RAM
128 Bytes
ADC Status and Control Register
General Control Register
LCD Prescaler Register
$00BF
$00C0
Reserved
2 Bytes
Stack
64 Bytes
EPROM Programming
1 Byte
Reserved
$0C
$0D
$0E
$0F
$10
$11
$12
$13
$14
$15
$16
$17
$18
$19
$1A
$1B
$1C
$1D
$1E
$1F
$00FF
Reserved
Reserved
3 Bytes
Reserved
EPROM Program Control Register
Reserved
$0200
$020F
Display RAM
16x4-bit
Reserved
Reserved
Timer Control Register
Timer
14 Bytes
Timer Status Register
Timer Input Capture High Register 1
Timer Input Capture Low Register 1
Timer Output Compare High Register 1
Timer Output Compare Low Register 1
Timer Counter High Register
Timer Counter Low Register
Timer Alternate Counter High Register
Timer Alternate Counter Low Register
Timer Input Capture High Register 2
Timer Input Capture Low Register 2
Timer Output Compare High Register 2
Timer Output Compare Low Register 2
Reserved
31
$0800
$17FF
$1E00
$0800
User ROM
4096 Bytes
User EPROM
5632 Bytes
Reserved
$1DFF
Self-Check
Program
496 Bytes
Bootstrap Program
496 Bytes
$1FF0
$1FF2
$1FF4
$1FF6
$1FF8
$1FFA
$1FFC
$1FFE
Reserved
Reserved
TIMOV
TIMOC
TIMIC
$1FDF
$1FE0
Self-Check
Vectors
16 Bytes
Bootstrap Vectors
16 Bytes
$1FEF
$1FF0
User Vectors
16 Bytes
IRQ
User Vectors
16 Bytes
SWI
$1FFF
RESET
MC68HC705L1
Figure 3-1 MC68HC05L1/MC68HC705L1 Memory Map
TPG
MOTOROLA
3-2
MEMORY AND REGISTERS
MC68HC05L1
Table 3-1 MC68HC05L1/MC68HC705L1 I/O Registers
State
on reset
Register Name
Port A data
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
$00
$01
$02
$03
$04
$05
$06
$07
$08
$09
$0A
$0B
$0C
$0D
$0E
$0F
$10
$11
$12
$13
$14
$15
$16
$17
$18
$19
$1A
$1B
$1C
$1D
$1E
$1F
bit 7
bit 7
bit 7
bit 6
bit 6
bit 6
bit 5
bit 5
bit 5
bit 4
bit 4
bit 4
bit 3
bit 3
bit 3
bit 3
bit 2
bit 2
bit 2
bit 2
bit 1
bit 1
bit 1
bit 1
bit 0 unaffected
bit 0 unaffected
bit 0 unaffected
bit 0 unaffected
bit 0 unaffected
3
Part B data
Port C input data
Port D data
Port E data
Port A data direction
Port B data direction
Port E data direction
ADC Data
DDR7 DDR6 DDR5 DDR4 DDR3 DDR2 DDR1 DDR0 0000 0000
DDR7 DDR6 DDR5 DDR4 DDR3 DDR2 DDR1 DDR0 0000 0000
DDR0 0000 0000
uuuu uuuu
ADC status and control
General control
COCO ADRC ADON
INTO TE2 TE1
CH3
CH2
CH1
INT
CH0 0000 0000
MS 0000 0000
DON
LCD prescaler
LCDP2 LCDP1 LCDP0 0000 0000
Reserved
Reserved
EPROM program control
Reserved
LATA EPGM uuuu uu00
Reserved
Reserved
Timer control
ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1 0000 00u0
Timer status
ICF1 OCF1 TOF ICF2 OCF2
uuuu u000
unaffected
unaffected
unaffected
unaffected
$FF
Timer input capture 1 high
Timer input capture 1 low
Timer output compare 1 high
Timer output compare 1 low
Timer counter high
Timer counter low
Timer alternate counter high
Timer alternate counter low
Timer input capture 2 high
Timer input capture 2 low
Timer output compare 2 high
Timer output compare 2 low
$FC
$FF
$FC
unaffected
unaffected
unaffected
unaffected
TPG
MC68HC05L1
MEMORY AND REGISTERS
MOTOROLA
3-3
3
THIS PAGE LEFT BLANK INTENTIONALLY
TPG
MOTOROLA
3-4
MEMORY AND REGISTERS
MC68HC05L1
4
RESETS AND INTERRUPTS
4
4.1
RESETS
The MC68HC05L1 can be reset in two ways: by the initial power-on reset function and by an active
low input to the RESET pin. Any of these resets will cause the program to go to its starting
address, specified by the contents of memory locations $1FFE and $1FFF, and cause the interrupt
mask of the Condition Code register to be set.
4.1.1
RESET Pin
The RESET input pin is used to reset the MCU to provide an orderly software start-up procedure.
When using the external reset, the RESET pin must stay low for a minimum of 1.5tcyc. The
RESET pin contains an internal Schmitt Trigger as part of its input to improve noise immunity.
4.1.2
Power-On Reset (POR)
The power-on reset occurs when a positive transition is detected on the supply voltage, V . The
DD
power-on reset is used strictly for power-up conditions, and should not be used to detect any drops
in the power supply voltage. There is no provision for a power-down reset. The power-on circuitry
provides for a 4064 tcyc delay from the time that the oscillator becomes active. If the external
RESET pin is low at the end of the 4064 tcyc time out, the processor remains in the reset condition
until RESET goes high. The user must ensure that V has risen to a point where the MCU can
DD
operate properly prior to the time the 4064 POR cycles have elapsed. If there is doubt, the external
RESET pin should remain low until such time that V has risen to the minimum operating voltage
DD
specified.
Table 4-1 shows the internal circuit actions on reset, but not necessary in order of occurrence.
TPG
MC68HC05L1
RESETS AND INTERRUPTS
MOTOROLA
4-1
Table 4-1 Reset Action on Internal Circuit
DEFAULT CONDITIONS AFTER RESET
1
2
Timer prescaler reset to zero state
Timer counter configures to $FFFC
3
Timer output compare (OCF1 and OCF2) bits reset to zero
All timer interrupt enable bits cleared (ICIE, OCIE, and TOIE) to disable timer interrupt
Timer OLVL1 and OLVL2 bits are cleared
4
5
6
All data direction registers cleared to zero (I/O ports set to input)
Configure stack pointer to $00FF
7
4
8
Force internal address bus to restart vector ($1FFE-$1FFF)
Set I bit in the condition code register to a logic one
Clear STOP latch
9
10
11
12
13
14
Clear external interrupt latch
Clear WAIT latch
All bits in address $09 and bits 4 to 7 in $0A are cleared; bits 0 and 1 in $0A are set
Bits 3 to 7 in $0B are cleared
Listed numbers do not represent order of occurrence.
tVDDR
VDD
VDD THRESHOLD (TYPICALLY 1-2V)
OSC1 PIN1
toxov
4064 tcyc
tcyc
INTERNAL
CLOCK2
INTERNAL
1FFE
1FFF
NEW PC
1FFE
1FFE
PCH
1FFF
PCL
NEW PC
ADDRESS
BUS2
INTERNAL
DATA
OP
CODE
NEW
PCL
NEW
PCH
OP
CODE
BUS2
tRL=1.5tCYC
3
RESET
NOTES:
1. OSC1 is not meant to represent frequency. It is only used to represent time.
2. Internal clock, internal address bus, and internal data bus signals are not available externally.
3. Next rising edge of internal clock after rising edge of RESET initiates reset sequence.
Figure 4-1 Power-On Reset and RESET Timing
TPG
MOTOROLA
4-2
RESETS AND INTERRUPTS
MC68HC05L1
4.2
INTERRUPTS
The MC68HC05L1 is capable of handling six types of interrupt, five hardware and one software.
The interrupt mask bit (“I” bit in the Condition Code register), if set, masks all interrupts except the
software interrupt, SWI.Timer interrupts have several flags which will cause the interrupt. Interrupt
flags are found in “read only” status registers, while their enables are in associated control
registers. They are never mixed in the same register. If the enable bit is “0”, it masks the interrupt
from occurring but does not inhibit the flag from being set. A reset clears all enable bits. The
general sequence for clearing an interrupt is a software sequence of reading the status register
while the flag is set followed by a read or write of an associated register. When any of these
interrupts occur, and if enabled, normal processing is suspended at the end of the current
instruction execution. The state of the machine is pushed onto the stack (see Figure 4-2 for
stacking order) and the appropriate vector points to the starting address of the interrupt service
routine (see Table 4-2). Also, the interrupt mask bit in the condition code register is set.This masks
further interrupts. At the completion of the service routine, the software normally contains an RTI
instruction which, when executed, restores the machine state and continues executing the
interrupted program. Interrupt priority is based on interrupt vector locations. The higher the vector
locations, the higher the priority. RESET has the highest priority.
4
Note:
The interrupt mask bit (I bit) will be cleared if and only if the corresponding bit stored
on the stack is zero.
$00C0 (BOTTOM OF STACK)
$00C1
$00C2
UNSTACKING
ORDER
•
•
•
•
•
•
5
4
3
2
1
1
2
3
4
5
CONDITION CODE REGISTER
ACCUMULATOR
INDEX REGISTER
PROGRAM COUNTER (HIGH BYTE)
PROGRAM COUNTER (LOW BYTE)
•
•
•
•
•
STACKING
ORDER
•
$00FD
$00FE
$00FF (TOP OF STACK)
Figure 4-2 Interrupt Stacking Order
TPG
MC68HC05L1
RESETS AND INTERRUPTS
MOTOROLA
4-3
Table 4-2 Reset/Interrupt Vector Addresses
Register
Flag Name
Interrupt
Reset
CPU Interrupt
RESET
SWI
Vector Address
$1FFE-$1FFF
$1FFC-$1FFD
$1FFA-$1FFB
$1FF8-$1FF9
$1FF6-$1FF7
$1FF4-$1FF5
–
–
–
–
–
Software
–
External Interrupt
Input Capture
Output Compare
Timer Overflow
IRQ
ICF
OCF
TOF
TIMIC
Timer Status
TIMOC
TIMOV
4
4.2.1
Hardware Controlled Sequences
The following three functions are not strictly interrupts, however, they are tied very closely to the
interrupts. These functions are RESET, STOP, WAIT.
1) RESET
The RESET input pin causes the program to go to its starting
address. This address is specified by the contents of memory
locations $1FFE and $1FFF. The interrupt mask of the condition
code register is also set. Most parts of the MCU is configured to
some known state as described in Table 4-1.
2) STOP
3) WAIT
The STOP instruction causes the oscillator to be turned off and
the processor “sleeps” until an external interrupt (IRQ) or RESET
occurs. See section 9 on Low Power Modes.
The WAIT instruction causes all processor clocks to stop, but
leaves the Timer running. This “rest” state of the processor can
be exited by RESET, an external interrupt (IRQ), or any Timer
interrupts. There are no special wait vectors for these individual
interrupts. See section 9 on Low Power Modes.
4.2.2
Software Interrupt (SWI)
The software interrupt is an executable instruction. The action of the SWI instruction is similar to
the hardware interrupts. The SWI is executed regardless of the state of the interrupt mask in the
condition code register. The service routine address is specified by the contents of memory
location $1FFC and $1FFD.
TPG
MOTOROLA
4-4
RESETS AND INTERRUPTS
MC68HC05L1
EXECUTE
INSTRUCTION
4
N
INSTRUCTION
COMPLETE?
Y
N
N
LOAD NEXT
INSTRUCTION
INTERRUPT?
Y
INTERRUPT
MASK BIT
I = 0 ?
Y
FORCE HWI
STACK CPU REGISTERS
SET INTERRUPT MASK BIT
FETCH INT VECTOR
HWI
INSTRUCTION
COMPLETE?
N
Y
Figure 4-3 Hardware Interrupt Flowchart
TPG
MC68HC05L1
RESETS AND INTERRUPTS
MOTOROLA
4-5
4.2.3
External Interrupt (IRQ)
The external interrupt IRQ can be software configured for “negative-edge” or “negative-edge and
level” sensitive triggering by the INTO bit in the General Control register.
State
on reset
Address bit 7
bit 6
bit 5
TE1
bit 4
DON
bit 3
bit 2
bit 1
INT
bit 0
General Control Register
$0A INTO TE2
MS 0000 0000
4
INTO
1 (set)
–
Negative edge triggering for IRQ only.
0 (clear) – Level and negative edge triggering for IRQ.
When the signal of the external interrupt pin, IRQ, satisfies the condition selected, an external
interrupt occurs. The actual processor interrupt is generated only if the interrupt mask bit of the
condition code register is also cleared. When the interrupt is recognized, the current state of the
processor is pushed onto the stack and the interrupt mask bit in the condition code register is set.
This masks further interrupts until the present one is serviced. The service routine address is
specified by the contents of $1FFA & $1FFB.
The interrupt logic recognizes negative edge transitions and pulses (special case of negative
edges) on the external interrupt line. Figure 4-4 shows both a block diagram and timing for the
interrupt line (IRQ) to the processor. The first method is used if pulses on the interrupt line are
spaced far enough apart to be serviced.The minimum time between pulses is equal to the number
of cycles required to execute the interrupt service routine plus 21 cycles. Once a pulse occurs, the
next pulse should not occur until the MCU software has exited the routine (an RTI occurs). The
second configuration shows several interrupt lines wired-OR to perform the interrupt at the
processor. Thus, if the interrupt lines remain low after servicing one interrupt, the next interrupt is
recognized.
Note:
The internal interrupt latch is cleared in the first part of the service routine; therefore,
one (and only one) external interrupt pulse could be latched during t
as soon as the I bit is cleared.
and serviced
ILIL
4.2.4
Programmable Timer Interrupt
Five timer interrupt flags are found in the five most significant bits of the Timer Status register
(TSR) at location $13. All five interrupts will vector to their respective addresses as indicated in
Table 4-2.
TPG
MOTOROLA
4-6
RESETS AND INTERRUPTS
MC68HC05L1
LEVEL SENSITIVE TRIGGER
IRQ
VDD
+
EXTERNAL
INTERRUPT
REQUEST
Q
Q
D
&
INTERRUPT PIN
IRQ
C
R
I BIT (CC)
4
POWER-ON RESET
EXTERNAL RESET
+
EXTERNAL INTERRUPT
BEING SERVICED
(a) Interrupt Function Diagram
EDGE SENSITIVE TRIGGER
CONDITION
IRQ
tILIH
The minimum pulse width tILIH is either
125ns (VDD=5V) or 250ns (VDD=3V).
The period tILIL should not be less than
the number of tcyc cycles it takes to
execute the interrupt service routine
plus 21 tcyc cycles.
tILIL
tILIL
LEVEL SENSITIVE TRIGGER
CONDITION
Wired ORed
Interrupt signals
if after servicing an interrupt the
external interrupt pins remain low, then
the next interrupt is recognized.
Normally used with wired OR
connection.
IRQ
(b) Interrupt Mode Diagram
Figure 4-4 External Interrupt Circuit and Timing
TPG
MC68HC05L1
RESETS AND INTERRUPTS
MOTOROLA
4-7
Each flag bit is defined as follows:
State
on reset
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Timer Status Register
$13 ICF1 OCF1 TOF ICF2 OCF2
uuuu u000
TOF - Timer Overflow Flag
TOF is set during the counter transition of $FFFF to $0000. It is cleared by
reading the TSR (with TOF set) followed by reading the Counter Low register
($19).
4
OCF1, OCF2 - Output Compare Flag 1 and Output Compare 2
The appropriate OCF is set when the corresponding Output Compare register
matches the Counter register. It is cleared by reading the TSR (with OCF set)
and then accessing the corresponding Output Compare Low register ($17 or
$1F).
ICF1, ICF2 - Input Capture Flag
The appropriate ICF is set when a proper edge has been sensed by the input
capture edge detector. It is cleared by an CPU read of the TSR (with ICF set) and
then accessing the corresponding Input Capture Low register ($15 or $1D).
There are three timer interrupt enable bits (TOIE, OCIE, and ICIE) in the Timer Control register
(TCR) at location $12, which controls these interrupt flags. Reset clears all enable bits preventing
an interrupt from occurring. The actual processor interrupt is generated only if the interrupt mask
bit of the condition code register is also cleared.When the interrupt is recognized, the current state
of the machine is pushed onto the stack and the interrupt mask bit in the condition code register
is set. This masks further interrupts until the present one is serviced. The service routine address
is specified by the contents of the respective vectors; see Table 4-2.
Refer to section 5 for detailed description of Programmable Timer.
TPG
MOTOROLA
4-8
RESETS AND INTERRUPTS
MC68HC05L1
5
PROGRAMMABLE TIMER
The programmable timer on the MC68HC05L1 consists of a 16-bit read-only free-running counter,
with a fixed divide-by-four prescaler, plus input capture/output compare circuitry.This timer can be
used for many purposes, including input waveform measurements while simultaneously
generating an output waveform. Pulse widths can vary from several microseconds to many
seconds. Figure 5-1 shows a block diagram for the Programmable Timer.
5
The timer has a 16-bit architecture, hence each specific functional segment is represented by two
8-bit registers (high byte and low byte). Generally, assessing the low byte of a specific timer
function allows full control of that function; however, an access of the high byte inhibits that specific
timer function until the low byte is also accessed.
Note:
The I bit in the condition code register should be set while manipulating both the high
and low byte register of a specific timer function to ensure that an interrupt does not
occur.
Fourteen 8-bit registers are associated with the programmable timer.
–
–
–
–
–
–
–
–
Timer Control Register (TCR)
Timer Status Register (TSR)
Input Capture Register 1
Output Compare Register 1
Counter Register
$12
$13
High byte - $14, Low byte - $15
High byte - $16, Low byte - $17
High byte - $18, Low byte - $19
High byte - $1A, Low byte - $1B
High byte - $1C, Low byte - $1D
High byte - $1E, Low byte - $1F
Alternate Counter Register
Input Capture Register 2
Output Compare Register 2
A description of each register is provided in the following paragraphs.
TPG
MC68HC05L1
PROGRAMMABLE TIMER
MOTOROLA
5-1
Internal bus
8
Internal
processor
clock
8-bit
buffer
High Low
High Low
High Low
High Low
High Low
byte byte
byte
byte
byte
byte
byte
byte
byte
byte
÷4
Output
compare
register 1
Output
compare
register 2
16-bit
free-running
counter
$0016
$0017
$001E
$001F
$0018
$0014 Input capture $001C
Input capture
register 1
$0019
$0015
register 2
$001D
Counter
alternate
register
$001A
$001B
5
Internal timer bus
Output
compare
circuit 1
Output
Overflow
detect
Edge
detect
Edge
detect
TCAP2
pin
compare
circuit 2
circuit
circuit 1
circuit 2
TCAP1
pin
TCMP2
pin
D
Q
C
+
+
Latch
TCMP1
pin
D
C
Q
Latch
7
6
5
4
3
Timer status
register
$0013
ICF1 OCF1 TOF ICF2 OCF2
Timer control
register
$0012
ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1
Interrupt circuit
Input capture
interrupt
$1FF8,9
Output compare
interrupt
$1FF6,7
Overflow interrupt
$1FF4,5
Figure 5-1 16-Bit Programmable Timer Block Diagram
TPG
MOTOROLA
5-2
PROGRAMMABLE TIMER
MC68HC05L1
5.1
Counter
The key element in the programmable timer is a 16-bit, free-running counter or counter register,
preceded by a prescaler that divides the internal processor clock by four. The prescaler gives the
timer a resolution of 2µs if the internal bus clock is 2MHz. The counter is incremented during the
low portion of the internal bus clock. Software can read the counter at any time without affecting
its value.
5.1.1
Counter Register and Alternate Counter Register
State
on reset
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
5
Timer counter high
Timer counter low
$0018
$0019
$FF
$FC
State
on reset
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Alternate counter high
Alternate counter low
$001A
$001B
$FF
$FC
The double-byte, free-running counter can be read from either of two locations, $18 & $19 (counter
register) or $1A & $1B (alternate counter register). Reading only the least significant byte (LSB)
of the free-running counter ($19 or $1B) receives the count value at the time of the read. If the
most significant byte (MSB) ($18 or $1A) is read first, the LSB ($19 or $1B) is transferred to a
buffer. This buffer value remains fixed after the first MSB read, even if the MSB is read several
times. This buffer is accessed when the LSB ($19 or $1B) is read, and thus, completes a read
sequence of the complete counter value.
Reading the timer counter register low byte after reading the timer status register clears the timer
overflow flag (TOF), but reading the alternate counter register does not affect TOF. Therefore, the
alternate counter register can be read any time without risk of missing timer overflow interrupts
due to a cleared TOF.
The free-running counter is preset to $FFFC during reset and is always a read-only register.
During a power-on reset, the counter is also preset to $FFFC and begins running after the
oscillator start-up delay. The value in the free-running counter repeats every 262144 internal bus
clock cycles.
TPG
MC68HC05L1
PROGRAMMABLE TIMER
MOTOROLA
5-3
5.2
Input Capture
‘Input Capture’ is a technique whereby an external signal (connected to TCAP1 or TCAP2 pin) is
used to trigger a read of the free-running counter. In this way it is possible to relate the timing of
an external signal to the internal counter value, and hence to elapsed time.
There are two input capture registers: Input Capture register 1 (ICR1) and Input Capture register 2
(ICR2).
The same input capture interrupt enable bit (ICIE) is used for the two input captures.
5.2.1
Input Capture Register 1 (ICR1)
5
State
on reset
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Input capture high 1
Input capture low 1
$0014
$0015
unaffected
unaffected
The two 8-bit registers that make up the 16-bit Input Capture register 1 are read-only, and are used
to latch the value of the free-running counter after the input capture edge detector circuit senses
a valid transition at pin TCAP1. The level transition that triggers the counter transfer is defined by
the input edge bit (IEDG1). When an input capture 1 occurs, the corresponding flag ICF1 in TSR
is set. An interrupt can also accompany an input capture 1 provided the ICIE bit in the TCR is set.
The 8 most significant bits are stored in the Input Capture High 1 register at $14, the 8 least
significant bits in the Input Capture Low 1 register at $15.
The results obtained from an input capture will be one greater than the value of the free-running
counter on the rising edge of the internal bus clock preceding the external transition. The delay is
required for internal synchronization. Resolution is one count of the free-running counter, which is
four internal bus clock cycles. The free-running counter contents are transferred to the Input
Capture register 1 on each valid signal transition whether the input capture 1 flag (ICF1) is set or
clear. The Input Capture register 1 always contains the free-running counter value that
corresponds to the most recent input capture 1. After a read of the Input Capture 1 register MSB
($14), the counter transfer is inhibited until the LSB ($15) is also read. This characteristic causes
the time used in the input capture software routine and its interaction with the main program to
determine the minimum pulse period. A read of the Input Capture 1 register LSB ($15) does not
inhibit the free-running counter transfer since the two actions occur on opposite edges of the
internal bus clock.
Reset does not affect the contents of the Input Capture 1 register, except when exiting Stop mode.
TPG
MOTOROLA
5-4
PROGRAMMABLE TIMER
MC68HC05L1
5.2.2
Input Capture Register 2 (ICR2)
State
on reset
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Input capture high 2
Input capture low 2
$001C
$001D
unaffected
unaffected
The two 8-bit registers that make up the 16-bit Input Capture register 2 are read-only, and are used
to latch the value of the free-running counter after the input capture edge detector circuit senses
a negative transition at pin TCAP2. When an input capture 2 occurs, the corresponding flag ICF2
in TSR is set. An interrupt can also accompany an input capture 2 provided the ICIE bit in the TCR
is set.The 8 most significant bits are stored in the Input Capture High 2 register at $1C, the 8 least
significant bits in the Input Capture Low 2 register at $1D.
5
The results obtained from an input capture will be one greater than the value of the free-running
counter on the rising edge of the internal bus clock preceding the external transition. The delay is
required for internal synchronization. Resolution is one count of the free-running counter, which is
four internal bus clock cycles. The free-running counter contents are transferred to the Input
Capture register 2 on each negative signal transition whether the input capture 2 flag (ICF2) is set
or clear. The Input Capture register 2 always contains the free-running counter value that
corresponds to the most recent input capture 2. After a read of the Input Capture 2 register MSB
($1C), the counter transfer is inhibited until the LSB ($1D) is also read. This characteristic causes
the time used in the input capture software routine and its interaction with the main program to
determine the minimum pulse period. A read of the Input Capture 2 register LSB ($1D) does not
inhibit the free-running counter transfer since the two actions occur on opposite edges of the
internal bus clock.
Reset does not affect the contents of the Input Capture 2 register, except when exiting Stop mode.
5.3
Output Compare
‘Output Compare’ is a technique which may be used, for example, to generate an output
waveform, or to signal when a specific time period has elapsed, by presetting the output compare
register to the appropriate value.
There are two output compare registers: output compare register 1 (OCR1) and output compare
register 2 (OCR2).
The same output compare interrupt enable bit (OCIE) is used for the two output compares.
TPG
MC68HC05L1
PROGRAMMABLE TIMER
MOTOROLA
5-5
5.3.1
Output Compare Register 1 (OCR1)
State
on reset
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Output compare high 1
Output compare low 1
$0016
$0017
unaffected
unaffected
The 16-bit Output Compare register is made up of two 8-bit registers at location $16 (MSB) and
$17 (LSB). The contents of the Output Compare register 1 are compared with the contents of the
free-running counter continually and, if a match is found, the corresponding Output Compare Flag
(OCF1) in the Timer Status register is set and the output level (OLVL1) is transferred to pin
TCMP1. The Output Compare register 1 values and the output level bit should be changed after
each successful comparison to establish a new elapsed time-out. An interrupt can also
accompany a successful output compare provided the corresponding interrupt enable bit (OCIE)
is set. (The free-running counter is updated every four internal bus clock cycles.)
5
After a processor write cycle to the Output Compare register 1 containing the MSB ($16), the
output compare function is inhibited until the LSB ($17) is also written. The user must write both
bytes (locations) if the MSB is written first. A write made only to the LSB ($17) will not inhibit the
compare 1 function. The processor can write to either byte of an Output Compare register 1
without affecting the other byte. The output level (OLVL1) bit is clocked to the output level register
and hence to the TCMP1 pin whether the output compare flag 1 (OCF1) is set or clear. The
minimum time required to update the Output Compare register 1 is a function of the program
rather than the internal hardware. Because the output compare flag 1 and Output Compare
register is not defined at power-on, and not affected by reset, care must be taken when initializing
output compare functions with software. The following procedure is recommended:
–
–
–
write to Output Compare High 1 to inhibit further compares;
read the Timer Status register to clear OCF1 (is set);
write to Output Compare Low 1 to enable the output compare 1 function.
The purpose of this procedure is to prevent the OCF1 bit from being set between the time it is read
and the write to the corresponding output compare register.
All bits of the output compare register are readable and writable and are not altered by the timer
hardware or reset. If the compare function is not needed, the two bytes of the output compare
register can be used as storage locations.
TPG
MOTOROLA
5-6
PROGRAMMABLE TIMER
MC68HC05L1
5.3.2
Output Compare Register 2 (OCR2)
State
on reset
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Output compare high 2
Output compare low 2
$001E
$001F
unaffected
unaffected
The 16-bit Output Compare register is made up of two 8-bit registers at location $1E (MSB) and
$1F (LSB). The contents of the Output Compare register 2 are compared with the contents of the
free-running counter continually and, if a match is found, the corresponding Output Compare Flag
(OCF2) in the Timer Status register is set and the output level (OLVL2) is transferred to pin
TCMP1. The Output Compare register 2 values and the output level bit should be changed after
each successful comparison to establish a new elapsed time-out. An interrupt can also
accompany a successful output compare provided the corresponding interrupt enable bit (OCIE)
is set. (The free-running counter is updated every four internal bus clock cycles.)
5
After a processor write cycle to the Output Compare register 2 containing the MSB ($1E), the
output compare function is inhibited until the LSB ($1F) is also written. The user must write both
bytes (locations) if the MSB is written first. A write made only to the LSB ($1F) will not inhibit the
compare 2 function. The processor can write to either byte of an Output Compare register 2
without affecting the other byte. The output level (OLVL2) bit is clocked to the output level register
and hence to the TCMP2 pin whether the output compare flag 2 (OCF2) is set or clear. The
minimum time required to update the Output Compare register 2 is a function of the program
rather than the internal hardware. Because the output compare flag 2 and Output Compare
register is not defined at power-on, and not affected by reset, care must be taken when initializing
output compare functions with software. The following procedure is recommended:
–
–
–
write to Output Compare High 2 to inhibit further compares;
read the Timer Status register to clear OCF2 (if set);
write to Output Compare Low 2 to enable the output compare 2 function.
The purpose of this procedure is to prevent the OCF2 bit from being set between the time it is read
and the write to the corresponding output compare register.
All bits of the output compare register are readable and writable and are not altered by the timer
hardware or reset. If the compare function is not needed, the two bytes of the output compare
register can be used as storage locations.
5.3.3
Software Force Compare
A software force compare is required in many applications.To achieve this, bit 3 (FOLV1 for OCR1)
and bit 4 (FOLV2 for OCR2) in the Timer Control register are used. These bits always read as
‘zero’, but a write to ‘one’ causes the respective OLVL1 or OLVL2 values to be copied to the
respective output level (TCMP1 and TCMP2 pins).
TPG
MC68HC05L1
PROGRAMMABLE TIMER
MOTOROLA
5-7
Internal logic is arranged such that in a single instruction, one can change OLVL1 and/or OLVL2,
at the same time causing a forced output compare with the new values of OLVL1 and OLVL2. In
conjunction with normal compare, this function allows a wide range of applications including fixed
frequency generation.
A software force compare will affect the corresponding output pin TCMP1 and/or TCMP2, but will
not affect the compare flag, thus it will not generate an interrupt.
5.4
Timer Control and Status
The various functions of the timer are monitored and controlled using the timer control and status
registers described below.
5
5.4.1
Timer Control Register (TCR)
The timer control register ($0012) is used to enable the input captures (ICIE), output compares
(OCIE), and timer overflow (TOIE) functions as well as forcing output compares (FOLV1 and
FOLV2), selecting input edge sensitivity (IEDG1) and levels of output polarity (OLV1 and OLV2).
State
on reset
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Timer control (TCR)
$0012
ICIE OCIE TOIE FOLV2 FOLV1 OLV2 IEDG1 OLVL1 0000 00u0
ICIE - Input Capture Interrupt Enable
If this bit is set, a timer interrupt is enabled whenever the ICF1 or ICF2 status flag (in the Timer
Status register) is set.
1 (set)
–
Input Capture interrupt enabled.
0 (clear) – Input Capture interrupt disabled.
OCIE - Output Compare Interrupt Enable
If this bit is set, a timer interrupt is enabled whenever the OCF1 or OCF2 status flag (in the Timer
Status register) is set.
1 (set)
–
Output Compare interrupt enabled.
0 (clear) – Output Compare interrupt disabled.
TOIE - Timer Overflow Interrupt Enable
If this bit is set, a timer interrupt is enabled whenever the TOF status flag (in the Timer Status
register) is set.
TPG
MOTOROLA
5-8
PROGRAMMABLE TIMER
MC68HC05L1
1 (set)
–
Timer Overflow interrupt enabled.
0 (clear) – Timer Overflow interrupt disabled.
FOLV2 - Force Output Compare 2
This bit always reads as zero, hence writing a zero to this bit has no effect. Writing a one at this
position will force the OLV2 bit to the corresponding output level latch, thus appearing at the
TCMP2 pin. Note that this bit does not affect the OCF2 bit of the Timer Status register.
1 (set)
–
OVL2 bit forced to output level latch.
0 (clear) – No effect.
FOLV1 - Force Output Compare 1
5
This bit always reads as zero, hence writing a zero to this bit has no effect. Writing a one at this
position will force the OLV1 bit to the corresponding output level latch, thus appearing at the
TCMP1 pin. Note that this bit does not affect the OCF1 bit of the Timer Status register.
1 (set)
–
OVL1 bit forced to output level latch.
0 (clear) – No effect.
OLVL2 - Output Level Voltage Latch 2
When OLVL2 is set a high output level will be clocked into the output level register by the next
successful output compare, and will appear on the TCMP2 pin. When clear, it will be a low level
which will appear on the TCMP2 pin.
1 (set)
–
High output on TCMP2 pin if counter compare 2 is true.
0 (clear) – Low output on TCMP2 pin if counter compare 2 is true.
IEDG1 - Input Edge 1
When IEDG is set, a positive-going edge on the TCAP1 pin will trigger a transfer of the
free-running counter value to the Input Capture register 1. When clear, a negative-going edge
triggers the transfer.
1 (set)
–
TCAP1 is positive-going edge sensitive.
0 (clear) – TCAP1 is negative-going edge sensitive.
Note:
There is no need for an equivalent bit for the Input Capture register 2 ad TCAP2 is
negative-going edge sensitive only.
TPG
MC68HC05L1
PROGRAMMABLE TIMER
MOTOROLA
5-9
OLVL1 - Output Level Voltage Latch 1
When OLVL1 is set a high output level will be clocked into the output level register by the next
successful output compare, and will appear on the TCMP1 pin. When clear, it will be a low level
which will appear on the TCMP1 pin.
1 (set)
–
High output on TCMP1 pin if counter compare 1 is true.
0 (clear) – Low output on TCMP1 pin if counter compare 1 is true.
5.4.2
Timer Status Register (TSR)
The Timer Status register ($13) contains the status bits corresponding to the four timer interrupt
conditions - ICF1, OCF1, TOF, ICF2 and OCF2.
5
Accessing the Timer Status register satisfies the first condition required to clear the status bits.
The remaining step is to access the register corresponding to the status bit.
State
on reset
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Timer status (TSR)
$0013 ICF1 OCF1 TOF ICF2 OCF2
uuuu u000
ICF1 - Input Capture Flag 1
This bit is set when the selected polarity of the edge is detected by the input capture edge detector
1 at TCAP1; an input capture interrupt will be generated if ICIE is set. ICF1 is cleared by reading
the TSR and then the Input Capture Low register 1 ($15).
1 (set)
–
A valid input capture has occurred at TCAP1 pin.
0 (clear) – No input capture has occurred at TCAP1 pin.
OCF1 - Output Compare Flag 1
This bit is set when the output compare 1 register contents match those of the free-running
counter; an output compare interrupt will be generated if OCIE is set. OCF1 is cleared by reading
the TSR and then the Output Compare 1 Low register ($17).
1 (set)
–
A valid output compare has occurred on output compare register 1.
0 (clear) – No output compare has occurred on output compare register 1.
TOF - Timer Overflow Flag
This bit is set when the free-running counter overflows from $FFFF to $0000; a timer overflow
interrupt will occur if TOIE is set.TOF is cleared by reading the TSR and the Counter Low register
($19).
TPG
MOTOROLA
5-10
PROGRAMMABLE TIMER
MC68HC05L1
1 (set)
–
Timer Overflow has occurred.
0 (clear) – No timer overflow has occurred.
When using the timer overflow function and reading the free-running counter at random times to
measure an elapsed time, a problem may occur whereby the timer overflow flag is unintentionally
cleared if:
1) the Timer Status register is read or written when the TOF is set, and
2) the LSB of the free-running counter is read, but not for the purpose of
servicing the flag.
Reading the Alternate Counter register instead of the Counter register will avoid this potential
problem.
5
ICF2 - Input Capture Flag 2
This bit is set when a negative edge is detected by the input capture edge detector 2 at TCAP2;
an input capture interrupt will be generated if ICIE is set. ICF2 is cleared by reading the TSR and
then the Input Capture Low register 2 ($1D).
1 (set)
–
A valid input capture has occurred at TCAP2 pin.
0 (clear) – No input capture has occurred at TCAP2 pin.
OCF2 - Output Compare Flag 2
This bit is set when the Output Compare 2 register contents match those of the free-running
counter; an output compare interrupt will be generated if OCIE is set. OCF2 is cleared by reading
the TSR and then the Output Compare 2 Low register ($1F).
1 (set)
–
A valid output compare has occurred on output compare register 2.
0 (clear) – No output compare has occurred on output compare register 2.
5.5
Programmable Timer Timing Diagrams
The relationships between the internal clock signals, the counter contents and the status of the
flag bits are shown in the following diagrams. It should be noted that the signals labelled ‘internal’
(processor clock, timer clocks and reset) are not available to the user.
TPG
MC68HC05L1
PROGRAMMABLE TIMER
MOTOROLA
5-11
INTERNAL
PROCESSOR
CLOCK
INTERNAL
RESET
T00
T01
INTERNAL
TIMER
CLOCKS
T10
T11
COUNTER
(16 BIT)
$FFFC
$FFFD
$FFFE
$FFFF
5
RESET
(external or end of POR)
Notes: RESET affects only the Counter register and Timer Control register.
Figure 5-2 Timer State Timing Diagram for Reset
INTERNAL
PROCESSOR
CLOCK
T00
T01
INTERNAL
TIMER
CLOCKS
T10
T11
COUNTER
(16 BIT)
$F123
$F124
$F125
$F126
$F127
INPUT
EDGE
(SEE NOTE)
INTERNAL
CAPTURE
LATCH
INPUT
CAPTURE
REGISTER
$????
$F125
INPUT
CAPTURE
FLAG
Note:
If the input edge occurs in the shaded area from one timer state T10 to the other timer state T10
the input capture flag is set during the next state T11.
Figure 5-3 Timer State Timing Diagram for Input Capture
TPG
MOTOROLA
5-12
PROGRAMMABLE TIMER
MC68HC05L1
INTERNAL
PROCESSOR
CLOCK
T00
T01
INTERNAL
TIMER
CLOCKS
T10
T11
COUNTER
(16 BIT)
$F455
$F456
$F457
$F458
$F459
Note 1
OUTPUT COMPARE
REGISTER
CPU writes $F457
$F457
5
Note 1
COMPARE REGISTER
LATCH
Note 2
OUTPUT COMPARE
Flag and TCMP1, 2
Note:
1. The CPU write to the compare registers may take place at any time, but a compare only occurs at
the timer state T01. Thus a 4-cycle difference may exist between the write to the compare register
and the actual compare.
2. The output compare flag is set at the timer state T11 that follows the comparison match ($F547 in
this example).
Figure 5-4 Timer State Timing Diagram for Output Compare
INTERNAL
PROCESSOR
CLOCK
T00
T01
INTERNAL
TIMER
CLOCKS
T10
T11
COUNTER
(16 BIT)
$FFFE
$FFFF
$0000
$0001
$0002
TIMER
OVERFLOW
FLAG (TOF)
Note:
The TOF bit is set at timer state T11 (transition of counter from $FFFF to $0000).
It is cleared by a read of the timer status register during the internal processor
clock high time followed by a read of the counter low register.
Figure 5-5 Timer State Diagram for Timer Overflow
TPG
MC68HC05L1
PROGRAMMABLE TIMER
MOTOROLA
5-13
5
THIS PAGE LEFT BLANK INTENTIONALLY
TPG
MOTOROLA
5-14
PROGRAMMABLE TIMER
MC68HC05L1
6
ANALOG TO DIGITAL CONVERTER
The analog to digital converter system consists of a single 8-bit successive approximation
converter and a 16-channel multiplexer. Six of the channels are available for output, and the other
ten channels are dedicated to internal test functions. There is one 8-bit Result Data register
(address $08) and one 8-bit Status/Control register (address $09).The reference supply, V and
RH
V
for the converter uses two input pins (shared with PC6 and PC7) instead of the power supply
RL
lines, because drops caused by loading in the power supply lines would degrade the accuracy of
the A/D conversion. An internal RC oscillator is available if the bus speed is low enough to degrade
the A/D accuracy. An ADON bit allows the A/D to be switched off to reduce power consumption,
which is particularly useful in the Wait mode.
6
VRH
VRL
8-bit capacitive DAC
AN0
AN1
AN2
AN3
AN4
AN5
with sample and hold
Successive approximation
register and control
Result
VRH
(VRH+VRL)/2
VRL
A/D Status/Control Register
CH0 CH1 CH2
CH3
ADON ADRC COCO
A/D Result Register
Figure 6-1 A/D Converter Block Diagram
TPG
MC68HC05L1
ANALOG TO DIGITAL CONVERTER
MOTOROLA
6-1
6.1
A/D Converter Operation
As shown in Figure 6-1, the A/D converter consists of an analog multiplexer, an 8-bit digital to
analog capacitor array, a comparator and a successive approximation register (SAR).
There are nine options that can be selected by the multiplexer; the AN0 to AN5 input pins, V
,
RH
(V +V )/s or V . Selection is done via the CHx bits in the ADC Status/Control register. AN0
RH
RL
RL
to AN5 are input points for A/D conversion operations; the others are reference points which can
be used for test purposes. The converter uses V and V as reference voltages. An input
RH
RL
voltage equal to or greater than V converts to $FF. An input voltage equal to or less than V
,
RH
RL
but greater than V , converts to $00. Maximum and minimum ratings must not be exceeded.
SS
Each analog input source should use V as the supply voltage and should be referenced to V
RH
RL
for the ratiometric conversions.To maintain full accuracy of the A/D, three requirements should be
followed:
1) V should be equal to or less than V
;
RH
CC
2) V should be equal to or greater than V but less than maximum
RL
SS
6
specifications; and
3) V –V should be equal to or greater than 4 Volts.
RH
RL
The A/D reference inputs (V
and V ) are applied to a precision internal digital to analog
RL
RH
converter. Control logic drives this D/A converter and the analog output is successively compared
with the selected analog input sampled at the beginning of the conversion. The conversion is
monotonic with no missing codes.
The result of each successive comparison is stored in the successive approximation register
(SAR) and, when the conversion is complete, the contents of the SAR are transferred to the
read-only Result Data register ($08), and the conversion complete flag, COCO, is set in the
ADC Status/Control register ($09).
Warning: Any write to the ADC Status/Control register will abort the current conversion, reset the
conversion complete flag and start a new conversion on the selected channel.
At power-on or external reset, both the ADRC and ADON bits are cleared, thus the A/D is disabled.
TPG
MOTOROLA
6-2
ANALOG TO DIGITAL CONVERTER
MC68HC05L1
6.2
ADC Status/Control Register (ACR)
State
on reset
Address bit 7
bit 6
bit 5
bit 4
bit 3
CH3
bit 2
CH2
bit 1
CH1
bit 0
CH0
$09 COCO ADRC
ADON
0000 0000
COCO - Conversion Complete Flag
1 (set)
–
Conversion complete; a new result can be read from the Result
register ($08).
0 (clear) – No conversion since last reset.
ADRC - A/D RC Oscillator Control
The ADRC bit allows the user to use the internal RC oscillator, which is used to provide a
sufficiently high clock rate to the A/D to ensure accuracy when the MCU is running at low speeds
(typically 1MHz CPU clock).
6
1 (set)
–
A/D uses RC clock as clock source.
0 (clear) – A/D uses CPU clock as clock source.
When the RC oscillator is turned on, it requires a time t
inaccurate during this time.
to stabilize, and results can be
ADRC
ADON -A/D Converter On
The ADON bit allows the user to enable/disable the A/D converter.
1 (set) A/D converter is switched on.
0 (clear) – A/D converter is switched off.
When the A/D is turned on, it requires a time t
–
for the current sources to stabilize. During this
ADON
time A/D conversion results may be inaccurate.
Table 6-1 A/D Clock Selection
RC
oscillator
A/D
converter
ADRC ADON
Comments
0
0
1
1
0
1
0
1
OFF
OFF
ON
OFF
ON
A/D switched off
A/D using CPU clock
OFF
ON
Allows the RC oscillator to stabilize
A/D using RC oscillator clock
ON
Note:
To conserve power, set ADRC=ADON=0.
TPG
MC68HC05L1
ANALOG TO DIGITAL CONVERTER
MOTOROLA
6-3
CH3-CH0 - Channel 3, 2, 1 and 0
These bits select the A/D channel assignment. See Table 6-2.
Table 6-2 ADC Channel Assignment
CH3
CH2
CH1
CH0
CHANNEL SELECTED
AN0, port C bit 0
AN1, port C bit 1
AN2, port C bit 2
AN3, port C bit 3
AN4, port C bit 4
AN5, port C bit 5
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
V
pin (high)
RH
0
0
1
1
1
0
1
1
0
0
1
0
(available in MC68HC05L1 only)
(V + V ) ÷ 2
RH
RL
V
pin (low)
RL
6
(available in MC68HC05L1 only)
1
1
1
1
1
1
1
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
V
V
V
V
V
V
V
pin (low)
pin (low)
pin (low)
pin (low)
pin (low)
pin (low)
pin (low)
RL
RL
RL
RL
RL
RL
RL
Note:
Using one or more pins of PC0/AN0-PC5/AN5 as analog inputs does not affect the
ability to use port C inputs as digital inputs. However, using port C for digital inputs
during an analog conversion sequence may inject noise on the analog inputs and
reduce the accuracy of the A/D result.
Performing a digital read of port C with levels other than V or V on the inputs causes greater
DD
SS
than normal power dissipation during the read and may give erroneous results.
6.3
ADC Result Data Register (ADDATA)
State
on reset
Address bit 7
$08
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
uuuu uuuu
ADDATA is a read-only register which is used to store the result of an A/D conversion. The result
is loaded into the register from the successive approximation register and the conversion complete
flag in the ADC Status/Control register (COCO at address $09) is set.
TPG
MOTOROLA
6-4
ANALOG TO DIGITAL CONVERTER
MC68HC05L1
7
LIQUID CRYSTAL DISPLAY DRIVER
The LCD driver module on the MC68HC05L1 can be configured with up to 16 frontplane
(segment) drivers and up to 4 backplane drivers. This allows a maximum of 64 LCD segments to
be driven. Each segment is controlled by a corresponding bit in the LCD RAM. At power-up or
reset the ON/OFF control for the display (the DON bit in the General Control register) is cleared
thus disabling the LCD drivers. Figure 7-1 shows a block diagram of the LCD system.
Internal Data Bus
7
Internal Address Bus
LCD
RAM
VBP0
VBP1
VBP2
VPB3
Backplane
Driver
Control
Logic
LCD Data
Latch
Segment
Driver
Voltage
Generator
VLCD
VSEG0 VSEG15
Figure 7-1 LCD Driver Block Diagram
TPG
MC68HC05L1
LIQUID CRYSTAL DISPLAY DRIVER
MOTOROLA
7-1
7.1
LCD Display RAM
Data to be displayed on the LCD must be written into the LCD RAM.The LCD RAM consists of 16
bytes of RAM at $0200-$020F. The 64 bits in the LCD RAM correspond to the 64 segments that
can be driven by the frontplane/backplane drivers. Table 7-1 shows how the LCD RAM is
organized. Writing a “1” to a given location will result in the corresponding display segment being
activated when the DON bit is set. The LCD RAM is a dual port RAM that interfaces with the
internal address and data buses of the MCU. It is possible to read from LCD RAM locations for
scrolling purposes. When DON=0, the LCD RAM can be used as main on-chip memory.
Table 7-1 LCD RAM Organization
Data
LCD RAM
Address
7
6
5
4
3
2
1
0
$0200
$0201
$0202
$0203
$0204
$0205
$0206
$0207
$0208
$0209
$020A
$020B
$020C
$020D
$020E
$020F
FP0-BP0 FP0-BP1 FP0-BP2 FP0-BP3
FP1-BP0 FP1-BP1 FP1-BP2 FP1-BP3
FP2-BP0 FP2-BP1 FP2-BP2 FP2-BP3
FP3-BP0 FP3-BP1 FP3-BP2 FP3-BP3
FP4-BP0 FP4-BP1 FP4-BP2 FP4-BP3
FP5-BP0 FP5-BP1 FP5-BP2 FP5-BP3
FP6-BP0 FP6-BP1 FP6-BP2 FP6-BP3
FP7-BP0 FP7-BP1 FP7-BP2 FP7-BP3
FP8-BP0 FP8-BP1 FP8-BP2 FP8-BP3
FP9-BP0 FP9-BP1 FP9-BP2 FP9-BP3
FP10-BP0 FP10-BP1 FP10-BP2 FP10-BP3
FP11-BP0 FP11-BP1 FP11-BP2 FP11-BP3
FP12-BP0 FP12-BP1 FP12-BP2 FP12-BP3
FP13-BP0 FP13-BP1 FP13-BP2 FP13-BP3
FP14-BP0 FP14-BP1 FP14-BP2 F14P-BP3
FP15-BP0 F15P-BP1 FP15-BP2 FP15-BP3
7
7.2
LCD Operation
The LCD driver module can operate in four modes as follows:
•
•
•
•
3x12 segment drive
3x16 segment drive
4x12 segment drive
4x16 segment drive
TPG
MOTOROLA
7-2
LIQUID CRYSTAL DISPLAY DRIVER
MC68HC05L1
The operating mode and ON/FF of the LCD is controlled by the General Control register at $0A.
State
on reset
Address bit 7
bit 6
bit 5
TE1
bit 4
DON
bit 3
bit 2
bit 1
INT
bit 0
General Control Register
$000A INTO TE2
MS 0000 0000
DON - Display On
1 (set)
–
LCD is on.
0 (clear) – LCD is off.
INT, MS - Multiplex Ratio
These two bits select the multiplex ratio to be either 3 or 4 backplanes.
Table 7-2 Multiplex Ratio/Backplane Selection
UNUSED PINS TO BE
INT
MS
MULTIPLEX RATIO
GROUNDED
7
0
0
1
1
0
1
0
1
4x16
3x16
4x12
3x12
–
VBP3
VSEG12-VSEG15
VBP3, VSEG12-VSEG15
It is recommended that the DON bit in the General Control register is not set (to activate the
display) until the multiplex rate is selected, to inhibit the LCD drivers. The voltage levels required
for the different multiplex rates are generated internally by a resistive divider chain between V
LCD
and V .When DON is set, the display is switched on and the resistive divider chain activated with
SS
a maximum voltage, V
, and a minimum, V . V
allows specific voltage thresholds to be
LCD
SS LCD
applied to the LCD and can be any voltage up to V . Figure 7-2 shows the resistive divider;
DD
values for R1, R2, and R3 can be found in Section 11.4.
7.3
Timing Signals and LCD Voltage Waveforms
Since only one oscillator (crystal or RC) is used for both the MCU and LCD driver and frame
frequency of LCD driver is 62.5Hz, a prescaler is used to divide the internal clock for LCD display
TPG
MC68HC05L1
LIQUID CRYSTAL DISPLAY DRIVER
MOTOROLA
7-3
VLCD (pad input)
DON
(Bit 4 of General Control register)
VLCD
R3
R2
R1
VH
VL
V0
VSS
Figure 7-2 LCD Voltage Level Divider
7
purposes. In the Control register 2, the three bits LCDP0, LCDP1 and LCDP2 are used to select
the appropriate divider for various input clock frequencies.
State
on reset
Address bit 7
$0B
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
LCD Prescaler Register
LCDP2 LCDP1 LCDP0 0000 0000
Table 7-3 illustrates the prescaler internal processor clock division versus bit levels. Users are
responsible to select the appropriate divider according to the input clock frequency. For example,
if the 4x multiplex is selected, ÷64 (LCDP2=LCDP1=LCDP0=0) should be selected for a 32KHz
input clock; ÷8192 (LCDP2=LCDP1=LCDP0=1) should be selected for a 4MHz input clock.
Table 7-3 LCD Prescaler Division Versus Bit Levels
Internal processor clock
LCDP2
LCDP1
LCDP0
divide by
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
64
128
256
512
1024
2048
4096
8192
TPG
MOTOROLA
7-4
LIQUID CRYSTAL DISPLAY DRIVER
MC68HC05L1
The backplane waveforms are continuous and repetitive (every 2 frames); they are fixed within
each operating mode and are not affected by the data in the LCD RAM.
1 frame
1 frame
VLCD
VH
BP0
VL
ON
V0
OFF
VLCD
VH
BP1
VL
V0
VLCD
VH
BP2
7
VL
V0
VLCD
VH
SEGx, example 1
SEGx, example 2
SEGx, example 3
VL
V0
VLCD
VH
VL
V0
VLCD
VH
VL
V0
Figure 7-3 LCD Waveform with 3 Backplanes
TPG
MC68HC05L1
LIQUID CRYSTAL DISPLAY DRIVER
MOTOROLA
7-5
1 frame
1 frame
VLCD
VH
BP0
VL
ON
V0
OFF
VLCD
VH
BP1
VL
V0
VLCD
VH
BP2
VL
V0
VLCD
VH
7
BP3
VL
V0
VLCD
VH
SEGx, example 1
SEGx, example 2
SEGx, example 3
VL
V0
VLCD
VH
VL
V0
VLCD
VH
VL
V0
Figure 7-4 LCD Waveform with 4 Backplanes
TPG
MOTOROLA
7-6
LIQUID CRYSTAL DISPLAY DRIVER
MC68HC05L1
8
CPU CORE AND INSTRUCTION SET
This section provides a description of the CPU core registers, the instruction set and the
addressing modes of the MC68HC05L1.
8.1
Registers
The MCU contains five registers, as shown in the programming model of Figure 8-1.The interrupt
stacking order is shown in Figure 8-2.
7
7
7
7
0
0
0
0
0
Accumulator
8
Index register
15
15
Program counter
Stack pointer
0 0 0 0 0 0 0 0 1 1
7
1 1 1 H I N Z C
Condition code register
Carry / borrow
Zero
Negative
Interrupt mask
Half carry
Figure 8-1 Programming model
8.1.1
Accumulator (A)
The accumulator is a general purpose 8-bit register used to hold operands and results of
arithmetic calculations or data manipulations.
TPG
MC68HC05L1
CPU CORE AND INSTRUCTION SET
MOTOROLA
8-1
Stack
7
0
Condition code register
Accumulator
Index register
Program counter high
Program counter low
Increasing
memory
address
Decreasing
memory
address
Unstack
Figure 8-2 Stacking order
8.1.2
Index register (X)
The index register is an 8-bit register, which can contain the indexed addressing value used to
create an effective address. The index register may also be used as a temporary storage area.
8.1.3
Program counter (PC)
The program counter is a 16-bit register, which contains the address of the next byte to be fetched.
8.1.4
Stack pointer (SP)
8
The stack pointer is a 16-bit register, which contains the address of the next free location on the
stack. During an MCU reset or the reset stack pointer (RSP) instruction, the stack pointer is set to
location $00FF. The stack pointer is then decremented as data is pushed onto the stack and
incremented as data is pulled from the stack.
When accessing memory, the ten most significant bits are permanently set to 0000000011.These
ten bits are appended to the six least significant register bits to produce an address within the
range of $00C0 to $00FF. Subroutines and interrupts may use up to 64 (decimal) locations. If 64
locations are exceeded, the stack pointer wraps around and overwrites the previously stored
information. A subroutine call occupies two locations on the stack; an interrupt uses five locations.
8.1.5
Condition code register (CCR)
The CCR is a 5-bit register in which four bits are used to indicate the results of the instruction just
executed, and the fifth bit indicates whether interrupts are masked. These bits can be individually
tested by a program, and specific actions can be taken as a result of their state. Each bit is
explained in the following paragraphs.
Half carry (H)
This bit is set during ADD and ADC operations to indicate that a carry occurred between bits 3 and 4.
TPG
MOTOROLA
8-2
CPU CORE AND INSTRUCTION SET
MC68HC05L1
Interrupt (I)
When this bit is set, all maskable interrupts are masked. If an interrupt occurs while this bit is set,
the interrupt is latched and remains pending until the interrupt bit is cleared.
Negative (N)
When set, this bit indicates that the result of the last arithmetic, logical, or data manipulation was
negative.
Zero (Z)
When set, this bit indicates that the result of the last arithmetic, logical, or data manipulation was
zero.
Carry/borrow (C)
When set, this bit indicates that a carry or borrow out of the arithmetic logical unit (ALU) occurred
during the last arithmetic operation.This bit is also affected during bit test and branch instructions
and during shifts and rotates.
8.2
Instruction set
8
The MCU has a set of 62 basic instructions. They can be grouped into five different types as
follows:
–
–
–
–
–
Register/memory
Read/modify/write
Branch
Bit manipulation
Control
The following paragraphs briefly explain each type. All the instructions within a given type are
presented in individual tables.
This MCU uses all the instructions available in the M146805 CMOS family plus one more: the
unsigned multiply (MUL) instruction. This instruction allows unsigned multiplication of the contents
of the accumulator (A) and the index register (X). The high-order product is then stored in the
index register and the low-order product is stored in the accumulator. A detailed definition of the
MUL instruction is shown in Table 8-1.
TPG
MC68HC05L1
CPU CORE AND INSTRUCTION SET
MOTOROLA
8-3
8.2.1
Register/memory Instructions
Most of these instructions use two operands. The first operand is either the accumulator or the
index register.The second operand is obtained from memory using one of the addressing modes.
The jump unconditional (JMP) and jump to subroutine (JSR) instructions have no register
operand. Refer to Table 8-2 for a complete list of register/memory instructions.
8.2.2
Branch instructions
These instructions cause the program to branch if a particular condition is met; otherwise, no
operation is performed. Branch instructions are two-byte instructions. Refer to Table 8-3.
8.2.3
Bit manipulation instructions
The MCU can set or clear any writable bit that resides in the first 256 bytes of the memory space
(page 0). All port data and data direction registers, timer and serial interface registers,
control/status registers and a portion of the on-chip RAM reside in page 0. An additional feature
allows the software to test and branch on the state of any bit within these locations.The bit set, bit
clear, bit test and branch functions are all implemented with single instructions. For the test and
branch instructions, the value of the bit tested is also placed in the carry bit of the condition code
register. Refer to Table 8-4.
8
8.2.4
Read/modify/write instructions
These instructions read a memory location or a register, modify or test its contents, and write the
modified value back to memory or to the register.The test for negative or zero (TST) instruction is
an exception to this sequence of reading, modifying and writing, since it does not modify the value.
Refer to Table 8-5 for a complete list of read/modify/write instructions.
8.2.5
Control instructions
These instructions are register reference instructions and are used to control processor operation
during program execution. Refer to Table 8-6 for a complete list of control instructions.
8.2.6
Tables
Tables for all the instruction types listed above follow. In addition there is a complete alphabetical
listing of all the instructions (see Table 8-7), and an opcode map for the instruction set of the
M68HC05 MCU family (see Table 8-8).
TPG
MOTOROLA
8-4
CPU CORE AND INSTRUCTION SET
MC68HC05L1
Table 8-1 MUL instruction
Operation
X:A ← X*A
Multiplies the eight bits in the index register by the eight
Description bits in the accumulator and places the 16-bit result in the
concatenated accumulator and index register.
H : Cleared
I : Not affected
N : Not affected
Z : Not affected
Condition
codes
C : Cleared
Source
Form
MUL
Cycles
11
Addressing mode
Inherent
Bytes
1
Opcode
$42
Table 8-2 Register/memory instructions
Addressing modes
Indexed
(no
offset)
Indexed
(8-bit
offset)
Indexed
(16-bit
offset)
Immediate
Direct
Extended
Function
8
Load A from memory
Load X from memory
Store A in memory
Store X in memory
Add memory to A
LDA A6
2
2
2
B6
BE
B7
BF
BB
B9
B0
2
2
2
2
2
2
2
3
3
4
4
3
3
3
C6
3
3
3
3
3
3
3
4
4
5
5
4
4
4
F6
FE
F7
FF
FB
F9
F0
1
1
1
1
1
1
1
3
3
4
4
3
3
3
E6
EE
E7
EF
EB
E9
E0
2
2
2
2
2
2
2
4
4
5
5
4
4
4
D6
DE
D7
DF
DB
D9
D0
3
3
3
3
3
3
3
5
5
6
6
5
5
5
LDX AE
STA
2
CE
C7
CF
CB
C9
C0
STX
ADD AB
ADC A9
SUB A0
2
2
2
2
2
2
Add memory and carry to A
Subtract memory
Subtract memory from A
with borrow
SBC A2
2
2
B2
2
3
C2
3
4
F2
1
3
E2
2
4
D2
3
5
AND memory with A
AND A4
ORA AA
EOR A8
2
2
2
2
2
2
B4
BA
B8
2
2
2
3
3
3
C4
CA
C8
3
3
3
4
4
4
F4
FA
F8
1
1
1
3
3
3
E4
EA
E8
2
2
2
4
4
4
D4
DA
D8
3
3
3
5
5
5
OR memory with A
Exclusive OR memory with A
Arithmetic compare A
with memory
CMP A1
CPX A3
2
2
2
2
2
2
B1
B3
B5
2
2
2
3
3
3
C1
C3
C5
3
3
3
4
4
4
F1
F3
F5
1
1
1
3
3
3
E1
E3
E5
2
2
2
4
4
4
D1
D3
D5
3
3
3
5
5
5
Arithmetic compare X
with memory
Bit test memory with A
(logical compare)
BIT
A5
Jump unconditional
Jump to subroutine
JMP
JSR
BC
BD
2
2
2
5
CC
CD
3
3
3
6
FC
FD
1
1
2
5
EC
ED
2
2
3
6
DC
DD
3
3
4
7
TPG
MC68HC05L1
CPU CORE AND INSTRUCTION SET
MOTOROLA
8-5
Table 8-3 Branch instructions
Relative addressing mode
Mnemonic Opcode # Bytes # Cycles
Function
Branch always
Branch never
Branch if higher
BRA
BRN
BHI
20
21
22
23
24
24
25
25
26
27
28
29
2A
2B
2C
2D
2E
2F
AD
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
6
Branch if lower or same
Branch if carry clear
BLS
BCC
(BHS)
BCS
(BLO)
BNE
BEQ
BHCC
BHCS
BPL
(Branch if higher or same)
Branch if carry set
(Branch if lower)
Branch if not equal
Branch if equal
Branch if half carry clear
Branch if half carry set
Branch if plus
Branch if minus
BMI
Branch if interrupt mask bit is clear
Branch if interrupt mask bit is set
Branch if interrupt line is low
Branch if interrupt line is high
Branch to subroutine
BMC
BMS
BIL
BIH
BSR
8
Table 8-4 Bit manipulation instructions
Addressing modes
Bit set/clear Bit test and branch
Opcode # Bytes # Cycles Opcode # Bytes # Cycles
Function
Branch if bit n is set
Branch if bit n is clear
Set bit n
Mnemonic
BRSET n (n=0–7)
BRCLR n (n=0–7)
BSET n (n=0–7)
BCLR n (n=0–7)
2•n
3
3
5
5
01+2•n
10+2•n
11+2•n
2
2
5
5
Clear bit n
TPG
MOTOROLA
8-6
CPU CORE AND INSTRUCTION SET
MC68HC05L1
Table 8-5 Read/modify/write instructions
Addressing modes
Indexed
(no
offset)
Indexed
(8-bit
offset)
Inherent
(A)
Inherent
(X)
Direct
Function
Increment
Decrement
Clear
INC 4C
1
1
1
1
1
1
1
1
1
1
1
1
3
3
5C
1
1
1
1
1
1
1
1
1
1
1
3
3
3
3
3
3
3
3
3
3
3
3C
3A
3F
33
30
39
36
38
34
37
3D
2
2
2
2
2
2
2
2
2
2
2
5
5
5
5
5
5
5
5
5
5
4
7C
1
1
1
1
1
1
1
1
1
1
1
5
5
5
5
5
5
5
5
5
5
4
6C
2
2
2
2
2
2
2
2
2
2
2
6
6
6
6
6
6
6
6
6
6
5
DEC 4A
CLR 4F
COM 43
NEG 40
ROL 49
ROR 46
LSL 48
LSR 44
ASR 47
TST 4D
MUL 42
5A
5F
53
50
59
56
58
54
57
5D
7A
7F
73
70
79
76
78
74
77
7D
6A
6F
63
60
69
66
68
64
67
6D
3
Complement
3
Negate (two’s complement)
Rotate left through carry
Rotate right through carry
Logical shift left
3
3
3
3
Logical shift right
3
Arithmetic shift right
Test for negative or zero
Multiply
3
3
11
8
Table 8-6 Control instructions
Inherent addressing mode
Function
Transfer A to X
Mnemonic Opcode # Bytes # Cycles
TAX
TXA
SEC
CLC
SEI
97
9F
99
98
9B
9A
83
81
80
9C
9D
8E
8F
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
Transfer X to A
Set carry bit
2
Clear carry bit
2
Set interrupt mask bit
Clear interrupt mask bit
Software interrupt
Return from subroutine
Return from interrupt
Reset stack pointer
No-operation
2
CLI
2
SWI
RTS
RTI
10
6
9
RSP
NOP
STOP
WAIT
2
2
Stop
2
Wait
2
TPG
MC68HC05L1
CPU CORE AND INSTRUCTION SET
MOTOROLA
8-7
Table 8-7 Instruction set
Addressing modes
Condition codes
Mnemonic
INH IMM DIR EXT REL IX
IX1 IX2 BSC BTB
H
◊
◊
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
I
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
0
•
•
N
◊
◊
◊
◊
◊
•
Z
◊
◊
◊
◊
◊
•
C
◊
◊
•
ADC
ADD
AND
ASL
◊
◊
•
ASR
BCC
BCLR
BCS
BEQ
BHCC
BHCS
BHI
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
BHS
BIH
•
•
•
•
•
•
BIL
•
•
•
BIT
◊
•
◊
•
•
BLO
BLS
•
•
•
•
BMC
BMI
•
•
•
8
•
•
•
BMS
BNE
BPL
•
•
•
•
•
•
•
•
•
BRA
BRN
BRCLR
BRSET
BSET
BSR
CLC
CLI
•
•
•
•
•
•
•
•
◊
◊
•
•
•
•
•
•
•
•
•
•
0
•
•
•
CLR
CMP
0
◊
1
◊
•
◊
Address mode abbreviations
Condition code symbols
BSC Bit set/clear
BTB Bit test & branch
DIR Direct
IMM Immediate
Tested and set if true,
cleared otherwise
H
Half carry (from bit 3)
◊
IX
Indexed (no offset)
I
Interrupt mask
Negate (sign bit)
Zero
•
Not affected
Load CCR from stack
Cleared
IX1
IX2
Indexed, 1 byte offset
Indexed, 2 byte offset
N
Z
C
?
0
1
EXT Extended
INH Inherent
REL Relative
Carry/borrow
Set
Not implemented
TPG
MOTOROLA
8-8
CPU CORE AND INSTRUCTION SET
MC68HC05L1
Table 8-7 Instruction set (Continued)
Addressing modes
Condition codes
Mnemonic
INH IMM DIR EXT REL IX
IX1 IX2 BSC BTB
H
•
•
•
•
•
•
•
•
•
•
•
0
•
•
•
•
•
•
?
•
•
•
•
•
•
•
•
•
•
•
•
•
I
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
?
•
•
•
1
•
0
•
•
1
•
•
•
0
N
◊
◊
◊
◊
◊
•
Z
◊
◊
◊
◊
◊
•
C
1
◊
•
COM
CPX
DEC
EOR
INC
•
•
JMP
JSR
LDA
LDX
LSL
•
•
•
•
◊
◊
◊
0
•
◊
◊
◊
◊
•
•
•
◊
◊
0
◊
•
LSR
MUL
NEG
NOP
ORA
ROL
ROR
RSP
RTI
◊
•
◊
•
◊
◊
◊
•
◊
◊
◊
•
•
◊
◊
•
?
•
?
•
?
•
8
RTS
SBC
SEC
SEI
◊
•
◊
•
◊
1
•
•
•
STA
◊
•
◊
•
•
STOP
STX
SUB
SWI
TAX
•
◊
◊
•
◊
◊
•
•
◊
•
•
•
•
TST
TXA
WAIT
◊
•
◊
•
•
•
•
•
•
Address mode abbreviations
Condition code symbols
BSC Bit set/clear
BTB Bit test & branch
DIR Direct
IMM Immediate
Tested and set if true,
cleared otherwise
H
Half carry (from bit 3)
◊
IX
Indexed (no offset)
I
Interrupt mask
Negate (sign bit)
Zero
•
Not affected
Load CCR from stack
Cleared
IX1
IX2
Indexed, 1 byte offset
Indexed, 2 byte offset
N
Z
C
?
0
1
EXT Extended
INH Inherent
REL Relative
Carry/borrow
Set
Not implemented
TPG
MC68HC05L1
CPU CORE AND INSTRUCTION SET
MOTOROLA
8-9
Table 8-8 M68HC05 opcode map
8
TPG
MOTOROLA
8-10
CPU CORE AND INSTRUCTION SET
MC68HC05L1
8.3
Addressing modes
Ten different addressing modes provide programmers with the flexibility to optimize their code for
all situations. The various indexed addressing modes make it possible to locate data tables, code
conversion tables and scaling tables anywhere in the memory space. Short indexed accesses are
single byte instructions; the longest instructions (three bytes) enable access to tables throughout
memory. Short absolute (direct) and long absolute (extended) addressing are also included. One
or two byte direct addressing instructions access all data bytes in most applications. Extended
addressing permits jump instructions to reach all memory locations.
The term ‘effective address’ (EA) is used in describing the various addressing modes. The
effective address is defined as the address from which the argument for an instruction is fetched
or stored.The ten addressing modes of the processor are described below. Parentheses are used
to indicate ‘contents of’ the location or register referred to. For example, (PC) indicates the
contents of the location pointed to by the PC (program counter). An arrow indicates ‘is replaced
by’ and a colon indicates concatenation of two bytes. For additional details and graphical
illustrations, refer to the M6805 HMOS/M146805 CMOS Family Microcomputer/
Microprocessor User's Manual or to the M68HC05 Applications Guide.
8.3.1
Inherent
In the inherent addressing mode, all the information necessary to execute the instruction is
contained in the opcode. Operations specifying only the index register or accumulator, as well as
the control instruction, with no other arguments are included in this mode. These instructions are
one byte long.
8
8.3.2
Immediate
In the immediate addressing mode, the operand is contained in the byte immediately following the
opcode. The immediate addressing mode is used to access constants that do not change during
program execution (e.g. a constant used to initialize a loop counter).
EA = PC+1; PC ← PC+2
8.3.3
Direct
In the direct addressing mode, the effective address of the argument is contained in a single byte
following the opcode byte. Direct addressing allows the user to directly address the lowest 256
bytes in memory with a single two-byte instruction.
EA = (PC+1); PC ← PC+2
Address bus high ← 0; Address bus low ← (PC+1)
TPG
MC68HC05L1
CPU CORE AND INSTRUCTION SET
MOTOROLA
8-11
8.3.4
Extended
In the extended addressing mode, the effective address of the argument is contained in the two
bytes following the opcode byte. Instructions with extended addressing mode are capable of
referencing arguments anywhere in memory with a single three-byte instruction. When using the
Motorola assembler, the user need not specify whether an instruction uses direct or extended
addressing. The assembler automatically selects the short form of the instruction.
EA = (PC+1):(PC+2); PC ← PC+3
Address bus high ← (PC+1); Address bus low ← (PC+2)
8.3.5
Indexed, no offset
In the indexed, no offset addressing mode, the effective address of the argument is contained in
the 8-bit index register. This addressing mode can access the first 256 memory locations. These
instructions are only one byte long. This mode is often used to move a pointer through a table or
to hold the address of a frequently referenced RAM or I/O location.
EA = X; PC ← PC+1
Address bus high ← 0; Address bus low ← X
8.3.6
Indexed, 8-bit offset
8
In the indexed, 8-bit offset addressing mode, the effective address is the sum of the contents of
the unsigned 8-bit index register and the unsigned byte following the opcode. Therefore the
operand can be located anywhere within the lowest 511 memory locations.This addressing mode
is useful for selecting the mth element in an n element table.
EA = X+(PC+1); PC ← PC+2
Address bus high ← K; Address bus low ← X+(PC+1)
where K = the carry from the addition of X and (PC+1)
8.3.7
Indexed, 16-bit offset
In the indexed, 16-bit offset addressing mode, the effective address is the sum of the contents of
the unsigned 8-bit index register and the two unsigned bytes following the opcode. This address
mode can be used in a manner similar to indexed, 8-bit offset except that this three-byte instruction
allows tables to be anywhere in memory. As with direct and extended addressing, the Motorola
assembler determines the shortest form of indexed addressing.
EA = X+[(PC+1):(PC+2)]; PC ← PC+3
Address bus high ← (PC+1)+K; Address bus low ← X+(PC+2)
where K = the carry from the addition of X and (PC+2)
TPG
MOTOROLA
8-12
CPU CORE AND INSTRUCTION SET
MC68HC05L1
8.3.8
Relative
The relative addressing mode is only used in branch instructions. In relative addressing, the
contents of the 8-bit signed byte (the offset) following the opcode are added to the PC if, and only
if, the branch conditions are true. Otherwise, control proceeds to the next instruction. The span of
relative addressing is from –126 to +129 from the opcode address. The programmer need not
calculate the offset when using the Motorola assembler, since it calculates the proper offset and
checks to see that it is within the span of the branch.
EA = PC+2+(PC+1); PC ← EA if branch taken;
otherwise EA = PC ← PC+2
8.3.9
Bit set/clear
In the bit set/clear addressing mode, the bit to be set or cleared is part of the opcode. The byte
following the opcode specifies the address of the byte in which the specified bit is to be set or
cleared. Any read/write bit in the first 256 locations of memory, including I/O, can be selectively
set or cleared with a single two-byte instruction.
EA = (PC+1); PC ← PC+2
Address bus high ← 0; Address bus low ← (PC+1)
8
8.3.10
Bit test and branch
The bit test and branch addressing mode is a combination of direct addressing and relative
addressing. The bit to be tested and its condition (set or clear) is included in the opcode. The
address of the byte to be tested is in the single byte immediately following the opcode byte (EA1).
The signed relative 8-bit offset in the third byte (EA2) is added to the PC if the specified bit is set
or cleared in the specified memory location. This single three-byte instruction allows the program
to branch based on the condition of any readable bit in the first 256 locations of memory.The span
of branch is from –125 to +130 from the opcode address. The state of the tested bit is also
transferred to the carry bit of the condition code register.
EA1 = (PC+1); PC ← PC+2
Address bus high ← 0; Address bus low ← (PC+1)
EA2 = PC+3+(PC+2); PC ← EA2 if branch taken;
otherwise PC ← PC+3
TPG
MC68HC05L1
CPU CORE AND INSTRUCTION SET
MOTOROLA
8-13
THIS PAGE LEFT BLANK INTENTIONALLY
8
TPG
MOTOROLA
8-14
CPU CORE AND INSTRUCTION SET
MC68HC05L1
9
LOW POWER MODES
There are two low power modes for the MC68HC05L1, Stop and Wait modes.They are described
in this section.
9.1
Stop Mode
This is the lowest power consumption mode for the MCU.When the processor executes the STOP
instruction, the internal clock is turned off. This halts all internal CPU processing, including the
operation of the Programmable Timer and ADC.The I bit in the Condition Code register is cleared
to enable external interrupt IRQ. All registers and memory remain unaltered, and all input/output
lines remain unchanged.
The MCU is exited from Stop mode by an interrupt on IRQ, or any resets (logic low on RESET pin
or a power-on reset). On exit from Stop mode, the program counter is loaded with the
corresponding interrupt vector (see Table 4-2). The effects of the Stop mode on each of the MCU
peripheral systems are below.
9
9.1.1
Timer during Stop Mode
When Stop mode is entered, the timer counter stops counting (the internal processor clock is
stopped) and remains at that particular count value until Stop mode is exited. If the exit was
caused by reset, the counter is forced to $FFFC. If the Stop mode is exited by an interrupt IRQ,
the counter resumes counting from the value when it entered the Stop mode. Another feature of
the programmable timer in the Stop mode is, that if at least one valid input capture edge occurs at
the TCAP1 or TCAP2 pin, the input capture detect circuitry is armed.This action does not set any
timer flags or "wake up" the MCU, but when the MCU does "wake up" there will be an active input
capture flag (and data) from that first valid edge which occurred during the Stop mode. Notice that
an exit by a reset will reset the entire MCU and thus, this function on the TCAP1/TCAP2 will not
happen.
TPG
MC68HC05L1
LOW POWER MODES
MOTOROLA
9-1
9.1.2
ADC during Stop Mode
When Stop mode is entered with the ADC turned on, the ADC clocks are stopped and the ADC is
disabled for the duration of Stop mode, including the 4064 cycle start-up time. If the ADC RC
oscillator is used, it will also be disabled.
When leaving Stop mode, after the 4064-cycle start-up time, the ADC and ADC RC oscillator
resume regular operation. However, a time t
is required for the ADC circuitry to stabilize.
ADON
During t
, ADC conversion results may be inaccurate.
ADON
9.2
Wait Mode
When the MCU enters the Wait mode, the CPU clock is halted. All CPU activities are halted, but
the 16-bit free-running counter and the ADC remain active. Any interrupts from the peripherals will
cause the processor to exit the Wait mode. A reset will also take the MCU out of Wait mode.
The Wait mode power consumption depends on how many systems are active. If a non-reset exit
from the Wait mode is performed (e.g. timer overflow interrupt exit), the state of the remaining
systems will be unchanged. If a reset exit from the Wait mode is performed, all the systems revert
to the default reset state.
9
TPG
MOTOROLA
9-2
LOW POWER MODES
MC68HC05L1
10
OPERATING MODES
The MC68HC05L1/MC68HC705L1 MCU has two modes of operation, the User Mode and the
Self-Check/Bootstrap Mode. Figure 10-1 shows the flowchart of entry to these two modes, and
Table 10-1 shows operating mode selection.
5V
RESET
9V
N
USER MODE
IRQ
?
(NORMAL MODE)
Y
TCAP1 = VDD
?
10
Y
Note:
SELF-CHECK/
BOOTSTRAP
MODE
Self-check mode is for MC68HC05L1
Bootstrap mode is for MC68HC705L1
Figure 10-1 Flowchart of Mode Entering
TPG
MC68HC05L1
OPERATING MODES
MOTOROLA
10-1
Table 10-1 Mode Selection
RESET
IRQ
to V
TCAP1
to V
MODE
5V
V
V
USER
SS
DD
SS
DD
9V
5V
SELF-CHECK/
BOOTSTRAP
+9V Rising Edge*
V
DD
* Minimum hold time should be 2 clock cycles, after that it can be used as a normal IRQ
function pin.
10.1
User Mode (Normal Operation)
The normal operating mode of the MC68HC05L1/MC68HC705L1 is the user mode. The user
mode will be entered if the RESET line is brought low, and the IRQ pin is within its normal
operational range (V to V ), the rising edge of the RESET will cause the MCU to enter the user
SS
DD
mode.
10.2
Self-Check Mode
The MC68HC05L1 self-check mode is for the user to check device functions with an on-chip
self-check program masked at location $1E00 to $1FDF under minimum hardware support. The
hardware is shown in Figure 10-3. Figure 10-2 is the criteria to enter self-check mode, where
TCAP1’s condition is latched within first two clock cycles after the rising edge of the reset.TCAP1
can then be used for other purposes. After entering the self-check mode, CPU branches to the
self-check program and carries out the self-check. Self-check is a repetitive test, i.e. if all parts are
checked to be good, the CPU will repeat the self-check again. Therefore, the LEDs attached to
Port A will be flashing if the device is good; else the combination of LEDs’ on-off pattern can show
what part of the device is suspected to be bad. Table 10-2 lists the LEDs’ on-off patterns and their
corresponding indications.
10
+5V
TCAP1
+9V
IRQ
+5V
RESET
Figure 10-2 Self-Check Mode Timing
TPG
MOTOROLA
10-2
OPERATING MODES
MC68HC05L1
+9V
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
+5V
4K7
IRQ
10K
10K
2N3904
PC0/AN0
PC1/AN1
PC2/AN2
PC3AN3
PC4AN4
PC5/AN5
PC6/VRH
PC7/VRL
10K
+5V
OSC1
OSC2
4MHz
10K
PD0/TCAP1
PD1/TCAP2
PD2/TCMP1
PD3/TCMP2
10M
+5V
20p
20p
PE0
MC68HC05L1
10K
1N4148
VSEG0
VSEG1
VSEG2
VSEG3
VSEG4
VSEG5
VSEG6
VSEG7
VSEG8
VSEG9
VSEG10
VSEG11
VSEG12
VSEG13
VSEG14
VSEG15
RESET
RESET
+
10µ
VBP0
VBP1
VBP2
VBP3
+5V
PA0
PA4
PA1
PA5
PA2
PA6
PA3
PA7
390
390
10
VLCD
VLCD
390
390
+5V
VDD
VSS
Figure 10-3 MC68HC05L1 Self-Test Circuit
TPG
MC68HC05L1
OPERATING MODES
MOTOROLA
10-3
Table 10-2 Self-Check Report
PA3
1
PA2
1
PA1
1
PA0
1
REMARKS
Bad Interrupts
Bad Timer
1
1
1
0
1
1
0
1
Bad ADC
1
1
0
0
Bad ROM
1
0
1
1
Bad Display RAM
Bad RAM
1
0
1
0
1
0
0
1
Bad I/O
Flashing
All Others
Good Device
Bad Device, Bad Port A, etc.
1=LED off; 0=LED on.
10.3
Bootstrap Mode
The bootstrap mode is provided in the EPROM part (MC68HC705L1) as a mean of
self-programming its EPROM with minimal circuitry. It is entered on the rising edge of RESET if
IRQ pin is at 1.8V and TCAP1 is at logic one. RESET must be held low for 4064 cycles after
DD
POR (power-on reset).
10.3.1
EPROM Programming
The Program Control register (PCR) is provided for EPROM programming. The function of the
EPROM depends on the device operating mode. Figure 10-4 shows the EPROM programming
circuit for MC68HC705L1.
10
10.3.2
Program Control Register (PCR)
State
on reset
Address bit 7
$0E
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
RESERVED
LATA
EPGM uuuu uu00
LATA - EPROM Latch Control
1 (set)
–
EPROM address and data bus configured for programming (writes to
EPROM cause address data to be latched). EPROM is in
programming mode and cannot be read if LATA is 1. This bit should
not be set unless a programming voltage is applied to the V pin.
PP
0 (clear) – EPROM address and data bus configured for normal reads.
TPG
MOTOROLA
10-4
OPERATING MODES
MC68HC05L1
EPGM - EPROM Program Command
1 (set)
–
Programming power connected to the EPROM array.If LATA ≠ 1 then
EPGM = 0.
0 (clear) – Programming power disconnected from the EPROM array.
10.3.3
EPROM Programming Sequence
Programming the EPROM of the MC68HC705L1 is as follows:
1) Set the LATA bit.
2) Write the data to be programmed to the address to be programmed.
3) Set the EPGM bit.
4) Delay for 1ms.
5) Clear the EPGM and the LATA bits.
The last action may be carried out in a single CPU write operation. It is important to remember
that an external programming voltage must be applied to the V pin while programming, but
PP
should be equal to V during normal operation.
DD
Example shows address $1000 is programmed with $00.
CLR
LDX
BSET
LDA
STA
BSET
JSR
CLR
PCR
#$00
;reset PCR
;load index register with 00
;set LATA bit
;load data=00 in to A
;latch data and address
;program
;call delay subroutine for 1ms
;reset PCR
1,PCR
#$00
$1000,X
0,PCR
DELAY
PCR
10
TPG
MC68HC05L1
OPERATING MODES
MOTOROLA
10-5
VPP=13V
470
+5V
VPP
TCAP1
A0
A1
A2
A3
R
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
QA
QB
QC
QD
D0
D1
D2
D3
D4
D5
D6
D7
HC393
100K
CLR
1N1418
RESET
QA
QB
QC
QD
R
HC393
CLR
A4
A5
A6
A7
RESET
+
0.01µ
27256
A8
A9
A10
A11
QA
QB
QC
QD
R
PB2
PB7
OE
HC393
WE
CLR
OSC1
OSC2
+5V
2.0MHz
A12
A13
A14
QA
QB
QC
QD
R
VPP
CE
HC393
10M
22p
MC68HC705L1
CLR
PB3
PB4
22p
+5V
4K7
4K7
+5V
Program/Verify
+5V
470
470
PB0
PB1
PB5
PB6
Open - Program & Verify
Closed - Verify
10K
10K
+5V
Verify
VSS
VDD
+
10
0.1µ
1µ
Figure 10-4 MC68HC705L1 EPROM Programming Circuit
TPG
MOTOROLA
10-6
OPERATING MODES
MC68HC05L1
11
ELECTRICAL SPECIFICATIONS
This section contains the electrical specifications and associated timing information for the
MC68HC05L1.
11.1
Maximum Ratings
Voltages referenced to V
SS
RATINGS
SYMBOL
VALUE
UNIT
V
Supply Voltage
Input Voltage
IRQ
V
–0.3 to +7.0
DD
V
V
–0.3 to V +0.3
V
in
in
SS
DD
V
V
–0.3 to 2xV +0.3
V
SS
DD
Current Drain per pin excluding V and V
I
D
25
mA
°C
°C
DD
SS
Operating Temperature
T
0 to 70
A
Storage Temperature Range
T
–65 to +150
stg
This device contains circuitry to protect the inputs against damage due to high static voltages or
electric fields. However, it is advised that normal precautions should be taken to avoid application
of any voltage higher than the maximum rated voltages to this high impedance circuit. For proper
operation it is recommended that Vin and Vout be constrained to the range V ≤(V or V )≤V .
DD
SS
in
out
Reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage
11
level (e.g. either V or V ).
SS
DD
11.2
Thermal Characteristics
CHARACTERISTICS
SYMBOL
VALUE
UNIT
Thermal resistance
– Plastic 56-pin SDIP package
– Plastic 64-pin QFP package
θ
θ
50
50
°C/W
°C/W
JA
JA
TPG
MC68HC05L1
ELECTRICAL SPECIFICATIONS
MOTOROLA
11-1
11.3
DC Electrical Characteristics
Table 11-1 DC Electrical Characteristics for 5V Operation
V
=5.0Vdc ±10%, V =0Vdc, temperature range=0 to 70°C
SS
DD
(1)
CHARACTERISTICS
Output voltage
SYMBOL
MINIMUM TYPICAL
MAXIMUM UNIT
I
I
= –10µA
= +10µA
V
V
V
–0.1
—
—
—
—
0.1
V
V
LOAD
LOAD
OH
DD
OL
Output high voltage (I
=–1.0mA)
LOAD
V
V
–0.8
—
—
—
V
V
OH
DD
PA0-PA7, PB0-PB7, PE0, TCMP1, TCMP2
Output low voltage (I =+1.0mA)
LOAD
V
—
0.3
OL
PA0-PA7, PB0-PB7, PE0, TCMP1, TCMP2
Input high voltage
PA0-PA7, PB0-PB7, PC0-PC7, PE0,
TCAP1, TCAP2, IRQ, RESET, OSC1
V
0.7xV
—
V
DD
V
IH
DD
Input low voltage
PA0-PA7, PB0-PB7, PC0-PC7, PE0,
TCAP1, TCAP2, IRQ, RESET, OSC1
V
V
—
—
0.2xV
—
V
V
IL
SS
DD
Data Retention Mode
V
2.0
RM
(2)
Supply current (f
=4.2MHz)
OSC
Run
Wait
Stop
—
—
—
3.3
0.6
2
5.0
2.0
10
mA
mA
µA
I
DD
I/O ports high-Z leakage current
PA0-PA7, PB0-PB7, PE0
I
—
—
—
—
±10
±1
µA
µA
IL
Input current
I
IN
TCAP1, TCAP2, IRQ, RESET, OSC1
Capacitance
ports (as input or output), RESET, IRQ,
TCAP1, TCAP2, OSC1
C
C
—
—
—
—
12
8
pF
OUT
IN
(1) Typical values are at mid point of voltage range and at 25°C only. All values reflect average measurements.
(2) Wait I : Timer system active. RUN and WAIT I : measured using an external square-wave clock source
DD
DD
(f
=4.2MHz); all inputs 0.2V from rail; no DC loads; maximum load on all outputs 50pF (20pF on OSC2).
OSC
11
STOP and WAIT I : all ports configured as inputs; V =0.2V and V =V –0.2V.
DD
IL
IH DD
TPG
MOTOROLA
11-2
ELECTRICAL SPECIFICATIONS
MC68HC05L1
Table 11-2 DC Electrical Characteristics for 2.7V Operation
V
=2.7Vdc ±10%, V =0Vdc, temperature range=0 to 70°C
SS
DD
(1)
CHARACTERISTICS
Output voltage
SYMBOL
MINIMUM TYPICAL
MAXIMUM UNIT
I
I
= –10µA
= +10µA
V
V
V
–0.1
—
—
—
—
0.1
V
V
LOAD
LOAD
OH
DD
OL
Output high voltage (I
=–0.4mA)
LOAD
V
V
–0.4
—
—
—
V
V
OH
DD
PA0-PA7, PB0-PB7, PE0, TCMP1, TCMP2
Output low voltage (I =+0.4mA)
LOAD
V
—
0.3
OL
PA0-PA7, PB0-PB7, PE0, TCMP1, TCMP2
Input high voltage
PA0-PA7, PB0-PB7, PC0-PC7, PE0,
TCAP1, TCAP2, IRQ, RESET, OSC1
V
0.7xV
—
V
DD
V
IH
DD
Input low voltage
PA0-PA7, PB0-PB7, PC0-PC7, PE0,
TCAP1, TCAP2, IRQ, RESET, OSC1
V
V
—
—
0.2xV
—
V
V
IL
SS
DD
Data Retention Mode
V
2.0
RM
(2)
Supply current (f
=2.1MHz)
OSC
Run
Wait
Stop
—
—
—
1.4
0.3
1.4
2.5
1.0
6
mA
mA
µA
I
DD
I/O ports high-Z leakage current
PA0-PA7, PB0-PB7, PE0
I
—
—
—
—
±10
±1
µA
µA
IL
Input current
I
IN
TCAP1, TCAP2, IRQ, RESET, OSC1
Capacitance
ports (as input or output), RESET, IRQ,
TCAP1, TCAP2, OSC1
C
C
—
—
—
—
12
8
pF
OUT
IN
(1) Typical values are at mid point of voltage range and at 25°C only. All values reflect average measurements.
(2) Wait I : Timer system active. RUN and WAIT I : measured using an external square-wave clock source
DD
DD
(f
=2.1MHz); all inputs 0.2V from rail; no DC loads; maximum load on all outputs 50pF (20pF on OSC2).
OSC
STOP and WAIT I : all ports configured as inputs; V =0.2V and V =V –0.2V.
DD
IL
IH DD
11
TPG
MC68HC05L1
ELECTRICAL SPECIFICATIONS
MOTOROLA
11-3
11.4
LCD Driver DC Electrical Characteristics
Table 11-3 LCD Driver DC Electrical Characteristics
CHARACTERISTICS
SYMBOL
MINIMUM TYPICAL MAXIMUM UNIT
V
V
V
—
—
—
—
V
—
—
V
V
V
LCD
DD
Voltage divider voltage level
2/3V
H
LCD
LCD
1/3V
L
VLCD
100KΩ
100KΩ
100KΩ
VH
VL
Figure 11-1 LCD Driver Voltage Divider
11
TPG
MOTOROLA
11-4
ELECTRICAL SPECIFICATIONS
MC68HC05L1
11.5
A/D Converter Electrical Characteristics
Table 11-4 A/D Converter Electrical Characteristics for 5V Operation
CHARACTERISTICS
Resolution
PARAMETER
MINIMUM MAXIMUM UNIT
Number of bits resolved by the ADC
8
8
bits
LSB
LSB
Maximum deviation from the best straight line through the
Non-linearity
—
—
±0.5
±0.5
ADC transfer characteristics (V =V and V =0V)
RH DD
RL
Quantization error
Uncertainty due to converter resolution
Difference between the actual input voltage and the
full-scale equivalent of the binary code output code for all
errors
Absolute accuracy
Conversion range
—
±1
LSB
Analog input voltage range
V
V
V
V
V
RL
RH
V
V
Maximum analog reference voltage
Minimum analog reference voltage
V
V
+0.1
RH
RL
RL
DD
V
–0.1
V
RH
SS
Total time to perform a single analog to digital conversion
(a) External clock (OSC1, OSC2)
(b) Internal RC oscillator
Conversion time
—
—
32
32
t
CYC
µs
Conversion result never decreases with an increase in
input voltage and has no missing codes
Monotonicity
Guaranteed
Zero-input reading
Full-scale reading
Conversion result when V =V
00
—
—
hex
hex
IN RL
Conversion result when V =V
FF
IN RH
Analog input acquisition sampling
(a) External clock (OSC1, OSC2)
(b) Internal RC oscillator
Sample acquisition time
Sample/hold capacitance
—
—
12
12
t
CYC
µs
(1)
Input capacitance on PC0/AN0-PC5/AN5
—
12
pF
Input leakage on ADC pins
(a) PC0/AN0-PC5/AN5
(2)
Input leakage
—
—
10
1
µA
µA
(b) V , V
RL RH
(1) Source impedances greater than 10KΩ will adversely affect internal charging time during input sampling.
(2) The external system error caused by input leakage current is approximately equal to the product of R source and input current.
11
TPG
MC68HC05L1
ELECTRICAL SPECIFICATIONS
MOTOROLA
11-5
Table 11-5 A/D Converter Electrical Characteristics for 2.7V Operation
CHARACTERISTICS
PARAMETER
MINIMUM MAXIMUM UNIT
Resolution
Number of bits resolved by the ADC
8
8
bits
LSB
LSB
Maximum deviation from the best straight line through the
Non-linearity
Quantization error
—
—
±1
ADC transfer characteristics (V =V and V =0V)
RH DD
RL
Uncertainty due to converter resolution
±0.5
Difference between the actual input voltage and the
full-scale equivalent of the binary code output code for all
errors
Absolute accuracy
Conversion range
—
±1.5
LSB
Analog input voltage range
V
V
V
V
V
RL
RH
V
V
Maximum analog reference voltage
Minimum analog reference voltage
V
V
+0.1
RH
RL
RL
DD
V
–0.1
V
RH
SS
Total time to perform a single analog to digital conversion
Internal RC oscillator
Conversion time
Monotonicity
—
32
µs
Conversion result never decreases with an increase in
input voltage and has no missing codes
Guaranteed
Zero-input reading
Full-scale reading
Conversion result when V =V
00
—
—
hex
hex
IN RL
Conversion result when V =V
FF
IN RH
Analog input acquisition sampling
Internal RC oscillator
Sample acquisition time
Sample/hold capacitance
(1)
—
—
12
12
µs
Input capacitance on PC0/AN0-PC5/AN5
pF
Input leakage on ADC pins
(a) PC0/AN0-PC5/AN5
(2)
Input leakage
—
—
10
1
µA
µA
(b) V , V
RL RH
(1) Source impedances greater than 10KΩ will adversely affect internal charging time during input sampling.
(2) The external system error caused by input leakage current is approximately equal to the product of R source and input current.
11
TPG
MOTOROLA
11-6
ELECTRICAL SPECIFICATIONS
MC68HC05L1
11.6
Control Timing
Table 11-6 Control Timing for 5V Operation
(V =5.0Vdc ±10%, V =0Vdc, temperature range=0 to 70°C)
DD
SS
CHARACTERISTICS
SYMBOL
MINIMUM MAXIMUM UNIT
Frequency of operation
Crystal option
—
dc
4.2
4.2
MHz
MHz
f
OSC
External clock option
Internal operating frequency (f /2)
OSC
Crystal
External clock
f
—
dc
2.1
2.1
MHz
MHz
OP
f
OP
Processor cycle time
t
480
—
—
ns
ms
ms
ms
µs
CYC
Crystal oscillator start-up time
Stop recovery start-up time (crystal oscillator)
RC oscillator stabilization time
A/D converter stabilization time
External RESET pulse width
t
100
100
100
500
—
OXOV
t
—
ILCH
t
—
ADRC
t
—
ADON
t
1.5
t
RL
CYC
Power-on RESET output pulse width
4064 cycle
16 cycle
t
t
4064
16
—
—
t
t
PORL
PORL
CYC
CYC
Timer
(1)
Resolution
t
4
—
—
—
t
t
RESL
, t
CYC
ns
Input capture pulse width
Input capture pulse period
t
125
TH TL
t
(2)
—
TLTL
CYC
Interrupt pulse width (edge-triggered)
Interrupt pulse period
t
125
—
—
ns
ILIH
(3)
t
—
t
ILIL
CYC
(1) Since a 2-bit prescaler in the timer must count four external cycles (t ), this is the limiting factor
CYC
in determining the timer resolution.
(2) The minimum period t
should not be less than the number of cycle times it takes to execute
TLTL
the capture interrupt service routine plus 24 t
.
CYC
(3) The minimum period t should not be less than the number of cycle times it takes to execute the
ILIL
interrupt service routine plus 21 t
.
CYC
11
TPG
MC68HC05L1
ELECTRICAL SPECIFICATIONS
MOTOROLA
11-7
Table 11-7 Control Timing for 2.7V Operation
(V =2.7Vdc ±10%, V =0Vdc, temperature range=0 to 70°C)
DD
SS
CHARACTERISTICS
SYMBOL
MINIMUM MAXIMUM UNIT
Frequency of operation
Crystal option
—
dc
2.0
2.0
MHz
MHz
f
OSC
External clock option
Internal operating frequency (f /2)
OSC
Crystal
External clock
f
—
dc
1.0
1.0
MHz
MHz
OP
f
OP
Processor cycle time
t
1000
—
—
ns
ms
ms
ms
µs
CYC
Crystal oscillator start-up time
Stop recovery start-up time (crystal oscillator)
RC oscillator stabilization time
A/D converter stabilization time
External RESET pulse width
t
100
100
100
500
—
OXOV
t
—
ILCH
t
—
ADRC
t
—
ADON
t
1.5
t
RL
CYC
Power-on RESET output pulse width
4064 cycle
16 cycle
t
t
4064
16
—
—
t
t
PORL
PORL
CYC
CYC
Timer
(1)
Resolution
t
4
—
—
—
t
t
RESL
, t
CYC
ns
Input capture pulse width
Input capture pulse period
t
250
TH TL
t
(2)
—
TLTL
CYC
Interrupt pulse width (edge-triggered)
Interrupt pulse period
t
250
—
—
ns
ILIH
(3)
t
—
t
ILIL
CYC
(1) Since a 2-bit prescaler in the timer must count four external cycles (t ), this is the limiting factor
CYC
in determining the timer resolution.
(2) The minimum period t
should not be less than the number of cycle times it takes to execute
TLTL
the capture interrupt service routine plus 24 t
.
CYC
(3) The minimum period t should not be less than the number of cycle times it takes to execute the
ILIL
interrupt service routine plus 21 t
.
CYC
11
TPG
MOTOROLA
11-8
ELECTRICAL SPECIFICATIONS
MC68HC05L1
12
MECHANICAL SPECIFICATIONS
This section provides the mechanical dimension for the 56-pin SDIP and 64-pin QFP packages
for the MC68HC05L1.
12.1
56-pin SDIP Package
- A -
L
H
56
1
29
28
Case No. 859-01
56 lead SDIP
- B -
M
J
0.25
T B
M
S
C
- T -
K
Seating
Plane
G
E
F
N
P
D
0.25
T A
S
M
Dim.
A
Min.
51.69
13.72
3.94
Max.
52.45
14.22
5.08
Notes
Dim.
H
Min.
Max.
7.62 BSC
12
B
J
0.20
2.92
0.38
3.43
1. Dimensions and tolerancing per ANSI Y 14.5 1982.
2. All dimensions in mm.
C
K
3. Dimension L to centre of lead when formed parallel.
D
0.36
0.56
L
15.24 BSC
4. Dimensions A and B do not include mould flash. Allowable mould
flash is 0.25 mm.
E
0.89 BSC
M
N
0°
15°
1.02
2.29
F
0.81
1.17
0.51
1.78
G
1.778 BSC
P
Figure 12-1 56-pin SDIP Mechanical Dimensions
TPG
MC68HC05L1
MECHANICAL SPECIFICATIONS
MOTOROLA
12-1
12.2
64-pin QFP Package
L
B
B
48
33
P
49
32
- A, B, D -
- A -
- B -
Detail “A”
Case No. 840C
64 lead QFP
L
B
V
F
Detail “A”
64
17
N
J
1
16
S
- D -
0.20
Base
Metal
D
A
C A – B
D
D
Section B–B
M
S
S
0.05 A – B
0.20
C A – B
D
S
M
S
S
U
0.20
H A – B
M
S
T
Detail “C”
M
M
E
R
Q
C
Datum
Plane
-H-
K
-C-
G
H
W
Seating
Plane
X
Dim.
Min.
Max.
14.10
14.10
2.457
0.45
2.40
—
Notes
Dim.
M
N
Min.
5°
Max.
10°
A
B
C
D
E
F
G
H
J
13.90
13.90
2.067
0.30
1. Datum Plane –H– is located at bottom of lead and is coincident with
the lead where the lead exits the plastic body at the bottom of the
parting line.
0.130
0.170
P
0.40 BSC
2. Datums –A–, –B–, and –D– to be determined at Datum Plane –H–.
3. Dimensions S and V to be determined at seating plane –C–.
4. Dimensions A and B do not include mould protrusion. Allowable
mould protrusion is 0.25mm per side. Dimensions A and B do
include mould mismatch and are determined at Datum Plane –H–.
5. Dimension D does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08 total in excess of the D dimension
at maximum material condition. Dambar cannot be located on the
lower radius or the foot.
Q
R
2°
8°
2.00
0.13
0.30
16.60
0.30
S
16.20
0.80 BSC
T
0.20 REF
12
0.067
0.250
0.230
0.66
U
9°
15°
0.130
0.50
V
16.20
16.60
K
L
W
X
0.042 NOM
6. Dimensions and tolerancing per ANSI Y 14.5M, 1982.
7. All dimensions in mm.
12.00 REF
1.10
1.30
Figure 12-2 64-pin QFP Mechanical Dimensions
TPG
MOTOROLA
12-2
MECHANICAL SPECIFICATIONS
MC68HC05L1
A
MC68HC705L1
This appendix summarizes the differences between the MC68HC05L1 and MC68HC705L1. The
same information can also be found in appropriate sections of the book.
The MC68HC705L1 is an EPROM version of the MC68HC05L1. The 4096 bytes of user ROM in
the MC68HC05L1 are replaced by 5632 bytes of user EPROM.
A.1
Features
•
•
•
Functionally equivalent to MC68HC05L1
5632 bytes of user EPROM
EPROM bootstrap mode replaces Self-Check mode on the MC68HC05L1
A.2
Memory Map
Figure A-1 shows the memory map for the MC68HC705L1.
A
TPG
MC68HC05L1
MC68HC705L1
MOTOROLA
A-1
$0000
0
Port A Data Register
Port B Data Register
$00
$01
$02
$03
$04
$05
$06
$07
$08
$09
$0A
$0B
I/O
32 Bytes
Ports
$001F
$0020
Port C Input Data Register
Port D Data Register
8 Bytes
User ROM
48 Bytes
Port E Data Register
Port A Data Direction Register
Port B Data Direction Register
Port E Data Direction Register
ADC Data Register
ADC
2 Bytes
$004F
$0080
Reserved
General Control
1 Bytes
LCD Prescaler
1 Bytes
User RAM
128 Bytes
ADC Status and Control Register
General Control Register
LCD Prescaler Register
$00BF
$00C0
Reserved
2 Bytes
Stack
64 Bytes
EPROM Programming
1 Byte
Reserved
$0C
$0D
$0E
$0F
$10
$11
$12
$13
$14
$15
$16
$17
$18
$19
$1A
$1B
$1C
$1D
$1E
$1F
$00FF
Reserved
Reserved
3 Bytes
Reserved
EPROM Program Control Register
Reserved
$0200
$020F
Display RAM
16x4-bit
Reserved
Reserved
Timer Control Register
Timer
14 Bytes
Timer Status Register
Timer Input Capture High Register 1
Timer Input Capture Low Register 1
Timer Output Compare High Register 1
Timer Output Compare Low Register 1
Timer Counter High Register
Timer Counter Low Register
Timer Alternate Counter High Register
Timer Alternate Counter Low Register
Timer Input Capture High Register 2
Timer Input Capture Low Register 2
Timer Output Compare High Register 2
Timer Output Compare Low Register 2
Reserved
31
$0800
User EPROM
5632 Bytes
$1DFF
Bootstrap Program
496 Bytes
$1FF0
$1FF2
$1FF4
$1FF6
$1FF8
$1FFA
$1FFC
$1FFE
Reserved
Reserved
TIMOV
TIMOC
TIMIC
IRQ
$1FDF
$1FE0
Bootstrap Vectors
16 Bytes
$1FEF
$1FF0
User Vectors
16 Bytes
SWI
RESET
$1FFF
A
Figure A-1 MC68HC705L1 Memory Map
TPG
MOTOROLA
A-2
MC68HC705L1
MC68HC05L1
A.3
Modes of Operation
The MC68HC705L1 also has two modes of operation – user mode and EPROM bootstrap mode.
Table A-1 shows the conditions required to enter each mode on the rising edge of RESET.
Table A-1 MC68HC705L1 Operating Mode Entry Conditions
RESET
IRQ
to V
TCAP1
to V
MODE
5V
V
V
USER
SS
DD
SS
DD
9V
5V
+9V Rising Edge*
V
BOOTSTRAP
DD
* Minimum hold time should be 2 clock cycles, after that it can be used as a normal IRQ function pin.
A.3.1
User Mode
The normal operating mode of the MC68HC705L1 is the user mode. The user mode will be
entered if the RESET line is brought low, and the IRQ pin is within its normal operational range
(V to V ), the rising edge of the RESET will cause the MCU to enter the user mode.
SS
DD
Warning: In the MC68HC705L1, all vectors are fetched from EPROM in user mode; therefore,
the EPROM must be programmed (via the bootstrap mode) before the device is
powered up in user mode.
A.3.2
Bootstrap Mode
The bootstrap mode is provided in the MC68HC705L1 as a mean of self-programming its EPROM
with minimal circuitry. It is entered on the rising edge of RESET if IRQ pin is at 1.8V and TCAP1
DD
is at logic one. RESET must be held low for 4064 cycles after POR (power-on reset).
A.4
EPROM Programming
The Program Control register (PCR) is provided for EPROM programming. The function of the
EPROM depends on the device operating mode. Figure A-2 shows the EPROM programming
circuit for MC68HC705L1.
A
TPG
MC68HC05L1
MC68HC705L1
MOTOROLA
A-3
A.4.1
Program Control Register (PCR)
State
on reset
Address bit 7
$0E
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
RESERVED
LATA
EPGM uuuu uu00
LATA - EPROM Latch Control
1 (set)
–
EPROM address and data bus configured for programming (writes to
EPROM cause address data to be latched). EPROM is in
programming mode and cannot be read if LATA is 1. This bit should
not be set unless a programming voltage is applied to the V pin.
PP
0 (clear) – EPROM address and data bus configured for normal reads.
EPGM - EPROM Program Command
1 (set)
–
Programming power connected to the EPROM array. If LATA not = 1
then EPGM = 0.
0 (clear) – Programming power disconnected from the EPROM array.
A.4.2
EPROM Programming Sequence
Programming the EPROM of the MC68HC705L1 is as follows:
1) Set the LATA bit.
2) Write the data to be programmed to the address to be programmed.
3) Set the EPGM bit.
4) Delay for 1ms.
5) Clear the EPGM and the LATA bits.
The last action may be carried out in a single CPU write operation. It is important to remember
that an external programming voltage must be applied to the V pin while programming, but
PP
should be equal to V during normal operation.
DD
Example shows address $1000 is programmed with $00.
CLR
LDX
BSET
LDA
STA
BSET
JSR
CLR
PCR
#$00
;reset PCR
;load index register with 00
;set LATA bit
;load data=00 in to A
;latch data and address
;program
;call delay subroutine for 1ms
;reset PCR
1,PCR
#$00
$1000,X
0,PCR
DELAY
PCR
A
TPG
MOTOROLA
A-4
MC68HC705L1
MC68HC05L1
VPP=13V
470
+5V
VPP
TCAP1
A0
A1
A2
A3
R
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
QA
QB
QC
QD
D0
D1
D2
D3
D4
D5
D6
D7
HC393
100K
CLR
1N1418
RESET
QA
QB
QC
QD
R
A4
A5
A6
A7
RESET
HC393
+
CLR
0.01µ
27256
A8
A9
A10
A11
QA
QB
QC
QD
R
PB2
PB7
OE
HC393
WE
CLR
OSC1
OSC2
+5V
2.0MHz
A12
A13
A14
QA
QB
QC
QD
R
VPP
CE
HC393
10M
22p
MC68HC705L1
CLR
PB3
PB4
22p
+5V
4K7
4K7
+5V
Program/Verify
+5V
470
470
PB0
PB1
PB5
PB6
Open - Program & Verify
Closed - Verify
10K
10K
+5V
Verify
VSS
VDD
+
0.1µ
1µ
Figure A-2 MC68HC705L1 EPROM Programming Circuit
A
TPG
MC68HC05L1
MC68HC705L1
MOTOROLA
A-5
A.5
Pin Assignments
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
VSEG7
VSEG6
VSEG5
VSEG4
VSEG3
VSEG2
VSEG1
VSEG0
VBP3
1
VSEG8
VSEG9
VSEG10
VSEG11
VSEG12
VSEG13
VSEG14
VSEG15
VLCD
2
3
4
5
6
7
8
9
VBP2
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
OSC2
VBP1
VBP0
PD2/TCMP1
PD3/TCMP2
PD1/TCAP2
PD0/TCAP1
PE0
OSC1
RESET
PC7/VRL
PC6/VRH
PC5/AN5
PC4/AN4
PC3/AN3
PC2/AN2
PC1/AN1
PC0/AN0
PB7
IRQ/VPP
PA0
PA1
PA2
PA3
PB6
PA4
PB5
PA5
PB4
PA6
PB3
PA7
PB2
VDD
PB1
VSS
PB0
Figure A-3 Pin Assignments for 56-pin SDIP package
VSEG1
VSEG0
VBP3
1
2
3
48 VSEG14
47 VSEG15
46 VLCD
VBP2
4
45 OSC2
VBP1
5
44 OSC1
VBP0
6
7
8
9
10
11
12
13
14
15
16
43 RESET
42 PC7/VRL
41 PC6/VRH
40 PC5/AN5
39 PC4/AN4
38 PC3/AN3
37 PC2/AN2
36 PC1/AN1
35 PC0/AN0
34 PB7
PD2/TCMP1
PD3/TCMP2
PD1/TCAP2
PD0/TCAP1
PE0
IRQ/VPP
PA0
PA1
PA2
PA3
A
33 PB6
Figure A-4 Pin Assignment for 64-pin QFP package
TPG
MOTOROLA
A-6
MC68HC705L1
MC68HC05L1
GENERAL DESCRIPTION
PIN DESCRIPTION AND INPUT/OUTPUT PORTS
MEMORY AND REGISTERS
1
2
3
RESETS AND INTERRUPTS
4
PROGRAMMABLE TIMER
5
ANALOG TO DIGITAL CONVERTER
LIQUID CRYSTAL DISPLAY DRIVER
CPU CORE AND INSTRUCTION SET
LOW POWER MODES
6
7
8
9
OPERATING MODES
10
11
12
A
ELECTRICAL SPECIFICATIONS
MECHANICAL SPECIFICATIONS
MC68HC705L1
TPG
GENERAL DESCRIPTION
1
2
PIN DESCRIPTION AND INPUT/OUTPUT PORTS
MEMORY AND REGISTERS
RESETS AND INTERRUPTS
PROGRAMMABLE TIMER
3
4
5
ANALOG TO DIGITAL CONVERTER
LIQUID CRYSTAL DISPLAY DRIVER
CPU CORE AND INSTRUCTION SET
LOW POWER MODES
6
7
8
9
OPERATING MODES
10
11
12
A
ELECTRICAL SPECIFICATIONS
MECHANICAL SPECIFICATIONS
MC68HC705L1
TPG
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
How to reach us:
MFAX: RMFAX0@email.sps.mot.com – TOUCHTONE (602) 244-6609
INTERNET: http://Design-NET.com
USA/EUROPE: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. 1-800-441-2447
JAPAN: Nippon Motorola Ltd.; Tatsumi-SPD-JLDC, Toshikatsu Otsuki, 6F Seibu-Butsuryu-Center,
3-14-2 Tatsumi Koto-Ku, Tokyo 135, Japan. 03-3521-8315
HONG KONG: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road,
Tai Po, N.T., Hong Kong. 852-26629298
!MOTOROLA
MC68HC05L1D/H
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