MC74AC273MEL [ROCHESTER]
D Flip-Flop, AC Series, 1-Func, Positive Edge Triggered, 8-Bit, True Output, CMOS, PDSO20, EIAJ, SO-20;
| 型号： | MC74AC273MEL |
| 厂家： | 
Rochester Electronics |
| 描述： | D Flip-Flop, AC Series, 1-Func, Positive Edge Triggered, 8-Bit, True Output, CMOS, PDSO20, EIAJ, SO-20 光电二极管 逻辑集成电路 触发器 |
| 文件： | 总9页 (文件大小：794K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC74AC273, MC74ACT273
Octal D Flip−Flop
The MC74AC273/74ACT273 has eight edge-triggered D−type
flip−flops with individual D inputs and Q outputs. The common
buffered Clock (CP) and Master Reset (MR) inputs load and reset
(clear) all flip−flops simultaneously.
The register is fully edge-triggered. The state of each D input, one
setup time before the LOW−to−HIGH clock transition, is transferred
to the corresponding flip−flop’s Q output.
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All outputs will be forced LOW independently of Clock or Data
inputs by a LOW voltage level on the MR input. The device is useful
for applications where the true output only is required and the Clock
and Master Reset are common to all storage elements.
PDIP−20
SUFFIX N
CASE 738
20
1
Features
• Ideal Buffer for MOS Microprocessor or Memory
• Eight Edge-Triggered D Flip−Flops
• Buffered Common Clock
• Buffered, Asynchronous Master Reset
• See MC74AC377 for Clock Enable Version
• See MC74AC373 for Transparent Latch Version
• See MC74AC374 for 3-State Version
• Outputs Source/Sink 24 mA
• ′ACT273 Has TTL Compatible Inputs
• Pb−Free Packages are Available*
SOIC−20WB
SUFFIX DW
CASE 751D
20
1
TSSOP−20
SUFFIX DT
CASE 948E
20
1
SOEIAJ−20
SUFFIX M
CASE 967
20
V
Q
D
D
Q
Q
D
D
Q
4
CP
11
CC
7
7
6
6
5
5
4
20
19
18
17
16
15
14
12
13
1
PIN ASSIGNMENT
PIN
D0−D
FUNCTION
Data Inputs
7
1
2
3
4
5
6
7
9
8
10
MR
CP
Master Reset
MR
Q
D
D
Q
Q
D
D
Q
3
GND
0
0
1
1
2
2
3
Clock Pulse Input
Data Outputs
(Top View)
Q −Q
0
7
Pinout: 20−Lead Packages Conductors
MODE SELECT-FUNCTION TABLE
D
D
D
D
D
D
D
D
6 7
0
1
2
3
4
5
Inputs
Outputs
CP
Operating Mode
MR
L
CP
X
D
Q
n
n
MR
Q
Q
Q
Q
Q
Q
Q
Q
6 7
Reset (Clear)
Load ′1′
X
L
H
L
0
1
2
3
4
5
H
H
L
Load ′0′
H
Logic Symbol
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
= LOW-to-HIGH Clock Transition
DEVICE MARKING INFORMATION
See general marking information in the device marking
section on page 6 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
©
Semiconductor Components Industries, LLC, 2005
1
Publication Order Number:
December, 2005 − Rev. 6
MC74AC273/D
MC74AC273, MC74ACT273
D
D
D
D
D
D
D
D
7
0
1
2
3
4
5
6
CP
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
CP
CP
CP
CP
CP
CP
CP
CP
R
R
R
R
R
R
R
R
D
D
D
D
D
D
D
D
MR
O
O
O
O
O
O
O
O
7
0
1
2
3
4
5
6
NOTE: That this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Figure 1. Logic Diagram
MAXIMUM RATINGS
Symbol
Parameter
DC Supply Voltage (Referenced to GND)
Value
Unit
V
V
− 0.5 to + 7.0
CC
V
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
− 0.5 to V + 0.5
V
IN
CC
V
− 0.5 to V + 0.5
V
OUT
CC
I
20
mA
mA
mA
°C
IN
I
DC Output Sink/Source Current, per Pin
50
50
OUT
I
DC V or GND Current per Output Pin
CC
CC
T
stg
Storage Temperature
− 65 to + 150
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
2.0
4.5
0
Typ
5.0
5.0
−
Max
6.0
Unit
V
′AC
V
Supply Voltage
CC
′ACT
5.5
V , V
in out
DC Input Voltage, Output Voltage (Ref. to GND)
V
V
CC
V
V
V
V
V
@ 3.0 V
@ 4.5 V
@ 5.5 V
@ 4.5 V
@ 5.5 V
−
150
40
25
10
8.0
−
−
CC
CC
CC
CC
CC
Input Rise and Fall Time (Note 1)
−
−
−
−
−
ns/V
t , t
r
f
f
′AC Devices except Schmitt Inputs
−
−
Input Rise and Fall Time (Note 2)
t , t
r
ns/V
′ACT Devices except Schmitt Inputs
−
T
Junction Temperature (PDIP)
Operating Ambient Temperature Range
Output Current − High
−
140
85
°C
°C
J
T
A
−40
−
25
−
I
−24
24
mA
mA
OH
I
Output Current − Low
−
−
OL
1. V from 30% to 70% V ; see individual Data Sheets for devices that differ from the typical input rise and fall times.
IN
CC
2. V from 0.8 V to 2.0 V; see individual Data Sheets for devices that differ from the typical input rise and fall times.
IN
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2
MC74AC273, MC74ACT273
DC CHARACTERISTICS
74AC
74AC
= −40°C to +85°C
A
V
CC
Symbol
Parameter
T
= +25°C
T
Unit
Conditions
A
(V)
Typ
Guaranteed Limits
V
Minimum High Level Input Voltage
Maximum Low Level Input Voltage
Minimum High Level Output Voltage
3.0
4.5
5.5
1.5
2.25
2.75
2.1
3.15
3.85
2.1
3.15
3.85
V
V
= 0.1 V
OUT
CC
IH
or V − 0.1 V
V
3.0
4.5
5.5
1.5
2.25
2.75
0.9
1.35
1.65
0.9
1.35
1.65
V
V
V
= 0.1 V
OUT
CC
IL
or V − 0.1 V
V
3.0
4.5
5.5
2.99
4.49
5.49
2.9
4.4
5.4
2.9
4.4
5.4
I
= −50 mA
OUT
OH
*V = V or V
IN
IL
IH
3.0
4.5
5.5
−
−
−
2.56
3.86
4.86
2.46
3.76
4.76
−12 mA
V
V
I
I
−24 mA
−24 mA
OH
V
Maximum Low Level Output Voltage
3.0
4.5
5.5
0.002
0.001
0.001
0.1
0.1
0.1
0.1
0.1
0.1
= 50 mA
OUT
OL
*V = V or V
IN
IL
IH
3.0
4.5
5.5
−
−
−
0.36
0.36
0.36
0.44
0.44
0.44
12 mA
V
I
24 mA
24 mA
OL
I
Maximum Input Leakage Current
†Minimum Dynamic Output Current
5.5
−
0.1
1.0
mA
V = V , GND
IN
I
CC
I
I
5.5
5.5
−
−
−
−
75
−75
mA
V
V
= 1.65 V Max
= 3.85 V Min
OLD
OHD
OLD
OHD
I
Maximum Quiescent Supply Current
5.5
−
8.0
80
mA
V
= V or GND
IN CC
CC
*All outputs loaded; thresholds on input associated with output under test.
†Maximum test duration 2.0 ms, one output loaded at a time.
NOTE: Note: I and I @ 3.0 V are guaranteed to be less than or equal to the respective limit @ 5.5 V V .
IN
CC
CC
AC CHARACTERISTICS (For Figures and Waveforms − See Section 3 of the ON Semiconductor FACT Data Book, DL138/D)
74AC
74AC
V
(V)
*
Figure
No.
CC
Symbol
Parameter
T
A
= +25°C C = 50 pF
T
A
= −40°C to +85°C C = 50 pF
Unit
L
L
Min
Typ
Max
Min
Max
Maximum Clock
Frequency
3.3
5.0
90
140
125
175
−
−
75
125
−
−
f
Mhz
ns
3−3
3−6
3−6
3−6
max
PLH
PHL
PHL
Propagation Delay
Clock to Output
3.3
5.0
4.0
3.0
7.0
5.5
12.5
9.0
3.0
2.5
14.0
10.0
t
t
t
Propagation Delay
Clock to Output
3.3
5.0
4.0
3.0
7.0
5.0
13.0
10.0
3.5
2.5
14.5
11.0
ns
Propagation Delay
MR to Output
3.3
5.0
4.0
3.0
7.0
5.0
13.0
10.0
3.5
2.5
14.0
10.5
ns
*Voltage Range 3.3 V is 3.3 V 0.3 V. Voltage Range 5.0 V is 5.0 V 0.5 V.
AC OPERATING REQUIREMENTS
74AC
74AC
= −40°C to +85°C C = 50 pF
V
*
CC
Figure
No.
Symbol
Parameter
T
A
= +25°C C = 50 pF
T
A
Unit
L
L
(V)
Typ
Guaranteed Minimum
Setup Time, HIGH or LOW
Data to CP
3.3
5.0
3.5
2.5
5.5
4.0
6.0
4.5
t
t
ns
ns
ns
ns
ns
3−9
3−9
3−6
3−6
3−9
s
Hold Time, HIGH or LOW
Data to CP
3.3
5.0
−2.0
−1.0
0
1.0
0
1.0
h
Clock Pulse Width
HIGH or LOW
3.3
5.0
3.5
2.5
5.5
4.0
6.0
4.5
t
t
w
w
MR Pulse Width
HIGH or LOW
3.3
5.0
2.0
1.5
5.5
4.0
6.0
4.5
Recovery Time
MR to CP
3.3
5.0
1.5
1.0
3.5
2.0
4.5
3.0
t
rec
*Voltage Range 3.3 V is 3.3 V 0.3 V. Voltage Range 5.0 V is 5.0 V 0.5 V.
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3
MC74AC273, MC74ACT273
DC CHARACTERISTICS
74ACT
74ACT
T
=
V
(V)
A
CC
T
A
= +25°C
Symbol
Parameter
Unit
Conditions
−40°C to +85°C
Typ
Guaranteed Limits
V
Minimum High Level Input Voltage
Maximum Low Level Input Voltage
Minimum High Level Output Voltage
4.5
5.5
1.5
1.5
2.0
2.0
2.0
2.0
V
= 0.1 V
OUT
IH
V
V
V
or V − 0.1 V
CC
V
4.5
5.5
1.5
1.5
0.8
0.8
0.8
0.8
V
= 0.1 V
OUT
IL
or V − 0.1 V
CC
V
4.5
5.5
4.49
5.49
4.4
5.4
4.4
5.4
I
= −50 mA
OUT
OH
*V = V or V
IN
IL
IH
IH
4.5
5.5
−
−
3.86
4.86
3.76
4.76
V
V
V
−24 mA
I
OH
−24 mA
V
Maximum Low Level Output Voltage
Maximum Input Leakage Current
4.5
5.5
0.001
0.001
0.1
0.1
0.1
0.1
I
= 50 mA
OUT
OL
*V = V or V
IN
IL
4.5
5.5
−
−
0.36
0.36
0.44
0.44
24 mA
24 mA
I
OL
I
5.5
5.5
−
0.1
−
1.0
1.5
mA
mA
mA
V = V , GND
I CC
IN
DI
Additional Max. I /Input
0.6
V = V − 2.1 V
CCT
CC
I
CC
I
I
5.5
5.5
−
−
−
−
75
−75
V
V
= 1.65 V Max
= 3.85 V Min
†Minimum Dynamic Output Current
OLD
OHD
OLD
OHD
I
Maximum Quiescent Supply Current
5.5
−
8.0
80
mA
V
= V or GND
IN CC
CC
*All outputs loaded; thresholds on input associated with output under test.
†Maximum test duration 2.0 ms, one output loaded at a time.
AC CHARACTERISTICS (For Figures and Waveforms − See Section 3 of the ON Semiconductor FACT Data Book, DL138/D)
74ACT
74ACT
T
A
= −40°C to +85°C
V
(V)
*
Figure
No.
CC
T
A
= +25°C C = 50 pF
Symbol
Parameter
Unit
L
C = 50 pF
L
Min
125
3.0
3.0
3.0
Typ
200
6.0
6.5
7.0
Max
−
Min
Max
−
f
Maximum Clock Frequency
5.0
5.0
5.0
5.0
125
2.5
2.5
2.5
MHz
ns
3−3
3−6
3−6
3−6
max
PHL
PLH
PHL
t
t
t
Propagation Delay Clock to Output
Propagation Delay Clock to Output
Propagation Delay MR to Output
10
11
11.0
12.0
11.5
ns
11
ns
*Voltage Range 5.0 V is 5.0 V 0.5 V.
AC OPERATING REQUIREMENTS
74ACT
74ACT
= −40°C to +85°C
A
V
(V)
*
T
Figure
No.
CC
T
A
= +25°C C = 50 pF
L
Symbol
Parameter
Unit
C = 50 pF
L
Typ
3.0
Guaranteed Minimum
t
t
Setup Time, HIGH or LOW − Data to CP
Hold Time, HIGH or LOW − Data to CP
Clock Pulse Width − HIGH or LOW
MR Pulse Width − HIGH or LOW
Recovery Time − MR to CP
5.0
5.0
5.0
5.0
5.0
4.5
5.0
2.0
4.5
4.5
3.0
ns
ns
ns
ns
ns
3−9
3−9
3−6
3−6
3−6
s
−2.5
2.5
2.0
4.0
4.0
2.0
h
t
t
w
w
2.5
t
−1.0
rec
*Voltage Range 5.0 V is 5.0 V 0.5 V.
CAPACITANCE
Symbol
Parameter
Value Typ
Unit
Test Conditions
C
Input Capacitance
4.5
50
pF
pF
V
V
= 5.0 V
= 5.0 V
IN
CC
CC
C
PD
Power Dissipation Capacitance
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4
MC74AC273, MC74ACT273
ORDERING INFORMATION
Device
†
Package
Shipping
MC74AC273N
PDIP−20
18 Units / Rail
18 Units / Rail
MC74AC273NG
PDIP−20
(Pb−Free)
MC74ACT273N
PDIP−20
18 Units / Rail
18 Units / Rail
MC74ACT273NG
PDIP−20
(Pb−Free)
MC74AC273DW
SOIC−20WB
38 Units / Rail
38 Units / Rail
MC74AC273DWG
SOIC−20WB
(Pb−Free)
MC74AC273DWR2
MC74AC273DWR2G
SOIC−20WB
1000 / Tape & Reel
1000 / Tape & Reel
SOIC−20WB
(Pb−Free)
MC74AC273DTR2
MC74AC273DTR2G
MC74ACT273DW
MC74ACT273DWG
TSSOP−20*
TSSOP−20*
SOIC−20WB
2500 / Tape & Reel
2500 / Tape & Reel
38 Units / Rail
SOIC−20WB
(Pb−Free)
38 Units / Rail
MC74ACT273DWR2
MC74ACT273DWR2G
SOIC−20WB
1000 / Tape & Reel
1000 / Tape & Reel
SOIC−20WB
(Pb−Free)
MC74ACT273DTR2
MC74ACT273DTR2G
MC74AC273MEL
TSSOP−20*
TSSOP−20*
SOEIAJ−20
2500 / Tape & Reel
2500 / Tape & Reel
2000 / Tape & Reel
2000 / Tape & Reel
MC74AC273MELG
SOEIAJ−20
(Pb−Free)
MC74ACT273M
SOEIAJ−20
40 Units / Rail
40 Units / Rail
MC74ACT273MG
SOEIAJ−20
(Pb−Free)
MC74ACT273MEL
MC74ACT273MELG
SOEIAJ−20
2000 / Tape & Reel
2000 / Tape & Reel
SOEIAJ−20
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
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5
MC74AC273, MC74ACT273
MARKING DIAGRAMS
PDIP−20
SOIC−20WB
TSSOP−20
SOEIAJ−20
20
20
20
1
20
1
AC
273
MC74AC273N
AWLYYWWG
AC273
AWLYYWWG
74AC273
AWLYWWG
ALYWG
G
1
1
20
20
20
1
20
1
ACT
273
MC74ACT273N
AWLYYWWG
ACT273
AWLYYWWG
74ACT273
AWLYWWG
ALYWG
G
1
1
A
WL, L
YY, Y
= Assembly Location
= Wafer Lot
= Year
WW, W = Work Week
G or G
= Pb−Free Package
(Note: Microdot may be in either location)
PACKAGE DIMENSIONS
PDIP−20
N SUFFIX
CASE 738−03
ISSUE E
NOTES:
−A−
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
20
1
11
B
10
INCHES
DIM MIN MAX
MILLIMETERS
L
C
MIN
25.66
6.10
3.81
0.39
MAX
27.17
6.60
4.57
0.55
A
B
C
D
E
F
1.010
0.240
0.150
0.015
1.070
0.260
0.180
0.022
−T−
SEATING
PLANE
0.050 BSC
1.27 BSC
K
0.050
0.070
1.27
1.77
G
J
0.100 BSC
2.54 BSC
M
0.008
0.110
0.015
0.140
0.21
2.80
0.38
3.55
N
E
K
L
0.300 BSC
7.62 BSC
G
F
J 20 PL
M
N
0
0.020
15
0.040
0
_
0.51
15
1.01
_
_
_
D 20 PL
M
M
B
0.25 (0.010)
T
M
M
A
0.25 (0.010)
T
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6
MC74AC273, MC74ACT273
PACKAGE DIMENSIONS
SOIC−20 WB
DW SUFFIX
CASE 751D−05
ISSUE G
NOTES:
D
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
A
q
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
20
11
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF B
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
E
B
MILLIMETERS
1
10
DIM MIN
MAX
2.65
0.25
0.49
0.32
12.95
7.60
A
A1
B
C
D
E
2.35
0.10
0.35
0.23
12.65
7.40
20X B
M
S
S
B
T
0.25
A
e
1.27 BSC
H
h
10.05
0.25
0.50
0
10.55
0.75
0.90
7
A
L
q
_
_
SEATING
PLANE
18X e
A1
C
T
TSSOP−20
D5 SUFFIX
CASE 948E−02
ISSUE B
NOTES:
20X K REF
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION:
MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE
MOLD FLASH, PROTRUSIONS OR GATE
BURRS. MOLD FLASH OR GATE BURRS
SHALL NOT EXCEED 0.15 (0.006) PER
SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION
SHALL NOT EXCEED 0.25 (0.010) PER
SIDE.
M
S
S
V
0.10 (0.004)
T
U
S
U
0.15 (0.006) T
K
K1
20
11
2X L/2
J J1
B
L
−U−
PIN 1
IDENT
SECTION N−N
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
1
10
0.25 (0.010)
N
S
0.15 (0.006) T
U
6. TERMINAL NUMBERS ARE SHOWN
FOR REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
M
A
−V−
N
MILLIMETERS
INCHES
DIM MIN
MAX
6.60
4.50
1.20
0.15
0.75
MIN
MAX
0.260
0.177
F
A
B
6.40
4.30
−−−
0.252
0.169
DETAIL E
C
−−− 0.047
0.006
0.030
D
0.05
0.50
0.002
0.020
F
−W−
C
G
H
0.65 BSC
0.026 BSC
0.27
0.09
0.09
0.19
0.19
0.37
0.20
0.16
0.30
0.25
0.011
0.004
0.004
0.007
0.007
0.015
0.008
0.006
0.012
0.010
J
G
J1
K
D
H
DETAIL E
K1
L
0.100 (0.004)
6.40 BSC
0.252 BSC
0
−T− SEATING
PLANE
M
0
8
8
_
_
_
_
http://onsemi.com
7
MC74AC273, MC74ACT273
PACKAGE DIMENSIONS
SOEIAJ−20
M SUFFIX
CASE 967−01
ISSUE A
NOTES:
ꢀꢁ1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
L
20
11
E
Q
ꢀꢁ2. CONTROLLING DIMENSION: MILLIMETER.
ꢀꢁ3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
1
H
E
E
_
M
ꢀꢁ4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
L
1
10
ꢀꢁ5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
DETAIL P
Z
D
VIEW P
e
A
c
MILLIMETERS
INCHES
MIN MAX
−−− 0.081
DIM MIN
MAX
A
−−−
0.05
2.05
A
1
A
b
1
0.20 0.002
0.50 0.014
0.25 0.006
12.80 0.486
5.45 0.201
0.008
0.020
0.010
0.504
0.215
b
c
0.35
0.15
M
0.10 (0.004)
0.13 (0.005)
D
E
e
12.35
5.10
1.27 BSC
0.050 BSC
H
7.40
0.50
1.10
8.20 0.291
0.85 0.020
1.50 0.043
0.323
0.033
0.059
E
L
L
E
M
Q
0
10
0.90 0.028
10
0.035
0
_
_
_
_
0.70
−−−
1
Z
0.81
−−− 0.032
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