MC74AC377DTR2G [ROCHESTER]
AC SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO20, LEAD FREE, TSSOP-20;
| 型号： | MC74AC377DTR2G |
| 厂家： | 
Rochester Electronics |
| 描述： | AC SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO20, LEAD FREE, TSSOP-20 光电二极管 输出元件 逻辑集成电路 触发器 |
| 文件： | 总11页 (文件大小：806K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC74AC377, MC74ACT377
Octal D Flip−Flop with
Clock Enable
The MC74AC377/74ACT377 has eight edge-triggered, D-type
flip-flops with individual D inputs and Q outputs. The common
buffered Clock (CP) input loads all flip-flops simultaneously, when
the Clock Enable (CE) is LOW. The register is fully edge-triggered.
The state of each D input, one setup time before the LOW-to-HIGH
clock transition, is transferred to the corresponding flip-flop’s Q
output. The CE input must be stable only one setup time prior to the
LOW-to-HIGH clock transition for predictable operation.
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PDIP−20
N SUFFIX
CASE 738
Features
1
• Ideal for Addressable Register Applications
• Clock Enable for Address and Data Synchronization Applications
• Eight Edge-Triggered D Flip-Flops
SOIC−20W
DW SUFFIX
CASE 751D
• Buffered Common Clock
• Outputs Source/Sink 24 mA
1
• See MC74AC273 for Master Reset Version
• See MC74AC373 for Transparent Latch Version
• See MC74AC374 for 3-State Version
• ACT377 Has TTL Compatible Inputs
• MSL = 1 for all Surface Mount
• Chip Complexity: 292 FETs or 73 Gates
• Pb−Free Packages are Available
TSSOP−20
DT SUFFIX
CASE 948E
1
SOEIAJ−20
M SUFFIX
CASE 967
V
O
D
D
O
O
D
D
O
4
CP
11
CC
7
7
6
6
5
5
4
1
20
19
18
17
16
15
14
12
13
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
DEVICE MARKING INFORMATION
1
2
3
4
5
6
7
9
8
10
See general marking information in the device marking
section on page 7 of this data sheet.
CE
O
D
0
D
1
O
O
D
2
D
3
O
3
GND
0
1
2
Figure 1. Pinout: 20−Lead Packages Conductors
(Top View)
PIN NAMES
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
PIN
FUNCTION
Data Inputs
CP
CE
D −D
0
7
O
O
O
O
O
O
O
O
7
CE
Clock Enable (Active LOW)
Data Outputs
0
1
2
3
4
5
6
Q −Q
0
7
CP
Clock Pulse Input
Figure 2. Logic Symbol
©
Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
December, 2006 − Rev. 9
MC74AC377/D
MC74AC377, MC74ACT377
MODE SELECT-FUNCTION TABLE
Operating Mode
Inputs
Outputs
CP
CE
D
n
Q
n
Load ′1′
Load ′0′
L
H
H
L
H
H
L
X
X
L
No Change
No Change
Hold (Do Nothing)
X
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
= LOW-to-HIGH Clock Transition
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
CE
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
CP
CP
CP
CP
CP
CP
CP
CP
CP
O
O
O
O
O
O
O
O
7
0
1
2
3
4
5
6
Please note that this diagram is provided only for the understanding of
logic operations and should not be used to estimate propagation delays.
Figure 3. Logic Diagram
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2
MC74AC377, MC74ACT377
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
DC Supply Voltage (Referenced to GND)
−0.5 to +7.0
V
CC
V
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
−0.5 to V +0.5
V
V
in
CC
V
out
−0.5 to V +0.5
CC
I
20
50
mA
mA
mA
°C
in
I
I
DC Output Sink/Source Current, per Pin
out
CC
DC V or GND Current per Output Pin
50
CC
T
stg
Storage Temperature
−65 to +150
q
Thermal Resistance, (Junction−to−Ambient)
SOIC
TSSOP
PDIP
97
129
69
°C/W
JA
V
ESD Withstand Voltage
Latchup Performance
Human Body Model (Note 1)
Machine Model (Note 2)
Charged Device Model (Note 3)
> 2000
> 200
> 1000
V
ESD
I
V
= 5.5 V; TA = 125°C (Note 4)
CC
> 100
mA
Latchup
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Tested to EIA/JESD22−A114−A
2. Tested to EIA/JESD22−A115−A
3. Tested to JESD22−C101−A
4. Tested to EIA/JESD78
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
2.0
4.5
0
Typ
5.0
5.0
−
Max
6.0
Unit
′AC
V
Supply Voltage
V
V
CC
′ACT
5.5
V , V
in out
DC Input Voltage, Output Voltage (Ref. to GND)
V
CC
V
V
V
V
V
@ 3.0 V
@ 4.5 V
@ 5.5 V
@ 4.5 V
@ 5.5 V
−
150
40
25
10
8.0
−
−
CC
CC
CC
CC
CC
Input Rise and Fall Time (Note 5)
−
−
−
−
−
ns/V
t , t
r
f
f
′AC Devices except Schmitt Inputs
−
−
Input Rise and Fall Time (Note 6)
t , t
r
ns/V
′ACT Devices except Schmitt Inputs
−
T
Junction Temperature (PDIP)
Operating Ambient Temperature Range
Output Current − High
−
140
85
°C
°C
J
T
A
−40
−
25
−
I
−24
24
mA
mA
OH
I
Output Current − Low
−
−
OL
5. V from 30% to 70% V ; see individual Data Sheets for devices that differ from the typical input rise and fall times.
in
CC
6. V from 0.8 V to 2.0 V; see individual Data Sheets for devices that differ from the typical input rise and fall times.
in
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3
MC74AC377, MC74ACT377
74AC − DC CHARACTERISTICS
T
=
A
T
= +25°C
A
V
(V)
CC
−40°C to +85°C
Symbol
Parameter
Unit
Conditions
Typ
Guaranteed Limits
V
Minimum High Level Input
Voltage
3.0
4.5
5.5
1.50
2.25
2.75
2.10
3.15
3.85
2.10
3.15
3.85
V
V
V
V
or
V
= 0.1 V
− 0.1 V
IH
OUT
CC
V
Maximum Low Level Input
Voltage
3.0
4.5
5.5
1.50
2.25
2.75
0.90
1.35
1.65
0.90
1.35
1.65
V
V
V
V
or
V
= 0.1 V
IL
OUT
− 0.1 V
CC
V
Minimum High Level Output
Voltage
3.0
4.5
5.5
2.99
4.49
5.49
2.9
4.4
5.4
2.9
4.4
5.4
V
V
V
I
= −50 mA
OH
OUT
3.0
4.5
5.5
−
2.56
3.86
4.86
2.46
3.76
4.76
V
V
V
*V = V or V
−12 mA
−24 mA
−24 mA
IN
IL
IH
I
OH
V
Maximum Low Level Output
Voltage
3.0
4.5
5.5
0.002
0.001
0.001
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
I
= 50 mA
OUT
OL
3.0
4.5
5.5
−
0.36
0.36
0.36
0.44
0.44
0.44
V
V
V
*V = V or V
IH
−12 mA
−24 mA
−24 mA
IN
IL
I
OH
I
Maximum Input Leakage Current
Maximum Input Leakage Current
5.5
−
−
0.1
−
1.0
mA
V = V , GND
IN
I
CC
I
I
5.5
5.5
75
−75
mA
mA
V
V
= 1.65 V Max
= 3.85 V Min
OLD
OHD
OLD
OHD
I
Maximum Quiescent Supply
Current
−
CC
5.5
8.0
80
mA
V
= V or GND
IN CC
*All outputs loaded; thresholds on input associated with output under test.
†Maximum test duration 2.0 ms, one output loaded at a time.
NOTE:
I
and I @ 3.0 V are guaranteed to be less than or equal to the respective limit @ 5.5 V V
.
IN
CC
CC
74AC − AC CHARACTERISTICS For Figures and Waveforms, See Figures 4, 5, and 6.
T
A
= −40°C to +85°C
T
= +25°C C = 50 pF
L
A
V
(V)
*
CC
C
= 50 pF
L
Symbol
Parameter
Unit
Min
Typ
Max
Min
Max
3.3
5.0
90
140
−
−
75
125
−
f
Maximum Clock Frequency
Propagation Delay
MHz
ns
max
PLH
PHL
3.3
5.0
3.0
2.0
−
−
13.0
9.0
1.5
1.5
14.0
10.0
t
t
CP to Q
CP to Q
n
n
3.3
5.0
3.5
2.5
13.0
10.0
2.0
1.5
14.5
11.0
Propagation Delay
ns
* Voltage Range 3.3 V is 3.3 V 0.3 V; Voltage Range 5.0 V is 5.0 V 0.5 V.
74AC − AC OPERATING REQUIREMENTS
T
= +25°C C = 50 pF
T = −40°C to +85°C
A
A
L
V
(V)
*
CC
Symbol
Parameter
Unit
Typ
Guaranteed Minimum
3.3
5.0
5.5
4.07
6.0
4.5
ns
t
t
t
t
Setup Time, HIGH or LOW
Hold Time, HIGH or LOW
Setup Time, HIGH or LOW
Hold Time, HIGH or LOW
CP Pulse Width
D to CP
−
s
h
s
h
n
3.3
5.0
0
1.0
0
1.0
ns
ns
ns
D to CP
n
−
−
−
−
3.3
5.0
6.0
4.0
7.5
4.5
CE to CP
CE to CP
3.3
5.0
0
1.0
0
1.0
3.3
5.0
5.5
4.0
6.0
4.5
t
HIGH or LOW
ns
w
* Voltage Range 3.3 V is 3.3 V 0.3 V; Voltage Range 5.0 V is 5.0 V 0.5 V.
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4
MC74AC377, MC74ACT377
74ACT − DC CHARACTERISTICS
T
=
A
T
= +255C
A
V
(V)
CC
−405C to +855C
Guaranteed Limits
Symbol
Parameter
Unit
Conditions
Typ
V
Minimum High Level Input Voltage
4.5
5.5
1.5
1.5
2.0
2.0
2.0
2.0
V
or
V
= 0.1 V
− 0.1 V
IH
OUT
V
CC
V
Maximum Low Level Input Voltage
4.5
5.5
1.5
1.5
0.8
0.8
0.8
0.8
V
or
= 0.1 V
IL
OUT
V
V
− 0.1 V
CC
V
Minimum High Level Output
Voltage
4.5
5.5
4.49
5.49
4.4
5.4
4.4
5.4
V
V
V
V
I
= −50 mA
OH
OUT
4.5
5.5
−
3.86
4.86
3.76
4.76
*V = V or V
I
−24 mA
−24 mA
IN
OH
IL
IH
IH
V
Maximum Low Level Output
Voltage
4.5
5.5
0.001
0.001
0.1
0.1
0.1
0.1
I
= 50 mA
OUT
OL
4.5
5.5
−
0.36
0.36
0.44
0.44
*V = V or V
I
−24 mA
−24 mA
IN
OH
IL
I
Maximum Input Leakage Current
5.5
5.5
5.5
−
0.6
−
0.1
−
1.0
1.5
mA
mA
mA
V = V , GND
I CC
IN
DI
Additional Max I /Input
V = V − 2.1 V
CCT
CC
I
CC
I
I
†Minimum Dynamic Output Current
−
75
−75
V
V
= 1.65 V Max
= 3.85 V Min
OLD
OHD
OLD
OHD
I
Maximum Quiescent Supply
Current
−
CC
5.5
8.0
80
mA
V
= V or GND
IN CC
*All outputs loaded; thresholds on input associated with output under test.
†Maximum test duration 2.0 ms, one output loaded at a time.
74ACT − AC CHARACTERISTICS For Figures and Waveforms — See Figures 4, 5, and 6.
T
A
= −40°C to +85°C
T
= +25°C C = 50 pF
L
A
V
(V)
*
CC
C
= 50 pF
L
Symbol
Parameter
Unit
Min
Typ
Max
Min
Max
f
Maximum Clock Frequency
Propagation Delay
5.0
5.0
5.0
140
−
−
125
−
MHz
ns
max
PLH
PHL
t
t
CP to Q
CP to Q
3.0
3.5
−
−
9.0
10
2.5
2.5
10
11
n
n
Propagation Delay
ns
*Voltage Range 5.0 V is 5.0 V 0.5 V.
74ACT − AC OPERATING REQUIREMENTS
T
= −40°C to +85°C
A
T
= +25°C C = 50 pF
L
A
V
(V)
*
CC
C
= 50 pF
L
Symbol
Parameter
Unit
Typ
Guaranteed Minimum
t
t
t
t
Setup Time, HIGH or LOW
Hold Time, HIGH or LOW
Setup Time, HIGH or LOW
Hold Time, HIGH or LOW
D to CP
5.0
5.0
5.0
5.0
5.0
−
4.5
5.5
1.0
5.5
1.0
4.5
ns
ns
ns
ns
ns
s
h
s
h
n
D to CP
n
−
−
−
−
1.0
4.5
1.0
4.0
CE to CP
CE to CP
t
CP Pulse Width
HIGH or LOW
w
*Voltage Range 5.0 V is 5.0 V 0.5 V.
CAPACITANCE
Symbol
Parameter
Input Capacitance
Power Dissipation Capacitance
Value Typ
Unit
pF
Test Conditions
C
IN
4.5
90
V
V
= 5.0 V
= 5.0 V
CC
CC
C
PD
pF
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5
MC74AC377, MC74ACT377
SWITCHING WAVEFORMS
t
t
f
r
V
CC
V
V
CC
CC
50%
CE
CLOCK
50%
t
GND
t
w
t
su
h
1/f
max
t
t
PHL
CLOCK
50%
PLH
GND
Q
50%
Figure 4.
Figure 5.
VALID
V
CC
DATA
50%
GND
t
t
su
h
V
CC
CLOCK
50%
GND
Figure 6.
450 W
OUTPUT
50 W SCOPE
DEVICE
TEST POINT
UNDER
TEST
C *
L
*Includes all probe and jig capacitance
Figure 7. Test Circuit
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6
MC74AC377, MC74ACT377
ORDERING INFORMATION
Device
†
Package
Shipping
MC74AC377N
PDIP−20
MC74AC377NG
PDIP−20
(Pb−Free)
18 Units / Rail
MC74ACT377N
PDIP−20
MC74ACT377NG
PDIP−20
(Pb−Free)
MC74AC377DW
SOIC−20
38 Units / Rail
1000 / Tape & Reel
38 Units / Rail
MC74AC377DWG
SOIC−20
(Pb−Free)
MC74AC377DWR2
MC74AC377DWR2G
SOIC−20
SOIC−20
(Pb−Free)
MC74ACT377DW
MC74ACT377DWG
SOIC−20
SOIC−20
(Pb−Free)
MC74ACT377DWR2
MC74ACT377DWR2G
SOIC−20
1000 / Tape & Reel
SOIC−20
(Pb−Free)
MC74AC377DT
TSSOP−20*
TSSOP−20*
TSSOP−20*
TSSOP−20*
SOEIAJ−20
75 Units / Rail
MC74AC377DTG
MC74AC377DTR2
MC74AC377DTR2G
MC74ACT377MEL
MC74ACT377MELG
2500 / Tape & Reel
2000 / Tape & Reel
SOEIAJ−20
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*These packages are inherently Pb−Free.
MARKING DIAGRAMS
PDIP−20
SOIC−20W
TSSOP−20
SOEIAJ−20
20
20
20
1
20
1
ACT
377
ACT377
AWLYYWWG
74ACT377
AWLYWWG
MC74ACT377N
AWLYYWWG
ALYWG
G
1
1
20
20
A
WL, L
YY, Y
= Assembly Location
= Wafer Lot
= Year
20
1
AC
377
AC377
AWLYYWWG
MC74AC377N
AWLYYWWG
ALYWG
WW, W = Work Week
G
G or G
= Pb−Free Package
1
(Note: Microdot may be in either location)
1
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7
MC74AC377, MC74ACT377
PACKAGE DIMENSIONS
PDIP−20
N SUFFIX
PLASTIC DIP PACKAGE
CASE 738−03
ISSUE E
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
−A−
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
20
1
11
10
B
INCHES
DIM MIN MAX
MILLIMETERS
L
C
MIN
25.66
6.10
3.81
0.39
MAX
27.17
6.60
4.57
0.55
A
B
C
D
E
F
1.010
0.240
0.150
0.015
1.070
0.260
0.180
0.022
0.050 BSC
1.27 BSC
−T−
SEATING
PLANE
K
0.050
0.070
1.27
1.77
G
J
0.100 BSC
2.54 BSC
M
0.008
0.110
0.015
0.140
0.21
2.80
0.38
3.55
N
E
K
L
0.300 BSC
7.62 BSC
G
F
M
N
0
0.020
15
0.040
0
_
0.51
15
1.01
J 20 PL
_
_
_
D 20 PL
M
M
T B
0.25 (0.010)
M
M
T A
0.25 (0.010)
SOIC−20W
DW SUFFIX
CASE 751D−05
ISSUE G
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
D
A
q
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
20
11
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF B
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
E
B
MILLIMETERS
1
10
DIM MIN
MAX
2.65
0.25
0.49
0.32
12.95
7.60
A
A1
B
C
D
E
2.35
0.10
0.35
0.23
12.65
7.40
20X B
M
S
S
B
0.25
T A
e
1.27 BSC
H
h
10.05
0.25
0.50
0
10.55
0.75
0.90
7
A
L
q
_
_
SEATING
PLANE
18X e
A1
C
T
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8
MC74AC377, MC74ACT377
PACKAGE DIMENSIONS
TSSOP−20
DT SUFFIX
CASE 948E−02
ISSUE C
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION:
MILLIMETER.
20X K REF
K
M
S
S
V
0.10 (0.004)
T U
S
K1
0.15 (0.006) T U
3. DIMENSION A DOES NOT INCLUDE
MOLD FLASH, PROTRUSIONS OR GATE
BURRS. MOLD FLASH OR GATE BURRS
SHALL NOT EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION
SHALL NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
J J1
20
11
2X L/2
B
SECTION N−N
L
−U−
PIN 1
IDENT
0.25 (0.010)
N
1
10
M
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
S
0.15 (0.006) T U
A
−V−
N
MILLIMETERS
INCHES
DIM MIN
MAX
6.60
4.50
1.20
0.15
0.75
MIN
MAX
0.260
0.177
F
A
B
6.40
4.30
−−−
0.252
0.169
DETAIL E
C
−−− 0.047
0.006
0.030
D
0.05
0.50
0.002
0.020
F
G
H
0.65 BSC
0.026 BSC
−W−
0.27
0.09
0.09
0.19
0.19
0.37
0.20
0.16
0.30
0.25
0.011
0.004
0.004
0.007
0.007
0.015
0.008
0.006
0.012
0.010
C
J
J1
K
G
D
H
K1
L
DETAIL E
6.40 BSC
0.252 BSC
0
0.100 (0.004)
−T− SEATING
M
0
8
8
_
_
_
_
PLANE
SOLDERING FOOTPRINT*
7.06
1
0.65
PITCH
16X
0.36
16X
1.26
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
9
MC74AC377, MC74ACT377
PACKAGE DIMENSIONS
SOEIAJ−20
M SUFFIX
CASE 967−01
ISSUE A
NOTES:
ꢀꢁ1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
L
20
11
E
Q
ꢀꢁ2. CONTROLLING DIMENSION: MILLIMETER.
ꢀꢁ3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
1
H
E
E
_
M
ꢀꢁ4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
L
1
10
ꢀꢁ5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
DETAIL P
Z
D
VIEW P
e
A
c
MILLIMETERS
INCHES
MIN MAX
−−− 0.081
DIM MIN
MAX
2.05
0.20
0.50
0.25
12.80
5.45
A
−−−
0.05
A
1
A
b
1
0.002
0.008
0.020
0.010
0.504
0.215
b
c
0.35
0.15
0.014
0.006
0.486
0.201
M
0.10 (0.004)
0.13 (0.005)
D
E
e
12.35
5.10
1.27 BSC
0.050 BSC
H
7.40
0.50
1.10
8.20
0.85
1.50
0.291
0.020
0.043
0.323
0.033
0.059
E
L
L
E
M
Q
0
10
10
0.035
0
0.028
_
_
_
_
0.70
−−−
0.90
0.81
1
Z
−−− 0.032
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to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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