MC74HC4052AFG [ROCHESTER]
4-CHANNEL, DIFFERENTIAL MULTIPLEXER, PDSO16, LEAD FREE, EIAJ, SOP-16;
| 型号： | MC74HC4052AFG |
| 厂家： | 
Rochester Electronics |
| 描述： | 4-CHANNEL, DIFFERENTIAL MULTIPLEXER, PDSO16, LEAD FREE, EIAJ, SOP-16 光电二极管 |
| 文件： | 总19页 (文件大小：868K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC74HC4051A,
MC74HC4052A,
MC74HC4053A
Analog Multiplexers /
Demultiplexers
http://onsemi.com
MARKING
DIAGRAMS
High-Performance Silicon-Gate CMOS
The MC74HC4051A, MC74HC4052A and MC74HC4053A utilize
silicon-gate CMOS technology to achieve fast propagation delays,
low ON resistances, and low OFF leakage currents. These analog
multiplexers/demultiplexers control analog voltages that may vary
16
1
PDIP-16
N SUFFIX
CASE 648
MC74HC405xAN
AWLYYWWG
16
across the complete power supply range (from V to V ).
EE
CC
1
The HC4051A, HC4052A and HC4053A are identical in pinout to
the metal-gate MC14051AB, MC14052AB and MC14053AB. The
Channel-Select inputs determine which one of the Analog
Inputs/Outputs is to be connected, by means of an analog switch, to the
Common Output/Input. When the Enable pin is HIGH, all analog
switches are turned off.
16
SOIC-16 WIDE
DW SUFFIX
CASE 751G
HC405xA
AWLYWWG
16
The Channel-Select and Enable inputs are compatible with standard
CMOS outputs; with pullup resistors they are compatible with LSTTL
outputs.
1
1
16
These devices have been designed so that the ON resistance (R ) is
on
more linear over input voltage than R of metal-gate CMOS analog
SOIC-16
D SUFFIX
CASE 751B
HC405xAG
AWLYWW
on
16
switches.
For a multiplexer/demultiplexer with injection current protection,
see HC4851A and HC4852A.
1
1
16
1
Features
TSSOP-16
DT SUFFIX
CASE 948F
HC40
5xA
16
•ꢀFast Switching and Propagation Speeds
•ꢀLow Crosstalk Between Switches
ALYWG
1
G
•ꢀDiode Protection on All Inputs/Outputs
•ꢀAnalog Power Supply Range (V - V ) = 2.0 to 12.0 V
CC
EE
16
•ꢀDigital (Control) Power Supply Range (V - GND) = 2.0 to 6.0 V
CC
SOEIAJ-16
F SUFFIX
CASE 966
16
74HC405xA
ALYWG
•ꢀImproved Linearity and Lower ON Resistance Than Metal-Gate
Counterparts
1
1
•ꢀLow Noise
•ꢀIn Compliance with the Requirements of JEDEC Standard No. 7A
•ꢀChip Complexity: HC4051A — 184 FETs or 46 Equivalent Gates
HC4052A — 168 FETs or 42 Equivalent Gates
HC4053A — 156 FETs or 39 Equivalent Gates
•ꢀPb-Free Packages are Available
x
= Specific Device Code
= Assembly Location
A
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G
= Pb-Free Package
= Pb-Free Package
G
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 13 of this data sheet.
©ꢀ Semiconductor Components Industries, LLC, 2007
July, 2007 - Rev. 4
1
Publication Order Number:
MC74HC4051A/D
MC74HC4051A, MC74HC4052A, MC74HC4053A
FUNCTION TABLE - MC74HC4051A
LOGIC DIAGRAM
MC74HC4051A
Single-Pole, 8-Position Plus Common Off
Control Inputs
Select
B
Enable
C
A
ON Channels
L
L
L
L
L
L
L
L
H
L
L
L
L
L
H
L
X0
X1
13
X0
14
L
H
H
L
X2
X3
X1
3
COMMON
OUTPUT/
INPUT
15
12
1
L
H
L
X
X2
X3
X4
X5
X6
X7
A
ANALOG
INPUTS/
OUTPUTS
H
H
H
H
X
X4
X5
MULTIPLEXER/
DEMULTIPLEXER
L
H
L
H
H
X
X6
X7
5
H
X
2
NONE
4
X = Don't Care
11
10
9
CHANNEL
SELECT
INPUTS
Pinout: MC74HC4051A (Top View)
B
V
X2
15
X1
14
X0
13
X3
12
A
B
C
9
C
CC
6
16
11
10
ENABLE
PIN 16 = V
CC
PIN 7 = V
EE
PIN 8 = GND
1
2
3
4
5
6
7
8
X4
X6
X
X7
X5 Enable
V
EE
GND
FUNCTION TABLE - MC74HC4052A
LOGIC DIAGRAM
MC74HC4052A
Double-Pole, 4-Position Plus Common Off
Control Inputs
Select
Enable
B
A
ON Channels
12
X0
L
L
L
L
H
L
L
L
H
L
Y0
Y1
Y2
Y3
X0
X1
X2
X3
14
X1
X2
X3
13
X SWITCH
Y SWITCH
X
Y
15
11
H
H
X
H
X
COMMON
OUTPUTS/INPUTS
ANALOG
INPUTS/OUTPUTS
NONE
1
5
Y0
Y1
Y2
Y3
A
X = Don't Care
3
2
4
Pinout: MC74HC4052A (Top View)
10
9
V
X2
15
X1
14
X
X0
12
X3
11
A
B
9
CHANNEL‐SELECT
INPUTS
CC
PIN 16 = V
CC
PIN 7 = V
B
16
13
10
EE
PIN 8 = GND
6
ENABLE
1
2
3
4
5
6
7
8
Y0
Y2
Y
Y3
Y1 Enable
V
EE
GND
http://onsemi.com
2
MC74HC4051A, MC74HC4052A, MC74HC4053A
FUNCTION TABLE - MC74HC4053A
Control Inputs
LOGIC DIAGRAM
MC74HC4053A
Triple Single-Pole, Double-Position Plus Common Off
Select
B
Enable
C
A
ON Channels
L
L
L
L
L
L
L
L
H
L
L
L
L
L
H
L
Z0
Y0
Y0
X0
12
Z0
Z0
Z0
Z1
Z1
Z1
Z1
X1
X0
X1
X0
X1
X0
X1
X0
X1
14
X
L
H
H
L
Y1
Y1
13
X SWITCH
L
H
L
H
H
H
H
X
Y0
Y0
2
1
L
H
L
Y0
Y1
15
4
COMMON
OUTPUTS/INPUTS
ANALOG
INPUTS/OUTPUTS
Y
Z
H
H
X
Y1
Y1
Y SWITCH
Z SWITCH
H
X
NONE
5
3
Z0
Z1
X = Don't Care
11
10
9
A
B
C
PIN 16 = V
CC
PIN 7 = V
PIN 8 = GND
CHANNEL‐SELECT
INPUTS
EE
Pinout: MC74HC4053A (Top View)
6
V
Y
X
X1
13
X0
12
A
B
C
9
CC
ENABLE
16
15
14
11
10
NOTE: This device allows independent control of each switch.
Channel-Select Input A controls the X-Switch, Input B controls
the Y-Switch and Input C controls the Z-Switch
1
2
3
4
5
6
7
8
Y1
Y0
Z1
Z
Z0 Enable
V
EE
GND
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
ꢁThisdevice contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high-impedance cir‐
V
CC
Positive DC Supply Voltage (Referenced to GND)
)
– 0.5 to + 7.0
– 0.5 to + 14.0
V
(Referenced to V
EE
V
EE
Negative DC Supply Voltage (Referenced to GND)
Analog Input Voltage
– 7.0 to + 5.0
V
V
V
IS
V
- 0.5 to
+ 0.5
EE
V
CC
cuit. For proper operation, V and
V
in
should be constrained to the
V
in
Digital Input Voltage (Referenced to GND)
DC Current, Into or Out of Any Pin
– 0.5 to V + 0.5
CC
V
out
range GND v (V or V ) v V
.
in
out
CC
I
25
mA
mW
ꢁUnusedinputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V ).
P
D
Power Dissipation in Still Air,
Plastic DIP†
EIAJ/SOIC Package†
TSSOP Package†
750
500
450
CC
Unused outputs must be left open.
T
Storage Temperature Range
– 65 to + 150
_C
_C
stg
T
Lead Temperature, 1 mm from Case for 10 Seconds
Plastic DIP, SOIC or TSSOP Package
L
260
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress
ratings only. Functional operation above the Recommended Operating Conditions is not implied.
Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
EIAJ/SOIC Package: – 7 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D).
TSSOP Package: - 6.1 mW/_C from 65_ to 125_C
http://onsemi.com
3
MC74HC4051A, MC74HC4052A, MC74HC4053A
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
V
CC
Positive DC Supply Voltage (Referenced to GND)
)
2.0
2.0
6.0
12.0
V
(Referenced to V
EE
V
EE
Negative DC Supply Voltage, Output (Referenced to
GND)
- 6.0
GND
V
V
Analog Input Voltage
V
V
V
V
V
IS
EE
CC
V
Digital Input Voltage (Referenced to GND)
Static or Dynamic Voltage Across Switch
Operating Temperature Range, All Package Types
GND
in
CC
V
IO
*
1.2
V
T
– 55
+ 125
_C
ns
A
t , t
r
Input Rise/Fall Time
ꢁ(Channel Select or Enable Inputs)
V
= 2.0 V
= 3.0 V
= 4.5 V
= 6.0 V
0
0
0
0
1000
600
500
400
f
CC
V
CC
V
CC
CC
V
*For voltage drops across switch greater than 1.2V (switch on), excessive V current may be
CC
drawn; i.e., the current out of the switch may contain both V and switch input components. The
CC
reliability of the device will be unaffected unless the Maximum Ratings are exceeded.
DC CHARACTERISTICS — Digital Section (Voltages Referenced to GND) V = GND, Except Where Noted
EE
Guaranteed Limit
-55 to 25°C ≤85°C ≤125°C
V
CC
V
Symbol
Parameter
Condition
= Per Spec
Unit
V
IH
Minimum High-Level Input Voltage,
Channel-Select or Enable Inputs
R
2.0
3.0
4.5
6.0
1.50
2.10
3.15
4.20
1.50
2.10
3.15
4.20
1.50
2.10
3.15
4.20
V
on
on
V
IL
Maximum Low-Level Input Voltage,
Channel-Select or Enable Inputs
R
= Per Spec
2.0
3.0
4.5
6.0
0.5
0.9
0.5
0.9
0.5
0.9
V
1.35
1.8
1.35
1.8
1.35
1.8
I
Maximum Input Leakage Current,
Channel-Select or Enable Inputs
V
V
= V or GND,
CC
= - 6.0 V
6.0
0.1
1.0
1.0
mA
mA
in
in
EE
I
Maximum Quiescent Supply
Current (per Package)
Channel Select, Enable and
CC
V
V
= V or GND;
CC
= 0 V
V
EE
V
EE
= GND
= - 6.0
6.0
6.0
1
4
10
40
20
80
IS
IO
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D).
http://onsemi.com
4
MC74HC4051A, MC74HC4052A, MC74HC4053A
DC CHARACTERISTICS — Analog Section
Guaranteed Limit
-55 to 25°C ≤85°C ≤125°C
Symbol
Parameter
Condition
= V or V ; V = V to
V
V
Unit
CC
EE
R
on
Maximum “ON” Resistance
V
V
4.5
4.5
6.0
0.0
- 4.5
- 6.0
190
120
100
240
150
125
280
170
140
W
in
IL
IH IS
CC
; I ≤ 2.0 mA
EE
S
(Figures 1, 2)
V
V
= V or V ; V = V or
IH IS
4.5
4.5
6.0
0.0
- 4.5
- 6.0
150
100
80
190
125
100
230
140
115
in
IL
CC
(Endpoints); I ≤ 2.0 mA
EE
S
(Figures 1, 2)
DR
Maximum Difference in “ON”
Resistance Between Any Two
Channels in the Same Package
V
V
I
= V or V ;
IH
4.5
4.5
6.0
0.0
- 4.5
- 6.0
30
12
10
35
15
12
40
18
14
W
on
in
IL
= 1/2 (V - V );
IS
CC
EE
≤ 2.0 mA
S
I
off
Maximum Off-Channel Leakage
Current, Any One Channel
V
V
= V or V
IL IH
= V - V
;
mA
in
;
6.0
- 6.0
0.1
0.5
1.0
IO
CC
EE
Switch Off (Figure 3)
Maximum Off-ChannelHC4051A
Leakage Current,
Common Channel
V
V
= V or V
IL IH
= V - V
;
6.0
6.0
6.0
- 6.0
- 6.0
- 6.0
0.2
0.1
0.1
2.0
1.0
1.0
4.0
2.0
2.0
in
HC4052A
;
IO
CC
EE
HC4053A Switch Off (Figure 4)
I
on
Maximum On-ChannelHC4051A
Leakage Current, HC4052A Switch-to-Switch =
Channel-to-Channel HC4053A - V ; (Figure 5)
V
= V or V
;
6.0
6.0
6.0
- 6.0
- 6.0
- 6.0
0.2
0.1
0.1
2.0
1.0
1.0
4.0
2.0
2.0
mA
in
IL
IH
V
CC
EE
AC CHARACTERISTICS (C = 50 pF, Input t = t = 6 ns)
L
r
f
Guaranteed Limit
-55 to 25°C ≤85°C ≤125°C
V
CC
V
Symbol
Parameter
Unit
t
t
t
t
,
Maximum Propagation Delay, Channel-Select to Analog Output
(Figure 9)
2.0
3.0
4.5
6.0
270
90
320
110
79
350
125
85
ns
PLH
t
PHL
59
45
65
75
,
Maximum Propagation Delay, Analog Input to Analog Output
(Figure 10)
2.0
3.0
4.5
6.0
40
25
12
10
60
30
15
13
70
32
18
15
ns
ns
ns
PLH
t
PHL
,
Maximum Propagation Delay, Enable to Analog Output
(Figure 11)
2.0
3.0
4.5
6.0
160
70
200
95
220
110
76
PLZ
t
PHZ
48
39
63
55
63
,
Maximum Propagation Delay, Enable to Analog Output
(Figure 11)
2.0
3.0
4.5
6.0
245
115
49
315
145
69
345
155
83
PZL
t
PZH
39
58
67
C
Maximum Input Capacitance, Channel-Select or Enable Inputs
10
35
10
35
10
35
pF
pF
in
C
I/O
Maximum Capacitance
(All Switches Off)
Analog I/O
Common O/I: HC4051A
HC4052A
HC4053A
130
80
130
80
130
80
50
50
50
Feed-through
1.0
1.0
1.0
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON
Semiconductor High-Speed CMOS Data Book (DL129/D)
Typical @ 25°C, V = 5.0 V, V = 0 V
CC
EE
45
80
45
C
PD
Power Dissipation Capacitance (Figure 13)*
HC4051A
HC4052A
HC4053A
pF
2
* Used to determine the no-load dynamic power consumption: P = C
D
ON Semiconductor High-Speed CMOS Data Book (DL129/D).
V
PD CC
f + I
V
CC CC
. For load considerations, see Chapter 2 of the
http://onsemi.com
5
MC74HC4051A, MC74HC4052A, MC74HC4053A
ADDITIONAL APPLICATION CHARACTERISTICS (GND = 0 V)
Limit*
25°C
`52
V
V
EE
CC
V
V
Symbol
Parameter
Condition
= 1MHz Sine Wave; Adjust f Voltage
to Obtain 0dBm at V ; Increase f
Unit
BW
Maximum On-Channel Bandwidth
or Minimum Frequency Response
(Figure 6)
f
in
`51
`53
MHz
in
OS
in
80
80
80
95
95
95
120
120
120
2.25
4.50
6.00
-2.25
-4.50
-6.00
Frequency Until dB Meter Reads -3dB;
R = 50W, C = 10pF
L
L
-
Off-Channel Feed-through
Isolation (Figure 7)
f
= Sine Wave; Adjust f Voltage to
in
2.25
4.50
-2.25
-4.50
-6.00
-50
-50
-50
dB
in
Obtain 0dBm at V
IS
f
in
= 10kHz, R = 600W, C = 50pF 6.00
L L
2.25
4.50
-2.25
-4.50
-6.00
-40
-40
-40
f
in
= 1.0MHz, R = 50W, C = 10pF 6.00
L L
-
Feedthrough Noise.
Channel-Select Input to Common
I/O (Figure 8)
V
≤ 1MHz Square Wave (t = t = 6ns);
2.25
4.50
-2.25
-4.50
-6.00
25
mV
in
r
f
Adjust R at Setup so that I = 0A;
PP
105
135
L
Enable = GND
S
R = 600W, C = 50pF 6.00
L L
2.25
4.50
-2.25
-4.50
-6.00
35
145
190
R = 10kW, C = 10pF 6.00
L
L
-
Crosstalk Between Any Two
Switches (Figure 12)
(Test does not apply to HC4051A)
f
= Sine Wave; Adjust f Voltage to
in
2.25
4.50
-2.25
-4.50
-6.00
-50
-50
-50
dB
in
Obtain 0dBm at V
IS
f
in
= 10kHz, R = 600W, C = 50pF 6.00
L
L
2.25
4.50
-2.25
-4.50
-6.00
-60
-60
-60
f
in
= 1.0MHz, R = 50W, C = 10pF 6.00
L L
THD
Total Harmonic Distortion
(Figure 14)
f
= 1kHz, R = 10kW, C = 50pF
L
%
in
THD = THD
L
- THD
measured
source
= 4.0V sine wave 2.25
V
V
-2.25
-4.50
-6.00
0.10
0.08
0.05
IS
PP
= 8.0V sine wave 4.50
IS
PP
= 11.0V sine wave 6.00
V
IS
PP
*Limits not tested. Determined by design and verified by qualification.
180
160
140
300
250
200
120
100
80
125°C
125°C
150
25°C
25°C
-ā55°C
100
60
-ā55°C
40
50
0
20
0
0
0.25 0.5
0.75
1.0
1.25
1.5 1.75
2.0 2.25
0
0.25 0.5 0.75 1.0 1.25 1.5 1.75 2.0 2.25 2.5 2.75 3.0
V , INPUT VOLTAGE (VOLTS), REFERENCED TO V
V , INPUT VOLTAGE (VOLTS), REFERENCED TO V
IS
EE
IS
EE
Figure 1a. Typical On Resistance, VCC - VEE = 2.0 V
Figure 1b. Typical On Resistance, VCC - VEE = 3.0 V
http://onsemi.com
6
MC74HC4051A, MC74HC4052A, MC74HC4053A
105
90
120
100
80
75
125°C
125°C
60
25°C
60
45
25°C
-ā55°C
40
20
0
30
-ā55°C
15
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
V , INPUT VOLTAGE (VOLTS), REFERENCED TO V
V , INPUT VOLTAGE (VOLTS), REFERENCED TO V
IS
EE
IS
EE
Figure 1c. Typical On Resistance, VCC - VEE = 4.5 V
Figure 1d. Typical On Resistance, VCC - VEE = 6.0 V
80
70
60
60
50
125°C
40
50
25°C
125°C
40
30
-ā55°C
25°C
30
20
-ā55°C
20
10
0
10
0
0
1
2
3
4
5
6
7
8
9
0
1
2
3
4
5
6
7
8
9
10 11 12
V , INPUT VOLTAGE (VOLTS), REFERENCED TO V
IS
V , INPUT VOLTAGE (VOLTS), REFERENCED TO V
IS
EE
EE
Figure 1e. Typical On Resistance, VCC - VEE = 9.0 V
Figure 1f. Typical On Resistance, VCC - VEE = 12.0 V
PLOTTER
PROGRAMMABLE
MINI COMPUTER
DC ANALYZER
POWER
SUPPLY
-
+
V
CC
DEVICE
UNDER TEST
ANALOG IN
COMMON OUT
V
EE
GND
Figure 2. On Resistance Test Set-Up
http://onsemi.com
7
MC74HC4051A, MC74HC4052A, MC74HC4053A
V
CC
V
CC
V
V
CC
CC
16
16
V
V
V
V
EE
EE
ANALOG I/O
OFF
OFF
OFF
OFF
A
CC
CC
COMMON O/I
NC
COMMON O/I
V
IH
V
IH
6
7
8
6
7
8
V
EE
V
EE
Figure 3. Maximum Off Channel Leakage Current,
Any One Channel, Test Set-Up
Figure 4. Maximum Off Channel Leakage Current,
Common Channel, Test Set-Up
V
CC
V
OS
V
V
CC
V
CC
16
16
0.1mF
A
dB
METER
f
in
ON
ON
N/C
R
L
C *
L
EE
CC
COMMON O/I
OFF
V
ANALOG I/O
V
IL
6
7
8
6
7
8
V
EE
V
EE
*Includes all probe and jig capacitance
Figure 5. Maximum On Channel Leakage Current,
Channel to Channel, Test Set-Up
Figure 6. Maximum On Channel Bandwidth,
Test Set-Up
V
CC
V
CC
V
IS
V
OS
16
16
0.1mF
dB
METER
R
L
f
in
OFF
ON/OFF
OFF/ON
COMMON O/I
TEST
POINT
ANALOG I/O
R
L
R
L
C *
L
R
L
C *
L
R
L
6
7
8
6
7
8
V
CC
V
≤ 1 MHz
f
11
in
t = t = 6 ns
r
V
EE
V
EE
V
CC
CHANNEL SELECT
*Includes all probe and jig capacitance
CHANNEL SELECT
*Includes all probe and jig capacitance
V
IL
or V
GND
IH
Figure 7. Off Channel Feedthrough Isolation,
Test Set-Up
Figure 8. Feedthrough Noise, Channel Select to
Common Out, Test Set-Up
http://onsemi.com
8
MC74HC4051A, MC74HC4052A, MC74HC4053A
V
CC
V
CC
16
V
CC
ON/OFF
OFF/ON
COMMON O/I
C *
CHANNEL
SELECT
TEST
POINT
50%
ANALOG I/O
GND
L
t
t
PHL
PLH
6
7
8
ANALOG
OUT
50%
CHANNEL SELECT
*Includes all probe and jig capacitance
Figure 9a. Propagation Delays, Channel Select
to Analog Out
Figure 9b. Propagation Delay, Test Set-Up Channel
Select to Analog Out
V
CC
16
COMMON O/I
C *
ANALOG I/O
TEST
POINT
V
CC
ON
ANALOG
IN
50%
L
GND
t
t
PHL
PLH
6
7
8
ANALOG
OUT
50%
*Includes all probe and jig capacitance
Figure 10a. Propagation Delays, Analog In
to Analog Out
Figure 10b. Propagation Delay, Test Set-Up
Analog In to Analog Out
t
t
POSITION 1 WHEN TESTING t
AND t
PZH
POSITION 2 WHEN TESTING t AND t
f
r
PHZ
1
2
PLZ
PZL
V
CC
90%
50%
10%
ENABLE
V
CC
GND
1kW
V
CC
16
t
t
PLZ
PZL
HIGH
IMPEDANCE
1
2
ANALOG I/O
ENABLE
TEST
POINT
ON/OFF
ANALOG
OUT
50%
C *
L
10%
V
OL
t
t
PHZ
PZH
6
7
8
V
OH
90%
ANALOG
OUT
50%
HIGH
IMPEDANCE
Figure 11a. Propagation Delays, Enable to
Analog Out
Figure 11b. Propagation Delay, Test Set-Up
Enable to Analog Out
http://onsemi.com
9
MC74HC4051A, MC74HC4052A, MC74HC4053A
V
CC
V
IS
A
V
CC
16
16
R
L
V
OS
ON/OFF
OFF/ON
COMMON O/I
f
in
ON
NC
ANALOG I/O
0.1mF
OFF
V
EE
R
L
R
L
C *
L
C *
L
V
CC
R
L
6
7
8
6
7
8
11
V
EE
CHANNEL SELECT
*Includes all probe and jig capacitance
Figure 12. Crosstalk Between Any Two
Switches, Test Set-Up
Figure 13. Power Dissipation Capacitance,
Test Set-Up
0
-ā10
-ā20
-ā30
-ā40
V
IS
FUNDAMENTAL FREQUENCY
V
CC
V
OS
16
0.1mF
TO
DISTORTION
METER
f
in
ON
R
L
C *
L
-ā50
-ā60
DEVICE
SOURCE
6
7
8
-ā70
-ā80
V
EE
-ā90
*Includes all probe and jig capacitance
-ꢁ100
1.0
2.0
3.125
FREQUENCY (kHz)
Figure 14a. Total Harmonic Distortion, Test Set-Up
Figure 14b. Plot, Harmonic Distortion
APPLICATIONS INFORMATION
The Channel Select and Enable control pins should be at
or GND logic levels. V being recognized as a logic
outputs to V or GND through a low value resistor helps
CC
V
CC
minimize crosstalk and feed-through noise that may be
picked up by an unused switch.
Although used here, balanced supplies are not a
requirement. The only constraints on the power supplies are
that:
CC
high and GND being recognized as a logic low. In this
example:
V
= +5V = logic high
GND = 0V = logic low
CC
V
- GND = 2 to 6 volts
CC
- GND = 0 to -6 volts
- V = 2 to 12 volts
The maximum analog voltage swings are determined by
the supply voltages V and V . The positive peak analog
V
EE
CC EE
voltage should not exceed V . Similarly, the negative peak
V
CC
EE
CC
analog voltage should not go below V . In this example,
and V ≤ GND
EE
EE
the difference between V and V is ten volts. Therefore,
When voltage transients above V and/or below V are
CC EE
anticipated on the analog channels, external Germanium or
CC
EE
using the configuration of Figure 15, a maximum analog
signal of ten volts peak-to-peak can be controlled. Unused
analog inputs/outputs may be left floating (i.e., not
connected). However, tying unused analog inputs and
Schottky diodes (D ) are recommended as shown in Figure
x
16. These diodes should be able to absorb the maximum
anticipated current surges during clipping.
http://onsemi.com
10
MC74HC4051A, MC74HC4052A, MC74HC4053A
V
CC
V
CC
+5V
V
CC
D
D
16
x
16
ON/OFF
x
+5V
-5V
+5V
-5V
ANALOG
SIGNAL
ANALOG
SIGNAL
ON
D
x
D
x
V
EE
V
EE
TO EXTERNAL CMOS
CIRCUITRY 0 to 5V
DIGITAL SIGNALS
6
7
8
11
10
9
7
8
-5V
V
EE
Figure 15. Application Example
Figure 16. External Germanium or
Schottky Clipping Diodes
+5V
+5V
16
16
+5V
+5V
+5V
+5V
ANALOG
SIGNAL
ANALOG
SIGNAL
ANALOG
SIGNAL
ANALOG
SIGNAL
ON/OFF
ON/OFF
V
EE
V
EE
V
EE
V
EE
+5V
*
R
R
R
+5V
6
7
8
11
10
9
6
7
8
11
10
9
LSTTL/NMOS
CIRCUITRY
LSTTL/NMOS
CIRCUITRY
V
EE
V
EE
* 2K ≤ R ≤ 10K
HCT
BUFFER
a. Using Pull-Up Resistors
b. Using HCT Interface
Figure 17. Interfacing LSTTL/NMOS to CMOS Inputs
11
13
X0
LEVEL
SHIFTER
A
14
X1
10
15
X2
LEVEL
SHIFTER
B
12
X3
9
1
LEVEL
SHIFTER
C
X4
5
X5
6
2
LEVEL
SHIFTER
ENABLE
X6
4
X7
3
X
Figure 18. Function Diagram, HC4051A
http://onsemi.com
11
MC74HC4051A, MC74HC4052A, MC74HC4053A
10
12
14
15
LEVEL
SHIFTER
A
B
X0
X1
X2
9
LEVEL
SHIFTER
11
13
1
X3
X
6
LEVEL
SHIFTER
ENABLE
Y0
5
2
4
3
Y1
Y2
Y3
Y
Figure 19. Function Diagram, HC4052A
11
10
9
13
LEVEL
SHIFTER
A
X1
12
14
1
X0
X
LEVEL
SHIFTER
B
Y1
2
15
3
Y0
Y
LEVEL
SHIFTER
C
Z1
5
4
Z0
Z
6
LEVEL
SHIFTER
ENABLE
Figure 20. Function Diagram, HC4053A
http://onsemi.com
12
MC74HC4051A, MC74HC4052A, MC74HC4053A
ORDERING INFORMATION
†
Device
MC74HC4051AN
Package
Shipping
PDIP-16
500 Units / Box
500 Units / Box
MC74HC4051ANG
PDIP-16
(Pb-Free)
MC74HC4051AD
SOIC-16
48 Units / Rail
48 Units / Rail
MC74HC4051ADG
SOIC-16
(Pb-Free)
MC74HC4051ADR2
MC74HC4051ADR2G
SOIC-16
2500 Units / Tape & Reel
2500 Units / Tape & Reel
SOIC-16
(Pb-Free)
MC74HC4051ADT
TSSOP-16*
TSSOP-16*
TSSOP-16*
TSSOP-16*
SOIC-16 WIDE
96 Units / Rail
96 Units / Rail
MC74HC4051ADTG
MC74HC4051ADTR2
MC74HC4051ADTR2G
MC74HC4051ADW
MC74HC4051ADWG
2500 Units / Tape & Reel
2500 Units / Tape & Reel
48 Units / Rail
SOIC-16 WIDE
(Pb-Free)
48 Units / Rail
MC74HC4051ADWR2
MC74HC4051ADWR2G
SOIC-16 WIDE
1000 Units / Tape & Reel
1000 Units / Tape & Reel
SOIC-16 WIDE
(Pb-Free)
MC74HC4051AFEL
MC74HC4051AFELG
SOEIAJ-16
2000 Units / Tape & Reel
2000 Units / Tape & Reel
SOEIAJ-16
(Pb-Free)
MC74HC4052AN
PDIP-16
500 Units / Box
500 Units / Box
MC74HC4052ANG
PDIP-16
(Pb-Free)
MC74HC4052AD
SOIC-16
48 Units / Rail
48 Units / Rail
MC74HC4052ADG
SOIC-16
(Pb-Free)
MC74HC4052ADR2
MC74HC4052ADR2G
SOIC-16
2500 Units / Tape & Reel
2500 Units / Tape & Reel
SOIC-16
(Pb-Free)
MC74HC4052ADT
TSSOP-16*
TSSOP-16*
TSSOP-16*
TSSOP-16*
SOIC-16 WIDE
96 Units / Rail
96 Units / Rail
MC74HC4052ADTG
MC74HC4052ADTR2
MC74HC4052ADTR2G
MC74HC4052ADW
MC74HC4052ADWG
2500 Units / Tape & Reel
2500 Units / Tape & Reel
48 Units / Rail
SOIC-16 WIDE
(Pb-Free)
48 Units / Rail
MC74HC4052ADWR2
MC74HC4052ADWR2G
SOIC-16 WIDE
1000 Units / Tape & Reel
1000 Units / Tape & Reel
SOIC-16 WIDE
(Pb-Free)
MC74HC4052AFG
SOEIAJ-16
(Pb-Free)
50 Units / Rail
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb-Free.
http://onsemi.com
13
MC74HC4051A, MC74HC4052A, MC74HC4053A
ORDERING INFORMATION
†
Device
MC74HC4053AN
Package
Shipping
PDIP-16
500 Units / Box
500 Units / Box
MC74HC4053ANG
PDIP-16
(Pb-Free)
MC74HC4053AD
SOIC-16
48 Units / Rail
48 Units / Rail
MC74HC4053ADG
SOIC-16
(Pb-Free)
MC74HC4053ADR2
MC74HC4053ADR2G
SOIC-16
2500 Units / Tape & Reel
2500 Units / Tape & Reel
SOIC-16
(Pb-Free)
MC74HC4053ADT
TSSOP-16*
TSSOP-16*
TSSOP-16*
TSSOP-16*
SOIC-16 WIDE
96 Units / Rail
96 Units / Rail
MC74HC4053ADTG
MC74HC4053ADTR2
MC74HC4053ADTR2G
MC74HC4053ADW
MC74HC4053ADWG
2500 Units / Tape & Reel
2500 Units / Tape & Reel
48 Units / Rail
SOIC-16 WIDE
(Pb-Free)
48 Units / Rail
MC74HC4053ADWR2
MC74HC4053ADWR2G
SOIC-16 WIDE
1000 Units / Tape & Reel
1000 Units / Tape & Reel
SOIC-16 WIDE
(Pb-Free)
MC74HC4053AF
SOEIAJ-16
50 Units / Rail
50 Units / Rail
MC74HC4053AFG
SOEIAJ-16
(Pb-Free)
MC74HC4053AFEL
MC74HC4053AFELG
SOEIAJ-16
2000 Units / Tape & Reel
2000 Units / Tape & Reel
SOEIAJ-16
(Pb-Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb-Free.
http://onsemi.com
14
MC74HC4051A, MC74HC4052A, MC74HC4053A
PACKAGE DIMENSIONS
PDIP-16
N SUFFIX
CASE 648-08
ISSUE T
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
-A-
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS
WHEN FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE
MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
16
1
9
8
B
S
INCHES
DIM MIN MAX
0.740 0.770 18.80 19.55
MILLIMETERS
F
C
L
MIN MAX
A
B
C
D
F
0.250 0.270
0.145 0.175
0.015 0.021
6.35
3.69
0.39
1.02
6.85
4.44
0.53
1.77
SEATING
PLANE
-T-
0.040
0.70
G
H
J
K
L
0.100 BSC
2.54 BSC
1.27 BSC
K
M
H
J
0.050 BSC
0.008 0.015
0.110 0.130
0.295 0.305
G
0.21
0.38
3.30
7.74
10
D 16 PL
2.80
7.50
0
M
M
0.25 (0.010)
T A
M
S
0
10
0.020 0.040
_
_
_
_
0.51
1.01
SOIC-16 WIDE
DW SUFFIX
CASE 751G-03
ISSUE C
NOTES:
A
D
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
q
3. DIMENSIONS D AND E DO NOT INLCUDE
MOLD PROTRUSION.
16
9
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 TOTAL IN
EXCESS OF THE B DIMENSION AT MAXIMUM
MATERIAL CONDITION.
MILLIMETERS
DIM MIN
2.35
A1 0.10
MAX
2.65
0.25
0.49
0.32
1
8
A
B
C
D
E
e
H
h
L
q
0.35
0.23
10.15 10.45
7.40 7.60
1.27 BSC
10.05 10.55
B
16X B
M
S
S
B
0.25
T
A
0.25
0.50
0
0.75
0.90
7
_
_
SEATING
PLANE
14X
e
C
T
http://onsemi.com
15
MC74HC4051A, MC74HC4052A, MC74HC4053A
PACKAGE DIMENSIONS
SOIC-16
D SUFFIX
CASE 751B-05
ISSUE K
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
-A-
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL CONDITION.
16
9
8
-B-
P 8 PL
M
S
B
0.25 (0.010)
1
MILLIMETERS
INCHES
DIM MIN
MAX
10.00
4.00
1.75
0.49
1.25
MIN
MAX
0.393
0.157
0.068
0.019
0.049
A
B
C
D
F
9.80
3.80
1.35
0.35
0.40
0.386
0.150
0.054
0.014
0.016
G
F
R X 45
K
_
G
J
1.27 BSC
0.050 BSC
0.19
0.10
0
0.25
0.25
7
0.008
0.004
0
0.009
0.009
7
K
M
P
R
C
_
_
_
_
-T-
SEATING
PLANE
5.80
0.25
6.20
0.50
0.229
0.010
0.244
0.019
J
M
D
16 PL
M
S
S
A
0.25 (0.010)
T
B
SOLDERING FOOTPRINT*
8X
6.40
16X
1.12
1
16
16X
0.58
1.27
PITCH
8
9
DIMENSIONS: MILLIMETERS
*For additional information on our Pb-Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
16
MC74HC4051A, MC74HC4052A, MC74HC4053A
PACKAGE DIMENSIONS
TSSOP-16
DT SUFFIX
CASE 948F-01
ISSUE B
16X K REF
NOTES:
ꢁăD1.IMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
M
S
S
0.10 (0.004)
T
U
V
S
U
0.15 (0.006) T
ꢁăC2.ONTROLLING DIMENSION: MILLIMETER.
ꢁăD3.IMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
ꢁăD4.IMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
ꢁăD5.IMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
K
K1
16
9
2X L/2
J1
SECTION N-N
B
-U-
L
J
PIN 1
IDENT.
N
8
0.25 (0.010)
1
ꢁăT6.ERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
M
ꢁăD7.IMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE -W-.
S
0.15 (0.006) T
U
A
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
N
-V-
A
B
C
D
F
4.90
4.30
---
0.05
0.50
5.10 0.193 0.200
4.50 0.169 0.177
F
1.20
--- 0.047
DETAIL E
0.15 0.002 0.006
0.75 0.020 0.030
G
H
J
J1
K
K1
L
0.65 BSC
0.026 BSC
0.28 0.007 0.011
-W-
0.18
0.09
0.09
0.19
0.19
C
0.20 0.004 0.008
0.16 0.004 0.006
0.30 0.007 0.012
0.25 0.007 0.010
0.10 (0.004)
H
DETAIL E
SEATING
PLANE
-T-
6.40 BSC
8
0.252 BSC
0
D
G
M
0
8
_
_
_
_
SOLDERING FOOTPRINT*
7.06
1
0.65
PITCH
16X
0.36
16X
1.26
DIMENSIONS: MILLIMETERS
*For additional information on our Pb-Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
17
MC74HC4051A, MC74HC4052A, MC74HC4053A
PACKAGE DIMENSIONS
SOEIAJ-16
F SUFFIX
CASE 966-01
ISSUE A
NOTES:
ąă1D.IMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
ąă2C.ONTROLLING DIMENSION: MILLIMETER.
ąă3D.IMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
L
16
9
E
Q
1
H
E
E
M
_
ąă4T.ERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
ąă5T.HE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
1
8
L
DETAIL P
Z
D
VIEW P
e
MILLIMETERS
INCHES
MIN
A
DIM MIN
MAX
2.05
0.20
0.50
0.20
10.50
5.45
MAX
0.081
0.008
0.020
0.011
0.413
0.215
c
A
---
0.05
0.35
0.10
9.90
5.10
---
0.002
0.014
0.007
0.390
0.201
A
1
b
c
D
E
A
1
b
0.13 (0.005)
e
1.27 BSC
0.050 BSC
0.10 (0.004)
M
H
7.40
0.50
1.10
8.20
0.85
1.50
0.291
0.020
0.043
0.323
0.033
0.059
E
L
L
E
M
Q
0
10
0
10
_
0.035
0.031
_
_
_
0.70
---
0.90
0.78
0.028
---
1
Z
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
ꢂLiterature Distribution Center for ON Semiconductor
ꢂP.O. Box 5163, Denver, Colorado 80217 USA
N. American Technical Support: 800-282-9855 Toll Free
ꢂUSA/Canada
Europe, Middle East and Africa Technical Support:
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
ꢂPhone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada ꢂPhone: 421 33 790 2910
ꢂFax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada
ꢂEmail: orderlit@onsemi.com
For additional information, please contact your local
Sales Representative
Japan Customer Focus Center
ꢂPhone: 81-3-5773-3850
MC74HC4051A/D
相关型号：
©2020 ICPDF网 联系我们和版权申明