MC74VHC1GT50DF2G [ROCHESTER]
IC,LOGIC GATE,BUFFER,AHC/VHC-CMOS,TSSOP,6PIN,PLASTIC;
| 型号： | MC74VHC1GT50DF2G |
| 厂家： | 
Rochester Electronics |
| 描述： | IC,LOGIC GATE,BUFFER,AHC/VHC-CMOS,TSSOP,6PIN,PLASTIC |
| 文件： | 总7页 (文件大小：755K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC74VHC1GT50
Noninverting Buffer /
CMOS Logic Level Shifter
TTL−Compatible Inputs
The MC74VHC1GT50 is a single gate noninverting buffer
fabricated with silicon gate CMOS technology. It achieves high speed
operation similar to equivalent Bipolar Schottky TTL while
maintaining CMOS low power dissipation.
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MARKING
DIAGRAMS
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output.
The device input is compatible with TTL−type input thresholds and
the output has a full 5.0 V CMOS level output swing. The input
protection circuitry on this device allows overvoltage tolerance on the
input, allowing the device to be used as a logic−level translator from
3.0 V CMOS logic to 5.0 V CMOS Logic or from 1.8 V CMOS logic to
3.0 V CMOS Logic while operating at the high−voltage power supply.
The MC74VHC1GT50 input structure provides protection when
voltages up to 7.0 V are applied, regardless of the supply voltage. This
allows the MC74VHC1GT50 to be used to interface high voltage to
low voltage circuits. The output structures also provide protection
5
5
1
VL M G
SC−88A/SOT−353/SC−70
DF SUFFIX
G
1
5
CASE 419A
5
VL AYW G
G
1
TSOP−5/SOT−23/SC−59
DT SUFFIX
1
when V = 0 V. These input and output structures help prevent
CC
device destruction caused by supply voltage − input/output voltage
mismatch, battery backup, hot insertion, etc.
CASE 483
Features
VL
M
A
= Device Code
= Date Code*
= Assembly Location
= Year
= Work Week
= Pb−Free Package
• Designed for 1.65 V to 5.5 V Operation
CC
• High Speed: t = 3.5 ns (Typ) at V = 5.0 V
PD
CC
Y
• Low Power Dissipation: I = 1 mA (Max) at T = 25°C
CC
A
W
G
• TTL−Compatible Inputs: V = 0.8 V; V = 2.0 V, V = 5.0 V
• CMOS−Compatible Outputs: V > 0.8 V ; V < 0.1 V @Load
• Power Down Protection Provided on Inputs and Outputs
• Balanced Propagation Delays
IL
IH
CC
(Note: Microdot may be in either location)
OH
CC
OL
CC
*Date Code orientation and/or position may
vary depending upon manufacturing location.
• Pin and Function Compatible with Other Standard Logic Families
• Chip Complexity: FETs = 104; Equivalent Gates = 26
• Pb−Free Packages are Available
PIN ASSIGNMENT
1
NC
IN A
2
3
4
5
GND
OUT Y
NC
5
V
CC
1
2
3
V
CC
IN A
FUNCTION TABLE
A Input
Y Output
GND
4
OUT Y
L
L
H
H
Figure 1. Pinout (Top View)
1
IN A
OUT Y
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
Figure 2. Logic Symbol
©
Semiconductor Components Industries, LLC, 2005
1
Publication Order Number:
July, 2005 − Rev. 12
MC74VHC1GT50/D
MC74VHC1GT50
MAXIMUM RATINGS
Symbol
Characteristics
Value
Unit
V
V
DC Supply Voltage
DC Input Voltage
DC Output Voltage
−0.5 to +7.0
−0.5 to +7.0
−0.5 to 7.0
CC
V
V
IN
V
V
= 0
CC
V
OUT
High or Low State
−0.5 to V + 0.5
CC
I
Input Diode Current
−20
+20
mA
mA
mA
mA
mW
°C/W
°C
IK
I
Output Diode Current
DC Output Current, per Pin
V
< GND; V
> V
OK
OUT
OUT CC
I
+25
OUT
I
DC Supply Current, V and GND
+50
CC
CC
P
Power dissipation in still air
Thermal resistance
SC−88A, TSOP−5
SC−88A, TSOP−5
200
D
q
333
JA
T
Lead temperature, 1 mm from case for 10 s
Junction temperature under bias
Storage temperature
260
L
J
T
+150
−65 to +150
°C
T
stg
°C
V
ESD Withstand Voltage
Human Body Model (Note 1)
Machine Model (Note 2)
Charged Device Model (Note 3)
> 2000
> 200
N/A
V
ESD
I
Latchup Performance
Above V and Below GND at 125°C (Note 4)
500
mA
Latchup
CC
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
1. Tested to EIA/JESD22−A114−A
2. Tested to EIA/JESD22−A115−A
3. Tested to JESD22−C101−A
4. Tested to EIA/JESD78
RECOMMENDED OPERATING CONDITIONS
Symbol
Characteristics
Min
1.65
0.0
Max
5.5
5.5
5.5
Unit
V
V
DC Supply Voltage
DC Input Voltage
DC Output Voltage
CC
V
V
IN
V
V
= 0
CC
0.0
0.0
V
OUT
V
High or Low State
CC
T
Operating Temperature Range
Input Rise and Fall Time
−55
+125
°C
A
t , t
r
V
V
= 3.3 V 0.3 V
= 5.0 V 0.5 V
0
0
100
20
ns/V
f
CC
CC
Device Junction Temperature versus
Time to 0.1% Bond Failures
Junction
FAILURE RATE OF PLASTIC = CERAMIC
UNTIL INTERMETALLICS OCCUR
Temperature °C
Time, Hours
Time, Years
80
1,032,200
419,300
178,700
79,600
37,000
17,800
8,900
117.8
47.9
20.4
9.4
90
100
110
120
130
140
1
4.2
1
10
100
1000
2.0
TIME, YEARS
1.0
Figure 3. Failure Rate vs. Time Junction Temperature
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2
MC74VHC1GT50
DC ELECTRICAL CHARACTERISTICS
Symbol Parameter Test Conditions
V
T
= 25°C
T
≤ 85°C
−55 ≤ T ≤ 125°C
A
CC
A
A
(V)
Min
Typ
Max
Min
0.50 V
0.45 V
Max
Min
0.50 V
0.45 V
Max
Unit
Minimum
1.65 to 2.29 0.50 V
V
V
CC
CC
CC
CC
CC
IH
High−Level
Input Voltage
2.3 to 2.99
0.45 V
CC
3.0
4.5
5.5
1.4
2.0
2.0
1.4
2.0
2.0
1.4
2.0
2.0
Maximum
Low−Level
Input Voltage
1.65 to 2.29
2.3 to 2.99
0.10 V
0.15 V
0.10 V
0.10 V
CC
V
V
V
CC
CC
CC
IL
0.15 V
0.15 V
CC
CC
3.0
4.5
5.5
0.53
0.8
0.8
0.53
0.8
0.8
0.53
0.8
0.8
Minimum
High−Level
Output
V
V
I
= V
1.65 to 2.99
V
− 0.1
V
− 0.1
V
− 0.1
CC
OH
IN
IH
CC
CC
= −50 mA
3.0
4.5
2.9
4.4
3.0
4.5
2.9
4.4
2.9
4.4
OH
Voltage
V
I
I
= V
= −4 mA
= −8 mA
V
V
IN
OH
OH
IH
3.0
4.5
2.58
3.94
2.48
3.80
2.34
3.66
Maximum
Low−Level
Output
V
V
I
= V
IL
1.65 to 2.99
0.0
0.0
0.1
0.1
0.1
OL
IN
= 50 mA
3.0
4.5
0.1
0.1
0.1
0.1
0.1
0.1
OL
Voltage
V
I
I
= V
= 4 mA
= 8 mA
V
IN
OL
OL
IL
3.0
4.5
0.36
0.36
0.44
0.44
0.52
0.52
Maximum
Input
V
IN
= 5.5 V or GND
0 to
5.5
$0.1
$1.0
$1.0
mA
I
IN
Leakage
Current
Maximum
Quiescent
Supply
V
= V or GND
CC
5.5
1.0
20
40
mA
I
IN
CC
Current
Quiescent
Supply
Current
Input: V = 3.4 V
5.5
0.0
1.35
0.5
1.50
5.0
1.65
10
mA
I
I
IN
CCT
Output
Leakage
Current
V
= 5.5 V
mA
OUT
OPD
AC ELECTRICAL CHARACTERISTICS C
= 50 pF, Input t = t = 3.0 ns
r f
load
−55 ≤ T
≤
A
125°C
T
A
= 25°C
T
A
≤ 85°C
Min
Typ
Max
Min
Max
Min
Max
Symbol
Parameter
Test Conditions
= 1.8 0.15 VC = 15 pF
Unit
ns
t
t
,
Maximum Propagation
V
V
16.6
18.0
22.0
PLH
PHL
CC
CC
L
= 2.5 0.2 V C = 15 pF
13.3
19.5
14.5
22.0
17.5
25.5
ns
L
Delay, Input A to Y
C = 50 pF
L
V
V
= 3.3 0.3 V C = 15 pF
4.5
6.3
10.0
13.5
11.0
15.0
13.0
17.5
ns
CC
CC
L
C = 50 pF
L
= 5.0 0.5 V C = 15 pF
3.5
4.3
6.7
7.7
7.5
8.5
8.5
9.5
L
C = 50 pF
L
C
Maximum Input
Capacitance
5
10
10
10
pF
pF
IN
Typical @ 25°C, V = 5.0 V
CC
12
C
PD
Power Dissipation Capacitance (Note 5)
5. C is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
PD
Average operating current can be obtained by the equation: I
power consumption; P = C ꢀ V
) = C ꢀ V ꢀ f + I . C is used to determine the no−load dynamic
CC(OPR
PD CC in CC PD
2
ꢀ f + I ꢀ V
.
D
PD
CC
in
CC
CC
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3
MC74VHC1GT50
TEST POINT
OUTPUT
V
CC
A
Y
50%
DEVICE
UNDER
TEST
GND
t
t
C *
L
PLH
PHL
V
V
OH
OL
50% V
CC
*Includes all probe and jig capacitance
Figure 4. Switching Waveforms
Figure 5. Test Circuit
DEVICE ORDERING INFORMATION
†
Device Order Number
Package Type
Tape and Reel Size
MC74VHC1GT50DFT1
SC−88A / SOT−353 / SC−70
178 mm (7”)
3000 Unit
M74VHC1GT50DFT1G
MC74VHC1GT50DFT2
M74VHC1GT50DFT2G
MC74VHC1GT50DTT1
M74VHC1GT50DTT1G
SC−88A / SOT−353 / SC−70
(Pb−Free)
178 mm (7”)
3000 Unit
SC−88A / SOT−353 / SC−70
178 mm (7”)
3000 Unit
SC−88A / SOT−353 / SC−70
(Pb−Free)
178 mm (7”)
3000 Unit
TSOP−5 / SOT−23 / SC−59
178 mm (7”)
3000 Unit
TSOP−5 / SOT−23 / SC−59
(Pb−Free)
178 mm (7”)
3000 Unit
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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4
MC74VHC1GT50
PACKAGE DIMENSIONS
SC−88A / SOT−353 / SC70
CASE 419A−02
ISSUE H
NOTES:
A
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. 419A−01 OBSOLETE. NEW STANDARD
419A−02.
G
4. DIMENSIONS A AND B DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS, OR GATE
BURRS.
5
4
3
−B−
S
INCHES
DIM MIN MAX
MILLIMETERS
MIN
1.80
1.15
0.80
0.10
MAX
2.20
1.35
1.10
0.30
1
2
A
B
C
D
G
H
J
0.071
0.045
0.031
0.004
0.087
0.053
0.043
0.012
0.026 BSC
0.65 BSC
M
M
B
D 5 PL
0.2 (0.008)
−−−
0.004
0.004
0.004
0.010
0.012
−−−
0.10
0.10
0.10
0.25
0.30
N
K
N
S
0.008 REF
0.20 REF
0.079
0.087
2.00
2.20
J
C
K
H
SOLDERING FOOTPRINT*
0.50
0.0197
0.65
0.025
0.65
0.025
0.40
0.0157
mm
inches
ǒ
Ǔ
1.9
0.0748
SCALE 20:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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5
MC74VHC1GT50
PACKAGE DIMENSIONS
TSOP−5 / SOT23−5 / SC59−5
DT SUFFIX
CASE 483−02
ISSUE D
NOTES:
D
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. MAXIMUM LEAD THICKNESS INCLUDES
LEAD FINISH THICKNESS. MINIMUM LEAD
THICKNESS IS THE MINIMUM THICKNESS
OF BASE MATERIAL.
4. A AND B DIMENSIONS DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS, OR GATE
BURRS.
5
4
3
B
C
S
1
2
L
G
A
MILLIMETERS
INCHES
MIN MAX
0.1142 0.1220
DIM
A
B
C
D
G
H
J
K
L
MIN
2.90
1.30
0.90
0.25
0.85
0.013
0.10
0.20
1.25
0
MAX
3.10
J
1.70 0.0512 0.0669
1.10 0.0354 0.0433
0.50 0.0098 0.0197
1.05 0.0335 0.0413
0.100 0.0005 0.0040
0.26 0.0040 0.0102
0.60 0.0079 0.0236
1.55 0.0493 0.0610
0.05 (0.002)
H
M
K
M
S
10
0
10
_
_
_
_
2.50
3.00 0.0985 0.1181
SOLDERING FOOTPRINT*
1.9
0.074
0.95
0.037
2.4
0.094
1.0
0.039
0.7
0.028
mm
inches
ǒ
Ǔ
SCALE 10:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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MC74VHC1GT50/D
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