MC74VHCT14AD [ROCHESTER]
AHCT/VHCT SERIES, HEX 1-INPUT INVERT GATE, PDSO14, SOIC-14;
| 型号： | MC74VHCT14AD |
| 厂家： | 
Rochester Electronics |
| 描述： | AHCT/VHCT SERIES, HEX 1-INPUT INVERT GATE, PDSO14, SOIC-14 栅 输入元件 光电二极管 逻辑集成电路 触发器 |
| 文件： | 总5页 (文件大小：777K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC74VHCT14A
Hex Schmitt Inverter
The MC74VHCT14A is an advanced high speed CMOS Schmitt
inverter fabricated with silicon gate CMOS technology. It achieves
high speed operation similar to equivalent Bipolar Schottky TTL
while maintaining CMOS low power dissipation.
Pin configuration and function are the same as the
MC74VHCT04A, but the inputs have hysteresis and, with its Schmitt
trigger function, the VHCT14A can be used as a line receiver which
will receive slow input signals.
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The VHCT inputs are compatible with TTL levels. This device can
be used as a level converter for interfacing 3.3V to 5.0V, because it has
full 5V CMOS level output swings.
The VHCT14A input structures provide protection when voltages
between 0V and 5.5V are applied, regardless of the supply voltage.
14–LEAD SOIC
D SUFFIX
CASE 751A
14–LEAD TSSOP
DT SUFFIX
CASE 948G
The output structures also provide protection when V
= 0V. These
CC
input and output structures help prevent device destruction caused by
supply voltage – input/output voltage mismatch, battery backup, hot
insertion, etc.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output. The
inputs tolerate voltages up to 7V, allowing the interface of 5V systems
to 3V systems.
14–LEAD SOIC EIAJ
M SUFFIX
CASE 965
PIN CONNECTIONS
• High Speed: t
= 5.5ns (Typ) at V
= 5V
PD
• Low Power Dissipation: I
CC
= 2µA (Max) at T = 25°C
V
A6
13
Y6
12
A5
11
Y5
10
A4
9
Y4
8
CC
CC
A
14
• TTL–Compatible Inputs: V = 0.8V; V = 2.0V
IL IH
• Power Down Protection Provided on Inputs
• Balanced Propagation Delays
• Designed for 2V to 5.5V Operating Range
• Low Noise: V
OLP
= 0.8V (Max)
• Pin and Function Compatible with Other Standard Logic Families
• Chip Complexity: 60 FETs or 15 Equivalent Gates
1
2
3
4
5
6
7
A1
Y1
A2
Y2
A3
Y3 GND
1
3
5
2
4
6
Pinout: 14–Lead Packages (Top View)
A1
A2
A3
Y1
Y2
Y3
ORDERING INFORMATION
Device
Package
SOIC
Shipping
MC74VHCT14AD
MC74VHCT14ADT
MC74VHCT14AM
55 Units/Rail
96 Units/Rail
50 Units/Rail
Y = A
TSSOP
9
8
10
12
A4
A5
A6
Y4
Y5
Y6
SOIC EIAJ
11
13
FUNCTION TABLE
Inputs
A
Outputs
Y
L
H
L
H
Figure 1. Logic Diagram
Semiconductor Components Industries, LLC, 2001
55
Publication Order Number:
June, 2001– Rev. 2
MC74VHCT14A/D
MC74VHCT14A
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
V
V
V
V
DC Supply Voltage
DC Input Voltage
DC Output Voltage
*0.5 to )7.0
*0.5 to )7.0
CC
V
IN
Output in HIGH or LOW State (Note 1.)
*0.5 to V
+0.5 V
V
OUT
OUT
CC
V
CC
= 0 V
*0.5 to 7.0
V
I
I
I
I
I
DC Input Diode Current
*20
$20
mA
mA
mA
mA
mA
_C
_C
_C
_C/W
IK
DC Output Diode Current
OK
O
DC Output Source/Sink Current
DC Supply Current per Supply Pin
DC Ground Current per Ground Pin
Storage Temperature Range
$25
$50
CC
GND
$50
T
T
T
q
*65 to )150
260
STG
Lead Temperature, 1 mm from Case for 10 Seconds
Junction Temperature under Bias
Thermal Resistance
L
J
)150
JA
SOIC
TSSOP
125
170
P
Power Dissipation in Still Air
ESD Withstand Voltage
mW
V
D
SOIC
TSSOP
500
450
V
ESD
Human Body Model (Note 2.)
Machine Model (Note 3.)
Charged Device Model (Note 4.)
> 2000
> 200
2000
I
Latch–Up Performance
Above V
and Below GND at 85_C (Note 5.)
$300
mA
Latch–Up
CC
Maximum Ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those
indicated may adversely affect device reliability. Functional operation under absolute maximum–rated conditions is not implied. Functional
operation should be restricted to the Recommended Operating Conditions.
1. I absolute maximum rating must be observed.
O
2. Tested to EIA/JESD22–A114–A.
3. Tested to EIA/JESD22–A115–A.
4. Tested to JESD22–C101–A.
5. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
4.5
0
Max
5.5
Unit
V
V
V
V
V
T
Supply Voltage
CC
Input Voltage
5.5
V
I
Output Voltage (Note 1.)
0
V
CC
V
O
O
V
CC
= 0 V
0
5.5
V
Operating Free–Air Temperature
*55
)125
_C
A
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56
MC74VHCT14A
DC ELECTRICAL CHARACTERISTICS
T
A
= 25°C
T
≤ 85°C
T ≤ 125°C
A
A
V
CC
V
Min
Typ
Max
Min
Max
Min
Max
Symbol
Parameter
Test Conditions
Unit
V
T+
Positive Threshold Voltage
4.5
5.5
1.9
2.1
1.9
2.1
1.9
2.1
V
V
Negative Threshold Voltage
Hysteresis Voltage
4.5
5.5
0.5
0.6
0.5
0.6
0.5
0.6
V
V
V
T–
V
4.5
5.5
0.40
0.40
1.40
1.50
0.40
0.40
1.40
1.50
0.40
0.40
1.40
1.50
H
V
OH
Minimum High–Level
Output Voltage
V
= V or V
IH
4.5
4.4
4.5
0.0
4.4
4.4
IN
IL
I
= – 50µA
OH
I
= –50µA
OH
I
= – 8mA
5.5
4.5
3.94
3.80
3.66
OH
V
OL
Maximum Low–Level
Output Voltage
V
= V or V
IH
0.1
0.1
0.1
V
IN
IL
I
= 50µA
OL
I
= 8mA
5.5
0.36
0.44
0.52
OL
I
Maximum Input Leakage
Current
V
= 5.5V or
0 to 5.5
± 0.1
± 1.0
± 1.0
µA
µA
IN
IN
GND
= V or GND
CC
I
Maximum Quiescent
Supply Current
V
IN
5.5
2.0
20
40
CC
I
Quiescent Supply Current
Output Leakage Current
Input: V = 3.4V
IN
5.5
0.0
1.35
0.5
1.50
5.0
1.65
10
mA
CCT
I
V
OUT
= 5.5V
µA
OFF
AC ELECTRICAL CHARACTERISTICS (Input t = t = 3.0ns)
r
f
T
A
= 25°C
T
A
≤ 85°C
T ≤ 125°C
A
Min
Typ
Max
Min
Max
Min
Max
Symbol
Parameter
Test Conditions
= 5.0 ± 0.5 VC = 15pF
Unit
t
t
,
Maximum Propagation
Delay, A to Y
V
CC
5.5
7.0
7.6
9.6
1.0
1.0
9.0
11.0
1.0
1.0
11.5
13.5
ns
PLH
L
C
= 50pF
L
PHL
C
Maximum Input
Capacitance
2
10
10
10
pF
IN
Typical @ 25°C, V
= 5.0 V
CC
11
C
Power Dissipation Capacitance (Note 6.)
pF
PD
6. C
is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
= C ꢀ V ꢀ f + I /6 (per buffer). C is used to determine the
PD
Average operating current can be obtained by the equation: I
no–load dynamic power consumption; P = C
PD
CC(OPR)
PD CC in CC PD
2
ꢀ V
CC
ꢀ f + I
in CC
ꢀ V .
CC
D
NOISE CHARACTERISTICS (Input t = t = 3.0ns, C = 50pF, V
= 5.0 V)
r
f
L
CC
T
A
= 25°C
Typ
Max
1.0
Symbol
Characteristic
Unit
V
V
OLP
Quiet Output Maximum Dynamic V
0.8
OL
V
Quiet Output Minimum Dynamic V
– 0.8
– 1.0
2.0
V
OLV
OL
V
Minimum High Level Dynamic Input Voltage
Maximum Low Level Dynamic Input Voltage
V
IHD
V
0.8
V
ILD
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57
MC74VHCT14A
TEST POINT
OUTPUT
3.0V
GND
1.5V
A
Y
DEVICE
UNDER
TEST
t
t
PHL
PLH
C *
L
V
OH
1.5V
V
OL
*Includes all probe and jig capacitance
Figure 2. Switching Waveforms
Figure 3. Test Circuit
(a) A Schmitt-Trigger Squares Up Inputs With Slow Rise and Fall Times
(b) A Schmitt-Trigger Offers Maximum Noise Immunity
V
CC
V
CC
V
H
V
H
V
V
V
T+
T+
V
in
V
in
V
T-
T-
GND
GND
V
OH
V
OH
V
out
V
out
V
OL
V
OL
Figure 4. Typical Schmitt–Trigger Applications
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58
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