MC9S12H128VPVE [ROCHESTER]
16-BIT, FLASH, 16MHz, MICROCONTROLLER, PQFP112, LQFP-112;
| 型号： | MC9S12H128VPVE |
| 厂家： | 
Rochester Electronics |
| 描述： | 16-BIT, FLASH, 16MHz, MICROCONTROLLER, PQFP112, LQFP-112 时钟 微控制器 外围集成电路 |
| 文件： | 总131页 (文件大小：1242K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC9S12H256 Device User Guide — V01.20
MC9S12H256
Device User Guide
V01.20
Covers also MC9S12H128
Original Release Date: 29 SEP 2000
Revised: 28 JUL 2008
Freescale Semiconductor Inc.
1
DOCUMENT NUMBER
9S12H256BDGV1/D
Revision History
Version Revision Effective
Author
Description of Changes
Number
Date
Date
07 MAR
2001
03 APR
2001
V01.00
Initial version.
- Minor formal corrections
10 MAI
2001
10 MAY
2001
V01.01
V01.02
- Changed ATD coupling ratio to10-2
- Changed VDD5 to 4.5V
- Removed 112-pin package references
- Changed ATD Electrical Characteristics separate coupling ratio for
positive and negative bulk current injection
14 MAY
2001
14 MAY
2001
30 MAY
2001
30 MAY
2001
V01.03
V01.04
- Reinserted 112-pin package information.
11 JUN
2001
11 JUN
2001
- Removed SRSv2 comment from preface
- Corrected RESET pin to active low in table 2-1
- Adapted style and wording to 9DP256 device user guide
- Minor format and wording improvements
- Added SRAM data retention disclaimer
18 JUN
2001
18 JUN
2001
V01.05
V01.06
- Changed Oscillator Characteristics tCQOUT max 2.5s and replaced
Clock Monitor Time-out by Clock Monitor Failure Assert Frequency
- Changed Self Clock Mode Frequency min 1MHz and max 5.5MHz
- Changed IDDPS (RTI and COP disabled) to 400µA
28 JUN
2001
28 JUN
2001
- Corrected typo in Figure 2-1 pin 76: PK3 -> PK2
- Added tEXTR and tEXTF to Oscillator Characteristics
- Added typ value for tUPOSC
- Corrected tEXTL and tEXTH values
- Updated thermal resistances as per Thermal Simulation Report,
July 10, 2001
12 JUL
2001
12 JUL
2001
V01.07
16 JUL
2001
16 JUL
2001
- updated EEPROM size
- added DC cutoff capacitor into layout proposals
V01.08
V01.09
V01.10
03 AUG
2001
03 AUG
2001
- minor updates
29 AUG
2001
29 AUG
2001
- updated electrical spec
Freescale reserves the right to make changes without further notice to any products herein to improve reliability, function or
design. Freescale does not assume any liability arising out of the application or use of any product or circuit described herein;
neither does it convey any license under its patent rights nor the rights of others. Freescale products are not designed, intended,
or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to
support or sustain life, or for any other application in which the failure of the Freescale product could create a situation where
personal injury or death may occur. Should Buyer purchase or use Freescale products for any such unintended or unauthorized
application, Buyer shall indemnify and hold Freescale and its officers, employees, subsidiaries, affiliates, and distributors
harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly,
any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Freescale was negligent regarding the design or manufacture of the part.
2
MC9S12H256 Device User Guide — V01.20
Description of Changes
Version Revision Effective
Author
Number
Date
Date
11 OCT
2001
11 OCT
2001
- Replaced references w.r.t. new family name HCS12.
- Corrected XCLKS reference in CRG electrical spec.
V01.11
07 NOV
2001
07 NOV
2001
V01.12
V01.13
- added ‘powered by’ column in pin list table
- new document numbering
- removed document order number except from cover sheet
- updated min VDD, VDDPLL
- updated currents on VOH,VOL for standard pins
- updated CIN, IDDS, IREF, CINS, TEXTL, TEXTH
- included missing lcd electrical spec
- updated NVM spec
08 MAR
2002
08 MAR
2002
- updated input leakage
- updated slew rate spec on PU,PV, PW
- updated supply currents
- included 1K78X
16 DEC
2002
16 DEC
2002
V01.14
- added detailed register map
31 MAR
2003
31 MAR
2003
- added K1 max value
- added chragepump current min/max values
V01.15
V01.16
V01.17
V01.18
V01.19
V01.20
05 NOV
2003
05 NOV
2003
- corrected pinout problem in LQFP112 layout proposal
- added MC9S12H128
04 AUG
2004
04 AUG
2004
13 AUG
2004
13 AUG
2004
- added Internal Pull Resistor columns to signal properties table
- changed SPI0 to SPI, ATD0 to ATD
05 NOV
2004
05 NOV
2004
28 JUL
2008
28 JUL
2008
- changed PU,PV,PW rise/fall times in EPP package at cold.
3
MC9S12H256 Device User Guide — V01.20
4
MC9S12H256 Device User Guide — V01.20
Section 1 Introduction
1.1
1.2
1.3
1.4
1.5
1.5.1
1.6
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Device Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Detailed Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Part ID Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Section 2 Signal Description
2.1
Device Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Signal Properties Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Detailed Signal Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
EXTAL, XTAL — Oscillator Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
RESET — External Reset Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
TEST — Test Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
XFC — PLL Loop Filter Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
BKGD / TAGHI / MODC — Background Debug, Tag High, and Mode Pin. . . . . . . . . . . . . 60
PAD[15:8] / AN[15:8] — Port AD Input Pins [15:8] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
PAD[7:0] / AN[7:0] — Port AD Input Pins [7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
PA[7:0] / FP[15:8] / ADDR[15:8] / DATA[15:8] — Port A I/O Pins . . . . . . . . . . . . . . . . . . 60
PB[7:0] / FP[7:0] / ADDR[7:0] / DATA[7:0] — Port B I/O Pins. . . . . . . . . . . . . . . . . . . . . . 61
PE7 / FP22 / XCLKS / NOACC — Port E I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
PE6 / MODB / IPIPE1 — Port E I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
PE5 / MODA / IPIPE0 — Port E I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
PE4 / ECLK — Port E I/O Pin 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
PE3 / FP21 / LSTRB / TAGLO — Port E I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
PE2 / FP20 / R/W — Port E I/O Pin 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
PE1 / IRQ — Port E Input Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
PE0 / XIRQ — Port E Input Pin 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
PH[7:0] / KWH[7:0] — Port H I/O Pins [7:0]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
PJ[3:0] / KWJ[3:0] — Port J I/O Pins [3:0]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
PK7 / FP23 / ECS / ROMONE — Port K I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
PK[3:0] / BP[3:0] / XADDR[17:14] — Port K I/O Pins [3:0] . . . . . . . . . . . . . . . . . . . . . . . . 62
PL[7:4] / FP[31:28] — Port L I/O Pins [7:4]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
PL[3:0] / FP[19:16] — Port L I/O Pins [3:0]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
2.2
2.3
2.3.1
2.3.2
2.3.3
2.3.4
2.3.5
2.3.6
2.3.7
2.3.8
2.3.9
2.3.10
2.3.11
2.3.12
2.3.13
2.3.14
2.3.15
2.3.16
2.3.17
2.3.18
2.3.19
2.3.20
2.3.21
2.3.22
2.3.23
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MC9S12H256 Device User Guide — V01.20
2.3.24
2.3.25
2.3.26
2.3.27
2.3.28
2.3.29
2.3.30
2.3.31
2.3.32
2.3.33
2.3.34
2.3.35
2.3.36
2.3.37
2.3.38
2.3.39
2.3.40
2.3.41
2.3.42
2.3.43
2.3.44
2.3.45
2.3.46
2.3.47
2.4
PM5 / TXCAN1 — Port M I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
PM4 / RXCAN1 — Port M I/O Pin 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
PM3 / TXCAN0 — Port M I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
PM2 / RXCAN0 — Port M I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
PM1 / SCL — Port M I/O Pin 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
PM0 / SDA — Port M I/O Pin 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
PP[5:2] / PWM[5:2] — Port P I/O Pins [5:2] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
PP[1:0] / PWM[1:0] — Port P I/O Pins [1:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
PS7 / SS — Port S I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
PS6 / SCK — Port S I/O Pin 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
PS5 / MOSI — Port S I/O Pin 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
PS4 / MISO — Port S I/O Pin 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
PS3 / TXD1 — Port S I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
PS2 / RXD1 — Port S I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
PS1 / TXD0 — Port S I/O Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
PS0 / RXD0 — Port S I/O Pin 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
PT[7:4] / IOC[7:4] — Port T I/O Pins [7:4] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
PT[3:0] / IOC[3:0] / FP[27:24] — Port T I/O Pins [3:0]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
PU[7:4] / M1C1P, M1C1M, M1C0P, M1C0M — Port U I/O Pins [7:4] . . . . . . . . . . . . . . . . 65
PU[3:0] / M0C1P, M0C1M, M0C0P, M0C0M — Port U I/O Pins [3:0] . . . . . . . . . . . . . . . . 65
PV[7:4] / M3C1P, M3C1M, M3C0P, M3C0M — Port V I/O Pins [7:4] . . . . . . . . . . . . . . . . 65
PV[3:0] / M2C1P, M2C1M, M2C0P, M2C0M — Port V I/O Pins [3:0] . . . . . . . . . . . . . . . . 66
PW[7:4] / M5C1P, M5C1M, M5C0P, M5C0M — Port W I/O Pins [7:4] . . . . . . . . . . . . . . . 66
PW[3:0] / M4C1P, M4C1M, M4C0P, M4C0M — Port W I/O Pins [3:0] . . . . . . . . . . . . . . . 66
Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
VDDR — External Power Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
VDDX1, VDDX2, VSSX1, VSSX2 — External Power and Ground Pins . . . . . . . . . . . . . . . 66
VDD1, VSS1, VSS2 — Core Power Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
VDDA, VSSA — Power Supply Pins for ATD and VREG . . . . . . . . . . . . . . . . . . . . . . . . . . 67
VDDM1, VDDM2, VDDM3 — Power Supply Pins for Motor 0 to 5 . . . . . . . . . . . . . . . . . . 67
VSSM1, VSSM2, VSSM3 — Ground Pins for Motor 0 to 5 . . . . . . . . . . . . . . . . . . . . . . . . . 67
VLCD — Power Supply Reference Pin for LCD driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
VRH, VRL — ATD Reference Voltage Input Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
VDDPLL, VSSPLL — Power Supply Pins for PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
2.4.1
2.4.2
2.4.3
2.4.4
2.4.5
2.4.6
2.4.7
2.4.8
2.4.9
Section 3 System Clock Description
6
MC9S12H256 Device User Guide — V01.20
3.1
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Section 4 Modes of Operation
4.1
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Normal Operating Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Special Operating Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Test Operating Mode (Freescale Use Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Securing the Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Operation of the Secured Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Unsecuring the Microcontroller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
4.2
4.2.1
4.2.2
4.2.3
4.3
4.3.1
4.3.2
4.3.3
4.4
Section 5 Resets and Interrupts
5.1
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Vector Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Effects of Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
I/O pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
5.2
5.2.1
5.3
5.3.1
5.3.2
Section 6 HCS12 Core Block Description
Section 7 Clock and Reset Generator (CRG) Block Description
7.1
Device-specific information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
XCLKS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
7.1.1
Section 8 Timer (TIM) Block Description
Section 9 Analog to Digital Converter (ATD) Block Description
Section 10 Inter-IC Bus (IIC) Block Description
Section 11 Serial Communications Interface (SCI) Block Description
Section 12 Serial Peripheral Interface (SPI) Block Description
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MC9S12H256 Device User Guide — V01.20
Section 13 Pulse Width Modulator (PWM) Block Description
Section 14 Flash EEPROM 256K Block Description
Section 15 EEPROM 4K Block Description
Section 16 RAM Block Description
Section 17 Liquid Crystal Display Driver (LCD) Block Description
Section 18 MSCAN Block Description
Section 19 PWM Motor Control (MC) Block Description
Section 20 Port Integration Module (PIM) Block Description
Section 21 Voltage Regulator (VREG) Block Description
21.1 Device-specific information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
21.1.1
21.1.2
VREGEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
21.2 Recommended PCB layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Appendix A Electrical Characteristics
A.1
General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Current Injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
ESD Protection and Latch-up Immunity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Power Dissipation and Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
A.1.1
A.1.2
A.1.3
A.1.4
A.1.5
A.1.6
A.1.7
A.1.8
A.1.9
A.1.10 Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
A.2
ATD Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
ATD Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Factors influencing accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
A.2.1
A.2.2
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MC9S12H256 Device User Guide — V01.20
A.2.3
A.3
ATD accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
NVM, Flash and EEPROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
NVM timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
NVM Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Reset, Oscillator and PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Phase Locked Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
MSCAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
SPI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
LCD_32F4B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
External Bus Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
General Muxed Bus Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
A.3.1
A.3.2
A.4
A.4.1
A.4.2
A.4.3
A.5
A.6
A.6.1
A.6.2
A.7
A.8
A.8.1
Appendix B Package Information
B.1
B.2
B.3
General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
112-pin LQFP package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
144-pin LQFP package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
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MC9S12H256 Device User Guide — V01.20
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Figure 1-1
Figure 1-2
Figure 1-3
Figure 1-4
Figure 2-1
Figure 2-2
Figure 3-1
Figure 21-1
Figure 21-2
Figure A-1
Figure A-2
Figure A-3
Figure A-4
Figure A-5
Figure A-6
Figure A-7
Figure A-8
Figure A-9
Figure B-1
Figure B-2
MC9S12H256 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
MC9S12H128 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
MC9S12H256 Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
MC9S12H128 Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Pin Assignments in 112-pin LQFP for MC9S12H256 and MC9S12H128. . . . . . . . . . 56
Pin Assignments in 144-pin LQFP for MC9S12H256 . . . . . . . . . . . . . . . . . . . . . . . . . 57
Clock Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
LQFP112 recommended PCB layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
LQFP144 recommended PCB layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
ATD Accuracy Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Basic PLL functional diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Jitter Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Maximum bus clock jitter approximation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
SPI Master Timing (CPHA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
SPI Master Timing (CPHA =1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
SPI Slave Timing (CPHA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
SPI Slave Timing (CPHA =1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
General External Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
112-pin LQFP mechanical dimensions (case no. 987) . . . . . . . . . . . . . . . . . . . . . . . 126
144-pin LQFP mechanical dimensions (case no. 918-03). . . . . . . . . . . . . . . . . . . . . 127
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MC9S12H256 Device User Guide — V01.20
Table 0-1
Table 1-1
Table 1-2
Table 1-3
Table 1-4
Table 1-5
Table 1-6
Table 2-1
Table 4-1
Table 5-1
Document References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Device Memory Map MC9S12H256 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Device Memory Map MC9S12H128 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Detailed MSCAN Foreground Receive and Transmit Buffer Layout. . . . . . . . . . . . . . . . . 44
Detailed MSCAN Foreground Receive and Transmit Buffer Layout. . . . . . . . . . . . . . . . . 46
Assigned Part ID Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Memory size registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Signal Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Reset and Interrupt Vector Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Table 21-1 Recommended Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table A-1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Table A-2 ESD and Latch-up Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Table A-3 ESD and Latch-Up Protection Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Table A-4 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Table A-5 Thermal Package Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Table A-6 5V I/O Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Table A-7 Supply Current Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Table A-8 ATD Operating Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Table A-9 ATD Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Table A-10 ATD Conversion Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Table A-11 NVM Timing Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Table A-12 NVM Reliability Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Table A-13 Startup Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Table A-14 Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Table A-15 PLL Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Table A-16 MSCAN Wake-up Pulse Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Table A-17 SPI Master Mode Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Table A-18 SPI Slave Mode Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
LCD_32F4B Driver Electrical Characteristics 119
Table A-20 Expanded Bus Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
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MC9S12H256 Device User Guide — V01.20
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MC9S12H256 Device User Guide — V01.20
Preface
The Device User Guide provides information about the MC9S12H256 and MC9S12H128 device made up
of standard HCS12 blocks and the HCS12 processor core.
This document is part of the customer documentation. A complete set of device manuals also includes the
HCS12 Core User Guide and all the individual Block User Guides of the implemented modules. In an
effort to reduce redundancy all module specific information is located only in the respective Block User
Guide. If applicable, special implementation details of the module are given in the block description
sections of this document.
See Table 0-1 for names and versions of the referenced documents throughout the Device User Guide.
Table 0-1 Document References
User Guide
Version
Document Order Number
HCS12COREUG
S12CRGV2/D
HCS12 V1.5 Core User Guide
CRG Block User Guide
1.2
V02
V01
V02
V02
V02
V02
V01
V02
V02
V01
V02
V02
V01
V01
TIM_16B8C Block User Guide
ATD_10B16C Block User Guide
IIC Block User Guide
S12TIM16B8CV1/D
S12ATD10B16CV2/D
S12IICV2/D
SCI Block User Guide
S12SCIV2/D
SPI Block User Guide
S12SPIV2/D
PWM_8B6C Block User Guide
FTS256K Block User Guide
EETS4K Block User Guide
LCD_32F4B Block User Guide
MSCAN Block User Guide
MC_10B12C Block User Guide
PIM_9H256 Block User Guide
VREG Block User Guide
S12PWM8B6CV1/D
S12FTS256KV2/D
S12EETS4KV2/D
S12LCD32F4BV1/D
S12MSCANV2/D
S12MC10B12CV2/D
S12PIMH256V1/D
S12VREGV1/D
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MC9S12H256 Device User Guide — V01.20
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MC9S12H256 Device User Guide — V01.20
Section 1 Introduction
1.1 Overview
The MC9S12H256 microcontroller unit (MCU) is a 16-bit device composed of standard on-chip
peripherals including a 16-bit central processing unit (HCS12 CPU), 256K bytes of Flash EEPROM, 12K
bytes of RAM, 4K bytes of EEPROM, two asynchronous serial communications interfaces (SCI), a serial
peripheral interface (SPI), an IIC-bus interface (IIC), an 8-channel 16-bit timer (TIM), a 16-channel, 10-bit
analog-to-digital converter (ATD), a six-channel pulse width modulator (PWM), and two CAN 2.0 A, B
software compatible modules (MSCAN).
The MC9S12H128 microcontroller unit (MCU) is a 16-bit device composed of standard on-chip
peripherals including a 16-bit central processing unit (HCS12 CPU), 128K bytes of Flash EEPROM, 6K
bytes of RAM, 2K bytes of EEPROM, one asynchronous serial communications interface (SCI), a serial
peripheral interface (SPI), an IIC-bus interface (IIC), an 8-channel 16-bit timer (TIM), a 8-channel, 10-bit
analog-to-digital converter (ATD), a two-channel pulse width modulator (PWM), and two CAN 2.0 A, B
software compatible modules (MSCAN).
In addition, it features a 32x4 liquid crystal display (LCD) controller/driver and a motor pulse width
modulator (MC) consisting of 24 high current outputs suited to drive up to 6 stepper motors. System
resource mapping, clock generation, interrupt control, and bus interfacing are managed by the HCS12
Core.
The MC9S12H256 has full 16-bit data paths throughout. The inclusion of a PLL circuit allows power
consumption and performance to be adjusted to suit operational requirements. In addition to the I/O ports
available in each module, 12 general purpose I/O pins are available with interrupt and wake-up capability
from STOP or WAIT mode.
1.2 Features
•
HCS12 Core
– 16-bit HCS12 CPU
i. Upward compatible with M68HC11 instruction set
ii. Interrupt stacking and programmer’s model identical to M68HC11
iii.20-bit ALU
iv. Instruction queue
v. Enhanced indexed addressing
– MEBI (Multiplexed External Bus Interface)
– MMC (Module Mapping Control)
– INT (Interrupt control)
– BKP (Breakpoints)
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MC9S12H256 Device User Guide — V01.20
– BDM (Background Debug Mode)
•
•
CRG (low current oscillator, PLL, reset, clocks, COP watchdog, real time interrupt, clock monitor)
8-bit and 4-bit ports with interrupt functionality
– Digital filtering
– Programmable rising or falling edge trigger
Memory
•
– 128K, 256K Flash EEPROM
– 2K, 4K byte EEPROM
– 6K, 12K byte RAM
•
•
Analog-to-Digital Converter
– 8, 16 channels, 10-bit resolution
– External conversion trigger capability
Two 1M bit per second, CAN 2.0 A, B software compatible modules
– Five receive and three transmit buffers
– Flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit or 8 x 8 bit
– Four separate interrupt channels for Rx, Tx, error and wake-up
– Low-pass filter wake-up function
– Loop-back for self test operation
•
•
Timer
– 16-bit main counter with 7-bit prescaler
– 8 programmable input capture or output compare channels
– Two 8-bit or one 16-bit pulse accumulators
2, 6 PWM channels
– Programmable period and duty cycle
– 8-bit 2, 6-channel or 16-bit 1, 3-channel
– Separate control for each pulse width and duty cycle
– Center-aligned or left-aligned outputs
– Programmable clock select logic with a wide range of frequencies
– Fast emergency shutdown input
•
Serial interfaces
– Two asynchronous Serial Communications Interfaces (SCI)
– Synchronous Serial Peripheral Interface (SPI)
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MC9S12H256 Device User Guide — V01.20
– Inter-Integrated Circuit interface (IIC)
•
•
Liquid Crystal Display driver with variable input voltage
– Configurable for up to 32 frontplanes and 4 backplanes or general purpose input or output
– 5 modes of operation allow for different display sizes to meet application requirements
– Unused frontplane and backplane pins can be used as general purpose I/O
16, 24 high current drivers suited for PWM motor control
– Each PWM channel switchable between two drivers in an H-bridge configuration
– Left, right and center aligned outputs
– Support for sine and cosine drive
– Dithering
– Output slew rate control
•
144-Pin or 112-Pin LQFP package
– I/O lines with 5V input and drive capability
– 5V A/D converter inputs
– Operation at 32MHz equivalent to 16MHz Bus Speed
– Development support
– Single-wire background debug™ mode (BDM)
– On-chip hardware breakpoints
1.3 Modes of Operation
User modes
•
Normal and Emulation Operating Modes
– Normal Single-Chip Mode
– Normal Expanded Wide Mode
– Normal Expanded Narrow Mode
– Emulation Expanded Wide Mode
– Emulation Expanded Narrow Mode
Special Operating Modes
•
– Special Single-Chip Mode with active Background Debug Mode
– Special Test Mode (Freescale Use Only)
– Special Peripheral Mode (Freescale Use Only)
Low power modes
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MC9S12H256 Device User Guide — V01.20
•
•
•
Stop Mode
Pseudo Stop Mode
Wait Mode
1.4 Block Diagram
Figure 1-1 is a block diagram of the MC9S12H256 device.
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MC9S12H256 Device User Guide — V01.20
VDDR
VDDA
VSSA
VRH
VDDA
VSSA
VRH
Voltage Regulator
VDD1
VSS1,VSS2
VRL
VRL
AN00
AN01
AN02
AN03
AN04
AN05
AN06
AN07
AN08
AN09
AN10
AN11
AN12
AN13
AN14
AN15
PAD00
PAD01
PAD02
PAD03
PAD04
PAD05
PAD06
PAD07
PAD08
PAD09
PAD10
PAD11
PAD12
PAD13
PAD14
PAD15
256k Bytes Flash EEPROM
4k Bytes EEPROM
Analog to
Digital
Converter
(ATD)
12K Bytes RAM
Single-wire Background
Debug Module
BKGD
CPU12
XFC
VDDPLL
VSSPLL
EXTAL
XTAL
Clock and
Reset
Generation
Module
Periodic Interrupt
COP Watchdog
Clock Monitor
Breakpoints
PLL
RESET
TEST
PE0
PE1
PE4
PE5
PE6
XIRQ
IRQ
ECLK
MODA
MODB
PW0
PW1
PW2
PW3
PW4
PW5
PP0
PP1
PP2
PP3
PP4
PP5
Integration
Module
Pulse
Width
Modulator
(PWM)
VLCD
VLCD
RXD0
TXD0
PS0
PS1
SCI0
SCI1
XADDR14 PK0
XADDR15 PK1
XADDR16 PK2
XADDR17 PK3
BP0
BP1
BP2
BP3
PIX0
PIX1
PIX2
PIX3
RXD1
TXD1
PS2
PS3
SDI/MISO
SDO/MOSI
SCK
PS4
PS5
PS6
PS7
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
FP0
FP1
FP2
FP3
FP4
FP5
FP6
FP7
ADDR0
ADDR1
ADDR2
ADDR3
ADDR4
ADDR5
ADDR6
ADDR7
SPI
SS
LCD
Driver
SDA
SCL
PM0
PM1
IIC
RXCAN0
TXCAN0
PM2
PM3
CAN0
CAN1
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
DATA8
DATA9
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
FP8
FP9
ADDR8
ADDR9
RXCAN1
TXCAN1
PM4
PM5
DATA10
DATA11
DATA12
DATA13
DATA14
DATA15
FP10
FP11
FP12
FP13
FP14
FP15
ADDR10
ADDR11
ADDR12
ADDR13
ADDR14
ADDR15
VDDM1
VSSM1
PU0
PU1
MOTOR0 and MOTOR1 Supply
M0C0M
PWM0
PWM1
PWM2
PWM3
M0C0P
MOTOR0
M0C1M
M0C1P
PU2
PU3
Multiplexed Multiplexed
PL0
PL1
PL2
PL3
PL4
PL5
PL6
PL7
FP16
FP17
FP18
FP19
FP28
FP29
FP30
FP31
Narrow
Bus
Wide
Bus
M1C0M
M1C0P
PU4
PU5
MOTOR1
M1C1M
M1C1P
PU6
PU7
VDDM2
VSSM2
PV0
PV1
MOTOR2 and MOTOR3 Supply
M2C0M
PE2
PE3
PE7
FP20
FP21
FP22
R/W
LSTRB/TAGLO
NOACC/XCLKS
PWM4
PWM5
PWM6
PWM7
M2C0P
MOTOR2
M2C1M
M2C1P
PV2
PV3
M3C0M
M3C0P
PV4
PV5
PK7
FP23
ECS/ROMONE
MOTOR3
M3C1M
M3C1P
PV6
PV7
PT0
PT1
PT2
PT3
FP24
FP25
FP26
FP27
IOC0
IOC1
IOC2
IOC3
NOTE: Not all
functionality shown
in this block
VDDM3
VSSM3
PW0
PW1
MOTOR4 and MOTOR5 Supply
M4C0M
diagram is
available in all
packages!
PWM8
PWM9
PWM10
PWM11
PT4
PT5
PT6
PT7
IOC4
IOC5
IOC6
IOC7
M4C0P
MOTOR4
Input Capture and
Output Compare
Timer
M4C1M
M4C1P
PW2
PW3
M5C0M
M5C0P
PW4
PW5
PH0
PH1
PH2
PH3
PH4
PH5
PH6
PH7
KWH0
KWH1
KWH2
KWH3
KWH4
KWH5
KWH6
KWH7
MOTOR5
M5C1M
M5C1P
PW6
PW7
Supply pins
Internal Logic 2.5V
VDD1
VSS1,2
I/O Driver 5V
VDDX1,2
VSSX1,2
Pin
Interrupt
Logic
A/D Converter 5V &
Voltage Regulator
Reference
PJ0
PJ1
PJ2
PJ3
KWJ0
KWJ1
KWJ2
PLL 2.5V
VREG Input 5V
VDDR
VDDA
VSSA
VDDPLL
VSSPLL
KWJ3
Figure 1-1 MC9S12H256 Block Diagram
21
MC9S12H256 Device User Guide — V01.20
Figure 1-2 is a block diagram of the MC9S12H128 device.
22
MC9S12H256 Device User Guide — V01.20
VDDR
VDDA
VSSA
VRH
VDDA
VSSA
VRH
Voltage Regulator
VDD1
VSS1,VSS2
VRL
VRL
AN00
AN01
AN02
AN03
AN04
AN05
AN06
AN07
AN08
PAD00
PAD01
PAD02
PAD03
PAD04
PAD05
PAD06
PAD07
128k Bytes Flash EEPROM
2k Bytes EEPROM
6K Bytes RAM
Analog to
Digital
Converter
(ATD)
Single-wire Background
Debug Module
BKGD
CPU12
XFC
VDDPLL
VSSPLL
EXTAL
XTAL
Clock and
Reset
Generation
Module
Periodic Interrupt
COP Watchdog
Clock Monitor
Breakpoints
PLL
RESET
TEST
PE0
PE1
PE4
PE5
PE6
XIRQ
IRQ
ECLK
MODA
MODB
PW0
PW1
PW2
PW3
PW4
PW5
PP0
PP1
PP2
PP3
PP4
PP5
Integration
Module
Pulse
Width
Modulator
(PWM)
VLCD
VLCD
RXD0
TXD0
PS0
PS1
SCI0
SPI
XADDR14 PK0
XADDR15 PK1
XADDR16 PK2
XADDR17 PK3
BP0
BP1
BP2
BP3
PIX0
PIX1
PIX2
PIX3
SDI/MISO
SDO/MOSI
SCK
PS4
PS5
PS6
PS7
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
FP0
FP1
FP2
FP3
FP4
FP5
FP6
FP7
ADDR0
ADDR1
ADDR2
ADDR3
ADDR4
ADDR5
ADDR6
ADDR7
SS
LCD
Driver
SDA
SCL
PM0
PM1
IIC
RXCAN0
TXCAN0
PM2
PM3
CAN0
CAN1
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
DATA8
DATA9
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
FP8
FP9
ADDR8
ADDR9
RXCAN1
TXCAN1
PM4
PM5
DATA10
DATA11
DATA12
DATA13
DATA14
DATA15
FP10
FP11
FP12
FP13
FP14
FP15
ADDR10
ADDR11
ADDR12
ADDR13
ADDR14
ADDR15
VDDM1
VSSM1
PU0
PU1
MOTOR0 and MOTOR1 Supply
M0C0M
PWM0
PWM1
PWM2
PWM3
M0C0P
MOTOR0
M0C1M
M0C1P
PU2
PU3
Multiplexed Multiplexed
PL0
PL1
PL2
PL3
FP16
FP17
FP18
FP19
Narrow
Bus
Wide
Bus
M1C0M
M1C0P
PU4
PU5
MOTOR1
M1C1M
M1C1P
PU6
PU7
VDDM2
VSSM2
PV0
PV1
MOTOR2 and MOTOR3 Supply
M2C0M
PE2
PE3
PE7
FP20
FP21
FP22
R/W
LSTRB/TAGLO
NOACC/XCLKS
PWM4
PWM5
PWM6
PWM7
M2C0P
MOTOR2
M2C1M
M2C1P
PV2
PV3
M3C0M
M3C0P
PV4
PV5
PK7
FP23
ECS/ROMONE
MOTOR3
M3C1M
M3C1P
PV6
PV7
PT0
PT1
PT2
PT3
FP24
FP25
FP26
FP27
IOC0
IOC1
IOC2
IOC3
NOTE: Not all
functionality shown
in this block
diagram is
available in all
packages!
VDDM3
VSSM3
PW0
PW1
MOTOR4 and MOTOR5 Supply
M4C0M
PWM8
PWM9
PWM10
PWM11
PT4
PT5
PT6
PT7
IOC4
IOC5
IOC6
IOC7
M4C0P
MOTOR4
Input Capture and
Output Compare
Timer
M4C1M
M4C1P
PW2
PW3
M5C0M
M5C0P
PW4
PW5
MOTOR5
M5C1M
M5C1P
PW6
PW7
Supply pins
Internal Logic 2.5V
VDD1
VSS1,2
I/O Driver 5V
VDDX1,2
VSSX1,2
A/D Converter 5V &
Voltage Regulator
Reference
PLL 2.5V
VREG Input 5V
VDDR
VDDA
VSSA
VDDPLL
VSSPLL
Figure 1-2 MC9S12H128 Block Diagram
23
MC9S12H256 Device User Guide — V01.20
1.5 Device Memory Map
24
MC9S12H256 Device User Guide — V01.20
25
MC9S12H256 Device User Guide — V01.20
Table 1-1 and Figure 1-3 show the device memory map of the MC9S12H256.
Table 1-1 Device Memory Map MC9S12H256
Size
(Bytes)
Address
Module
$0000 – $0017 CORE (Ports A, B, E, Modes, Inits, Test)
$0018 – $0019 Reserved
24
2
$001A – $001B Device ID register (PARTID)
$001C – $001F CORE (MEMSIZ, IRQ, HPRIO)
$0020 – $0027 Reserved
2
4
8
$0028 – $002F CORE (Background Debug Mode)
$0030 – $0033 CORE (PPAGE, Port K)
8
4
$0034 – $003F Clock and Reset Generator (PLL, RTI, COP)
$0040 – $006F Standard Timer Module 16-bit 8 channels (TIM)
$0070 – $007F Reserved
12
48
16
48
16
8
$0080 – $00AF Analog to Digital Converter 10-bit 16 channels (ATD)
$00B0 – $00BF Reserved
$00C0 – $00C7 Inter Integrated Circuit (IIC)
$00C8 – $00CF Serial Communications Interface 0 (SCI0)
$00D0 – $00D7 Serial Communications Interface 1 (SCI1)
$00D8 – $00DF Serial Peripheral Interface (SPI)
$00E0 – $00FF Pulse Width Modulator 8-bit 6 channels (PWM)
$0100 – $010F Flash control registers
8
8
8
32
16
12
4
$0110 – $011B EEPROM control registers
$011C – $011F Reserved
$0120 – $0137 Liquid Crystal Display Driver 32x4 (LCD)
24
Freescale Scalable Controller Area Network 0
$0140 – $017F
(MSCAN0)
64
64
Freescale Scalable Controller Area Network 1
$0180 – $01BF
(MSCAN1)
$01C0 – $01FF Motor Control Module (MC)
$0200 – $027F Port Integration Module (PIM)
$0280 – $03FF Reserved
64
128
384
$0000 – $0FFF EEPROM array
$1000 – $3FFF RAM array
4096
12288
Fixed Flash EEPROM array
$4000 – $7FFF
16384
16384
incl. 0.5K, 1K, 2K or 4K Protected Sector at start
$8000 – $BFFF Flash EEPROM Page Window
Fixed Flash EEPROM array
$C000 – $FFFF incl. 0.5K, 1K, 2K or 4K Protected Sector at end
and 256 bytes of Vector Space at $FF80 – $FFFF
16384
26
MC9S12H256 Device User Guide — V01.20
$0000
1K Register Space
$03FF
$0000
Mappable to any 2K Boundary
$0000
$0400
$0800
4K Bytes EEPROM
initially overlapped by register space
$1000
$0FFF
$1000
Mappable to any 4K Boundary
12K Bytes RAM
Alignable to top ($1000 – $3FFF)
or bottom ($0000 – $2FFF)
$3FFF
$4000
Mappable to any 16K Boundary
$4000
0.5K, 1K, 2K or 4K Protected Sector
16K Fixed Flash EEPROM
$7FFF
$8000
$8000
16K Page Window
Sixteen * 16K Flash EEPROM Pages
EXT
$BFFF
$C000
$C000
16K Fixed Flash EEPROM
2K, 4K, 8K or 16K Protected Boot Sector
$FFFF
$FF00
BDM
(If Active)
$FF00
$FFFF
VECTORS
VECTORS
VECTORS
$FFFF
NORMAL
SINGLE CHIP
EXPANDED*
SPECIAL
SINGLE CHIP
* Assuming that a ‘0’ was driven onto port K7 during reset to normal expanded mode
Figure 1-3 MC9S12H256 Memory Map
Table 1-2 and Figure 1-4 show the device memory map of the MC9S12H128.
Table 1-2 Device Memory Map MC9S12H128
Size
(Bytes)
Address
Module
$0000 – $0017 CORE (Ports A, B, E, Modes, Inits, Test)
$0018 – $0019 Reserved
24
2
$001A – $001B Device ID register (PARTID)
$001C – $001F CORE (MEMSIZ, IRQ, HPRIO)
$0020 – $0027 Reserved
2
4
8
$0028 – $002F CORE (Background Debug Mode)
$0030 – $0033 CORE (PPAGE, Port K)
8
4
$0034 – $003F Clock and Reset Generator (PLL, RTI, COP)
$0040 – $006F Standard Timer Module 16-bit 8 channels (TIM)
$0070 – $007F Reserved
12
48
16
48
16
8
$0080 – $00AF Analog to Digital Converter 10-bit 16 channels (ATD)
$00B0 – $00BF Reserved
$00C0 – $00C7 Inter Integrated Circuit (IIC)
27
MC9S12H256 Device User Guide — V01.20
Table 1-2 Device Memory Map MC9S12H128
Size
(Bytes)
Address
Module
$00C8 – $00CF Serial Communications Interface 0 (SCI0)
$00D0 – $00D7 Reserved
8
8
$00D8 – $00DF Serial Peripheral Interface (SPI)
$00E0 – $00FF Pulse Width Modulator 8-bit 6 channels (PWM)
$0100 – $010F Flash control registers
8
32
16
12
4
$0110 – $011B EEPROM control registers
$011C – $011F Reserved
$0120 – $0137 Liquid Crystal Display Driver 32x4 (LCD)
24
Freescale Scalable Controller Area Network 0
$0140 – $017F
(MSCAN0)
64
64
Freescale Scalable Controller Area Network 1
$0180 – $01BF
(MSCAN1)
$01C0 – $01FF Motor Control Module (MC)
$0200 – $027F Port Integration Module (PIM)
$0280 – $03FF Reserved
64
128
384
$0000 – $07FF EEPROM array
$1000 – $3FFF RAM array
2048
12288
Fixed Flash EEPROM array
$4000 – $7FFF
16384
16384
incl. 0.5K, 1K, 2K or 4K Protected Sector at start
$8000 – $BFFF Flash EEPROM Page Window
Fixed Flash EEPROM array
$C000 – $FFFF incl. 0.5K, 1K, 2K or 4K Protected Sector at end
and 256 bytes of Vector Space at $FF80 – $FFFF
16384
28
MC9S12H256 Device User Guide — V01.20
$0000
1K Register Space
$03FF
$0000
Mappable to any 2K Boundary
$0000
$0400
2K Bytes EEPROM
initially overlapped by register space
$0800
$2800
$07FF
$2800
Mappable to any 4K Boundary
6K Bytes RAM
Alignable to top ($2800 – $3FFF)
or bottom ($0000 – $17FF)
$3FFF
$4000
Mappable to any 16K Boundary
$4000
$8000
$C000
0.5K, 1K, 2K or 4K Protected Sector
16K Fixed Flash EEPROM
$7FFF
$8000
16K Page Window
Sixteen * 16K Flash EEPROM Pages
EXT
$BFFF
$C000
16K Fixed Flash EEPROM
2K, 4K, 8K or 16K Protected Boot Sector
$FFFF
$FF00
BDM
(If Active)
$FF00
$FFFF
VECTORS
VECTORS
VECTORS
$FFFF
NORMAL
SINGLE CHIP
EXPANDED*
SPECIAL
SINGLE CHIP
* Assuming that a ‘0’ was driven onto port K7 during reset to normal expanded mode
Figure 1-4 MC9S12H128 Memory Map
29
MC9S12H256 Device User Guide — V01.20
1.5.1 Detailed Register Map
$0000 - $000F
MEBI map 1 of 3 (Core User Guide)
Address
$0000
Name
Bit 7
Bit 7
Bit 6
6
Bit 5
5
Bit 4
4
Bit 3
3
Bit 2
2
Bit 1
1
Bit 0
Bit 0
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
PORTA
$0001
$0002
$0003
$0004
$0005
$0006
$0007
$0008
$0009
$000A
$000B
$000C
$000D
$000E
$000F
PORTB
DDRA
Bit 7
Bit 7
6
6
5
5
4
4
3
3
2
2
1
1
Bit 0
Bit 0
DDRB
Bit 7
0
6
0
5
0
4
0
3
0
2
0
1
0
Bit 0
0
Reserved
Reserved
Reserved
Reserved
PORTE
DDRE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit 1
0
Bit 0
0
Bit 7
Bit 7
6
5
5
4
4
3
3
2
6
0
Bit 2
0
0
PEAR
NOACCE
MODC
PUPKE
PIPOE
NECLK
0
LSTRE
RDWE
0
MODE
MODB
0
MODA
0
IVIS
0
EMK
EME
0
0
0
0
PUCR
PUPEE
PUPBE PUPAE
0
0
0
0
0
0
0
0
0
RDRIV
RDPK
0
RDPE
0
RDPB
0
RDPA
EBICTL
Reserved
ESTR
0
0
0
0
$0010 - $0014
MMC map 1 of 4 (Core User Guide)
Address
$0010
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
0
Bit 1
0
Bit 0
RAMHAL
0
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
INITRM
RAM15 RAM14 RAM13 RAM12 RAM11
0
0
0
0
0
$0011
$0012
$0013
$0014
INITRG
INITEE
MISC
REG14
REG13
REG12
REG11
0
EE15
0
EE14
0
EE13
0
EE12
0
EEON
EXSTR1 EXSTR0 ROMHM ROMON
Bit 0
Bit 7
6
5
4
3
2
1
MTST0
Test Only
30
MC9S12H256 Device User Guide — V01.20
$0015 - $0016
INT map 1 of 2 (Core User Guide)
Address
$0015
Name
ITCR
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Read:
Write:
Read:
Write:
WRINT
ADR3
ADR2
ADR1
ADR0
$0016
ITEST
INTE
INTC
INTA
INT8
INT6
INT4
INT2
INT0
$0017 - $0017
MMC map 2 of 4 (Core User Guide)
Address
$0017
Name
Bit 7
Bit 7
Bit 6
6
Bit 5
5
Bit 4
4
Bit 3
3
Bit 2
2
Bit 1
1
Bit 0
Bit 0
Read:
Write:
MTST1
Test Only
$0018 - $001B
Miscellaneous Peripherals (Device User Guide, Table 1-5)
Address
$0018
Name
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Reserved
0
0
0
0
0
0
0
0
$0019
$001A
$001B
Reserved
PARTIDH
PARTIDL
ID15
ID7
ID14
ID6
ID13
ID5
ID12
ID4
ID11
ID3
ID10
ID2
ID9
ID1
ID8
ID0
$001C - $001D
MMC map 3 of 4 (Core and Device User Guide, Table 1-6)
Address
$001C
Name
Bit 7
Read: reg_sw0
Write:
Bit 6
0
Bit 5
Bit 4
Bit 3
0
Bit 2
Bit 1
Bit 0
eep_sw1 eep_sw0
ram_sw2 ram_sw1 ram_sw0
MEMSIZ0
Read: rom_sw1 rom_sw0
Write:
0
0
0
0
pag_sw1 pag_sw0
$001D
MEMSIZ1
$001E - $001E
MEBI map 2 of 3 (Core User Guide)
Address
$001E
Name
Bit 7
Bit 6
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
Read:
Write:
INTCR
IRQE
IRQEN
$001F - $001F
INT map 2 of 2 (Core User Guide)
Address
$001F
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
Read:
Write:
HPRIO
PSEL7
PSEL6
PSEL5
PSEL4
PSEL3
PSEL2
PSEL1
31
MC9S12H256 Device User Guide — V01.20
$0020 - $0027
Reserved
Address
Name
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
Read:
Write:
$0020 -
$0027
Reserved
$0028 - $002F
BKP (Core User Guide)
Address
$0028
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
BKPCT0
BKEN
BKFULL BKBDM BKTAG
$0029
$002A
$002B
$002C
$002D
$002E
$002F
BKPCT1
BKP0X
BKP0H
BKP0L
BKP1X
BKP1H
BKP1L
BK0MBH BK0MBL BK1MBH BK1MBL BK0RWE BK0RW BK1RWE BK1RW
0
0
BK0V5
BK0V4
BK0V3
BK0V2
BK0V1
BK0V0
Bit 8
Bit 15
14
13
12
11
10
9
Bit 7
0
6
0
5
BK1V5
13
4
BK1V4
12
3
BK1V3
11
2
BK1V2
10
1
Bit 0
BK1V1
BK1V0
Bit 8
Bit 15
Bit 7
14
6
9
1
5
4
3
2
Bit 0
$0030 - $0031
MMC map 4 of 4 (Core User Guide)
Address
$0030
Name
Bit 7
0
Bit 6
0
Bit 5
PIX5
0
Bit 4
PIX4
0
Bit 3
PIX3
0
Bit 2
PIX2
0
Bit 1
PIX1
0
Bit 0
PIX0
0
Read:
Write:
Read:
Write:
PPAGE
0
0
$0031
Reserved
$0032 - $0033
MEBI map 3 of 3 (Core User Guide)
Address
$0032
Name
Bit 7
Bit 7
Bit 6
6
Bit 5
5
Bit 4
4
Bit 3
3
Bit 2
2
Bit 1
1
Bit 0
Bit 0
Read:
Write:
Read:
Write:
PORTK
$0033
DDRK
Bit 7
6
5
4
3
2
1
Bit 0
32
MC9S12H256 Device User Guide — V01.20
$0034 - $003F
CRG (Clock and Reset Generator)
Address
$0034
Name
SYNR
Bit 7
0
Bit 6
0
Bit 5
SYN5
0
Bit 4
SYN4
0
Bit 3
Bit 2
Bit 1
Bit 0
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
SYN3
SYN2
SYN1
SYN0
0
0
0
0
$0035
$0036
$0037
$0038
$0039
$003A
$003B
$003C
$003D
$003E
$003F
REFDV
REFDV3 REFDV2 REFDV1 REFDV0
0
0
0
0
0
LOCK
0
0
TRACK
0
0
0
SCM
0
CTFLG
TEST ONLY
CRGFLG
CRGINT
CLKSEL
PLLCTL
RTICTL
RTIF
RTIE
PORF
0
LOCKIF
LOCKIE
SCMIF
SCMIE
PLLSEL
PSTP
PLLON
RTR6
SYSWAI ROAWAI PLLWAI
0
CWAI
PRE
RTIWAI COPWAI
CME
0
AUTO
ACQ
PCE
SCME
RTR0
RTR5
0
RTR4
0
RTR3
0
RTR2
RTR1
COPCTL
WCOP
0
RSBCK
0
CR2
0
CR1
0
CR0
0
0
0
0
0
0
0
FORBYP
TEST ONLY
0
0
0
0
0
CTCTL
TEST ONLY
0
Bit 7
0
6
0
5
0
4
0
3
0
2
0
1
0
Bit 0
ARMCOP
$0040 - $006F
TIM (Timer 16 Bit 8 Channels)
Address
$0040
Name
TIOS
Bit 7
IOS7
0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Read:
Write:
Read:
IOS6
IOS5
IOS4
IOS3
IOS2
IOS1
IOS0
0
0
0
0
0
0
0
$0041
$0042
$0043
$0044
$0045
$0046
$0047
$0048
$0049
CFORC
OC7M
Write: FOC7
Read:
FOC6
FOC5
FOC4
FOC3
FOC2
FOC1
FOC0
OC7M7 OC7M6 OC7M5 OC7M4 OC7M3 OC7M2 OC7M1 OC7M0
OC7D7 OC7D6 OC7D5 OC7D4 OC7D3 OC7D2 OC7D1 OC7D0
Write:
Read:
Write:
OC7D
Read: Bit 15
Write:
14
6
13
5
12
4
11
3
10
2
9
1
0
Bit 8
Bit 0
0
TCNT (hi)
TCNT (lo)
TSCR1
TTOV
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Bit 7
0
0
TEN
TOV7
OM7
OM3
TSWAI
TOV6
OL7
TSFRZ
TOV5
OM6
TFFCA
TOV4
OL6
TOV3
OM5
OM1
TOV2
OL5
TOV1
OM4
OM0
TOV0
OL4
TCTL1
TCTL2
OL3
OM2
OL2
OL1
OL0
33
MC9S12H256 Device User Guide — V01.20
$0040 - $006F
TIM (Timer 16 Bit 8 Channels)
Address
$004A
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
TCTL3
EDG7B EDG7A EDG6B EDG6A EDG5B EDG5A EDG4B EDG4A
EDG3B EDG3A EDG2B EDG2A EDG1B EDG1A EDG0B EDG0A
$004B
$004C
$004D
$004E
$004F
$0050
$0051
$0052
$0053
$0054
$0055
$0056
$0057
$0058
$0059
$005A
$005B
$005C
$005D
$005E
$005F
$0060
$0061
$0062
TCTL4
TIE
C7I
TOI
C6I
0
C5I
0
C4I
0
C3I
C2I
C1I
C0I
TSCR2
TFLG1
TCRE
PR2
PR1
PR0
C7F
C6F
0
C5F
0
C4F
0
C3F
0
C2F
0
C1F
0
C0F
0
TFLG2
TOF
TC0 (hi)
TC0 (lo)
TC1 (hi)
TC1 (lo)
TC2 (hi)
TC2 (lo)
TC3 (hi)
TC3 (lo)
TC4 (hi)
TC4 (lo)
TC5 (hi)
TC5 (lo)
TC6 (hi)
TC6 (lo)
TC7 (hi)
TC7 (lo)
PACTL
Bit 15
Bit 7
14
6
13
5
12
4
11
3
10
2
9
Bit 8
Bit 0
Bit 8
Bit 0
Bit 8
Bit 0
Bit 8
Bit 0
Bit 8
Bit 0
Bit 8
Bit 0
Bit 8
Bit 0
Bit 8
Bit 0
PAI
1
Bit 15
Bit 7
14
6
13
5
12
4
11
3
10
2
9
1
Bit 15
Bit 7
14
6
13
5
12
4
11
3
10
2
9
1
Bit 15
Bit 7
14
6
13
5
12
4
11
3
10
2
9
1
Bit 15
Bit 7
14
6
13
5
12
4
11
3
10
2
9
1
Bit 15
Bit 7
14
6
13
5
12
4
11
3
10
2
9
1
Bit 15
Bit 7
14
6
13
5
12
4
11
3
10
2
9
1
Bit 15
14
6
13
5
12
4
11
3
10
2
9
1
Bit 7
0
PAEN
0
PAMOD PEDGE
CLK1
0
CLK0
0
PAOVI
PAOVF
1
0
0
0
PAFLG
PAIF
Bit 0
PACNT (hi)
Bit 7
6
5
4
3
2
34
MC9S12H256 Device User Guide — V01.20
$0040 - $006F
TIM (Timer 16 Bit 8 Channels)
Address
$0063
Name
Bit 7
Bit 7
Bit 6
6
Bit 5
5
Bit 4
4
Bit 3
3
Bit 2
2
Bit 1
1
Bit 0
Bit 0
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
PACNT (lo)
$0064
$0065
$0066
$0067
$0068
$0069
$006A
$006B
$006C
$006D
$006E
$006F
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0
0
0
0
0
0
TIMTST
Test Only
TCBYP PCBYP
Reserved
Reserved
$0070 - $007F
Reserved
Address
Name
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
Read:
Write:
$0070 -
$007F
Reserved
$0080 - $00AF
ATD (Analog to Digital Converter 10 Bit 16 Channel)
Address
$0080
Name
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
ATDCTL0
0
0
0
0
0
0
0
0
$0081
$0082
$0083
$0084
$0085
ATDCTL1
ATDCTL2
ATDCTL3
ATDCTL4
ATDCTL5
ASCIF
ADPU
0
AFFC
S8C
AWAI ETRIGLE ETRIGP ETRIG
ASCIE
FRZ1
PRS1
CB
S4C
S2C
PRS4
MULT
S1C
PRS3
CD
FIFO
PRS2
CC
FRZ0
PRS0
CA
SRES8
DJM
SMP1
DSGN
SMP0
SCAN
35
MC9S12H256 Device User Guide — V01.20
$0080 - $00AF
ATD (Analog to Digital Converter 10 Bit 16 Channel)
Address
$0086
Name
Bit 7
SCF
Bit 6
0
Bit 5
ETORF
Bit 4
FIFOR
Bit 3
CC3
Bit 2
CC2
Bit 1
CC1
Bit 0
CC0
Read:
Write:
Read:
Write:
ATDSTAT0
0
0
0
0
0
0
0
0
$0087
$0088
$0089
$008A
$008B
$008C
$008D
$008E
$008F
$0090
$0091
$0092
$0093
$0094
$0095
$0096
$0097
$0098
$0099
$009A
$009B
$009C
$009D
$009E
Reserved
ATDTEST0
ATDTEST1
ATDSTAT2
ATDSTAT1
ATDDIEN0
ATDDIEN1
PORTAD0
PORTAD1
ATDDR0H
ATDDR0L
ATDDR1H
ATDDR1L
ATDDR2H
ATDDR2L
ATDDR3H
ATDDR3L
ATDDR4H
ATDDR4L
ATDDR5H
ATDDR5L
ATDDR6H
ATDDR6L
ATDDR7H
Read: SAR9
Write:
Read: SAR1
Write:
Read: CCF15
Write:
Read: CCF7
Write:
SAR8
SAR0
CCF14
CCF6
SAR7
0
SAR6
0
SAR5
0
SAR4
SAR3
ATDCLK
CCF9
CCF1
SAR2
RST
SC
CCF13
CCF5
CCF12
CCF4
CCF11
CCF3
CCF10
CCF8
CCF2
10
CCF0
Bit 8
Read:
Bit 15
Write:
14
13
12
11
9
Read:
Write:
Bit 7
6
5
4
3
2
1
9
Bit 0
Bit8
Read: Bit15
Write:
14
13
12
11
10
Read:
Write:
Bit7
6
14
6
5
13
5
4
12
4
3
11
3
2
10
2
1
9
1
9
1
9
1
9
1
9
1
9
1
9
1
9
BIT 0
Bit8
Bit0
Bit8
Bit0
Bit8
Bit0
Bit8
Bit0
Bit8
Bit0
Bit8
Bit0
Bit8
Bit0
Bit8
Read: Bit15
Write:
Read:
Write:
Bit7
Read: Bit15
Write:
14
6
13
5
12
4
11
3
10
2
Read:
Write:
Bit7
Read: Bit15
Write:
14
6
13
5
12
4
11
3
10
2
Read:
Write:
Bit7
Read: Bit15
Write:
14
6
13
5
12
4
11
3
10
2
Read:
Write:
Bit7
Read: Bit15
Write:
14
6
13
5
12
4
11
3
10
2
Read:
Write:
Bit7
Read: Bit15
Write:
14
6
13
5
12
4
11
3
10
2
Read:
Write:
Bit7
Read: Bit15
Write:
14
6
13
5
12
4
11
3
10
2
Read:
Write:
Bit7
Read: Bit15
Write:
14
13
12
11
10
36
MC9S12H256 Device User Guide — V01.20
$0080 - $00AF
ATD (Analog to Digital Converter 10 Bit 16 Channel)
Address
$009F
Name
Bit 7
Bit7
Bit 6
6
Bit 5
5
Bit 4
4
Bit 3
3
Bit 2
2
Bit 1
1
Bit 0
Bit0
Read:
Write:
ATDDR7L
Read: Bit15
Write:
14
6
13
5
12
4
11
3
10
2
9
1
9
1
9
1
9
1
9
1
9
1
9
1
9
1
Bit8
Bit0
Bit8
Bit0
Bit8
Bit0
Bit8
Bit0
Bit8
Bit0
Bit8
Bit0
Bit8
Bit0
Bit8
Bit0
$00A0
$00A1
$00A2
$00A3
$00A4
$00A5
$00A6
$00A7
$00A8
$00A9
$00AA
$00AB
$00AC
$00AD
$00aE
$00AF
ATDDR8H
ATDDR8L
Read:
Write:
Bit7
Read: Bit15
Write:
14
6
13
5
12
4
11
3
10
2
ATDDR9H
ATDDR9L
Read:
Write:
Bit7
Read: Bit15
Write:
14
6
13
5
12
4
11
3
10
2
ATDDR10H
ATDDR10L
ATDDR11H
ATDDR11L
ATDDR12H
ATDDR12L
ATDDR13H
ATDDR13L
ATDDR14H
ATDDR14L
ATDDR15H
ATDDR15L
Read:
Write:
Bit7
Read: Bit15
Write:
14
6
13
5
12
4
11
3
10
2
Read:
Write:
Bit7
Read: Bit15
Write:
14
6
13
5
12
4
11
3
10
2
Read:
Write:
Bit7
Read: Bit15
Write:
14
6
13
5
12
4
11
3
10
2
Read:
Write:
Bit7
Read: Bit15
Write:
14
6
13
5
12
4
11
3
10
2
Read:
Write:
Bit7
Read: Bit15
Write:
14
6
13
5
12
4
11
3
10
2
Read:
Write:
Bit7
$00B0 - $00BF
Reserved
Address
Name
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
Read:
Write:
$00B0 -
$00BF
Reserved
$00C0 - $00C7
IIC (Inter IC Bus)
Address
$00C0
Name
IBAD
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
Read:
Write:
Read:
Write:
ADR7
ADR6
ADR5
ADR4
ADR3
ADR2
ADR1
$00E1
IBFD
IBC7
IBC6
IBC5
IBC4
IBC3
IBC2
IBC1
IBC0
37
MC9S12H256 Device User Guide — V01.20
$00C0 - $00C7
IIC (Inter IC Bus)
Address
$00C2
Name
IBCR
Bit 7
IBEN
TCF
Bit 6
IBIE
Bit 5
MS/SL
IBB
Bit 4
Bit 3
TXAK
0
Bit 2
0
RSTA
SRW
Bit 1
0
Bit 0
IBSWAI
RXAK
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
TX/RX
IAAS
$00C3
$00C4
$00C5
$00C6
$00C7
IBSR
IBAL
IBIF
IBDR
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D 0
0
Reserved
Reserved
Reserved
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
$00C8 - $00CF
SCI0 (Asynchronous Serial Interface)
Address
$00C8
Name
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
SCI0BDH
SBR12
SBR11
SBR10
SBR9
SBR8
$00C9
$00CA
$00CB
$00CC
$00CD
$00CE
$00CF
SCI0BDL
SCI0CR1
SCI0CR2
SCI0SR1
SCI0SR2
SCI0DRH
SCI0DRL
SBR7
SBR6
SBR5
SBR4
M
SBR3
SBR2
ILT
SBR1
PE
SBR0
PT
LOOPS SCISWAI RSRC
WAKE
TIE
TCIE
TC
RIE
ILIE
TE
RE
NF
RWU
FE
SBK
PF
Read: TDRE
Write:
RDRF
IDLE
OR
Read:
Write:
Read:
Write:
Read:
Write:
0
0
0
0
0
0
0
0
RAF
0
BRK13
0
TXDIR
0
R8
T8
R7
T7
R6
T6
R5
T5
R4
T4
R3
T3
R2
T2
R1
T1
R0
T0
$00D0 - $00D7
SCI1 (Asynchronous Serial Interface) only on MC9S12H256
Address
$00D0
Name
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
SCI1BDH
SBR12
SBR11
SBR10
SBR9
SBR8
$00D1
$00D2
$00D3
$00D4
SCI1BDL
SCI1CR1
SCI1CR2
SCI1SR1
SBR7
SBR6
SBR5
SBR4
M
SBR3
SBR2
ILT
SBR1
PE
SBR0
PT
LOOPS SCISWAI RSRC
WAKE
TIE
TCIE
TC
RIE
ILIE
TE
RE
NF
RWU
FE
SBK
PF
Read: TDRE
Write:
RDRF
IDLE
OR
38
MC9S12H256 Device User Guide — V01.20
$00D0 - $00D7
SCI1 (Asynchronous Serial Interface) only on MC9S12H256
Address
$00D5
Name
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
BRK13
0
Bit 1
TXDIR
0
Bit 0
RAF
Read:
Write:
Read:
Write:
Read:
Write:
SCI1SR2
R8
0
0
0
0
$00D6
$00D7
SCI1DRH
SCI1DRL
T8
R7
T7
R6
T6
R5
T5
R4
T4
R3
T3
R2
T2
R1
T1
R0
T0
$00D8 - $00DF
SPI (Serial Peripheral Interface)
Address
$00D8
Name
Bit 7
SPIE
0
Bit 6
SPE
0
Bit 5
SPTIE
0
Bit 4
Bit 3
Bit 2
CPHA
0
Bit 1
Bit 0
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
SPICR1
MSTR
CPOL
SSOE
LSBFE
$00D9
$00DA
$00DB
$00DC
$00DD
$00DE
$00DF
SPICR2
SPIBR
MODFEN BIDIROE
SPISWAI SPC0
0
SPIF
0
0
SPPR2
0
SPPR1
SPTEF
SPPR0
SPR2
0
SPR1
0
SPR0
0
MODF
0
0
0
SPISR
0
0
0
0
0
Reserved
SPIDR
Bit7
0
6
0
5
0
4
0
3
0
2
0
1
0
Bit0
0
Reserved
Reserved
0
0
0
0
0
0
0
0
$00E0 - $00FF
PWM (Pulse Width Modulator 8 Bit 6 Channel)
Address
$00E0
Name
Bit 7
0
Bit 6
0
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
PWME
PWME5 PWME4 PWME3 PWME2 PWME1 PWME0
0
0
0
0
0
0
0
0
0
$00E1
$00E2
$00E3
$00E4
$00E5
$00E6
$00E7
$00E8
PWMPOL
PWMCLK
PWMPRCLK
PWMCAE
PWMCTL
PPOL5
PCLK5
PCKB1
CAE5
PPOL4
PCLK4
PCKB0
CAE4
PPOL3
PPOL2
PCLK2
PCKA2
CAE2
PPOL1
PCLK1
PCKA1
PPOL0
PCLK0
PCKA0
PCLK3
0
PCKB2
0
CAE3
CAE1
0
CAE0
0
CON45 CON23 CON01
PSWAI
0
PFRZ
0
0
0
0
0
0
0
0
0
0
0
PWMTST
Test Only
0
3
0
2
PWMPRSC
Test Only
PWMSCLA
Bit 7
6
5
4
1
Bit 0
39
MC9S12H256 Device User Guide — V01.20
$00E0 - $00FF
PWM (Pulse Width Modulator 8 Bit 6 Channel)
Address
$00E9
Name
Bit 7
Bit 7
0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 0
0
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
PWMSCLB
6
0
5
0
4
0
3
0
2
0
1
0
PWMSCNTA
Test Only
$00EA
$00EB
$00EC
$00ED
$00EE
$00EF
$00F0
$00F1
$00F2
$00F3
$00F4
$00F5
$00F6
$00F7
$00F8
$00F9
$00FA
$00FB
$00FC
$00FD
$00FE
$00FF
0
0
0
0
0
0
0
0
PWMSCNTB
Test Only
Bit 7
0
Bit 7
0
Bit 7
0
Bit 7
0
Bit 7
0
Bit 7
0
6
0
6
0
6
0
6
0
6
0
6
0
5
0
5
0
5
0
5
0
5
0
5
0
4
0
4
0
4
0
4
0
4
0
4
0
3
0
3
0
3
0
3
0
3
0
3
0
2
0
2
0
2
0
2
0
2
0
2
0
1
0
1
0
1
0
1
0
1
0
1
0
Bit 0
0
Bit 0
0
Bit 0
0
Bit 0
0
Bit 0
0
Bit 0
0
PWMCNT0
PWMCNT1
PWMCNT2
PWMCNT3
PWMCNT4
PWMCNT5
PWMPER0
PWMPER1
PWMPER2
PWMPER3
PWMPER4
PWMPER5
PWMDTY0
PWMDTY1
PWMDTY2
PWMDTY3
PWMDTY4
PWMDTY5
PWMSDN
Reserved
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
6
6
6
6
6
6
6
6
6
6
6
6
5
5
5
5
5
5
5
5
5
5
5
5
4
4
4
4
4
4
4
4
4
4
4
4
3
3
3
3
3
3
3
3
3
3
3
2
2
2
2
2
2
2
2
2
2
2
1
1
1
1
1
1
1
1
1
1
1
1
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
3
0
2
PWM5IN
PWMRSTRT
PWMIF PWMIE
PWMLVL
0
PWM5INL PWM5ENA
0
0
0
0
0
0
0
40
MC9S12H256 Device User Guide — V01.20
$0100 - $010F
Flash Control Register (fts256k)
Address
$0100
Name
Bit 7
Read: FDIVLD
Write:
Read: KEYEN
Write:
Bit 6
PRDIV8
NV6
Bit 5
FDIV5
NV5
Bit 4
FDIV4
NV4
Bit 3
FDIV3
NV3
Bit 2
FDIV2
NV2
Bit 1
FDIV1
SEC1
Bit 0
FDIV0
SEC0
FCLKDIV
$0101
$0102
$0103
$0104
$0105
$0106
$0107
$0108
$0109
$010A
$010B
FSEC
Reserved
FCNFG
FPROT
FSTAT
Read:
Write:
0
0
0
0
0
0
0
0
WRALL
0
0
Read:
CBEIE
Write:
CCIE
KEYACC
BKSEL1 BKSEL0
Read:
Write:
FPOPEN
NV6
FPHDIS FPHS1
FPHS0 FPLDIS
FPLS1
0
FPLS0
0
Read:
CBEIF
Write:
CCIF
0
PVIOL ACCERR
0
BLANK
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
0
0
0
0
0
0
FCMD
CMDB6 CMDB5
CMDB2
CMDB0
0
0
0
0
0
0
Reserved for
Factory Test
FADDRHI
FADDRLO
FDATAHI
FDATALO
Reserved
Bit 14
6
13
5
12
4
11
3
10
2
9
1
9
Bit 8
Bit 0
Bit 8
Bit 7
Bit 15
14
13
12
11
10
Bit 7
0
6
0
5
0
4
0
3
0
2
0
1
0
Bit 0
0
$010C -
$010F
$0110 - $011B
EEPROM Control Register (eets4k)
Address
$0110
Name
Bit 7
Read: EDIVLD
Write:
Bit 6
PRDIV8
0
Bit 5
EDIV5
0
Bit 4
EDIV4
0
Bit 3
EDIV3
0
Bit 2
EDIV2
0
Bit 1
EDIV1
0
Bit 0
EDIV0
0
ECLKDIV
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
0
$0111
$0112
$0113
$0114
$0115
$0116
$0117
$0118
Reserved
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reserved for
Factory Test
ECNFG
EPROT
ESTAT
ECMD
CBEIE
CCIE
EPOPEN
NV6
NV5
NV4
EPDIS
0
EP2
EP1
0
EP0
0
CCIF
CBEIF
0
PVIOL ACCERR
0
BLANK
0
0
0
0
0
CMDB6 CMDB5
CMDB2
0
CMDB0
0
0
0
0
0
0
0
0
0
Reserved for
Factory Test
EADDRHI
10
9
Bit 8
41
MC9S12H256 Device User Guide — V01.20
$0110 - $011B
EEPROM Control Register (eets4k)
Address
$0119
Name
Bit 7
Bit 7
Bit 6
6
Bit 5
5
Bit 4
4
Bit 3
3
Bit 2
2
Bit 1
1
Bit 0
Bit 0
Read:
Write:
Read:
Write:
Read:
Write:
EADDRLO
$011A
$011B
EDATAHI
EDATALO
Bit 15
Bit 7
14
6
13
5
12
4
11
3
10
2
9
1
Bit 8
Bit 0
$011C - $011F
Reserved for RAM Control Register
Address
Name
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
Read:
Write:
$011C -
$011F
Reserved
$0120 - $0137
LCD (Liquid Crystal Display 32 frontplanes, 4 backplanes)
Address
$0120
Name
Bit 7
LCDEN
0
Bit 6
0
Bit 5
LCLK2
0
Bit 4
LCLK1
0
Bit 3
LCLK0
0
Bit 2
BIAS
0
Bit 1
Bit 0
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
LCDCR0
DUTY1
DUTY0
0
LCDSWAI LCDRPSTP
$0121
$0122
$0123
$0124
$0125
$0126
$0127
$0128
$0129
$012A
$012B
$012C
$012D
$012E
$012F
LCDCR1
FPENR0
FPEN7
FPEN6
FPEN5
FPEN4
FPEN3
FPEN2
FPEN1
FPEN0
FPEN8
FPENR1
FPEN15 FPEN14 FPEN13 FPEN12 FPEN11 FPEN10 FPEN9
FPENR2
FPEN23 FPEN22 FPEN21 FPEN20 FPEN19 FPEN18 FPEN17 FPEN16
FPEN31 FPEN30 FPEN29 FPEN28 FPEN27 FPEN26 FPEN25 FPEN24
FPENR3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reserved
Reserved
LCDRAM0
LCDRAM1
LCDRAM2
LCDRAM3
LCDRAM4
LCDRAM5
LCDRAM6
LCDRAM7
FP1BP3 FP1BP2 FP1BP1 FP1BP0 FP0BP3 FP0BP2 FP0BP1 FP0BP0
FP3BP3 FP3BP2 FP3BP1 FP3BP0 FP2BP3 FP2BP2 FP2BP1 FP2BP0
FP5BP3 FP5BP2 FP5BP1 FP5BP0 FP4BP3 FP4BP2 FP4BP1 FP4BP0
FP7BP3 FP7BP2 FP7BP1 FP7BP0 FP6BP3 FP6BP2 FP6BP1 FP6BP0
FP9BP3 FP9BP2 FP9BP1 FP9BP0 FP8BP3 FP8BP2 FP8BP1 FP8BP0
FP11BP3 FP11BP2 FP11BP1 FP11BP0 FP10BP3 FP10BP2 FP10BP1 FP10BP0
FP13BP3 FP13BP2 FP13BP1 FP13BP0 FP12BP3 FP12BP2 FP12BP1 FP12BP0
FP15BP3 FP15BP2 FP15BP1 FP15BP0 FP14BP3 FP14BP2 FP14BP1 FP14BP0
42
MC9S12H256 Device User Guide — V01.20
$0120 - $0137
LCD (Liquid Crystal Display 32 frontplanes, 4 backplanes)
Address
$0130
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
LCDRAM8
FP17BP3 FP17BP2 FP17BP1 FP17BP0 FP16BP3 FP16BP2 FP16BP1 FP16BP0
FP19BP3 FP19BP2 FP19BP1 FP19BP0 FP18BP3 FP18BP2 FP18BP1 FP18BP0
FP21BP3 FP21BP2 FP21BP1 FP21BP0 FP20BP3 FP20BP2 FP20BP1 FP20BP0
FP23BP3 FP23BP2 FP23BP1 FP23BP0 FP22BP3 FP22BP2 FP22BP1 FP22BP0
FP25BP3 FP25BP2 FP25BP1 FP25BP0 FP24BP3 FP24BP2 FP24BP1 FP24BP0
FP27BP3 FP27BP2 FP27BP1 FP27BP0 FP26BP3 FP26BP2 FP26BP1 FP26BP0
FP29BP3 FP29BP2 FP29BP1 FP29BP0 FP28BP3 FP28BP2 FP28BP1 FP28BP0
FP31BP3 FP31BP2 FP31BP1 FP31BP0 FP30BP3 FP30BP2 FP30BP1 FP30BP0
$0131
$0132
$0133
$0134
$0135
$0136
$0137
LCDRAM9
LCDRAM10
LCDRAM11
LCDRAM12
LCDRAM13
LCDRAM14
LCDRAM15
$0140 - $017F
CAN0 (Freescale Scalable CAN - MSCAN)
Address
$0140
Name
Bit 7
Bit 6
RXACT
Bit 5
Bit 4
SYNCH
Bit 3
TIME
0
Bit 2
Bit 1
Bit 0
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
CAN0CTL0
RXFRM
CSWAI
WUPE
SLPRQ INITRQ
SLPAK
BRP1
INITAK
BRP0
$0141
$0142
$0143
$0144
$0145
$0146
$0147
$0148
$0149
$014A
$014B
$014C
$014D
$014E
CAN0CTL1
CAN0BTR0
CAN0BTR1
CAN0RFLG
CAN0RIER
CAN0TFLG
CAN0TIER
CAN0TARQ
CAN0TAAK
CAN0TBSEL
CAN0IDAC
Reserved
CANE CLKSRC LOOPB LISTEN
SJW1 SJW0 BRP5 BRP4
WUPM
BRP2
BRP3
SAMP TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10
RSTAT1 RSTAT0 TSTAT1 TSTAT0
WUPIF
CSCIF
OVRIF
RXF
RXFIE
TXE0
WUPIE
0
CSCIE RSTATE1 RSTATE0 TSTATE1 TSTATE0 OVRIE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TXE2
TXE1
0
0
0
0
0
0
0
TXEIE2 TXEIE1 TXEIE0
ABTRQ2 ABTRQ1 ABTRQ0
ABTAK2 ABTAK1 ABTAK0
TX2
TX1
TX0
IDHIT2
IDHIT1
IDHIT0
IDAM1
0
IDAM0
0
0
0
0
0
0
0
0
0
Reserved
Read: RXERR7 RXERR6 RXERR5 RXERR4 RXERR3 RXERR2 RXERR1 RXERR0
Write:
CAN0RXERR
43
MC9S12H256 Device User Guide — V01.20
$0140 - $017F
CAN0 (Freescale Scalable CAN - MSCAN)
Address
$014F
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Read: TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 TXERR2 TXERR1 TXERR0
CAN0TXERR
Write:
Read:
$0150 - CAN0IDAR0 -
$0153 CAN0IDAR3
$0154 - CAN0IDMR0 -
$0157 CAN0IDMR3
$0158 - CAN0IDAR4 -
$015B CAN0IDAR7
$015C - CAN0IDMR4 -
AC7
AM7
AC7
AM7
AC6
AM6
AC6
AM6
AC5
AM5
AC5
AM5
AC4
AM4
AC4
AM4
AC3
AM3
AC3
AM3
AC2
AM2
AC2
AM2
AC1
AM1
AC1
AM1
AC0
AM0
AC0
AM0
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
$015F
CAN0IDMR7
FOREGROUND RECEIVE BUFFER see Table 1-3
$0160 -
$016F
CAN0RXFG
$0170 -
$017F
CAN0TXFG
FOREGROUND TRANSMIT BUFFER see Table 1-3
Table 1-3 Detailed MSCAN Foreground Receive and Transmit Buffer Layout
Address
$0160
Name
Bit 7
ID28
ID10
Bit 6
ID27
ID9
Bit 5
ID26
ID8
Bit 4
ID25
ID7
Bit 3
ID24
ID6
Bit 2
ID23
ID5
Bit 1
ID22
ID4
Bit 0
ID21
ID3
Extended ID Read:
Standard ID Read:
CAN0RIDR0 Write:
Extended ID Read:
Standard ID Read:
CAN0RIDR1 Write:
Extended ID Read:
Standard ID Read:
CAN0RIDR2 Write:
Extended ID Read:
Standard ID Read:
CAN0RIDR3 Write:
ID20
ID2
ID19
ID1
ID18
ID0
SRR=1
RTR
IDE=1
IDE=0
ID17
ID9
ID16
ID8
ID15
ID7
$0161
$0162
ID14
ID6
ID13
ID5
ID12
ID4
ID11
ID3
ID10
ID2
ID1
ID0
RTR
$0163
Read:
Write:
Read:
Write:
Read:
Write:
Read: TSR15
Write:
Read: TSR7
Write:
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
$0164- CAN0RDSR0 -
$016B
CAN0RDSR7
DLC3
DLC2
DLC1
DLC0
$016C
CAN0RDLR
$016D
$016E
$016F
Reserved
TSR14
TSR6
TSR13
TSR5
TSR12
TSR4
TSR11
TSR3
TSR10
TSR2
TSR9
TSR1
TSR8
TSR0
CAN0RTSRH
CAN0RTSRL
Extended ID Read:
CAN0TIDR0 Write:
Standard ID Read:
Write:
Extended ID Read:
CAN0TIDR1 Write:
Standard ID Read:
Write:
ID28
ID10
ID20
ID2
ID27
ID9
ID26
ID8
ID25
ID7
ID24
ID6
ID23
ID5
ID22
ID4
ID21
ID3
$0170
$0171
ID19
ID1
ID18
ID0
SRR=1
RTR
IDE=1
IDE=0
ID17
ID16
ID15
44
MC9S12H256 Device User Guide — V01.20
Table 1-3 Detailed MSCAN Foreground Receive and Transmit Buffer Layout
Address
Name
Bit 7
ID14
Bit 6
ID13
Bit 5
ID12
Bit 4
ID11
Bit 3
ID10
Bit 2
ID9
Bit 1
ID8
Bit 0
ID7
Extended ID Read:
CAN0TIDR2 Write:
Standard ID Read:
Write:
$0172
Extended ID Read:
CAN0TIDR3 Write:
Standard ID Read:
Write:
ID6
DB7
ID5
ID4
ID3
ID2
ID1
ID0
RTR
$0173
Read:
Write:
Read:
Write:
Read:
Write:
$0174- CAN0TDSR0 -
DB6
DB5
DB4
DB3
DB2
DB1
DB0
$017B
CAN0TDSR7
$017C
CAN0TDLR
DLC3
DLC2
DLC1
DLC0
$017D
$017E
$017F
CON0TTBPR
CAN0TTSRH
CAN0TTSRL
PRIO7
PRIO6
TSR14
PRIO5
TSR13
PRIO4
TSR12
PRIO3
TSR11
PRIO2
TSR10
PRIO1
TSR9
PRIO0
TSR8
Read: TSR15
Write:
Read: TSR7
Write:
TSR6
TSR5
TSR4
TSR3
TSR2
TSR1
TSR0
$0180 - $01BF
CAN1 (Freescale Scalable CAN - MSCAN)
Address
$0180
Name
Bit 7
Bit 6
RXACT
Bit 5
Bit 4
SYNCH
Bit 3
TIME
0
Bit 2
Bit 1
Bit 0
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
CAN1CTL0
RXFRM
CSWAI
WUPE
SLPRQ INITRQ
SLPAK
INITAK
$0181
$0182
$0183
$0184
$0185
$0186
$0187
$0188
$0189
$018A
$018B
$018C
$018D
CAN1CTL1
CAN1BTR0
CAN1BTR1
CAN1RFLG
CAN1RIER
CAN1TFLG
CAN1TIER
CAN1TARQ
CAN1TAAK
CAN1TBSEL
CAN1IDAC
Reserved
CANE CLKSRC LOOPB LISTEN
SJW1 SJW0 BRP5 BRP4
WUPM
BRP2
BRP3
BRP1
BRP0
SAMP TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10
RSTAT1 RSTAT0 TSTAT1 TSTAT0
WUPIF
CSCIF
OVRIF
RXF
RXFIE
TXE0
WUPIE
0
CSCIE RSTATE1 RSTATE0 TSTATE1 TSTATE0 OVRIE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TXE2
TXE1
0
0
0
0
0
0
0
TXEIE2 TXEIE1 TXEIE0
ABTRQ2 ABTRQ1 ABTRQ0
ABTAK2 ABTAK1 ABTAK0
TX2
TX1
TX0
IDHIT2
IDHIT1
IDHIT0
IDAM1
0
IDAM0
0
0
0
0
0
0
0
0
0
Reserved
45
MC9S12H256 Device User Guide — V01.20
$0180 - $01BF
CAN1 (Freescale Scalable CAN - MSCAN)
Address
$018E
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Read: RXERR7 RXERR6 RXERR5 RXERR4 RXERR3 RXERR2 RXERR1 RXERR0
CAN1RXERR
Write:
Read: TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 TXERR2 TXERR1 TXERR0
$018F
CAN1TXERR
Write:
Read:
$0190 - CAN1IDAR0 -
$0193 CAN1IDAR3
$0194 - CAN1IDMR0 -
$0197 CAN1IDMR3
$0198 - CAN1IDAR4 -
$019B CAN1IDAR7
$019C - CAN1IDMR4 -
AC7
AM7
AC7
AM7
AC6
AM6
AC6
AM6
AC5
AM5
AC5
AM5
AC4
AM4
AC4
AM4
AC3
AM3
AC3
AM3
AC2
AM2
AC2
AM2
AC1
AM1
AC1
AM1
AC0
AM0
AC0
AM0
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
$019F
CAN1IDMR7
FOREGROUND RECEIVE BUFFER see Table 1-3
$01A0 -
$01AF
CAN1RXFG
$01B0 -
$01BF
CAN1TXFG
FOREGROUND TRANSMIT BUFFER see Table 1-3
Table 1-4 Detailed MSCAN Foreground Receive and Transmit Buffer Layout
Address
$01A0
Name
Bit 7
ID28
ID10
Bit 6
ID27
ID9
Bit 5
ID26
ID8
Bit 4
ID25
ID7
Bit 3
ID24
ID6
Bit 2
ID23
ID5
Bit 1
ID22
ID4
Bit 0
ID21
ID3
Extended ID Read:
Standard ID Read:
CAN1RIDR0 Write:
Extended ID Read:
Standard ID Read:
CAN1RIDR1 Write:
Extended ID Read:
Standard ID Read:
CAN1RIDR2 Write:
Extended ID Read:
Standard ID Read:
CAN1RIDR3 Write:
ID20
ID2
ID19
ID1
ID18
ID0
SRR=1
RTR
IDE=1
IDE=0
ID17
ID9
ID16
ID8
ID15
ID7
$01A1
$01A2
ID14
ID6
ID13
ID5
ID12
ID4
ID11
ID3
ID10
ID2
ID1
ID0
RTR
$01A3
Read:
Write:
Read:
Write:
Read:
Write:
Read: TSR15
Write:
Read: TSR7
Write:
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
$01A4- CAN1RDSR0 -
$01AB
CAN1RDSR7
DLC3
DLC2
DLC1
DLC0
$01AC
CAN1RDLR
$01AD
$01AE
$01AF
Reserved
TSR14
TSR6
TSR13
TSR5
TSR12
TSR4
TSR11
TSR3
TSR10
TSR2
TSR9
TSR1
TSR8
TSR0
CAN1RTSRH
CAN1RTSRL
Extended ID Read:
CAN1TIDR0 Write:
Standard ID Read:
Write:
ID28
ID10
ID27
ID9
ID26
ID8
ID25
ID7
ID24
ID6
ID23
ID5
ID22
ID4
ID21
ID3
$01B0
46
MC9S12H256 Device User Guide — V01.20
Table 1-4 Detailed MSCAN Foreground Receive and Transmit Buffer Layout
Address
Name
Bit 7
ID20
Bit 6
ID19
Bit 5
ID18
Bit 4
Bit 3
Bit 2
ID17
Bit 1
ID16
Bit 0
ID15
Extended ID Read:
CAN1TIDR1 Write:
Standard ID Read:
Write:
Extended ID Read:
CAN1TIDR2 Write:
Standard ID Read:
Write:
Extended ID Read:
CAN1TIDR3 Write:
Standard ID Read:
Write:
SRR=1
IDE=1
$01B1
ID2
ID1
ID0
RTR
ID11
IDE=0
ID10
ID14
ID13
ID12
ID9
ID1
ID8
ID0
ID7
$01B2
ID6
DB7
ID5
ID4
ID3
ID2
RTR
$01B3
Read:
Write:
Read:
Write:
Read:
Write:
$01B4- CAN1TDSR0 -
$01BB
DB6
DB5
DB4
DB3
DB2
DB1
DB0
CAN1TDSR7
$01BC
CAN1TDLR
DLC3
DLC2
DLC1
DLC0
$01BD
$01BE
$01BF
CON1TTBPR
CAN1TTSRH
CAN1TTSRL
PRIO7
PRIO6
TSR14
PRIO5
TSR13
PRIO4
TSR12
PRIO3
TSR11
PRIO2
TSR10
PRIO1
TSR9
PRIO0
TSR8
Read: TSR15
Write:
Read: TSR7
Write:
TSR6
TSR5
TSR4
TSR3
TSR2
TSR1
TSR0
$01C0 - $01FF
MC (Motor Controller 10bit 12 channels)
Address
$01C0
Name
Bit 7
0
Bit 6
Bit 5
Bit 4
Bit 3
FAST
0
Bit 2
DITH
0
Bit 1
0
Bit 0
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
MCCTL0
MCPRE1 MCPRE0 MCSWAI
MCTOIF
0
0
0
0
0
0
0
$01C1
$01C2
$01C3
$01C4
$01C5
$01C6
$01C7
$01C8
$01C9
$01CA
$01CB
MCCTL1
MCPER (hi)
MCPER (lo)
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
RECIRC
0
MCTOIE
P8
0
P10
P9
P7
0
P6
0
P5
0
P4
0
P3
0
P2
0
P1
0
P0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
47
MC9S12H256 Device User Guide — V01.20
$01C0 - $01FF
MC (Motor Controller 10bit 12 channels)
Address
$01CC
Name
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Reserved
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
S
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
$01CD
$01CE
$01CF
$01D0
$01D1
$01D2
$01D3
$01D4
$01D5
$01D6
$01D7
$01D8
$01D9
$01DA
$01DB
$01DC
$01DD
$01DE
$01DF
$01E0
$01E1
$01E2
$01E3
$01E4
Reserved
Reserved
Reserved
MCCC0
OM1
OM1
OM1
OM1
OM1
OM1
OM1
OM1
OM1
OM1
OM1
OM0
OM0
OM0
OM0
OM0
OM0
OM0
OM0
OM0
OM0
OM0
AM1
AM1
AM1
AM1
AM1
AM1
AM1
AM1
AM1
AM1
AM1
AM0
AM0
AM0
AM0
AM0
AM0
AM0
AM0
AM0
AM0
AM0
CD1
CD1
CD1
CD1
CD1
CD1
CD1
CD1
CD1
CD1
CD1
CD0
CD0
CD0
CD0
CD0
CD0
CD0
CD0
CD0
CD0
CD0
MCCC1
MCCC2
MCCC3
MCCC4
MCCC5
MCCC6
MCCC7
MCCC8
MCCC9
MCCC10
MCCC11
Reserved
Reserved
Reserved
Reserved
MCDC0 (hi)
MCDC0 (lo)
MCDC1 (hi)
MCDC1 (lo)
MCDC2 (hi)
OM1
0
OM0
0
AM1
0
AM0
0
CD1
0
CD0
0
0
0
0
0
0
0
S
0
0
0
S
0
0
0
S
0
0
0
0
0
0
S
D7
S
D10
D2
D9
D1
D9
D1
D9
D8
D0
D8
D0
D8
D6
S
D5
S
D4
S
D3
S
D10
D2
D7
S
D6
S
D5
S
D4
S
D3
S
D10
48
MC9S12H256 Device User Guide — V01.20
$01C0 - $01FF
MC (Motor Controller 10bit 12 channels)
Address
$01E5
Name
Bit 7
D7
Bit 6
D6
S
Bit 5
D5
S
Bit 4
D4
S
Bit 3
D3
S
Bit 2
D2
Bit 1
D1
Bit 0
D0
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
MCDC2 (lo)
$01E6
$01E7
$01E8
$01E9
$01EA
$01EB
$01EC
$01ED
$01EE
$01EF
$01F0
$01F1
$01F2
$01F3
$01F4
$01F5
$01F6
$01F7
$01F8
$01F9
$01FA
$01FB
$01FC
MCDC3 (hi)
MCDC3 (lo)
MCDC4 (hi)
MCDC4 (lo)
MCDC5 (hi)
MCDC5 (lo)
MCDC6 (hi)
MCDC6 (lo)
MCDC7 (hi)
MCDC7 (lo)
MCDC8 (hi)
MCDC8 (lo)
MCDC9 (hi)
MCDC9 (lo)
MCDC10 (hi)
MCDC10 (lo)
MCDC11 (hi)
MCDC11 (lo)
Reserved
S
D7
S
D10
D2
D9
D1
D9
D1
D9
D1
D9
D1
D9
D1
D9
D1
D9
D1
D9
D1
D9
D8
D0
D8
D0
D8
D0
D8
D0
D8
D0
D8
D0
D8
D0
D8
D0
D8
D6
S
D5
S
D4
S
D3
S
D10
D2
D7
S
D6
S
D5
S
D4
S
D3
S
D10
D2
D7
S
D6
S
D5
S
D4
S
D3
S
D10
D2
D7
S
D6
S
D5
S
D4
S
D3
S
D10
D2
D7
S
D6
S
D5
S
D4
S
D3
S
D10
D2
D7
S
D6
S
D5
S
D4
S
D3
S
D10
D2
D7
S
D6
S
D5
S
D4
S
D3
S
D10
D2
D7
S
D6
S
D5
S
D4
S
D3
S
D10
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reserved
Reserved
Reserved
Reserved
49
MC9S12H256 Device User Guide — V01.20
$01C0 - $01FF
MC (Motor Controller 10bit 12 channels)
Address
$01FD
Name
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
Read:
Write:
Read:
Write:
Read:
Write:
Reserved
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
$01FE
$01FF
Reserved
Reserved
$0200 - $027F
PIM (Port Integration Module)
Address
$0200
Name
PTT
Bit 7
Bit 6
PTT6
PTIT6
Bit 5
PTT5
PTIT5
Bit 4
PTT4
PTIT4
Bit 3
PTT3
PTIT3
Bit 2
PTT2
PTIT2
Bit 1
PTT1
PTIT1
Bit 0
PTT0
PTIT0
Read:
Write:
PTT7
Read: PTIT7
Write:
$0201
$0202
$0203
$0204
$0205
$0206
$0207
$0208
$0209
$020A
$020B
$020C
$020D
$020E
$020F
$0210
$0211
$0212
PTIT
DDRT
RDRT
PERT
Read:
DDRT7 DDRT7 DDRT5 DDRT4 DDRT3 DDRT2 DDRT1 DDRT0
RDRT7 RDRT6 RDRT5 RDRT4 RDRT3 RDRT2 RDRT1 RDRT0
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
PERT7
PERT6
PERT5
PERT4
PERT3
PERT2
PERT1
PERT0
PPST
PPST7
0
PPST6
0
PPST5
0
PPST4
0
PPST3
0
PPST2
0
PPST1
0
PPST0
0
Reserved
Reserved
PTS
0
0
0
0
0
0
0
0
PTS7
PTS6
PTS5
PTS4
PTS3
PTS2
PTS1
PTS0
Read: PTIS7
Write:
PTIS6
PTIS5
PTIS4
PTIS3
PTIS2
PTIS1
PTIS0
PTIS
Read:
DDRS
RDRS
PERS
PPSS
WOMS
Reserved
PTM
DDRS7 DDRS7 DDRS5 DDRS4 DDRS3 DDRS2 DDRS1 DDRS0
RDRS7 RDRS6 RDRS5 RDRS4 RDRS3 RDRS2 RDRS1 RDRS0
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
PERS7
PPSS7
PERS6
PPSS6
PERS5
PPSS5
PERS4
PPSS4
PERS3
PPSS3
PERS2
PPSS2
PERS1
PPSS1
PERS0
PPSS0
WOMS7 WOMS6 WOMS5 WOMS4 WOMS3 WOMS2 WOMS1 WOMS0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PTM5
PTM4
PTM3
PTM2
PTM1
PTM0
PTIM5
PTIM4
PTIM3
PTIM2
PTIM1
PTIM0
PTIM
DDRM
DDRM5 DDRM4 DDRM3 DDRM2 DDRM1 DDRM0
50
MC9S12H256 Device User Guide — V01.20
$0200 - $027F
PIM (Port Integration Module)
Address
$0213
Name
Bit 7
0
Bit 6
0
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
RDRM
RDRM5 RDRM4 RDRM3 RDRM2 RDRM1 RDRM0
PERM5 PERM4 PERM3 PERM2 PERM1 PERM0
PPSM5 PPSM4 PPSM3 PPSM2 PPSM1 PPSM0
WOMM5 WOMM4 WOMM3 WOMM2 WOMM1 WOMM0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
$0214
$0215
$0216
$0217
$0218
$0219
$021A
$021B
$021C
$021D
$021E
$021F
$0220
$0221
$0222
$0223
$0224
$0225
$0226
$0227
$0228
$0229
$022A
$022B
PERM
PPSM
WOMM
Reserved
PTP
0
0
0
0
0
0
PTP5
PTP4
PTP3
PTP2
PTP1
PTP0
PTIP5
PTIP4
PTIP3
PTIP2
PTIP1
PTIP0
PTIP
DDRP
RDRP
PERP
PPSP
Reserved
Reserved
PTH
DDRP5 DDRP4 DDRP3 DDRP2 DDRP1 DDRP0
RDRP5 RDRP4 RDRP3 RDRP2 RDRP1 RDRP0
PERP5
PERP4
PERP3
PERP2
PERP1
PERP0
PPSP5
0
PPSP4
0
PPSP3
0
PPSP2
0
PPSP1
0
PPSS0
0
0
0
0
0
0
0
PTH7
PTH6
PTH5
PTH4
PTH3
PTH2
PTH1
PTH0
Read: PTIH7
Write:
PTIH6
PTIH5
PTIH4
PTIH3
PTIH2
PTIH1
PTIH0
PTIH
Read:
DDRH
RDRH
PERH
PPSH
PIEH
DDRH7 DDRH7 DDRH5 DDRH4 DDRH3 DDRH2 DDRH1 DDRH0
RDRH7 RDRH6 RDRH5 RDRH4 RDRH3 RDRH2 RDRH1 RDRH0
PERH7 PERH6 PERH5 PERH4 PERH3 PERH2 PERH1 PERH0
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
PPSH7
PIEH7
PPSH6
PIEH6
PPSH5
PIEH5
PPSH4
PIEH4
PPSH3
PIEH3
PIFH3
PPSH2
PIEH2
PIFH2
PPSH1
PIEH1
PIFH1
PPSH0
PIEH0
PIFH0
PIFH
PIFH7
0
PIFH6
0
PIFH5
0
PIFH4
0
PTJ
PTJ3
PTJ2
PTJ1
PTJ0
0
0
0
0
0
0
0
0
0
0
0
0
PTIJ3
PTIJ2
PTIJ1
PTIJ0
PTIJ
DDRJ
RDRJ
DDRJ3
RDRJ3
DDRJ2
RDRJ2
DDRJ1
RDRJ1
DDRJ0
RDRJ0
51
MC9S12H256 Device User Guide — V01.20
$0200 - $027F
PIM (Port Integration Module)
Address
$022C
Name
PERJ
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
Bit 2
Bit 1
Bit 0
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
PERJ3
PERJ2
PERJ1
PERJ0
0
0
0
0
0
0
0
0
0
0
0
0
$022D
$022E
$022F
$0230
$0231
$0232
$0233
$0234
$0235
$0236
$0237
$0238
$0239
$023A
$023B
$023C
$023D
$023E
$023F
$0240
$0241
$0242
$0243
$0244
PPSJ
PIEJ
PPSJ3
PIEJ3
PIFJ3
PPSJ2
PIEJ2
PIFJ2
PPSJ1
PIEJ1
PIFJ1
PPSJ0
PIEJ0
PIFJ0
PIFJ
PTL
PTL7
PTL6
PTL5
PTL4
PTL3
PTL2
PTL1
PTL0
Read: PTIL7
Write:
Read:
DDRL7
Write:
Read:
RDRL7
Write:
Read:
PERL7
Write:
PTIL6
PTIL5
PTIL4
PTIL3
PTIL2
PTIL1
PTIL0
PTIL
DDRL
RDRL
PERL
PPSL
Reserved
Reserved
PTU
DDRL7
RDRL6
PERL6
DDRL5
RDRL5
PERL5
DDRL4
RDRL4
PERL4
DDRL3
RDRL3
PERL3
DDRL2
RDRL2
PERL2
DDRL1
RDRL1
PERL1
DDRL0
RDRL0
PERL0
Read:
PPSL7
Write:
PPSL6
0
PPSL5
0
PPSL4
0
PPSL3
0
PPSL2
0
PPSL1
0
PPSL0
0
Read:
Write:
Read:
Write:
Read:
Write:
0
0
0
0
0
0
0
0
0
PTU7
PTU6
PTU5
PTU4
PTU3
PTU2
PTU1
PTU0
Read: PTIU7
Write:
PTIU6
PTIU5
PTIU4
PTIU3
PTIU2
PTIU1
PTIU0
PTIU
Read:
DDRU
SRRU
PERU
PPSU
Reserved
Reserved
PTV
DDRU7 DDRU7 DDRU5 DDRU4 DDRU3 DDRU2 DDRU1 DDRU0
SRRU7 SRRU6 SRRU5 SRRU4 SRRU3 SRRU2 SRRU1 SRRU0
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
PERU7
PERU6
PERU5
PERU4
PERU3
PERU2
PERU1
PERU0
PPSU7
0
PPSU6
0
PPSU5
0
PPSU4
0
PPSU3
0
PPSU2
0
PPSU1
0
PPSU0
0
0
0
0
0
0
0
0
0
PTV7
PTV6
PTV5
PTV4
PTV3
PTV2
PTV1
PTV0
Read: PTIV7
Write:
PTIV6
PTIV5
PTIV4
PTIV3
PTIV2
PTIV1
PTIV0
PTIV
Read:
DDRV
SRRV
PERV
DDRV7 DDRV7 DDRV5 DDRV4 DDRV3 DDRV2 DDRV1 DDRV0
Write:
Read:
Write:
Read:
Write:
SRRV7
PERV7
SRRV6
PERV6
SRRV5
PERV5
SRRV4
PERV4
SRRV3
PERV3
SRRV2
PERV2
SRRV1
PERV1
SRRV0
PERV0
52
MC9S12H256 Device User Guide — V01.20
$0200 - $027F
PIM (Port Integration Module)
Address
$0245
Name
PPSV
Bit 7
PPSV7
0
Bit 6
PPSV6
0
Bit 5
PPSV5
0
Bit 4
PPSV4
0
Bit 3
PPSV3
0
Bit 2
PPSV2
0
Bit 1
PPSV1
0
Bit 0
PPSV0
0
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
$0246
$0247
$0248
$0249
$024A
$024B
$024C
$024D
$024E
$024F
Reserved
Reserved
PTW
0
0
0
0
0
0
0
0
PTW7
PTW6
PTW5
PTW4
PTW3
PTW2
PTW1
PTW0
Read: PTIW7
Write:
PTIW6
PTIW5
PTIW4
PTIW3
PTIW2
PTIW1
PTIW0
PTIW
Read:
DDRW
DDRW7 DDRW7 DDRW5 DDRW4 DDRW3 DDRW2 DDRW1 DDRW0
SRRW7 SRRW6 SRRW5 SRRW4 SRRW3 SRRW2 SRRW1 SRRW0
PERW7 PERW6 PERW5 PERW4 PERW3 PERW2 PERW1 PERW0
PPSW7 PPSW6 PPSW5 PPSW4 PPSW3 PPSW2 PPSW1 PPSW0
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
SRRW
PERW
PPSW
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reserved
Reserved
Reserved
$0250 -
$027F
$0280 - $03FF
Reserved
Address
Name
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
Read:
Write:
$0280 -
$03FF
Reserved
1.6 Part ID Assignments
The part ID is located in two 8-bit registers PARTIDH and PARTIDL at addresses $001A,$001B,
respectively. The read-only value is a unique part ID for each revision of the chip. Table 1-5 shows the
assigned part ID numbers.
Table 1-5 Assigned Part ID Numbers
1
Device
Mask Set Number
0K78X
Part ID
$1000
$1001
MC9S12H256
MC9S12H256
1K78X
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MC9S12H256 Device User Guide — V01.20
NOTES:
1. The coding is as follows:
Bit 15-12: Major family identifier
Bit 11-8: Minor family identifier
Bit 7-4: Major mask set revision number including FAB transfers
Bit 3-0: Minor - non full - mask set revision
The device memory sizes are located in two 8-bit registers MEMSIZ0 and MEMSIZ1 (addresses $001C
and $001D after reset). Table 1-6 shows the read-only values of these registers. Refer to section Module
Mapping and Control (MMC) of HCS12 Core User Guide for further details.
Table 1-6 Memory size registers
Register name
MEMSIZ0
Value
$25
MEMSIZ1
$81
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MC9S12H256 Device User Guide — V01.20
Section 2 Signal Description
This section describes signals that connect off-chip. It includes a pinout diagram, a table of signal
properties, and detailed discussion of signals. It is built from the signal description sections of the Block
User Guides of the individual IP blocks on the device.
2.1 Device Pinout
The MC9S12H256 is available in a 112-pin and 144-pin quad flat pack (LQFP), the MC9S12H128 is
available in a 112-pin quad flat pack (LQFP). Most pins perform two or more functions, as described in
the Signal Descriptions. Figure 2-1 and Figure 2-2 show the pin assignments.
NOTE: In expanded narrow modes the lower byte data is multiplexed with higher byte data
through pins 64-71 on the 112-pin LQFP or through pins 111-118 on the 144-pin
LQFP version.
55
MC9S12H256 Device User Guide — V01.20
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
PB5/ADDR5/DATA5/FP5
PB4/ADDR4/DATA4/FP4
PB3/ADDR3/DATA3/FP3
PB2/ADDR2/DATA2/FP2
PB1/ADDR1/DATA1/FP1
PB0/ADDR0/DATA0/FP0
PK0/XADDR14/BP0
PK1/XADDR15/BP1
PK2/XADDR16/BP2
PK3/XADDR17/BP3
VLCD
VSS1
VDD1
PAD07/AN07
PAD06/AN06
PAD05/AN05
PAD04/AN04
PAD03/AN03
PAD02/AN02
PAD01/AN01
PAD00/AN00
VDDA
VRH
VRL
VSSA
PE0/XIRQ
PE4/ECLK
1
2
3
4
5
6
7
8
M0C0M/PU0
M0C0P/PU1
M0C1M/PU2
M0C1P/PU3
VDDM1
VSSM1
M1C0M/PU4
M1C0P/PU5
M1C1M/PU6
M1C1P/PU7
M2C0M/PV0
M2C0P/PV1
M2C1M/PV2
M2C1P/PV3
VDDM2
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
MC9S12H-Family
112 LQFP
VSSM2
M3C0M/PV4
M3C0P/PV5
M3C1M/PV6
M3C1P/PV7
M4C0M/PW0
M4C0P/PW1
M4C1M/PW2
M4C1P/PW3
VDDM3
VSSM3
M5C0M/PW4
M5C0P/PW5
PE6/IPIPE1/MODB
Figure 2-1 Pin Assignments in 112-pin LQFP for MC9S12H256 and MC9S12H128
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MC9S12H256 Device User Guide — V01.20
M0C0M/PU0
M0C0P/PU1
M0C1M/PU2
M0C1P/PU3
VDDM1
1
2
3
4
5
6
7
8
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
PB5/ADDR5/DATA5/FP5
PB4/ADDR4/DATA4/FP4
PB3/ADDR3/DATA3/FP3
PB2/ADDR2/DATA2/FP2
PB1/ADDR1/DATA1/FP1
PB0/ADDR0/DATA0/FP0
PK0/XADDR14/BP0
PK1/XADDR15/BP1
PK2/XADDR16/BP2
PK3/XADDR17/BP3
VLCD
VSSM1
M1C0M/PU4
M1C0P/PU5
M1C1M/PU6
M1C1P/PU7
KWH0/PH0
KWH1/PH1
KWH2/PH2
KWH3/PH3
M2C0M/PV0
M2C0P/PV1
M2C1M/PV2
M2C1P/PV3
VDDM2
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
VSS1
VDD1
PAD15/AN15
PAD07/AN07
PAD14/AN14
PAD06/AN06
PAD13/AN13
PAD05/AN05
PAD12/AN12
PAD04/AN04
PAD11/AN11
PAD03/AN03
PAD10/AN10
PAD02/AN02
PAD09/AN09
PAD01/AN01
PAD08/AN08
PAD00/AN00
VDDA
MC9S12H-Family
144 LQFP
VSSM2
M3C0M/PV4
M3C0P/PV5
M3C1M/PV6
M3C1P/PV7
KWH4/PH4
KWH5/PH5
KWH6/PH6
KWH7/PH7
M4C0M/PW0
M4C0P/PW1
M4C1M/PW2
M4C1P/PW3
VDDM3
VRH
VRL
VSSA
PE0/XIRQ
PE4/ECLK
PE6/IPIPE1/MODB
Pins shown in BOLD are not available in the 112 LQFP package
VSSM3
M5C0M/PW4
M5C0P/PW5
74
73
Figure 2-2 Pin Assignments in 144-pin LQFP for MC9S12H256
57
MC9S12H256 Device User Guide — V01.20
2.2 Signal Properties Summary
Table 2-1 summarizes all pin functions.
NOTE: Bold entries determine pins not available on 112-pin LQFP.
Table 2-1 Signal Properties
Internal Pull
Resistor
Pin Name Pin Name
Pin Name
Pin Name Powered
Description
Function 1 Function 2 Function 3 Function 4
by
Reset
CTRL
State
EXTAL
XTAL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VDDPLL
VDDPLL
VDDX2
Oscillator Pins
RESET
TEST
XFC
None
None
External Reset Pin
Test Input
VDDX2
VDDPLL
PLL Loop Filter
Always
Up
Background Debug, Tag High, Mode
Pin
BKGD
PAD[7:0]
PAD[15:8]
TAGHI
AN[7:0]
AN[15:8]
MODC
—
—
—
—
VDDX2
VDDA
VDDA
Up
Port AD Inputs, Analog Inputs (ATD)
None
None
Port AD Inputs, Analog Inputs
(ATD)
—
ADDR[15:8]/
DATA[15:8]
PUCR/
PUPAE
PA[7:0]
PB[7:0]
PE7
FP[15:8]
FP[7:0]
FP22
—
—
VDDX1
VDDX1
VDDX1
Down
Down
Down
Port A I/O, Multiplexed Address/Data
Port B I/O, Multiplexed Address/Data
ADDR[7:0]/
DATA[7:0]
PUCR/
PUPBE
PUCR/
PUPEE
Port E I/O, Access, Clock Select,
LCD driver
XCLKS
NOACC
PE6
PE5
PE4
IPIPE1
IPIPE0
ECLK
MODB
MODA
—
—
—
—
VDDX2
VDDX2
VDDX2
Port E I/O, Pipe Status, Mode Input
Port E I/O, Pipe Status, Mode Input
Port E I/O, Bus Clock Output
While RESET pin is
low: Down
Mode de- Port E I/O, LCD driver, Byte Strobe,
pendent Tag Low
PE3
FP21
LSTRB
TAGLO
VDDX1
PUCR/
PUPEE
PE2
PE1
PE0
FP20
IRQ
R/W
—
—
—
—
VDDX1
VDDX2
VDDX2
Port E I/O, R/W in expanded modes
Port E Input, Maskable Interrupt
Up
XIRQ
—
Port E Input, Non Maskable Interrupt
PERH/
PPSH
PH[7:0]
PJ[3:0]
PK7
KWH[7:0]
KWJ[3:0]
FP23
—
—
—
—
VDDM
VDDX1
VDDX1
VDDX1
Disabled Port H I/O, Interrupts
PERJ/
PPSJ
Disabled Port J I/O, Interrupts
Port K I/O, Emulation Chip Select,
ECS
ROMONE
—
ROM On Enable
PUCR/
PUPKE
Down
Port K I/O, LCD driver, Extended
PK[3:0]
BP[3:0]
XADDR[17:14]
Addresses
PL[3:0]
FP[19:16]
—
—
—
VDDX1
VDDX1
Port L I/O, LCD drivers
Down
PERL/
PPSL
PL[7:4]
FP[31:28]
—
Port L I/O, LCD drivers
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MC9S12H256 Device User Guide — V01.20
Internal Pull
Resistor
Description
Reset
Pin Name Pin Name
Pin Name
Pin Name Powered
Function 1 Function 2 Function 3 Function 4
by
CTRL
State
PM5
PM4
PM3
PM2
PM1
PM0
PP[5:2]
PP[1:0]
PS7
TXCAN1
RXCAN1
TXCAN0
RXCAN0
SCL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VDDX2
VDDX2
VDDX2
VDDX2
VDDX2
VDDX2
VDDX2
VDDX2
VDDX2
VDDX2
VDDX2
VDDX2
VDDX2
VDDX2
VDDX2
VDDX2
VDDX1
Port M I/O, TX of CAN1
Port M I/O, RX of CAN1
Port M I/O, TX of CAN0
Port M I/O, RX of CAN0
Port M I/O, SCL of IIC
Port M I/O, SDA of IIC
Port P I/O, PWM channels
Port P I/O, PWM channels
Port S I/O, SS of SPI
PERM/
PPSM
Disabled
SDA
PWM[5:2]
PWM[1:0]
SS
PERP/
PPSP
Disabled
Disabled
PS6
SCK
Port S I/O, SCK of SPI
Port S I/O, MOSI of SPI
Port S I/O, MISO of SPI
Port S I/O, TXD of SCI1
Port S I/O, RXD of SCI1
Port S I/O, TXD of SCI0
Port S I/O, RXD of SCI0
Port T I/O, Timer channels
PS5
MOSI
PS4
MISO
PERS/
PPSS
PS3
TXD1
PS2
RXD1
PS1
TXD0
PS0
RXD0
PT[7:4]
IOC[7:4]
PERT/
PPST
Down
Port T I/O, Timer channels, LCD
driver
PT[3:0]
PU[3:0]
IOC[3:0]
FP[27:24]
—
VDDX1
M0C0M
M0C0P
M0C1M
M0C1P
—
—
VDDM
Port U I/O, Motor0 of MC
Port U I/O, Motor1 of MC
Port V I/O, Motor2 of MC
Port V I/O, Motor3 of MC
Port W I/O, Motor4 of MC
Port W I/O, Motor5 of MC
PERU/
PPSU
Disabled
M1C0M
M1C0P
M1C1M
M1C1P
PU[7:4]
PV[3:0]
PV[7:4]
PW[3:0]
PW[7:4]
—
—
—
—
—
—
—
—
—
—
VDDM
VDDM
VDDM
VDDM
VDDM
M2C0M
M2C0P
M2C1M
M2C1P
PERV/
PPSV
Disabled
M3C0M
M3C0P
M3C1M
M3C1P
M4C0M
M4C0P
M4C1M
M4C1P
PERW/
PPSW
Disabled
M5C0M
M5C0P,
M5C1M
M5C1P
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MC9S12H256 Device User Guide — V01.20
2.3 Detailed Signal Descriptions
2.3.1 EXTAL, XTAL — Oscillator Pins
EXTAL and XTAL are the crystal driver and external clock pins. On reset all the device clocks are derived
from the EXTAL input frequency. XTAL is the crystal output.
2.3.2 RESET — External Reset Pin
An active low bidirectional control signal, it acts as an input to initialize the MCU to a known start-up
state, and an output when an internal MCU function causes a reset.
2.3.3 TEST — Test Pin
This pin is reserved for test.
NOTE: The TEST pin must be tied to VSS in all applications.
2.3.4 XFC — PLL Loop Filter Pin
Dedicated pin used to create the PLL loop filter.
2.3.5 BKGD / TAGHI / MODC — Background Debug, Tag High, and Mode Pin
The BKGD/TAGHI/MODC pin is used as a pseudo-open-drain pin for the background debug
communication. In MCU expanded modes of operation when instruction tagging is on, an input low on
this pin during the falling edge of E-clock tags the high half of the instruction word being read into the
instruction queue. It is used as a MCU operating mode select pin during reset. The state of this pin is
latched to the MODC bit at the rising edge of RESET.
2.3.6 PAD[15:8] / AN[15:8] — Port AD Input Pins [15:8]
PAD15-PAD8 are general purpose input pins and analog inputs for the analog to digital converter.
NOTE: These pins are not available in the 112-pin LQFP version.
2.3.7 PAD[7:0] / AN[7:0] — Port AD Input Pins [7:0]
PAD7-PAD0 are general purpose input pins and analog inputs for the analog to digital converter.
2.3.8 PA[7:0] / FP[15:8] / ADDR[15:8] / DATA[15:8] — Port A I/O Pins
PA7-PA0 are general purpose input or output pins. They can be configured as frontplane segment driver
outputs FP15-FP8 of the LCD. In MCU expanded modes of operation, these pins are used for the
multiplexed external address and data bus.
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MC9S12H256 Device User Guide — V01.20
2.3.9 PB[7:0] / FP[7:0] / ADDR[7:0] / DATA[7:0] — Port B I/O Pins
PB7-PB0 are general purpose input or output pins. They can be configured as frontplane segment driver
outputs FP7-FP0 of the LCD. In MCU expanded modes of operation, these pins are used for the
multiplexed external address and data bus.
2.3.10 PE7 / FP22 / XCLKS / NOACC — Port E I/O Pin 7
PE7 is a general purpose input or output pin. It can be configured as frontplane segment driver output FP22
of the LCD module. The XCLKS signal selects between an external clock or oscillator configuration
during reset.
The XCLKS input selects between an external clock or oscillator configuration. The state of this pin is
latched at the rising edge of RESET. If the input is a logic high the EXTAL pin is configured for an
external clock drive. If input is a logic low an oscillator circuit is configured on EXTAL and XTAL. Since
this pin is an input with a pull-down device during reset, if the pin is left floating, the default configuration
is an oscillator circuit on EXTAL and XTAL.
During MCU expanded modes of operation, the NOACC signal, when enabled, is used to indicate that the
current bus cycle is an unused or “free” cycle. This signal will assert when the CPU is not using the bus.
2.3.11 PE6 / MODB / IPIPE1 — Port E I/O Pin 6
PE6 is a general purpose input or output pin. It is used as a MCU operating mode select pin during reset.
The state of this pin is latched to the MODB bit at the rising edge of RESET. This pin is shared with the
instruction queue tracking signal IPIPE1. This pin is an input with a pull-down device which is only active
when RESET is low.
2.3.12 PE5 / MODA / IPIPE0 — Port E I/O Pin 5
PE5 is a general purpose input or output pin. It is used as a MCU operating mode select pin during reset.
The state of this pin is latched to the MODA bit at the rising edge of RESET. This pin is shared with the
instruction queue tracking signal IPIPE0. This pin is an input with a pull-down device which is only active
when RESET is low.
2.3.13 PE4 / ECLK — Port E I/O Pin 4
PE4 is a general purpose input or output pin. It can be configured to drive the internal bus clock ECLK.
ECLK can be used as a timing reference.
2.3.14 PE3 / FP21 / LSTRB / TAGLO — Port E I/O Pin 3
PE3 is a general purpose input or output pin. It can be configured as frontplane segment driver output FP21
of the LCD module. In MCU expanded modes of operation, LSTRB is used for the low-byte strobe
function to indicate the type of bus access and when instruction tagging is on, TAGLO is used to tag the
low half of the instruction word being read into the instruction queue.
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MC9S12H256 Device User Guide — V01.20
2.3.15 PE2 / FP20 / R/W — Port E I/O Pin 2
PE2 is a general purpose input or output pin. It can be configured as frontplane segment driver output FP20
of the LCD module. In MCU expanded modes of operations, this pin performs the read/write output signal
for the external bus. It indicates the direction of data on the external bus.
2.3.16 PE1 / IRQ — Port E Input Pin 1
PE1 is a general purpose input pin and also the maskable interrupt request input that provides a means of
applying asynchronous interrupt requests. This will wake up the MCU from STOP or WAIT mode.
2.3.17 PE0 / XIRQ — Port E Input Pin 0
PE0 is a general purpose input pin and also the non-maskable interrupt request input that provides a means
of applying asynchronous interrupt requests. This will wake up the MCU from STOP or WAIT mode.
2.3.18 PH[7:0] / KWH[7:0] — Port H I/O Pins [7:0]
PH7-PH0 are general purpose input or output pins. They can be configured to generate an interrupt causing
the MCU to exit STOP or WAIT mode.
NOTE: These pins are not available in the 112-pin LQFP version.
2.3.19 PJ[3:0] / KWJ[3:0] — Port J I/O Pins [3:0]
PJ3-PJ0 are general purpose input or output pins. They can be configured to generate an interrupt causing
the MCU to exit STOP or WAIT mode.and are shared with the interrupt function.
NOTE: These pins are not available in the 112-pin LQFP version.
2.3.20 PK7 / FP23 / ECS / ROMONE — Port K I/O Pin 7
PK7 is a general purpose input or output pin. It can be configured as frontplane segment driver output FP23
of the LCD module. During MCU expanded modes of operation, this pin is used as the emulation chip
select signal (ECS). During reset of the MCU to normal expanded modes of operation, this pin is used to
enable the Flash EEPROM memory in the memory map (ROMONE). At the rising edge of RESET, the
state of this pin is latched to the ROMON bit.
2.3.21 PK[3:0] / BP[3:0] / XADDR[17:14] — Port K I/O Pins [3:0]
PK3-PK0 are general purpose input or output pins. They can be configured as backplane segment driver
outputs BP3-BP0 of the LCD module. In MCU expanded modes of operation, these pins provide the
expanded address XADDR[17:14] for the external bus.
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MC9S12H256 Device User Guide — V01.20
2.3.22 FreescalePL[7:4] / FP[31:28] — Port L I/O Pins [7:4]
PL7-PL4 are general purpose input or output pins. They can be configured as frontplane segment driver
outputs FP31-FP28 of the LCD module.
NOTE: These pins are not available in the 112-pin LQFP version.
2.3.23 PL[3:0] / FP[19:16] — Port L I/O Pins [3:0]
PL3-PL0 are general purpose input or output pins. They can be configured as frontplane segment driver
outputs FP19-FP16 of the LCD module.
2.3.24 PM5 / TXCAN1 — Port M I/O Pin 5
PM5 is a general purpose input or output pin. It can be configured as the transmit pin TXCAN1 of the
Freescale Scalable Controller Area Network controller 1 (CAN1)
2.3.25 PM4 / RXCAN1 — Port M I/O Pin 4
PM4 is a general purpose input or output pin. It can be configured as the receive pin RXCAN1 of the
Freescale Scalable Controller Area Network controller 1 (CAN1)
2.3.26 PM3 / TXCAN0 — Port M I/O Pin 3
PM3 is a general purpose input or output pin. It can be configured as the transmit pin TXCAN0 of the
Freescale Scalable Controller Area Network controller 0 (CAN0)
2.3.27 PM2 / RXCAN0 — Port M I/O Pin 2
PM2 is a general purpose input or output pin. It can be configured as the receive pin RXCAN0 of the
Freescale Scalable Controller Area Network controller 0 (CAN0)
2.3.28 PM1 / SCL — Port M I/O Pin 1
PM1 is a general purpose input or output pin. It can be configured as the serial clock pin SCL of the
Inter-IC Bus Interface (IIC).
NOTE: This pin is not available in the 112-pin LQFP version.
2.3.29 PM0 / SDA — Port M I/O Pin 0
PM0 is a general purpose input or output pin. It can be configured as the serial data pin SDA of the Inter-IC
Bus Interface (IIC).
NOTE: This pin is not available in the 112-pin LQFP version.
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MC9S12H256 Device User Guide — V01.20
2.3.30 PP[5:2] / PWM[5:2] — Port P I/O Pins [5:2]
PP5-PP2 are general purpose input or output pins. They can be configured as Pulse Width Modulator
(PWM) channel outputs PWM5-PWM2.
NOTE: These pins are not available in the 112-pin LQFP version.
2.3.31 PP[1:0] / PWM[1:0] — Port P I/O Pins [1:0]
PP1-PP0 are general purpose input or output pins. They can be configured as Pulse Width Modulator
(PWM) channel outputs PWM1-PWM0.
2.3.32 PS7 / SS — Port S I/O Pin 7
PS7 is a general purpose input or output pin. It can be configured as slave select pin SS of the Serial
Peripheral Interface (SPI).
2.3.33 PS6 / SCK — Port S I/O Pin 6
PS6 is a general purpose input or output pin. It can be configured as serial clock pin SCK of the Serial
Peripheral Interface (SPI).
2.3.34 PS5 / MOSI — Port S I/O Pin 5
PS5 is a general purpose input or output pin. It can be configured as the master output (during master
mode) or slave input (during slave mode) pin MOSI of the Serial Peripheral Interface (SPI).
2.3.35 PS4 / MISO — Port S I/O Pin 4
PS4 is a general purpose input or output pin. It can be configured as master input (during master mode) or
slave output (during slave mode) pin MISO for the Serial Peripheral Interface (SPI).
2.3.36 PS3 / TXD1 — Port S I/O Pin 3
PS3 is a general purpose input or output pin. It can be configured as transmit pin TXD1 of the Serial
Communication Interface 1 (SCI1).
NOTE: This pin is not available in the 112-pin LQFP version.
2.3.37 PS2 / RXD1 — Port S I/O Pin 2
PS2 is a general purpose input or output pin. It can be configured as receive pin RXD1 of the Serial
Communication Interface 1 (SCI1).
NOTE: This pin is not available in the 112-pin LQFP version.
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MC9S12H256 Device User Guide — V01.20
2.3.38 PS1 / TXD0 — Port S I/O Pin 1
PS1 is a general purpose input or output pin. It can be configured as transmit pin TXD0 of the Serial
Communication Interface 0 (SCI0).
2.3.39 PS0 / RXD0 — Port S I/O Pin 0
PS0 is a general purpose input or output pin. It can be configured as receive pin RXD0 of the Serial
Communication Interface 0 (SCI0).
2.3.40 PT[7:4] / IOC[7:4] — Port T I/O Pins [7:4]
PT7-PT4 are general purpose input or output pins. They can be configured as input capture or output
compare pins IOC7-IOC4 of the Timer (TIM).
2.3.41 PT[3:0] / IOC[3:0] / FP[27:24] — Port T I/O Pins [3:0]
PT3-PT0 are general purpose input or output pins. They can be configured as input capture or output
compare pins IOC3-IOC0 of the Timer (TIM). They can be configured as frontplane segment driver
outputs FP27-FP24 of the LCD module.
2.3.42 PU[7:4] / M1C1P, M1C1M, M1C0P, M1C0M — Port U I/O Pins [7:4]
PU7-PU4 are general purpose input or output pins. They can be configured as high current PWM output
pins which can be used for motor drive. These pins interface to the coils of motor 1. PWM output on
M1C0M results in a positive current flow through coil 0 when M1C0P is driven to a logic high state. PWM
output on M1C1M results in a positive current flow through coil 1 when M1C1P is driven to a logic high
state.
2.3.43 PU[3:0] / M0C1P, M0C1M, M0C0P, M0C0M — Port U I/O Pins [3:0]
PU3-PU0 are general purpose input or output pins. They can be configured as high current PWM output
pins which can be used for motor drive. These pins interface to the coils of motor 0. PWM output on
M0C0M results in a positive current flow through coil 0 when M0C0P is driven to a logic high state. PWM
output on M0C1M results in a positive current flow through coil 1 when M0C1P is driven to a logic high
state.
2.3.44 PV[7:4] / M3C1P, M3C1M, M3C0P, M3C0M — Port V I/O Pins [7:4]
PV7-PV4 are general purpose input or output pins. They can be configured as high current PWM output
pins which can be used for motor drive. These pins interface to the coils of motor 3. PWM output on
M3C0M results in a positive current flow through coil 0 when M3C0P is driven to a logic high state. PWM
output on M3C1M results in a positive current flow through coil 1 when M3C1P is driven to a logic high
state.
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2.3.45 PV[3:0] / M2C1P, M2C1M, M2C0P, M2C0M — Port V I/O Pins [3:0]
PV3-PV0 are general purpose input or output pins. They can be configured as high current PWM output
pins which can be used for motor drive. These pins interface to the coils of motor 2. PWM output on
M2C0M results in a positive current flow through coil 0 when M2C0P is driven to a logic high state. PWM
output on M2C1M results in a positive current flow through coil 1 when M2C1P is driven to a logic high
state.
2.3.46 PW[7:4] / M5C1P, M5C1M, M5C0P, M5C0M — Port W I/O Pins [7:4]
PW7-PW4 are general purpose input or output pins. They can be configured as high current PWM output
pins which can be used for motor drive. These pins interface to the coils of motor 5. PWM output on
M5C0M results in a positive current flow through coil 0 when M5C0P is driven to a logic high state. PWM
output on M5C1M results in a positive current flow through coil 1 when M5C1P is driven to a logic high
state.
2.3.47 PW[3:0] / M4C1P, M4C1M, M4C0P, M4C0M — Port W I/O Pins [3:0]
PW3-PW0 are general purpose input or output pins. They can be configured as high current PWM output
pins which can be used for motor drive. These pins interface to the coils of motor 4. PWM output on
M4C0M results in a positive current flow through coil 0 when M4C0P is driven to a logic high state. PWM
output on M4C1M results in a positive current flow through coil 1 when M4C1P is driven to a logic high
state.
2.4 Power Supply Pins
MC9S12H256 power and ground pins are described below.
NOTE: All VSS pins must be connected together in the application (21.2 Recommended
PCB layout).
Because fast signal transitions place high, short-duration current demands on the
power supply, use bypass capacitors with high-frequency characteristics and place
them as close to the MCU as possible. Bypass requirements depend on how heavily
the MCU pins are loaded (Table 21-1).
2.4.1 VDDR — External Power Pin
VDDR is the power supply pin for the internal voltage regulator.
2.4.2 VDDX1, VDDX2, VSSX1, VSSX2 — External Power and Ground Pins
VDDX1, VDDX2, VSSX1 and VSSX2 are the power supply and ground pins for input/output
drivers.VDDX1 and VDDX2 as well as VSSX1 and VSSX2 are not internally connected.
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2.4.3 VDD1, VSS1, VSS2 — Core Power Pins
VDD1, VSS1 and VSS2 are the core power and ground pins and related to the voltage regulator output.
These pins serve as connection points for filter capacitors. VSS1 and VSS2 are internally connected.
NOTE: No load allowed except for bypass capacitors.
2.4.4 VDDA, VSSA — Power Supply Pins for ATD and VREG
VDDA, VSSA are the power supply and ground pins for the voltage regulator and the analog to digital
converter.
2.4.5 VDDM1, VDDM2, VDDM3 — Power Supply Pins for Motor 0 to 5
VDDM1, VDDM2 and VDDM3 are the supply pins for the ports U,V and W. VDDM1, VDDM2 and
VDDM3 are internally connected.
2.4.6 VSSM1, VSSM2, VSSM3 — Ground Pins for Motor 0 to 5
VSSM1, VSSM2 and VSSM3 are the ground pins for the ports U,V and W. VSSM1, VSSM2 and VSSM3
are internally connected.
2.4.7 VLCD — Power Supply Reference Pin for LCD driver
VLCD is the voltage reference pin for the LCD driver. Adjusting the voltage on this pin will change the
display contrast.
2.4.8 VRH, VRL — ATD Reference Voltage Input Pins
VRH and VRL are the voltage reference pins for the analog to digital converter.
2.4.9 VDDPLL, VSSPLL — Power Supply Pins for PLL
VDDPLL and VSSPLL are the PLL supply pins and serve as connection points for external loop filter
components.
NOTE: No load allowed except for bypass capacitors.
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Section 3 System Clock Description
3.1 Overview
The Clock and Reset Generator provides the internal clock signals for the core and all peripheral modules.
Figure 3-1 shows the clock connections from the CRG to all modules.
Consult the CRG Block User Guide for details on clock generation.
S12_CORE
core clock
Flash
RAM
EEPROM
TIM
ATD
EXTAL
XTAL
PWM
bus clock
CRG
SCI0, SCI1
SPI
oscillator clock
CAN0, CAN1
IIC
MC
LCD
PIM
Figure 3-1 Clock Connections
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Section 4 Modes of Operation
4.1 Overview
Eight possible modes determine the operating configuration of the MC9S12H256. Each mode has an
associated default memory map and external bus configuration.
Three low power modes exist for the device.
4.2 Modes of Operation
The operating mode out of reset is determined by the states of the MODC, MODB, and MODA pins during
reset (Table 4-1). The MODC, MODB, and MODA bits in the MODE register show the current operating
mode and provide limited mode switching during operation. The states of the MODC, MODB, and MODA
pins are latched into these bits on the rising edge of the reset signal.
Table 4-1 Mode Selection
MODC
MODB
MODA
Mode Description
Special Single Chip, BDM allowed and ACTIVE. BDM is allowed in all
other modes but a serial command is required to make BDM active.
0
0
0
0
0
0
1
1
0
1
1
0
0
1
0
1
0
1
Emulation Expanded Narrow, BDM allowed
Special Test (Expanded Wide) (Freescale Use Only), BDM allowed
Emulation Expanded Wide, BDM allowed
Normal Single Chip, BDM allowed
Normal Expanded Narrow, BDM allowed
Peripheral (Freescale Use Only); BDM allowed but bus operations
would cause bus conflicts (must not be used)
1
1
1
1
0
1
Normal Expanded Wide, BDM allowed
There are two basic types of operating modes:
1. Normal modes: Some registers and bits are protected against accidental changes.
2. Special modes: Allow greater access to protected control registers and bits for special purposes such
as testing.
A system development and debug feature, background debug mode (BDM), is available in all modes. In
special single-chip mode, BDM is active immediately after reset.
Some aspects of Port E are not mode dependent. Bit 1 of Port E is a general purpose input or the IRQ
interrupt input. IRQ can be enabled by bits in the CPU’s condition codes register but it is inhibited at reset
so this pin is initially configured as a simple input with a pull-up. Bit 0 of Port E is a general purpose input
or the XIRQ interrupt input. XIRQ can be enabled by bits in the CPU’s condition codes register but it is
inhibited at reset so this pin is initially configured as a simple input with a pull-up. The ESTR bit in the
EBICTL register is set to one by reset in any user mode. This assures that the reset vector can be fetched
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MC9S12H256 Device User Guide — V01.20
even if it is located in an external slow memory device. The PE6/MODB/IPIPE1 and PE5/MODA/IPIPE0
pins act as high-impedance mode select inputs during reset.
The following paragraphs discuss the default bus setup and describe which aspects of the bus can be
changed after reset on a per mode basis.
4.2.1 Normal Operating Modes
These modes provide three operating configurations. Background debug is available in all three modes,
but must first be enabled for some operations by means of a BDM background command, then activated.
4.2.1.1 Normal Single-Chip Mode
There is no external expansion bus in this mode. All pins of Ports A, B and E are configured as general
purpose I/O pins Port E bits 1 and 0 are available as general purpose input only pins with internal pull-ups
enabled. All other pins of Port E are bidirectional I/O pins that are initially configured as high-impedance
inputs with internal pull-ups enabled. Ports A and B are configured as high-impedance inputs with their
internal pull-ups disabled.
The pins associated with Port E bits 6, 5, 3, and 2 cannot be configured for their alternate functions IPIPE1,
IPIPE0, LSTRB, and R/W while the MCU is in single chip modes. In single chip modes, the associated
control bits PIPOE, LSTRE, and RDWE are reset to zero. Writing the opposite state into them in single
chip mode does not change the operation of the associated Port E pins.
In normal single chip mode, the MODE register is writable one time. This allows a user program to change
the bus mode to narrow or wide expanded mode and/or turn on visibility of internal accesses.
Port E, bit 4 can be configured for a free-running E clock output by clearing NECLK=0. Typically the only
use for an E clock output while the MCU is in single chip modes would be to get a constant speed clock
for use in the external application system.
4.2.1.2 Normal Expanded Wide Mode
In expanded wide modes, Ports A and B are configured as a 16-bit multiplexed address and data bus and
Port E bit 4 is configured as the E clock output signal. These signals allow external memory and peripheral
devices to be interfaced to the MCU.
Port E pins other than PE4/ECLK are configured as general purpose I/O pins (initially high-impedance
inputs with internal pull-up resistors enabled). Control bits PIPOE, NECLK, LSTRE, and RDWE in the
PEAR register can be used to configure Port E pins to act as bus control outputs instead of general purpose
I/O pins.
It is possible to enable the pipe status signals on Port E bits 6 and 5 by setting the PIPOE bit in PEAR, but
it would be unusual to do so in this mode. Development systems where pipe status signals are monitored
would typically use the special variation of this mode.
The Port E bit 2 pin can be reconfigured as the R/W bus control signal by writing “1” to the RDWE bit in
PEAR. If the expanded system includes external devices that can be written, such as RAM, the RDWE bit
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MC9S12H256 Device User Guide — V01.20
would need to be set before any attempt to write to an external location. If there are no writable resources
in the external system, PE2 can be left as a general purpose I/O pin. The
Port E bit 3 pin can be reconfigured as the LSTRB bus control signal by writing “1” to the LSTRE bit in
PEAR. The default condition of this pin is a general purpose input because the LSTRB function is not
needed in all expanded wide applications.
The Port E bit 4 pin is initially configured as ECLK output with stretch. The E clock output function
depends upon the settings of the NECLK bit in the PEAR register, the IVIS bit in the MODE register and
the ESTR bit in the EBICTL register. The E clock is available for use in external select decode logic or as
a constant speed clock for use in the external application system.
4.2.1.3 Normal Expanded Narrow Mode
This mode is used for lower cost production systems that use 8-bit wide external EPROMs or RAMs. Such
systems take extra bus cycles to access 16-bit locations but this may be preferred over the extra cost of
additional external memory devices.
Ports A and B are configured as a 16-bit address bus and Port A is multiplexed with data. Internal visibility
is not available in this mode because the internal cycles would need to be split into two 8-bit cycles.
Since the PEAR register can only be written one time in this mode, use care to set all bits to the desired
states during the single allowed write.
The PE3/LSTRB pin is always a general purpose I/O pin in normal expanded narrow mode. Although it
is possible to write the LSTRE bit in PEAR to “1” in this mode, the state of LSTRE is overridden and Port
E bit 3 cannot be reconfigured as the LSTRB output.
It is possible to enable the pipe status signals on Port E bits 6 and 5 by setting the PIPOE bit in PEAR, but
it would be unusual to do so in this mode. LSTRB would also be needed to fully understand system
activity. Development systems where pipe status signals are monitored would typically use special
expanded wide mode or occasionally special expanded narrow mode.
The PE4/ECLK pin is initially configured as ECLK output with stretch. The E clock output function
depends upon the settings of the NECLK bit in the PEAR register, the IVIS bit in the MODE register and
the ESTR bit in the EBICTL register. In normal expanded narrow mode, the E clock is available for use
in external select decode logic or as a constant speed clock for use in the external application system.
The PE2/R/W pin is initially configured as a general purpose input with a pull-up but this pin can be
reconfigured as the R/W bus control signal by writing “1” to the RDWE bit in PEAR. If the expanded
narrow system includes external devices that can be written such as RAM, the RDWE bit would need to
be set before any attempt to write to an external location. If there are no writable resources in the external
system, PE2 can be left as a general purpose I/O pin.
4.2.1.4 Internal Visibility
Internal visibility is available when the MCU is operating in expanded wide modes or special narrow
mode. It is not available in single-chip, peripheral or normal expanded narrow modes. Internal visibility is
enabled by setting the IVIS bit in the MODE register.
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If an internal access is made while E, R/W, and LSTRB are configured as bus control outputs and internal
visibility is off (IVIS=0), E will remain low for the cycle, R/W will remain high, and address, data and the
LSTRB pins will remain at their previous state.
When internal visibility is enabled (IVIS=1), certain internal cycles will be blocked from going external.
During cycles when the BDM is selected, R/W will remain high, data will maintain its previous state, and
address and LSTRB pins will be updated with the internal value. During CPU no access cycles when the
BDM is not driving, R/W will remain high, and address, data and the LSTRB pins will remain at their
previous state.
4.2.1.5 Emulation Expanded Wide Mode
In expanded wide modes, Ports A and B are configured as a 16-bit multiplexed address and data bus and
Port E provides bus control and status signals. These signals allow external memory and peripheral devices
to be interfaced to the MCU. These signals can also be used by a logic analyzer to monitor the progress of
application programs.
The bus control related pins in Port E (PE7/NOACC, PE6/MODB/IPIPE1, PE5/MODA/IPIPE0,
PE4/ECLK, PE3/LSTRB/TAGLO, and PE2/R/W) are all configured to serve their bus control output
functions rather than general purpose I/O. Notice that writes to the bus control enable bits in the PEAR
register in special mode are restricted.
4.2.1.6 Emulation Expanded Narrow Mode
Expanded narrow modes are intended to allow connection of single 8-bit external memory devices for
lower cost systems that do not need the performance of a full 16-bit external data bus. Accesses to internal
resources that have been mapped external (i.e. PORTA, PORTB, DDRA, DDRB, PORTE, DDRE, PEAR,
PUCR, RDRIV) will be accessed with a 16-bit data bus on Ports A and B. Accesses of 16-bit external
words to addresses which are normally mapped external will be broken into two separate 8-bit accesses
using Port A as an 8-bit data bus. Internal operations continue to use full 16-bit data paths. They are only
visible externally as 16-bit information if IVIS=1.
Ports A and B are configured as multiplexed address and data output ports. During external accesses,
address A15, data D15 and D7 are associated with PA7, address A0 is associated with PB0 and data D8
and D0 are associated with PA0. During internal visible accesses and accesses to internal resources that
have been mapped external, address A15 and data D15 is associated with PA7 and address A0 and data
D0 is associated with PB0.
The bus control related pins in Port E (PE7/NOACC, PE6/MODB/IPIPE1, PE5/MODA/IPIPE0,
PE4/ECLK, PE3/LSTRB/TAGLO, and PE2/R/W) are all configured to serve their bus control output
functions rather than general purpose I/O. Notice that writes to the bus control enable bits in the PEAR
register in special mode are restricted.
4.2.2 Special Operating Modes
There are two special operating modes that correspond to normal operating modes. These operating modes
are commonly used in factory testing and system development.
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4.2.2.1 Special Single-Chip Mode
When the MCU is reset in this mode, the background debug mode is enabled and active. The MCU does
not fetch the reset vector and execute application code as it would in other modes. Instead the active
background mode is in control of CPU execution and BDM firmware is waiting for additional serial
commands through the BKGD pin. When a serial command instructs the MCU to return to normal
execution, the system will be configured as described below unless the reset states of internal control
registers have been changed through background commands after the MCU was reset.
There is no external expansion bus after reset in this mode. Ports A and B are initially simple bidirectional
I/O pins that are configured as high-impedance inputs with internal pull-ups disabled; however, writing to
the mode select bits in the MODE register (which is allowed in special modes) can change this after reset.
All of the Port E pins (except PE4/ECLK) are initially configured as general purpose high-impedance
inputs with pull-ups enabled. PE4/ECLK is configured as the E clock output in this mode.
The pins associated with Port E bits 6, 5, 3, and 2 cannot be configured for their alternate functions IPIPE1,
IPIPE0, LSTRB, and R/W while the MCU is in single chip modes. In single chip modes, the associated
control bits PIPOE, LSTRE and RDWE are reset to zero. Writing the opposite value into these bits in
single chip mode does not change the operation of the associated Port E pins.
Port E, bit 4 can be configured for a free-running E clock output by clearing NECLK=0. Typically the only
use for an E clock output while the MCU is in single chip modes would be to get a constant speed clock
for use in the external application system.
4.2.2.2 Special Test Mode (Freescale Use Only)
In expanded wide modes, Ports A and B are configured as a 16-bit multiplexed address and data bus and
Port E provides bus control and status signals. In special test mode, the write protection of many control
bits is lifted so that they can be thoroughly tested without needing to go through reset.
4.2.3 Test Operating Mode (Freescale Use Only)
There is a test operating mode in which an external master, such as an I.C. tester, can control the on-chip
peripherals.
4.2.3.1 Peripheral Mode
This mode is intended for Freescale factory testing of the MCU. In this mode, the CPU is inactive and an
external (tester) bus master drives address, data and bus control signals in through Ports A, B and E. In
effect, the whole MCU acts as if it was a peripheral under control of an external CPU. This allows faster
testing of on-chip memory and peripherals than previous testing methods. Since the mode control register
is not accessible in peripheral mode, the only way to change to another mode is to reset the MCU into a
different mode. Background debugging should not be used while the MCU is in special peripheral mode
as internal bus conflicts between BDM and the external master can cause improper operation of both
functions.
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4.3 Security
The device will make available a security feature preventing the unauthorized read and write of the
memory contents. This feature allows:
•
•
•
•
Protection of the contents of FLASH,
Protection of the contents of EEPROM,
Operation in single-chip mode,
Operation from external memory with internal FLASH and EEPROM disabled.
The user must be reminded that part of the security must lie with the user’s code. An extreme example
would be user’s code that dumps the contents of the internal program. This code would defeat the purpose
of security. At the same time the user may also wish to put a back door in the user’s program. An example
of this is the user downloads a key through the SCI which allows access to a programming routine that
updates parameters stored in EEPROM.
4.3.1 Securing the Microcontroller
Once the user has programmed the FLASH and EEPROM (if desired), the part can be secured by
programming the security bits located in the FLASH module. These non-volatile bits will keep the part
secured through resetting the part and through powering down the part.
The security byte resides in a portion of the Flash array.
Check the Flash Block User Guide for more details on the security configuration.
4.3.2 Operation of the Secured Microcontroller
4.3.2.1 Normal Single Chip Mode
This will be the most common usage of the secured part. Everything will appear the same as if the part was
not secured with the exception of BDM operation. The BDM operation will be blocked.
4.3.2.2 Executing from External Memory
The user may wish to execute from external space with a secured microcontroller. This is accomplished
by resetting directly into expanded mode. The internal FLASH and EEPROM will be disabled. BDM
operations will be blocked.
4.3.3 Unsecuring the Microcontroller
In order to unsecure the microcontroller, the internal FLASH and EEPROM must be erased. This can be
done through an external program in expanded mode.
Once the user has erased the FLASH and EEPROM, the part can be reset into special single chip mode.
This invokes a program that verifies the erasure of the internal FLASH and EEPROM. Once this program
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MC9S12H256 Device User Guide — V01.20
completes, the user can erase and program the FLASH security bits to the unsecured state. This is generally
done through the BDM, but the user could also change to expanded mode (by writing the mode bits
through the BDM) and jumping to an external program (again through BDM commands). Note that if the
part goes through a reset before the security bits are reprogrammed to the unsecure state, the part will be
secured again.
4.4 Low Power Modes
Consult the respective Block User Guide for information on the module behavior in Stop, Pseudo Stop,
and Wait Mode.
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Section 5 Resets and Interrupts
5.1 Overview
Consult the Exception Processing section of the HCS12 Core User Guide for information on resets and
interrupts.
5.2 Vectors
5.2.1 Vector Table
Table 5-1 lists interrupt sources and vectors in default order of priority.
Table 5-1 Reset and Interrupt Vector Table
CCR
Mask
HPRIO Value
to Elevate
Vector Address
Interrupt Source
Local Enable
$FFFE, $FFFF
$FFFC, $FFFD
$FFFA, $FFFB
$FFF8, $FFF9
$FFF6, $FFF7
$FFF4, $FFF5
$FFF2, $FFF3
$FFF0, $FFF1
$FFEE, $FFEF
$FFEC, $FFED
$FFEA, $FFEB
$FFE8, $FFE9
$FFE6, $FFE7
$FFE4, $FFE5
$FFE2, $FFE3
$FFE0, $FFE1
$FFDE, $FFDF
$FFDC, $FFDD
$FFDA, $FFDB
$FFD8, $FFD9
External or Power On Reset
Clock Monitor fail reset
COP failure reset
None
None
None
None
COPCTL (CME, FCME)
COP rate select
None
-
-
-
Unimplemented instruction trap None
-
SWI
XIRQ
None
X-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
None
-
None
-
IRQ
INTCR (IRQEN)
RTICTL (RTIE)
TIE (C0I)
$F2
$F0
$EE
$EC
$EA
$E8
$E6
$E4
$E2
$E0
$DE
$DC
$DA
$D8
Real Time Interrupt
Timer channel 0
Timer channel 1
Timer channel 2
Timer channel 3
Timer channel 4
Timer channel 5
Timer channel 6
Timer channel 7
Timer overflow
Pulse accumulator A overflow
Pulse accumulator input edge
SPI
TIE (C1I)
TIE (C2I)
TIE (C3I)
TIE (C4I)
TIE (C5I)
TIE (C6I)
TIE (C7I)
TSCR2 (TOI)
PACTL (PAOVI)
PACTL (PAI)
SPICR1 (SPIE)
SC0CR2
(TIE, TCIE, RIE, ILIE)
$FFD6, $FFD7
$FFD4, $FFD5
SCI0
I-Bit
$D6
SC1CR2
(TIE, TCIE, RIE, ILIE)
SCI1
ATD
I-Bit
I-Bit
$D4
$D2
$FFD2, $FFD3
$FFD0, $FFD1
$FFCE, $FFCF
$FFCC, $FFCD
$FFCA, $FFCB
ATDCTL2 (ASCIE)
Reserved
Port J
Port H
I-Bit
I-Bit
PTJIF (PTJIE)
PTHIF (PTHIE)
$CE
$CC
Reserved
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Table 5-1 Reset and Interrupt Vector Table
CCR
Mask
HPRIO Value
to Elevate
Vector Address
Interrupt Source
Local Enable
$FFC8, $FFC9
$FFC6, $FFC7
$FFC4, $FFC5
$FFC2, $FFC3
$FFC0, $FFC1
$FFBE, $FFBF
$FFBC, $FFBD
$FFBA, $FFBB
$FFB8, $FFB9
$FFB6, $FFB7
Reserved
CRG PLL lock
CRG Self Clock Mode
Reserved
I-Bit
I-Bit
CRGINT (LOCKIE)
CRGINT (SCMIE)
$C6
$C4
IIC Bus
I-Bit
IBCR (IBIE)
$C0
Reserved
Reserved
EEPROM
FLASH
I-Bit
EECTL (CCIE, CBEIE)
FCTL (CCIE, CBEIE)
CAN0RIER (WUPIE)
$BA
$B8
$B6
I-Bit
I-Bit
CAN0 wake-up
CAN0RIER (CSCIE,
OVRIE)
$FFB4, $FFB5
CAN0 errors
I-Bit
$B4
$FFB2, $FFB3
$FFB0, $FFB1
$FFAE, $FFAF
CAN0 receive
CAN0 transmit
CAN1 wake-up
I-Bit
I-Bit
I-Bit
CAN0RIER (RXFIE)
CAN0TIER (TXEIE[2:0])
CAN0RIER (WUPIE)
$B2
$B0
$AE
CAN1RIER (CSCIE,
OVRIE)
$FFAC, $FFAD
CAN1 errors
I-Bit
$AC
$FFAA, $FFAB
$FFA8, $FFA9
CAN1 receive
CAN1 transmit
I-Bit
I-Bit
CAN1RIER (RXFIE)
$AA
$A8
CAN1TIER (TXEIE[2:0])
$FF98 to
$FFA7
Reserved
$FF96, $FF97
Motor Control Timer Overflow
PWM Emergency Shutdown
I-Bit
MCCTL1 (MCOCIE)
PWMSDN(PWMIE)
$96
$8C
$FF9E to
$FF95
Reserved
$FF8C, $FF8D
I-Bit
Reserved
$FF80 to
$FF8B
5.3 Effects of Reset
When a reset occurs, MCU registers and control bits are changed to known start-up states. Refer to the
respective module Block User Guides for register reset states.
5.3.1 I/O pins
Refer to the HCS12 Core User Guides for mode dependent pin configuration of port A, B, E and K out of
reset.
Refer to the PIM Block User Guide for reset configurations of all peripheral module ports.
NOTE: For devices assembled in 112-pin LQFP packages all non-bonded out pins should
be configured as outputs after reset in order to avoid current drawn from floating
inputs. Refer to Table 2-1 for affected pins.
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MC9S12H256 Device User Guide — V01.20
5.3.2 Memory
Refer to Table 1-1 for locations of the memories depending on the operating mode after reset
The RAM array is not automatically initialized out of reset.
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MC9S12H256 Device User Guide — V01.20
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MC9S12H256 Device User Guide — V01.20
Section 6 HCS12 Core Block Description
Consult the HCS12 Core User Guide for information about the HCS12 core modules, i.e. central
processing unit (CPU), interrupt module (INT), module mapping control module (MMC), multiplexed
external bus interface (MEBI), breakpoint module (BKP) and background debug mode module (BDM).
Section 7 Clock and Reset Generator (CRG) Block
Description
Consult the CRG Block User Guide for information about the Clock and Reset Generator module.
7.1 Device-specific information
7.1.1 XCLKS
The XCLKS input signal is active high (see 2.3.10 PE7 / FP22 / XCLKS / NOACC — Port E I/O Pin 7).
Section 8 Timer (TIM) Block Description
Consult the TIM_16B8C Block User Guide for information about the Timer module.
Section 9 Analog to Digital Converter (ATD) Block
Description
Consult the ATD_10B16C Block User Guide for information about the Analog to Digital Converter
module.
Section 10 Inter-IC Bus (IIC) Block Description
Consult the IIC Block User Guide for information about the Inter-IC Bus module.
Section 11 Serial Communications Interface (SCI) Block
Description
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MC9S12H256 Device User Guide — V01.20
There are two Serial Communications Interfaces (SCI0 and SCI1) implemented on the MC9S12H256
device and one SCI (SCI0) on MC9S12H128. Consult the SCI Block User Guide for information about
each Serial Communications Interface module.
Section 12 Serial Peripheral Interface (SPI) Block
Description
Consult the SPI Block User Guide for information about the Serial Peripheral Interface module.
Section 13 Pulse Width Modulator (PWM) Block
Description
Consult the PWM_8B6C Block User Guide for information about the Pulse Width Modulator module.
Section 14 Flash EEPROM 256K Block Description
Consult the FTS256K Block User Guide for information about the flash module.
Section 15 EEPROM 4K Block Description
Consult the EETS4K Block User Guide for information about the EEPROM module.
Section 16 RAM Block Description
The RAM module does not contain any control registers. Thus no Block User Guide is available.
This module supports single-cycle misaligned word accesses without wait states.
Section 17 Liquid Crystal Display Driver (LCD) Block
Description
Consult the LCD_32F4B Block User Guide for information about the Liquid Crystal Display Driver
module.
Section 18 MSCAN Block Description
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MC9S12H256 Device User Guide — V01.20
There are two MSCAN modules (CAN0 and CAN1) implemented on the MC9S12H256 device. Consult
the MSCAN Block User Guide for information on each MSCAN.
Section 19 PWM Motor Control (MC) Block Description
Consult the MC_10B12C Block User Guide for information about the PWM Motor Control module.
Section 20 Port Integration Module (PIM) Block Description
Consult the PIM_9H256 Block User Guide for information about the Port Integration Module.
Section 21 Voltage Regulator (VREG) Block Description
Consult the VREG Block User Guide for information about the dual output linear voltage regulator.
21.1 Device-specific information
21.1.1 VREGEN
There is no VREGEN pin implemented on this device.
21.1.2 Modes of Operation
21.1.2.1 Run Mode
VREG enters run mode whenever the CPU is neither in Stop nor in Pseudo Stop mode. Both regulating
loops operate in Run mode with full performance.
21.1.2.2 Standby Mode
VREG enters Standby mode when the CPU operates either in Stop or in Pseudo Stop mode. The supply of
the core logic as well as the oscillators are derived from two voltage clamps. Standby mode minimizes
quiescent current drawn by the voltage regulator block.
21.1.2.3 Shutdown Mode
VREG Shutdown mode is not available on MC9S12H family devices.
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MC9S12H256 Device User Guide — V01.20
21.2 Recommended PCB layout
Figure 21-1 LQFP112 recommended PCB layout
VDDX1
VDDM1
C7
VSSM1
VSS1
C1
VDD1
VDDM2
C6
VSSM2
VDDA
VDDM3
C5
C2
VSSA
VSSM3
VDDR/
VDDX2
Q1
VSSPLL
VDDPLL
R1
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MC9S12H256 Device User Guide — V01.20
Figure 21-2 LQFP144 recommended PCB layout
VDDX1
VDDM1
C7
VSSM1
VSS1
C1
VDD1
VDDM2
C6
VSSM2
VDDA
VDDM3
C5
C2
VSSA
VSSM3
VDDR/
VDDX2
Q1
VSSPLL
VDDPLL
R1
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MC9S12H256 Device User Guide — V01.20
Table 21-1 Recommended Components
Component
Purpose
Type
Value
100 .. 220nF
>=100nF
C1
C2
VDD1 filter cap
VDDA filter cap
VDDX2 filter cap
VDDR filter cap
VDDM3 filter cap
VDDM2 filter cap
VDDM1 filter cap
VDDX1 filter cap
VDDPLL filter cap
OSC load cap
ceramic X7R
X7R/tantalum
X7R/tantalum
X7R/tantalum
X7R/tantalum
X7R/tantalum
X7R/tantalum
X7R/tantalum
ceramic X7R
C3
>=100nF
C4
>=100nF
C5
>=100nF
C6
>=100nF
C7
>=100nF
C8
>=100nF
C9
100nF .. 220nF
C10
C11
C12
C13
C14
R1
OSC load cap
PLL loop filter cap
PLL loop filter cap
DC cutoff cap
See CRG Block User Guide
PLL loop filter res
Quartz/Resonator
Q1
The PCB must be carefully laid out to ensure proper operation of the voltage regulator as well as of the
MCU itself. The following rules must be observed:
•
Every supply pair must be decoupled by a ceramic/tantalum capacitor connected as near as possible
to the corresponding pins(C1 – C9).
•
•
Central point of the ground star should be the VSS1 pin.
Use low ohmic low inductance connections between VSS1, VSS2, VSSA, VSSX1,2 and
VSSM1,2,3.
•
•
VSSPLL must be directly connected to VSS1.
Keep traces of VSSPLL, EXTAL and XTAL as short as possible and occupied board area for C10,
C11, C14 and Q1 as small as possible.
•
•
Do not place other signals or supplies underneath area occupied by C10, C11, C14 and Q1 and the
connection area to the MCU.
Central power input should be fed in at the VDDA/VSSA pins.
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MC9S12H256 Device User Guide — V01.20
Appendix A Electrical Characteristics
A.1 General
This supplement contains the most accurate electrical information for the MC9S12H256 and
MC9S12H128 microcontroller available at the time of publication.
This introduction is intended to give an overview on several common topics like power supply, current
injection etc.
A.1.1 Parameter Classification
The electrical parameters shown in this supplement are guaranteed by various methods. To give the
customer a better understanding the following classification is used and the parameters are tagged
accordingly in the tables where appropriate.
NOTE: This classification is shown in the column labeled “C” in the parameter tables
where appropriate.
P:
Those parameters are guaranteed during production testing on each individual device.
C:
Those parameters are achieved by the design characterization by measuring a statistically relevant
sample size across process variations.
T:
Those parameters are achieved by design characterization on a small sample size from typical devices
under typical conditions unless otherwise noted. All values shown in the typical column are within
this category.
D:
Those parameters are derived mainly from simulations.
A.1.2 Power Supply
The MC9S12H256 utilizes several pins to supply power to the I/O ports, A/D converter, oscillator and PLL
as well as the digital core.
The VDDA, VSSA pair supplies the A/D converter and the resistor ladder of the internal voltage regulator.
The VDDX1/VSSX1 and VDDX2/VSSX2 pairs supply the I/O pins except PH, PU, PV and PW. VDDR
supplies the internal voltage regulator.
VDDM1/VSSM1, VDDM2/VSSM2 and VDDM3/VSSM3 pairs supply the ports PH, PU, PV and PW.
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MC9S12H256 Device User Guide — V01.20
VDD1, VSS1 and VSS2 are the supply pins for the digital logic, VDDPLL, VSSPLL supply the oscillator
and the PLL.
VSS1 and VSS2 are internally connected by metal.
VDDA, VDDX1, VDDX2, VDDM as well as VSSA, VSSX1, VSSX2 and VSSM are connected by
anti-parallel diodes for ESD protection.
NOTE: In the following context VDD5 is used for either VDDA, VDDM, VDDR and
VDDX1/2; VSS5 is used for either VSSA, VSSR and VSSX unless otherwise noted.
IDD5 denotes the sum of the currents flowing into the VDDA, VDDX1/2, VDDM
and VDDR pins.
VDD is used for VDD1 and VDDPLL, VSS is used for VSS1, VSS2 and VSSPLL.
IDD is used for the sum of the currents flowing into VDD1 and VDDPLL.
A.1.3 Pins
There are four groups of functional pins.
A.1.3.1 5V I/O pins
Those I/O pins have a nominal level of 5V. This class of pins is comprised of all port I/O pins, the analog
inputs, BKGD and the RESET pins.The internal structure of all those pins is identical, however some of
the functionality may be disabled. E.g. for the analog inputs the output drivers, pull-up and pull-down
resistors are disabled permanently.
A.1.3.2 Analog Reference
This group is made up by the VRH and VRL pins.
A.1.3.3 Oscillator
The pins XFC, EXTAL, XTAL dedicated to the oscillator have a nominal 2.5V level. They are supplied
by VDDPLL.
A.1.3.4 TEST
This pin is used for production testing only.
A.1.4 Current Injection
Power supply must maintain regulation within operating V
or V range during instantaneous and
DD
DD5
operating maximum current conditions. If positive injection current (V > V
) is greater than I
, the
in
DD5
DD5
injection current may flow out of VDD5 and could result in external power supply going out of regulation.
Ensure external VDD5 load will shunt current greater than maximum injection current. This will be the
90
MC9S12H256 Device User Guide — V01.20
greatest risk when the MCU is not consuming power; e.g. if no system clock is present, or if clock rate is
very low which would reduce overall power consumption.
A.1.5 Absolute Maximum Ratings
Absolute maximum ratings are stress ratings only. A functional operation under or outside those maxima
is not guaranteed. Stress beyond those limits may affect the reliability or cause permanent damage of the
device.
This device contains circuitry protecting against damage due to high static voltage or electrical fields;
however, it is advised that normal precautions be taken to avoid application of any voltages higher than
maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused
inputs are tied to an appropriate logic voltage level (e.g., either V
or V
).
SS5
DD5
1
Table A-1 Absolute Maximum Ratings
Num
Rating
Symbol
Min
–0.3
–0.3
–0.3
Max
6.0
Unit
V
VDD5
1
2
3
I/O, Regulator and Analog Supply Voltage
Digital Logic Supply Voltage 2
PLL Supply Voltage 2
VDD
3.0
V
VDDPLL
3.0
V
Voltage difference VDDX1 to VDDX2 to VDDM and
VDDA
∆
4
–0.3
0.3
V
VDDX
∆
5
6
7
8
9
Voltage difference VSSX to VSSR and VSSA
Digital I/O Input Voltage
Analog Reference
–0.3
–0.3
–0.3
–0.3
–0.3
0.3
6.0
V
V
V
V
V
VSSX
VIN
V
RH, VRL
VILV
VTEST
6.0
XFC, EXTAL, XTAL inputs
TEST input
3.0
10.0
Instantaneous Maximum Current
ID
Single pin limit for all digital I/O pins except PU, PV
and PW 3
10
–25
+25
mA
Instantaneous Maximum Current
Single pin limit for Port PU, PV and PW 4
ID
11
12
13
–55
–25
+55
+25
mA
mA
Instantaneous Maximum Current
Single pin limit for XFC, EXTAL, XTAL5
IDL
Instantaneous Maximum Current
Single pin limit for TEST 6
IDT
–0.25
– 65
0
mA
Tstg
14
Storage Temperature Range
155
°C
NOTES:
1. Beyond absolute maximum ratings device might be damaged.
2. The device contains an internal voltage regulator to generate the logic and PLL supply out of the I/O supply.
The absolute maximum ratings apply when the device is powered from an external source.
3. All digital I/O pins are internally clamped to VSSX1/2 and VDDX1/2, VSSM and VDDM or VSSA and VDDA
.
4. Ports PU, PV, PW are internally clamped to VSSM and VDDM
.
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MC9S12H256 Device User Guide — V01.20
5. Those pins are internally clamped to VSSPLL and VDDPLL
.
6. This pin is clamped low to VSSPLL, but not clamped high. This pin must be tied low in applications.
A.1.6 ESD Protection and Latch-up Immunity
All ESD testing is in conformity with CDF-AEC-Q100 Stress test qualification for Automotive Grade
Integrated Circuits. During the device qualification ESD stresses were performed for the Human Body
Model (HBM), the Machine Model (MM) and the Charge Device Model.
A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device
specification. Complete DC parametric and functional testing is performed per the applicable device
specification at room temperature followed by hot temperature, unless specified otherwise in the device
specification.
Table A-2 ESD and Latch-up Test Conditions
Model
Description
Symbol
Value
1500
100
Unit
Ω
Series Resistance
R1
C
Storage Capacitance
pF
Human Body
Number of Pulse per pin
positive
negative
–
3
3
–
Series Resistance
R1
C
0
Ω
pF
Storage Capacitance
200
Machine
Latch-up
Number of Pulse per pin
positive
negative
–
3
3
–
Minimum input voltage limit
Maximum input voltage limit
–2.5
7.5
V
V
Table A-3 ESD and Latch-Up Protection Characteristics
Num C
Rating
Symbol
VHBM
Min
2000
200
Max
Unit
1
2
3
C Human Body Model (HBM)
–
–
–
V
V
V
VMM
C Machine Model (MM)
VCDM
C Charge Device Model (CDM)
Latch-up Current at TA = 125°C
500
ILAT
4
5
C
+100
–100
–
–
mA
mA
positive
negative
Latch-up Current at TA = 27°C
ILAT
C
+200
–200
positive
negative
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MC9S12H256 Device User Guide — V01.20
A.1.7 Operating Conditions
This chapter describes the operating conditions of the device. Unless otherwise noted those conditions
apply to all the following data.
NOTE: Please refer to the temperature rating of the device (C, V, M) with regards to the
ambient temperature T and the junction temperature T . For power dissipation
A
J
calculations refer to Section A.1.8 Power Dissipation and Thermal
Characteristics.
Table A-4 Operating Conditions
Rating
Symbol
Min
4.5
Typ
5
Max
5.25
2.75
2.75
0.1
Unit
V
VDD5
I/O, Regulator and Analog Supply Voltage
Digital Logic Supply Voltage 1
VDD
2.35
2.35
–0.1
–0.1
0.5
2.5
2.5
0
V
PLL Supply Voltage 2
VDDPLL
V
∆
Voltage Difference VDDX to VDDR and VDDA
Voltage Difference VSSX to VSSR and VSSA
Oscillator
V
VDDX
∆
0
0.1
V
VSSX
fosc
fbus
–
16
MHz
MHz
Bus Frequency
0.5
–
16
MC9S12H256C, MC9S12H128C
Operating Junction Temperature Range
TJ
TA
–40
–40
–
100
85
°C
°C
Operating Ambient Temperature Range 2
MC9S12H256V, MC9S12H128V
27
TJ
TA
Operating Junction Temperature Range
–40
–40
–
120
105
°C
°C
Operating Ambient Temperature Range 2
MC9S12H256M, MC9S12H128M
27
TJ
TA
Operating Junction Temperature Range
–40
–40
–
140
125
°C
°C
Operating Ambient Temperature Range 2
27
NOTES:
1. The device contains an internal voltage regulator to generate the logic and PLL supply out of the I/O supply. The
absolute maximum ratings apply when this regulator is disabled and the device is powered from an external
source.
2. Please refer to Section A.1.8 Power Dissipation and Thermal Characteristics for more details about the rela-
tion between ambient temperature TA and device junction temperature TJ.
A.1.8 Power Dissipation and Thermal Characteristics
Power dissipation and thermal characteristics are closely related. The user must assure that the maximum
operating junction temperature is not exceeded. The average chip-junction temperature (T ) in °C can be
J
obtained from:
93
MC9S12H256 Device User Guide — V01.20
T = T + (P • Θ
)
J
A
D
JA
T = Junction Temperature, [°C]
J
T
= Ambient Temperature, [°C]
A
D
P
= Total Chip Power Dissipation, [W]
Θ
= Package Thermal Resistance, [°C/W]
JA
The total power dissipation can be calculated from:
= P
P
+ P
D
INT
IO
P
= Chip Internal Power Dissipation, [W]
INT
P
= I
P
⋅ V
+ I
⋅ V
INT
DDR DDR DDA DDA
2
=
R
⋅ I
DSON IO
∑
IO
i
i
P is the sum of all output currents on I/O ports associated with VDDX1,2 and VDDM1,2,3.
IO
1
Table A-5 Thermal Package Characteristics
Num C
Rating
Symbol
Min
Typ
Max
Unit
Thermal Resistance LQFP112, single sided PCB2
oC/W
θJA
1
2
3
4
T
–
–
54
Thermal Resistance LQFP112, double sided PCB
with 2 internal planes3
oC/W
oC/W
oC/W
θJA
θJA
θJA
T
–
–
–
–
–
–
41
45
37
T Thermal Resistance LQFP 144, single sided PCB
Thermal Resistance LQFP 144, double sided PCB
with 2 internal planes
T
NOTES:
1. The values for thermal resistance are achieved by package simulations
2. PC Board according to EIA/JEDEC Standard 51-2
3. PC Board according to EIA/JEDEC Standard 51-7
A.1.9 I/O Characteristics
This section describes the characteristics of all 5V I/O pins. All parameters are not always applicable, e.g.
not all pins feature pull up/down resistances.
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MC9S12H256 Device User Guide — V01.20
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MC9S12H256 Device User Guide — V01.20
Table A-6 5V I/O Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C
Rating
Symbol
Min
Typ
Max
Unit
VIH
0.65*VDD5
VDD5 + 0.3
1
2
3
P Input High Voltage
–
V
VIL
VSS5 – 0.3
0.35*VDD5
P Input Low Voltage
C Input Hysteresis
–
V
VHYS
250
mV
Input Leakage Current except PU, PV, PW (pins in
high impedance input mode)1
Vin = VDD5 or VSS5
Iin
4
5
P
P
–1.0
–2.5
–
–
1.0
2.5
µA
µA
Input Leakage Current PU, PV, PW (pins in high
impedance input mode)2
Vin = VDD5 or VSS5
Iin
Output High Voltage (pins in output mode, except PU,
PV and PW)
VOH
VDD5 – 0.8
6
7
P
P
–
–
–
V
V
Partial Drive I
= –1.0mA
OH
= –10mA
Full Drive I
OH
Output Low Voltage (pins in output mode except PU,
PV and PW)
VOL
–
0.8
Partial Drive I
= +1.0mA
OL
= +10mA
Full Drive I
OL
Output High Voltage (pins PU, PV and PW in output
VOH
VOL
VDD5 – 0.32 VDD5 – 0.2
8
9
P
P
–
V
V
mode) I
= –20mA
OH
Output Low Voltage (pins PU, PV and PW in output
–
.2
0.32
mode) I = +20mA
OL
Output Rise Time (pins PU, PV and PW in output
mode with slew control enabled) VDD5=5V,
10
11
P Rload=1KΩ, 10% to 90% of VOH
tr
1203
100
1803
130
60
60
ns
-40°C, EPP package
25°C, 140°C
Output Fall Time (pins PU, PV and PW in output
mode with slew control enabled) VDD5=5V,
tf
P Rload=1KΩ, 10% to 90% of VOH
1203
100
1803
130
60
60
ns
-40°C, EPP package
25°C, 140°C
Internal Pull Up Device Current,
tested at VIL Max.
IPUL
IPUH
IPDH
IPDL
12
13
14
15
P
–
–10
–
–
–
–
–
–130
–
µA
µA
µA
µA
Internal Pull Up Device Current,
tested at VIH Min.
P
Internal Pull Down Device Current,
tested at VIH Min.
P
130
–
Internal Pull Down Device Current,
tested at VIL Max.
P
10
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MC9S12H256 Device User Guide — V01.20
Table A-6 5V I/O Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Cin
16 D Input Capacitance
Injection current4
6
–
–
pF
IICS
IICP
17
T
–2.5
–25
2.5
25
mA
Single Pin limit
Total Device Limit. Sum of all injected currents
Port H, J Interrupt Input Pulse filtered5
Port H, J Interrupt Input Pulse passed5
tPULSE
tPULSE
18
19
P
P
3
µs
µs
10
NOTES:
1. Maximum leakage current occurs at maximum operating temperature. Current decreases by approximately one-half for
each 8 C to 12 C in the temperature range from 50 C to 125 C.
2. Maximum leakage current occurs at maximum operating temperature. Current decreases by approximately one-half for
each 8 C to 12 C in the temperature range from 50 C to 125 C.
3. This only applies to the EPP package, non-EPP packages retain the 100ns typ and 130ns max spec.
4. Refer to Section A.1.4 Current Injection, for more details
5. Parameter only applies in STOP or Pseudo STOP mode.
A.1.10 Supply Currents
This section describes the current consumption characteristics of the device as well as the conditions for
the measurements.
A.1.10.1 Measurement Conditions
All measurements are without output loads. Unless otherwise noted the currents are measured in single
chip mode, internal voltage regulator enabled and at 16MHz bus frequency using a 4MHz oscillator in
Colpitts mode. Production testing is performed using a square wave signal at the EXTAL input.
A.1.10.2 Additional Remarks
In expanded modes the currents flowing in the system are highly dependent on the load at the address, data
and control signals as well as on the duty cycle of those signals. No generally applicable numbers can be
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MC9S12H256 Device User Guide — V01.20
given. A very good estimate is to take the single chip currents and add the currents due to the external
loads.
Table A-7 Supply Current Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C
Rating
Symbol
Min
Typ
Max
Unit
Run supply currents
1
P
mA
IDD5
Single Chip, Internal regulator enabled
65
Wait Supply current
All modules enabled, PLL on
only RTI enabled 1
IDDW
2
P
P
40
5
mA
Pseudo Stop Current (RTI and COP disabled) 1, 2
–40°C
C
P
C
C
P
C
P
C
P
360
420
760
800
950
1000
1500
1700
2500
27°C
520
70°C
85°C
IDDPS
3
4
5
µA
C Temp Option 100°C
105°C
V Temp Option 120°C
125°C
M Temp Option 140° C
2000
3300
4800
Pseudo Stop Current (RTI and COP enabled) 1, 2
C
C
C
C
C
C
C
420
480
820
–40°C
27°C
70°C
85°C
105°C
125°C
140°C
IDDPS
µA
860
1050
1700
2500
Stop Current 2
C
P
C
C
P
C
P
C
P
20
40
–40°C
27°C
70°C
85°C
100
200
300
550
700
1200
1400
2200
IDDS
µA
1500
2900
4500
C Temp Option 100°C
105°C
V Temp Option 120°C
125°C
M Temp Option 140°C
NOTES:
1. PLL off
2. At those low power dissipation levels TJ = TA can be assumed
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MC9S12H256 Device User Guide — V01.20
A.2 ATD Characteristics
This section describes the characteristics of the analog to digital converter.
A.2.1 ATD Operating Characteristics
The Table A-8 shows conditions under which the ATD operates.
The following constraints exist to obtain full-scale, full range results:
V
≤ V ≤ V ≤ V ≤ V
. This constraint exists since the sample buffer amplifier can not drive
SSA
RL
IN
RH
DDA
beyond the power supply levels that it ties to. If the input level goes outside of this range it will effectively
be clipped.
Table A-8 ATD Operating Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C
Rating
Symbol
Min
Typ
Max
/2
Unit
Reference Potential
1
D
Low
High
V
V
V
V
V
RL
SSA
DDA
V
V
/2
V
RH
DDA
DDA
Differential Reference Voltage1
2
3
C
V
f
–V
4.50
0.5
5.00
5.25
2.0
V
RH
RL
D ATD Clock Frequency
MHz
ATDCLK
ATD 10-Bit Conversion Period
D
Clock Cycles2
4
5
N
T
14
7
28
14
Cycles
µs
CONV10
Conv, Time at 2.0MHz ATD Clock fATDCLK
CONV10
ATD 8-Bit Conversion Period
Clock Cycles2
D
D
N
T
12
6
26
13
Cycles
µs
CONV8
CONV8
Conv, Time at 2.0MHz ATD Clock fATDCLK
Stop Recovery Time (VDDA=5.0 Volts)
6
7
t
20
µs
SR
P Reference Supply current
I
0.375
mA
REF
NOTES:
1. Full accuracy is not guaranteed when differential voltage is less than 4.50V
2. The minimum time assumes a final sample period of 2 ATD clocks cycles while the maximum time assumes a final sample
period of 16 ATD clocks.
A.2.2 Factors influencing accuracy
Three factors – source resistance, source capacitance and current injection – have an influence on the
accuracy of the ATD.
A.2.2.1 Source Resistance:
Due to the input pin leakage current as specified in Table A-6 in conjunction with the source resistance
there will be a voltage drop from the signal source to the ATD input. The maximum source resistance R
specifies results in an error of less than 1/2 LSB (2.5mV) at the maximum leakage current. If device or
S
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MC9S12H256 Device User Guide — V01.20
operating conditions are less than worst case or leakage-induced error is acceptable, larger values of source
resistance is allowed.
A.2.2.2 Source Capacitance
When sampling an additional internal capacitor is switched to the input. This can cause a voltage drop due
to charge sharing with the external and the pin capacitance. For a maximum sampling error of the input
voltage ≤ 1LSB, then the external filter capacitor, C ≥ 1024 * (C – C ).
f
INS
INN
A.2.2.3 Current Injection
There are two cases to consider.
1. A current is injected into the channel being converted. The channel being stressed has conversion
values of $3FF ($FF in 8-bit mode) for analog inputs greater than V and $000 for values less than
RH
V
unless the current is higher than specified as disruptive condition.
RL
2. Current is injected into pins in the neighborhood of the channel being converted. A portion of this
current is picked up by the channel (coupling ratio K), This additional current impacts the accuracy
of the conversion depending on the source resistance.
The additional input voltage error on the converted channel can be calculated as V
= K * R *
ERR
S
I
, with I being the sum of the currents injected into the two pins adjacent to the converted
INJ
INJ
channel.
Table A-9 ATD Electrical Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C
Rating
Symbol
Min
Typ
Max
Unit
RS
1
C Max input Source Resistance
–
–
1
KΩ
Total Input Capacitance
T Non Sampling
Sampling
CINN
CINS
2
10
22
pF
INA
Kp
Kn
3
4
5
C Disruptive Analog Input Current
–2.5
2.5
mA
A/A
A/A
10–4
10–2
C Coupling Ratio positive current injection
C Coupling Ratio negative current injection
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MC9S12H256 Device User Guide — V01.20
A.2.3 ATD accuracy
Table A-10 specifies the ATD conversion performance excluding any errors due to current injection, input
capacitance and source resistance.
Table A-10 ATD Conversion Performance
Conditions are shown in Table A-4 unless otherwise noted
VREF = VRH – VRL = 5.12V. Resulting to one 8 bit count = 20mV and one 10 bit count = 5mV
f
= 2.0MHz
ATDCLK
Num C
Rating
Symbol
LSB
DNL
INL
Min
Typ
Max
Unit
mV
1
2
3
4
5
6
7
8
P 10-Bit Resolution
5
P 10-Bit Differential Nonlinearity
P 10-Bit Integral Nonlinearity
–1
–2.5
–3
1
2.5
3
Counts
Counts
Counts
mV
1.5
2.0
20
10-Bit Absolute Error1
P
AE
P 8-Bit Resolution
LSB
DNL
INL
P 8-Bit Differential Nonlinearity
P 8-Bit Integral Nonlinearity
–0.5
–1.0
–1.5
0.5
1.0
1.5
Counts
Counts
Counts
0.5
1.0
8-Bit Absolute Error1
P
AE
NOTES:
1. These values include the quantization error which is inherently 1/2 count for any A/D converter.
For the following definitions see also Figure A-1.
Differential Non-Linearity (DNL) is defined as the difference between two adjacent switching steps.
V – V
i
i – 1
DNL(i) =
– 1
------------------------
1LSB
The Integral Non-Linearity (INL) is defined as the sum of all DNLs:
n
V – V
n
0
-------------------
1LSB
INL(n) =
DNL(i) =
– n
∑
i = 1
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MC9S12H256 Device User Guide — V01.20
DNL
10-Bit Absolute Error Boundary
LSB
V
V
i
i–1
$3FF
$3FE
$3FD
$3FC
$3FB
$3FA
$3F9
$3F8
$3F7
$3F6
$3F5
$3F4
$3F3
8-Bit Absolute Error Boundary
$FF
$FE
$FD
2
9
8
7
6
5
4
3
2
1
0
Ideal Transfer Curve
10-Bit Transfer Curve
1
8-Bit Transfer Curve
5
10
15
20
25
30
35
40
45
5055 5060 5065 5070 5075 5080 5085 5090 5095 5100 5105 5110 5115 5120
Vin
mV
Figure A-1 ATD Accuracy Definitions
NOTE: Figure A-1 shows only definitions, for specification values refer to Table A-10.
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MC9S12H256 Device User Guide — V01.20
A.3 NVM, Flash and EEPROM
NOTE: Unless otherwise noted the abbreviation NVM (Non Volatile Memory) is used for
both Flash and EEPROM.
A.3.1 NVM timing
The time base for all NVM program or erase operations is derived from the oscillator. A minimum
oscillator frequency f
is required for performing program or erase operations. The NVM modules
NVMOSC
do not have any means to monitor the frequency and will not prevent program or erase operation at
frequencies above or below the specified minimum. Attempting to program or erase the NVM modules at
a lower frequency a full program or erase transition is not assured.
The Flash and EEPROM program and erase operations are timed using a clock derived from the oscillator
using the FCLKDIV and ECLKDIV registers respectively. The frequency of this clock must be set within
the limits specified as f
.
NVMOP
The minimum program and erase times shown in Table A-11 are calculated for maximum f
and
NVMOP
maximum f . The maximum times are calculated for minimum f
and a f of 2MHz.
bus
NVMOP
bus
A.3.1.1 Single Word Programming
The programming time for single word programming is dependant on the bus frequency as a well as on
the frequency f and can be calculated according to the following formula.
NVMOP
1
1
t
= 9 ⋅
+ 25 ⋅
---------------------
----------
swpgm
f
f
NVMOP
bus
A.3.1.2 Burst Programming
This applies only to the Flash where up to 32 words in a row can be programmed consecutively using burst
programming by keeping the command pipeline filled. The time to program a consecutive word can be
calculated as:
1
1
t
= 4 ⋅
+ 9 ⋅
---------------------
----------
bwpgm
f
f
NVMOP
bus
The time to program a whole row is:
t
= t
+ 31 ⋅ t
swpgm bwpgm
brpgm
Burst programming is more than 2 times faster than single word programming.
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MC9S12H256 Device User Guide — V01.20
A.3.1.3 Sector Erase
Erasing a 512 byte Flash sector or a 4 byte EEPROM sector takes:
1
t
≈ 4000 ⋅
---------------------
era
f
NVMOP
The setup time can be ignored for this operation.
A.3.1.4 Mass Erase
Erasing a NVM block takes:
1
t
≈ 20000 ⋅
---------------------
mass
The setup time can be ignored for this operation.
f
NVMOP
Table A-11 NVM Timing Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C
Rating
Symbol
fNVMOSC
fNVMBUS
fNVMOP
tswpgm
Min
0.5
1
Typ
Max
Unit
MHz
MHz
kHz
µs
32 1
1
2
3
4
5
6
7
8
D External Oscillator Clock
D Bus frequency for Programming or Erase Operations
D Operating Frequency
150
200
74.5 3
31 3
46 2
20.4 2
678.4 2
20 5
P Single Word Programming Time
Flash Burst Programming consecutive word 4
Flash Burst Programming Time for 32 Words 4
tbwpgm
tbrpgm
tera
D
D
µs
1035.5 3
26.7 3
133 3
µs
P Sector Erase Time
P Mass Erase Time
ms
100 5
tmass
ms
NOTES:
1. Restrictions for oscillator in crystal mode apply!
2. Minimum Programming times are achieved under maximum NVM operating frequency fNVMOP and maximum bus frequency
fbus
.
3. Maximum Erase and Programming times are achieved under particular combinations of fNVMOP and bus frequency fbus
Refer to formulae in Sections A.3.1.1 - A.3.1.4 for guidance.
.
4. urst Programming operations are not applicable to EEPROM
5. Minimum Erase times are achieved under maximum NVM operating frequency fNVMOP
.
A.3.2 NVM Reliability
The reliability of the NVM blocks is guaranteed by stress test during qualification, constant process
monitors and burn-in to screen early life failures.
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MC9S12H256 Device User Guide — V01.20
The failure rates for data retention and program/erase cycling are specified at the operating conditions
noted.
The program/erase cycle count on the sector is incremented every time a sector or mass erase event is
executed.
Table A-12 NVM Reliability Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Data Retention
Num C
Rating
Cycles
Unit
Lifetime
10
1
2
C Flash/EEPROM (-40˚C to +125˚C)
C EEPROM (-40˚C to +125˚C)
15
5
Years
Years
10,000
NOTE: Flash cycling performance is 10 cycles at -40˚C to +125˚C. Data retention is
specified for 15 years.
NOTE: EEPROM cycling performance is 10K cycles at -40˚C to 125˚C. Data retention is
specified for 5 years on words after cycling 10K times. However if only 10 cycles
are executed on a word the data retention is specified for 15 years.
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MC9S12H256 Device User Guide — V01.20
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MC9S12H256 Device User Guide — V01.20
A.4 Reset, Oscillator and PLL
This section summarizes the electrical characteristics of the various startup scenarios for Oscillator and
Phase-Locked-Loop (PLL).
A.4.1 Startup
Table A-13 summarizes several startup characteristics explained in this section. Detailed description of
the startup behavior can be found in the Clock and Reset Generator (CRG) Block User Guide.
Table A-13 Startup Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C
Rating
Symbol
VPORR
VPORA
PWRSTL
nRST
Min
Typ
Max
Unit
V
1
2
3
4
5
6
T POR release level
T POR assert level
2.07
0.97
2
V
tosc
nosc
D Reset input pulse width, minimum input time
D Startup from Reset
192
20
196
14
PWIRQ
tWRS
D Interrupt pulse width, IRQ edge-sensitive mode
D Wait recovery startup time
ns
tcyc
A.4.1.1 POR
The release level V
and the assert level V
are derived from the VDD supply. They are also valid
PORA
PORR
if the device is powered externally. After releasing the POR reset the oscillator and the clock quality check
are started. If after a time t no valid oscillation is detected, the MCU will start using the internal self
CQOUT
clock. The fastest startup time possible is given by n
.
uposc
A.4.1.2 SRAM Data Retention
Provided an appropriate external reset signal is applied to the MCU, preventing the CPU from executing
code when VDD5 is out of specification limits, the SRAM contents integrity is guaranteed if after the reset
the PORF bit in the CRG Flags Register has not been set.
A.4.1.3 External Reset
When external reset is asserted for a time greater than PW
the CRG module generates an internal
RSTL
reset, and the CPU starts fetching the reset vector without doing a clock quality check, if there was an
oscillation before reset.
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MC9S12H256 Device User Guide — V01.20
A.4.1.4 Stop Recovery
Out of STOP the controller can be woken up by an external interrupt. A clock quality check as after POR
is performed before releasing the clocks to the system.
A.4.1.5 Pseudo Stop and Wait Recovery
The recovery from Pseudo STOP and Wait are essentially the same since the oscillator was not stopped in
both modes. The controller can be woken up by internal or external interrupts. After t the CPU starts
wrs
fetching the interrupt vector.
A.4.2 Oscillator
The device features an internal Colpitts oscillator. By asserting the XCLKS input during reset this
oscillator can be bypassed allowing the input of a square wave. Before asserting the oscillator to the
internal system clocks the quality of the oscillation is checked for each start from either power-on, STOP
or oscillator fail. t
specifies the maximum time before switching to the internal self clock mode after
CQOUT
POR or STOP if a proper oscillation is not detected. The quality check also determines the minimum
oscillator start-up time t . The device also features a clock monitor. A Clock Monitor Failure is
UPOSC
asserted if the frequency of the incoming clock signal is below the Assert Frequency f
CMFA.
Table A-14 Oscillator Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C
Rating
Symbol
fOSC
Min
0.5
Typ
Max
Unit
MHz
1
2
3
4
5
6
7
8
9
C Crystal oscillator range
P Startup Current
16
iOSC
100
µA
nUPOSC
cycOSC
D Oscillator start-up time from POR or STOP
C Oscillator start-up time
4100
81
1002
2.5
tUPOSC
tCQOUT
fCMFA
fEXT
ms
s
D Clock Quality check time-out
0.45
50
P Clock Monitor Failure Assert Frequency
100
200
32
KHz
MHz
ns
External square wave input frequency3
P
0.5
15
tEXTL
tEXTH
tEXTR
tEXTF
CIN
D External square wave pulse width low
D External square wave pulse width high
15
ns
10 D External square wave rise time
11 D External square wave fall time
12 D Input Capacitance EXTAL pin
13 D Input Capacitance XTAL pin
DC Operating Bias in Colpitts Configuration on
1
1
ns
ns
9
pF
pF
CIN
13
VDCBIAS
14
C
1.1
V
EXTAL Pin
NOTES:
1. fosc = 4MHz, C = 22pF.
2. Maximum value is for extreme cases using high Q, low frequency crystals
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MC9S12H256 Device User Guide — V01.20
3. XCLKS =1 during reset
A.4.3 Phase Locked Loop
The oscillator provides the reference clock for the PLL. The PLL´s Voltage Controlled Oscillator (VCO)
is also the system clock source in self clock mode.
A.4.3.1 XFC Component Selection
This section describes the selection of the XFC components to achieve a good filter characteristics.
VDDPLL
C
C
s
p
R
Phase
VCO
f
f
vco
f
1
ref
osc
∆
K
K
Φ
V
refdv+1
Detector
f
cmp
Loop Divider
1
1
synr+1
2
Figure A-2 Basic PLL functional diagram
The following procedure can be used to calculate the resistance and capacitance values using typical
values for K , f and i from Table A-15.
1
1
ch
The VCO Gain at the desired VCO output frequency is approximated by:
(f1 – fvco
)
-----------------------
K1 ⋅ 1V
K = K ⋅ e
V
1
The phase detector relationship is given by:
K = i ⋅ K
V
Φ
ch
i is the current in tracking mode.
ch
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MC9S12H256 Device User Guide — V01.20
The loop bandwidth f should be chosen to fulfill the Gardner’s stability criteria by at least a factor of 10,
C
typical values are 50. ζ = 0.9 ensures a good transient response.
2 ⋅ ζ ⋅ f
f
ref
1
ref
f < ------------------------------------------
→ f < ------------- ;(ζ = 0.9)
------
50
C
C
4 ⋅ 50
2
⎛
⎞
π ⋅ ζ + 1 + ζ
⎝
⎠
And finally the frequency relationship is defined as
f
VCO
n = ------------- = 2 ⋅ (s y n r + 1 )
f
ref
With the above inputs the resistance can be calculated as:
2 ⋅ π ⋅ n ⋅ f
C
R = ----------------------------
K
Φ
The capacitance C can now be calculated as:
s
2
0.516
2 ⋅ ζ
C =
≈ --------------;(ζ = 0.9)
---------------------
s
f ⋅ R
π ⋅ f ⋅ R
C
C
The capacitance C should be chosen in the range of:
p
C ⁄ 20 ≤ C ≤ C ⁄ 10
s
p
s
The stabilization delays shown in Table A-15 are dependant on PLL operational settings and external
component selection (e.g. crystal, XFC filter).
A.4.3.2 Jitter Information
The basic functionality of the PLL is shown in Figure A-2. With each transition of the clock f , the
cmp
deviation from the reference clock f is measured and input voltage to the VCO is adjusted
ref
accordingly.The adjustment is done continuously with no abrupt changes in the clock output frequency.
Noise, voltage, temperature and other factors cause slight variations in the control loop resulting in a clock
jitter. This jitter affects the real minimum and maximum clock periods as illustrated in Figure A-3.
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MC9S12H256 Device User Guide — V01.20
1
2
3
N–1
N
0
t
min1
t
nom
t
max1
t
minN
t
maxN
Figure A-3 Jitter Definitions
is at its maximum for one clock period, and decreases towards zero for larger
The relative deviation of t
nom
number of clock periods (N).
Defining the jitter as:
t
(N)
t
(N)
min
⎛
⎞
⎟
⎠
max
J(N) = max 1 –
, 1 –
--------------------
---------------------
⎜
N ⋅ t
N ⋅ t
⎝
nom
nom
For N < 100, the following equation is a good fit for the maximum jitter:
j
1
J(N) =
+ j
-------
2
N
J(N)
1
5
10
20
N
Figure A-4 Maximum bus clock jitter approximation
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MC9S12H256 Device User Guide — V01.20
This is very important to notice with respect to timers, serial modules where a pre-scaler will eliminate the
effect of the jitter to a large extent.
Table A-15 PLL Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C
Rating
Symbol
fSCM
Min
1
Typ
Max
5.5
Unit
MHz
MHz
1
2
P Self Clock Mode frequency
D VCO locking range
fVCO
8
32
Lock Detector transition from Acquisition to Tracking
mode
1
|∆trk
|
3
D
3
4
%
1
|∆Lock
|
4
5
D Lock Detection
0
1.5
2.5
%
1
|∆unl
|
D Un-Lock Detection
0.5
%
Lock Detector transition from Tracking to Acquisition
mode
1
|∆unt
|
6
D
6
8
%
PLLON Total Stabilization delay (Auto Mode) 2
C
tstab
tacq
tal
7
8
0.5
0.3
ms
ms
PLLON Acquisition mode stabilization delay 2
D
PLLON Tracking mode stabilization delay 2
D
9
0.2
ms
Fitting parameter VCO loop gain3
P
K1
f1
10
–120
75
-224
MHz/V
MHz
µA
11 D Fitting parameter VCO loop frequency
| ich
| ich
j1
|
12
13
14
15
P Charge pump current acquisition mode
P Charge pump current tracking mode
20
2
38.5
3.5
60
6
|
µA
Jitter fit parameter 12
C
1.1
0.13
%
Jitter fit parameter 22
C
j2
%
NOTES:
1. % deviation from target frequency
2. fREF = 4MHz, fBUS = 16MHz equivalent fVCO = 32MHz: REFDV = #$03, SYNR = #$0F, Cs = 4.7nF, Cp = 470pF, Rs = 10KΩ.
3. K1 is measured with VXFC = 1.4V and VXFC = 1.7V @ VDD5 = 5.25V
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MC9S12H256 Device User Guide — V01.20
A.5 MSCAN
Table A-16 MSCAN Wake-up Pulse Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C
Rating
Symbol
tWUP
Min
Typ
Max
Unit
µs
1
2
P MSCAN Wake-up dominant pulse filtered
P MSCAN Wake-up dominant pulse pass
2
tWUP
5
µs
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A.6 SPI
A.6.1 Master Mode
Figure A-5 and Figure A-6 illustrate the master mode timing. Timing values are shown in Table A-17.
SS1
(OUTPUT)
2
1
11
12
3
SCK
(CPOL = 0)
(OUTPUT)
4
4
SCK
(CPOL = 1)
(OUTPUT)
5
6
MISO
(INPUT)
MSB IN2
LSB IN
BIT 6 . . . 1
9
9
10
MOSI
(OUTPUT)
MSB OUT2
BIT 6 . . . 1
LSB OUT
1. If configured as output.
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure A-5 SPI Master Timing (CPHA = 0)
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MC9S12H256 Device User Guide — V01.20
SS1
(OUTPUT)
1
12
11
11
12
3
2
SCK
(CPOL = 0)
(OUTPUT)
4
4
SCK
(CPOL = 1)
(OUTPUT)
5
6
MISO
(INPUT)
MSB IN2
BIT 6 . . . 1
10
BIT 6 . . . 1
LSB IN
9
MOSI
(OUTPUT)
MASTER MSB OUT2
PORT DATA
MASTER LSB OUT
PORT DATA
1. If configured as output
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure A-6 SPI Master Timing (CPHA =1)
1
Table A-17 SPI Master Mode Timing Characteristics
Conditions are shown in Table A-4 unless otherwise noted, CLOAD = 200pF on all outputs
Num C
Rating
Symbol
Min
DC
Typ
Max
1/4
Unit
fbus
tbus
tsck
fop
tsck
tlead
tlag
twsck
tsu
thi
1
1
2
3
4
5
6
9
P Operating Frequency
SCK Period tsck = 1./fop
P
4
2048
—
D Enable Lead Time
1/2
tsck
D Enable Lag Time
1/2
tbus − 30
1024 tbus
D Clock (SCK) High or Low Time
D Data Setup Time (Inputs)
D Data Hold Time (Inputs)
D Data Valid (after SCK Edge)
ns
ns
ns
ns
ns
ns
ns
25
0
tv
25
tho
tr
10 D Data Hold Time (Outputs)
11 D Rise Time Inputs and Outputs
12 D Fall Time Inputs and Outputs
NOTES:
0
25
25
tf
1. The numbers 7, 8 in the column labeled “Num” are missing. This has been done on purpose to be consistent between the
Master and the Slave timing shown in Table A-18.
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MC9S12H256 Device User Guide — V01.20
A.6.2 Slave Mode
Figure A-7 and Figure A-8 illustrate the slave mode timing. Timing values are shown in Table A-18.
SS
(INPUT)
1
12
11
11
12
3
SCK
(CPOL = 0)
(INPUT)
4
4
2
SCK
(CPOL = 1)
(INPUT)
8
7
9
10
10
MISO
(OUTPUT)
BIT 6 . . . 1
SLAVE LSB OUT
MSB OUT
6
SLAVE
5
MOSI
(INPUT)
BIT 6 . . . 1
MSB IN
LSB IN
Figure A-7 SPI Slave Timing (CPHA = 0)
SS
(INPUT)
3
1
12
11
12
2
SCK
(CPOL = 0)
(INPUT)
4
4
11
10
SCK
(CPOL = 1)
(INPUT)
8
9
MISO
(OUTPUT)
BIT 6 . . . 1
SLAVE LSB OUT
LSB IN
SLAVE MSB OUT
7
5
6
MOSI
(INPUT)
MSB IN
BIT 6 . . . 1
Figure A-8 SPI Slave Timing (CPHA =1)
117
MC9S12H256 Device User Guide — V01.20
Table A-18 SPI Slave Mode Timing Characteristics
Conditions are shown in Table A-4 unless otherwise noted, CLOAD = 200pF on all outputs
Num C
Rating
Symbol
fop
Min
Typ
Max
1/4
Unit
fbus
tbus
tcyc
1
1
2
3
4
5
6
7
8
9
P Operating Frequency
SCK Period tsck = 1./fop
DC
tsck
tlead
tlag
twsck
tsu
P
4
2048
D Enable Lead Time
1
1
tcyc
D Enable Lag Time
tcyc − 30
D Clock (SCK) High or Low Time
D Data Setup Time (Inputs)
D Data Hold Time (Inputs)
D Slave Access Time
ns
ns
25
25
thi
ns
ta
tcyc
tcyc
1
1
tdis
tv
D Slave MISO Disable Time
D Data Valid (after SCK Edge)
25
ns
ns
ns
ns
tho
10 D Data Hold Time (Outputs)
11 D Rise Time Inputs and Outputs
12 D Fall Time Inputs and Outputs
0
tr
25
25
tf
118
MC9S12H256 Device User Guide — V01.20
A.7 LCD_32F4B
Table A.7-19 LCD_32F4B Driver Electrical Characteristics
Characteristic
Symbol
Min.
Typ.
Max.
Unit
LCD Supply Voltage
VLCD
-0.25
-
VDDX + 0.25
V
LCD Output Impedance(BP[3:0],FP[31:0])
for outputs to charge to higher voltage level or to
GND 1
ZBP/FP
-
-
-
5.0
-
kOhm
uA
LCD Output Current (BP[3:0],FP[31:0])
for outputs to discharge to lower voltage level
except GND 2
IBP/FP
50
NOTES:
1. Outputs measured one at a time, low impedance voltage source connected to the VLCD pin.
2. Outputs measured one at a time, low impedance voltage source connected to the VLCD pin.
119
MC9S12H256 Device User Guide — V01.20
120
MC9S12H256 Device User Guide — V01.20
A.8 External Bus Timing
A timing diagram of the external multiplexed-bus is illustrated in Figure A-9 with the actual timing values
shown on table Table A-20. All major bus signals are included in the diagram. While both a data write
and data read cycle are shown, only one or the other would occur on a particular bus cycle.
A.8.1 General Muxed Bus Timing
The expanded bus timings are highly dependent on the load conditions. The timing parameters shown
assume a balanced load across all outputs.
121
MC9S12H256 Device User Guide — V01.20
1, 2
3
4
ECLK
PE4
5
9
6
16
10
15
11
Addr/Data
(read)
PA, PB
data
data
addr
7
8
12
14
data
13
Addr/Data
(write)
PA, PB
data
addr
17
19
23
26
18
Non-Multiplexed
Addresses
PK5:0
20
21
22
ECS
PK7
24
25
28
R/W
PE2
27
29
32
LSTRB
PE3
31
34
30
NOACC
PE7
35
36
33
IPIPO0
IPIPO1, PE6,5
Figure A-9 General External Bus Timing
122
MC9S12H256 Device User Guide — V01.20
Table A-20 Expanded Bus Timing Characteristics
Conditions are shown in Table A-4 unless otherwise noted, CLOAD = 50pF
Num C
Rating
Symbol
fo
Min
0
Typ
Max
Unit
MHz
ns
1
2
3
4
5
6
7
8
9
P Frequency of operation (E-clock)
P Cycle time
16.0
tcyc
62.5
30
PWEL
D Pulse width, E low
ns
Pulse width, E high1
D
PWEH
tAD
30
ns
D Address delay time
8
ns
Address valid time to E rise (PWEL–tAD
)
tAV
D
22
2
ns
tMAH
tAHDS
tDHA
tDSR
tDHR
tDDW
tDHW
tDSW
D Muxed address hold time
D Address hold to data valid
D Data hold to address
ns
7
ns
2
ns
10 D Read data setup time
11 D Read data hold time
12 D Write data delay time
13 D Write data hold time
24
0
ns
ns
7
ns
2
23
30
6
ns
Write data setup time1 (PWEH–tDDW
)
14
15
16
D
D
D
ns
ns
Address access time1 (tcyc–tAD–tDSR
E high access time1 (PWEH–tDSR
)
tACCA
tACCE
tNAD
tNAV
tNAH
tCSD
tACCS
tCSH
tCSN
tRWD
tRWV
tRWH
tLSD
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
)
17 D Non-multiplexed address delay time
Non-muxed address valid to E rise (PWEL–tNAD
6
)
18
D
26
2
19 D Non-multiplexed address hold time
20 D Chip select delay time
6 + tcyc/4
Chip select access time1 (tcyc–tCSD–tDSR
D
)
tcyc/4 – 2
21
22 D Chip select hold time
23 D Chip select negated time
24 D Read/write delay time
2
8
7
7
7
Read/write valid time to E rise (PWEL–tRWD
)
25
D
25
2
26 D Read/write hold time
27 D Low strobe delay time
Low strobe valid time to E rise (PWEL–tLSD
)
tLSV
28
D
25
2
tLSH
29 D Low strobe hold time
tNOD
tNOV
30 D NOACC strobe delay time
NOACC valid time to E rise (PWEL–tNOD
)
31
D
25
123
MC9S12H256 Device User Guide — V01.20
Table A-20 Expanded Bus Timing Characteristics
Conditions are shown in Table A-4 unless otherwise noted, CLOAD = 50pF
Num C
Rating
Symbol
tNOH
Min
2
Typ
Max
Unit
ns
32 D NOACC hold time
33 D IPIPO[1:0] delay time
tP0D
2
7
ns
IPIPO[1:0] valid time to E rise (PWEL–tP0D
)
tP0V
34
35
D
D
22
ns
IPIPO[1:0] delay time1 (PWEH–tP1V
)
tP1D
tP1V
2
25
ns
ns
36 D IPIPO[1:0] valid time to E fall
22
NOTES:
1. Affected by clock stretch: add N x tcyc where N=0,1,2 or 3, depending on the number of clock stretches.
124
MC9S12H256 Device User Guide — V01.20
Appendix B Package Information
B.1 General
This section provides the physical dimensions of the MC9S12H256 and MC9S12H128 packages.
125
MC9S12H256 Device User Guide — V01.20
B.2 112-pin LQFP package
4X
0.20 T L-M N
4X 28 TIPS
0.20 T L-M N
4X
P
J1
J1
PIN 1
IDENT
112
85
C
1
84
L
VIEW Y
X
108X
G
X=L, M OR N
VIEW Y
V
B
L
M
AA
J
B1
V1
28
57
BASE
METAL
F
D
29
56
M
0.13
T L-M N
N
SECTION J1-J1
A1
S1
ROTATED 90 COUNTERCLOCKWISE
°
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
A
2. DIMENSIONS IN MILLIMETERS.
3. DATUMS L, M AND N TO BE DETERMINED AT
SEATING PLANE, DATUM T.
S
4. DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE, DATUM T.
5. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION. ALLOWABLE
PROTRUSION IS 0.25 PER SIDE. DIMENSIONS
A AND B INCLUDE MOLD MISMATCH.
6. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL NOT CAUSE THE D
DIMENSION TO EXCEED 0.46.
C2
VIEW AB
θ2
C
0.050
112X
0.10
T
SEATING
PLANE
MILLIMETERS
DIM MIN
MAX
20.000 BSC
10.000 BSC
θ3
A
A1
B
B1
C
T
20.000 BSC
10.000 BSC
---
1.600
C1 0.050
C2 1.350
0.150
1.450
0.370
0.750
0.330
θ
D
E
F
0.270
0.450
0.270
G
J
K
0.650 BSC
0.090
0.170
R R2
0.500 REF
0.325 BSC
P
R1 0.100
R2 0.100
0.200
0.200
0.25
R R1
S
S1
V
V1
Y
22.000 BSC
11.000 BSC
GAGE PLANE
22.000 BSC
11.000 BSC
0.250 REF
1.000 REF
Z
(K)
C1
θ1
AA 0.090
0.160
8 °
E
0 °
θ
θ1
θ2
θ3
3 °
11 °
11 °
7 °
(Y)
(Z)
13 °
13 °
VIEW AB
Figure B-1 112-pin LQFP mechanical dimensions (case no. 987)
126
MC9S12H256 Device User Guide — V01.20
B.3 144-pin LQFP package
0.20 T L-M N
0.20 T L-M N
4X
4X 36 TIPS
PIN 1
IDENT
144
109
1
108
4X
P
J1
J1
L
M
C
L
V
B
X
X=L, M OR N
140X
G
B1
V1
VIEW Y
VIEW Y
NOTES:
36
73
1. DIMENSIONS AND TOLERANCING PER ASME
Y14.5M, 1994.
2. DIMENSIONS IN MILLIMETERS.
3. DATUMS L, M, N TO BE DETERMINED AT THE
SEATING PLANE, DATUM T.
4. DIMENSIONS S AND V TO BE DETERMINED
AT SEATING PLANE, DATUM T.
5. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION. ALLOWABLE
PROTRUSION IS 0.25 PER SIDE. DIMENSIONS
A AND B DO INCLUDE MOLD MISMATCH
AND ARE DETERMINED AT DATUM PLANE H.
6. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL NOT CAUSE THE D
DIMENSION TO EXCEED 0.35.
37
72
N
A1
S1
A
S
VIEW AB
C
144X
MILLIMETERS
DIM MIN MAX
0.1 T
θ2
θ2
A
A1
B
B1
C
C1
C2
D
20.00 BSC
10.00 BSC
20.00 BSC
10.00 BSC
SEATING
PLANE
1.40
0.05
1.35
0.17
0.45
0.17
1.60
T
0.15
1.45
0.27
0.75
0.23
E
F
PLATING
G
J
0.50 BSC
J
C2
AA
F
0.09
0.20
0.05
K
P
0.50 REF
0.25 BSC
R2
R1
R2
S
S1
V
V1
Y
Z
0.13
0.13
0.20
0.20
θ
R1
22.00 BSC
11.00 BSC
22.00 BSC
11.00 BSC
0.25 REF
1.00 REF
BASE
METAL
0.25
D
GAGE PLANE
M
0.08
T L-M N
AA
θ
θ1
θ2
0.09
0
0.16
°
SECTION J1-J1
(ROTATED 90
144 PL
(K)
E
0
7
13
°
°
°
°
)
°
11
C1
θ 1
(Y)
VIEW AB
CASE 918-03
ISSUE C
(Z)
Figure B-2 144-pin LQFP mechanical dimensions (case no. 918-03)
127
MC9S12H256 Device User Guide — V01.20
128
MC9S12H256 Device User Guide — V01.20
User Guide End Sheet
129
MC9S12H256 Device User Guide — V01.20
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130
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