MM54HC138J [ROCHESTER]
Decoder/Driver, HC/UH Series, Inverted Output, CMOS, CDIP16, DIP-16;
| 型号： | MM54HC138J |
| 厂家： | 
Rochester Electronics |
| 描述： | Decoder/Driver, HC/UH Series, Inverted Output, CMOS, CDIP16, DIP-16 驱动 CD 输入元件 逻辑集成电路 |
| 文件： | 总4页 (文件大小：114K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
January 1988
MM54HC138/MM74HC138
3-to-8 Line Decoder
General Description
This decoder utilizes advanced silicon-gate CMOS technol-
ogy, and is well suited to memory address decoding or data
routing applications. The circuit features high noise immuni-
ty and low power consumption usually associated with
CMOS circuitry, yet has speeds comparable to low power
Schottky TTL logic.
The decoder’s outputs can drive 10 low power Schottky TTL
equivalent loads, and are functionally and pin equivalent to
the 54LS138/74LS138. All inputs are protected from dam-
age due to static discharge by diodes to V
and ground.
CC
Features
Y
The MM54HC138/MM74HC138 has 3 binary select inputs
(A, B, and C). If the device is enabled these inputs deter-
mine which one of the eight normally high outputs will go
low. Two active low and one active high enables (G1, G2A
and G2B) are provided to ease the cascading of decoders.
Typical propagation delay: 20 ns
Y
Wide power supply range: 2V–6V
Y
Low quiescent current: 80 mA maximum (74HC Series)
Low input current: 1 mA maximum
Y
Y
Fanout of 10 LS-TTL loads
Connection and Logic Diagrams
Dual-In-Line Package
TL/F/5120–1
Order Number MM54HC138
or MM74HC138
TL/F/5120–2
Truth Table
Inputs
Outputs
Enable
Select
G1 G2*
C
B
A
Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
X
L
H
X
L
L
L
L
L
L
L
L
X
X
L
X
X
L
X
X
L
H
L
H
L
H
L
H
H
L
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
H
H
H
L
L
H
H
H
H
H
H
H
H
H
H
H
H
e
a
* G2 G2A G2B
e
e e
high level, L low level, X don’t care
H
C
1995 National Semiconductor Corporation
TL/F/5120
RRD-B30M105/Printed in U. S. A.
Absolute Maximum Ratings (Notes 1 & 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Operating Conditions
Min
Max
6
Units
V
Supply Voltage (V
)
CC
2
DC Input or Output Voltage
(V , V
0
V
CC
V
b
a
0.5 to 7.0V
Supply Voltage (V
)
CC
)
IN OUT
b
b
a
a
DC Input Voltage (V
)
1.5 to V
1.5V
0.5V
Operating Temp. Range (T )
A
MM74HC
MM54HC
IN
CC
CC
b
b
a
85
40
55
C
C
§
DC Output Voltage (V
)
0.5 to V
OUT
a
125
§
g
g
g
Clamp Diode Current (I , I
)
20 mA
25 mA
50 mA
IK OK
Input Rise or Fall Times
DC Output Current, per pin (I
)
OUT
e
e
e
(t , t )
r f
V
V
V
2.0V
4.5V
6.0V
1000
500
400
ns
ns
ns
CC
CC
CC
DC V or GND Current, per pin (I
CC
)
CC
b
a
65 C to 150 C
Storage Temperature Range (T
)
§
§
STG
Power Dissipation (P )
D
(Note 3)
600 mW
500 mW
S.O. Package only
Lead Temp. (T ) (Soldering 10 seconds)
L
260 C
§
DC Electrical Characteristics (Note 4)
74HC
eb
54HC
e
T
A
25 C
§
eb
A
T
A
40 to 85 C
§
T
55 to 125 C
§
Symbol
Parameter
Conditions
V
CC
Units
Typ
Guaranteed Limits
V
V
V
Minimum High Level
Input Voltage
2.0V
4.5V
6.0V
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
V
IH
Maximum Low Level
2.0V
4.5V
6.0V
0.5
1.35
1.8
0.5
1.35
1.8
0.5
1.35
1.8
V
V
V
IL
Input Voltage**
e
V or V
IH IL
Minimum High Level
Output Voltage
V
I
OH
IN
s
20 mA
2.0V
4.5V
6.0V
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
V
l
OUT
l
e
V
I
V
or V
IH IL
IN
s
s
4.0 mA
5.2 mA
4.5V
6.0V
4.2
5.7
3.98
5.48
3.84
5.34
3.7
5.2
V
V
l
l
OUT
OUT
l
l
I
e
V or V
IH IL
V
OL
Maximum Low Level
Output Voltage
V
IN
s
I
20 mA
2.0V
4.5V
6.0V
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
l
OUT
l
e
V
I
V
or V
IH IL
IN
s
s
4.0 mA
5.2 mA
4.5V
6.0V
0.2
0.2
0.26
0.26
0.33
0.33
0.4
0.4
V
V
l
l
OUT
OUT
l
l
I
e
g
g
g
1.0
I
I
Maximum Input
Current
V
V
or GND 6.0V
0.1
1.0
mA
IN
IN
CC
e
Maximum Quiescent
Supply Current
V
IN
V
CC
or GND 6.0V
8.0
80
160
mA
CC
e
I
0 mA
OUT
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
b
b
Note 3: Power Dissipation temperature derating Ð plastic ‘‘N’’ package: 12 mW/ C from 65 C to 85 C; ceramic ‘‘J’’ package: 12 mW/ C from 100 C to 125 C.
§
§
§
§
Note 4: For a power supply of 5V 10% the worst case output voltages (V , and V ) occur for HC at 4.5V. Thus the 4.5V values should be used when designing
§
§
g
OH OL
5.5V and 4.5V respectively. (The V value at 5.5V is 3.85V.) The worst case leakage current (I , I , and
IH IN CC
e
with this supply. Worst case V and V occur at V
IH IL
CC
) occur for CMOS at the higher voltage and so the 6.0V values should be used.
I
OZ
**V limits are currently tested at 20% of V . The above V specification (30% of V ) will be implemented no later than Q1, CY’89.
IL CC IL CC
2
e
e
e
e e
15 pF, t t 6 ns
r f
AC Electrical Characteristics V
5V, T
25 C, C
§
CC
A
L
Guaranteed
Limit
Symbol
Parameter
Conditions
Typ
Units
t
t
t
t
Maximum Propagation
18
28
18
23
25
35
25
30
ns
ns
ns
ns
PLH
Delay, Binary Select to any Output
Maximum Propagation
PHL
Delay, Binary Select to any Output
, t
PHL PLH
Maximum Propagation
Delay, G1 to any Output
Maximum Propagation
Delay G2A or G2B to
Output
PHL
t
Maximum Propagation
Delay G2A or G2B to
Output
18
25
ns
PLH
e
e
e
t 6 ns (unless otherwise specified)
f
AC Electrical Characteristics C 50 pF, t
L
r
74HC
54HC
e
T
A
25 C
§
eb
eb
T
40 to 85 C
§
T
A
55 to 125 C
§
Symbol
Parameter
Conditions
V
Units
A
CC
Typ
Guaranteed Limits
t
t
t
t
t
t
Maximum Propagation
Delay Binary Select to
any Output Low to High
2.0V
4.5V
6.0V
75
15
13
150
30
189
38
224
45
ns
ns
ns
PLH
26
32
38
Maximum Propagation
Delay Binary Select to any
Output High to Low
2.0V
4.5V
6.0V
100
20
200
40
252
50
298
60
ns
ns
ns
PHL
17
34
43
51
, t
PHL PLH
Maximum Propagation
Delay G1 to any
Output
2.0V
4.5V
6.0V
75
15
13
150
30
189
38
224
45
ns
ns
ns
26
32
38
Maximum Propagation
Delay G2A or G2B to
Output
2.0V
4.5V
6.0V
82
28
22
175
35
221
44
261
52
ns
ns
ns
PHL
PLH
30
37
44
Maximum Propagation
Delay G2A or G2B to
Output
2.0V
4.5V
6.0V
75
15
13
150
30
189
38
224
45
ns
ns
ns
26
32
38
, t
TLH THL
Output Rise and
Fall Time
2.0V
4.5V
6.0V
30
8
75
15
13
95
19
16
110
22
ns
ns
ns
7
19
C
C
Maximum Input
Capacitance
3
10
10
10
pF
IN
Power Dissipation
Capacitance
(Note 5)
75
pF
PD
2
e
a
e
a
f I
PD CC CC
Note 5: C determines the no load dynamic power consumption, P
PD
C
V
PD CC
f
I
V
CC CC
, and the no load dynamic current consumption, I
C
V
.
D
S
3
Physical Dimensions inches (millimeters)
Order Number MM54HC138J or MM74HC138J
NS Package Number J16A
Order Number MM74HC138N
NS Package Number N16E
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and whose
failure to perform, when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
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Corporation
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相关型号：
MM54HC138W
IC HC/UH SERIES, OTHER DECODER/DRIVER, INVERTED OUTPUT, CDFP16, CERAMIC, FP-16, Decoder/Driver
TI
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