MM74C76N [ROCHESTER]
J-K Flip-Flop, CMOS Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output, CMOS, PDIP16, 0.300 INCH, PLASTIC, MS-001, DIP-16;
| 型号： | MM74C76N |
| 厂家： | 
Rochester Electronics |
| 描述： | J-K Flip-Flop, CMOS Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output, CMOS, PDIP16, 0.300 INCH, PLASTIC, MS-001, DIP-16 光电二极管 逻辑集成电路 触发器 |
| 文件： | 总8页 (文件大小：240K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
REI Datasheet
MM74C73, MM74C76
Dual J-K Flip-Flops with Clear and Preset
The MM74C73 and MM74C76 dual J-K flip-flops are monolithic complementary MOS (CMOS)
integrated circuits constructed with N- and P-channel enhancement transistors. Each flip-flop has
independent J, K, clock and clear inputs and Q and Q outputs. The MM74C76 flip flops also include
preset inputs and are supplied in 16 pin packages. This flip-flop is edge sensitive to the clock input
and change state on the negative going transition of the clock pulse. Clear or preset is independent
of the clock and is accomplished by a low level on the respective input.
Quality Overview
Rochester Electronics
Manufactured Components
•
•
•
ISO-9001
AS9120 certification
Qualified Manufacturers List (QML) MIL-PRF-38535
Rochester branded components are
manufactured using either die/wafers
purchased from the original suppliers
or Rochester wafers recreated from the
original IP. All recreations are done with
the approval of the OCM.
•
•
Class Q Military
Class V Space Level
•
Qualified Suppliers List of Distributors (QSLD)
•
Rochester is a critical supplier to DLA and
meets all industry and DLA standards.
Parts are tested using original factory
test programs or Rochester developed
test solutions to guarantee product
meets or exceeds the OCM data sheet.
RochesterElectronics, LLCiscommittedtosupplying
products that satisfy customer expectations for
quality and are equal to those originally supplied by
industry manufacturers.
The original manufacturer’s datasheet accompanying this document reflects the performance
and specifications of the Rochester manufactured version of this device. Rochester Electronics
guarantees the performance of its semiconductor products to the original OEM specifications.
‘Typical’ values are for reference purposes only. Certain minimum or maximum ratings may be
based on product characterization, design, simulation, or sample testing.
© 2013 Rochester Electronics, LLC. All Rights Reserved 12122013
To learn more, please visit www.rocelec.com
October 1987
Revised May 2002
MM74C73 • MM74C76
Dual J-K Flip-Flops with Clear and Preset
General Description
Features
The MM74C73 and MM74C76 dual J-K flip-flops are mono-
lithic complementary MOS (CMOS) integrated circuits con-
structed with N- and P-channel enhancement transistors.
Each flip-flop has independent J, K, clock and clear inputs
and Q and Q outputs. The MM74C76 flip flops also include
preset inputs and are supplied in 16 pin packages. This
flip-flop is edge sensitive to the clock input and change
state on the negative going transition of the clock pulse.
Clear or preset is independent of the clock and is accom-
plished by a low level on the respective input.
■ Supply voltage range: 3V to 15V
■ Tenth power TTL compatible: Drive 2 LPTTL loads
■ High noise immunity: 0.45 VCC (typ.)
■ Low power: 50 nW (typ.)
■ Medium speed operation: 10 MHz (typ.)
Applications
•
•
•
•
•
•
•
•
Automotive
Data terminals
Instrumentation
Medical electronics
Alarm systems
Industrial electronics
Remote metering
Computers
Ordering Code:
Order Number Package Number
Package Description
MM74C73N
MM74C76M
MM74C76N
N14A
M16A
N16E
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagrams
MM74C73
MM74C76
Note: A logic “0” on clear sets Q to a logic “0”.
Note: A logic “0” on preset sets Q to a logic “1”.
Note: A logic “0” on clear sets Q to logic “0”.
Top View
Top View
© 2002 Fairchild Semiconductor Corporation
DS005884
www.fairchildsemi.com
Truth Table
tn
tn+1
Qn
Qn
Preset
Clear
J
0
0
1
1
K
0
1
0
1
Q
Qn
0
0
0
1
1
0
1
0
1
0
0
1
0
0
1
1
Qn
Qn
Qn
(Note 1)
(Note 1)
t
t
n = bit time before clock pulse
n+1 = bit time after clock pulse
Note 1: No change in output from previous state
Logic Diagrams
MM74C73
MM74C76
Transmission Gate
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2
Absolute Maximum Ratings(Note 2)
Voltage at Any Pin
Operating Temperature Range
Storage Temperature
Power Dissipation
Dual-In-Line
−0.3V to VCC + 0.3V
−55°C to +125°C
−65°C to +150°C
700 mW
500 mW
Small Outline
Note 2: “Absolute Maximum Ratings” are those values beyond which the
safety of the device cannot be guaranteed. Except for “Operating Tempera-
ture Range” they are not meant to imply that the devices should be oper-
ated at these limits. The table of Electrical Characteristics provides
conditions for actual device operation.
Lead Temperature
(Soldering, 10 seconds)
Operating VCC Range
VCC (Max)
260°C
+3V to 15V
18V
DC Electrical Characteristics
Min/Max limits apply across temperature range unless otherwise noted
Symbol
Parameter
Conditions
Min
Typ
Max
Units
CMOS TO CMOS
VIN(1)
Logical “1” Input Voltage
Logical “0” Input Voltage
Logical “1” Output Voltage
Logical “0” Output Voltage
V
V
V
V
V
V
V
V
V
V
V
CC = 5V
3.5
8
V
V
V
V
CC = 10V
CC = 5V
VIN(0)
1.5
2
CC = 10V
CC = 5V
VOUT(1)
4.5
9
CC = 10V
CC = 5V
VOUT(0)
0.5
1
CC = 10V
CC = 15V
CC = 15V
CC = 15V
IIN(1)
IIN(0)
ICC
Logical “1” Input Current
Logical “0” Input Current
Supply Current
1
µA
µA
µA
−1
0.050
60
LOW POWER TTL TO CMOS INTERFACE
VIN(1)
Logical “1” Input Voltage
Logical “0” Input Voltage
Logical “1” Output Voltage
Logical “0” Output Voltage
V
V
V
V
CC = 4.75V
V
CC − 1.5
V
V
V
V
VIN(0)
CC = 4.75V
0.8
0.4
VOUT(1)
VOUT(0)
CC = 4.75V, IO = −360 µA
CC = 4.75V, IO = 360 µA
2.4
OUTPUT DRIVE (See Family Characteristics Data Sheet) (Short Circuit Current)
ISOURCE
ISOURCE
ISINK
Output Source Current
Output Source Current
Output Sink Current
Output Sink Current
V
CC = 5V, VIN(0) = 0V
A = 25°C, VOUT = 0V
CC = 10V, VIN(0) = 0V
A = 25°C, VOUT = 0V
CC = 5V, VIN(1) = 5V
A = 25°C, VOUT = VCC
CC = 10V, VIN(1) = 10V
−1.75
−8
mA
mA
mA
mA
T
V
T
V
1.75
8
T
ISINK
V
TA = 25°C, VOUT = VCC
3
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AC Electrical Characteristics (Note 3)
T
A = 25°C, CL = 50 pF, unless otherwise noted
Symbol Parameter
Input Capacitance
Conditions
Min
Typ
5
Max
Units
CIN
Any Input
pF
tpd0, tpd1
Propagation Delay Time to a
Logical “0” or Logical “1” from
Clock to Q or Q
V
CC = 5V
180
70
300
110
ns
VCC = 10V
tpd0
Propagation Delay Time to a
Logical “0” from Preset or Clear
Propagation Delay Time to a
Logical “1” from Preset or Clear
Time Prior to Clock Pulse that
Data must be Present
VCC = 5V
VCC = 10V
VCC = 5V
VCC = 10V
VCC = 5V
VCC = 10V
VCC = 5V
VCC = 10V
VCC = 5V
VCC = 10V
VCC = 5V
VCC = 10V
VCC = 5V
VCC = 10V
VCC = 5V
VCC = 10V
200
80
300
130
300
130
175
70
ns
ns
tpd
200
80
tS
110
45
ns
tH
Time after Clock Pulse that J
and K must be Held
−40
−20
120
50
0
ns
0
tPW
tPW
tMAX
tr, tf
Minimum Clock Pulse Width
190
80
ns
t
WL = tWH
Minimum Preset and Clear
Pulse Width
90
130
60
ns
40
Maximum Toggle Frequency
2.5
7
4
MHz
µs
11
Clock Pulse Rise and Fall Time
15
5
Note 3: AC Parameters are guaranteed by DC correlated testing.
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4
AC Test Circuit
Switching Time Waveforms
CMOS to CMOS
t
r = tf = 20 ns
Typical Applications
Ripple Binary Counters
Shift Registers
74C Compatibility
Guaranteed Noise Margin
as a Function of VCC
5
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Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Package Number N14A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package Number M16A
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6
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Package Number N16E
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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7
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相关型号：
MM74C76NBPLUS
J-K Flip-Flop, CMOS Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output, CMOS, PDIP16, 0.300 INCH, PLASTIC, MS-001, DIP-16
FAIRCHILD
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