MM74HC08MTC [ROCHESTER]
HC/UH SERIES, QUAD 2-INPUT AND GATE, PDSO14, 4.40 MM, MO-153, TSSOP-14;
| 型号： | MM74HC08MTC |
| 厂家： | 
Rochester Electronics |
| 描述： | HC/UH SERIES, QUAD 2-INPUT AND GATE, PDSO14, 4.40 MM, MO-153, TSSOP-14 栅 输入元件 光电二极管 逻辑集成电路 触发器 |
| 文件： | 总10页 (文件大小：974K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
February 2008
MM74HC08
Quad 2-Input AND Gate
Features
General Description
■ Typical propagation delay: 7ns (t
■ Fanout of 10 LS-TTL loads
), 12ns (t
)
The MM74HC08 AND gates utilize advanced silicon-
gate CMOS technology to achieve operating speeds
similar to LS-TTL gates with the low power consumption
of standard CMOS integrated circuits. The HC08 has
buffered outputs, providing high noise immunity and the
ability to drive 10 LS-TTL loads. The 74HC logic family is
functionally as well as pin-out compatible with the stan-
dard 74LS logic family. All inputs are protected from
damage due to static discharge by internal diode clamps
PHL
PLH
■ Quiescent power consumption: 2µA maximum at
room temperature
■ Low input current: 1µA maximum
to V and ground.
CC
Ordering Information
Package
Order Number Number
Package Description
MM74HC08M
MM74HC08SJ
MM74HC08MTC
MM74HC08N
M14A
M14D
MTC14
N14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Device also available in Tape and Reel except for N14A. Specify by appending suffix letter “X” to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
Connection Diagram
Top View
©1983 Fairchild Semiconductor Corporation
MM74HC08 Rev. 1.4.0
www.fairchildsemi.com
(1)
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
Parameter
Rating
V
Supply Voltage
–0.5 to +7.0V
–1.5 to V +1.5V
CC
V
DC Input Voltage
IN
CC
V
DC Output Voltage
Clamp Diode Current
DC Output Current, per pin
–0.5 to V +0.5V
OUT
CC
I , I
20mA
25mA
IK OK
I
OUT
I
DC V or GND Current, per pin
50mA
CC
CC
T
Storage Temperature Range
–65°C to +150°C
STG
P
Power Dissipation
Note 2
D
600mW
500mW
260°C
S.O. Package only
T
Lead Temperature (Soldering 10 seconds)
L
Notes:
1. Unless otherwise specified all voltages are referenced to ground.
2. Power Dissipation temperature derating — plastic “N” package: –12mW/°C from 65°C to 85°C.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
Parameter
Min.
2
Max.
Units
V
Supply Voltage
6
V
V
CC
V , V
DC Input or Output Voltage
0
V
CC
IN OUT
T
Operating Temperature Range
Input Rise or Fall Times
–40
+85
°C
A
t , t
r
f
V
V
V
= 2.0V
= 4.5V
= 6.0V
1000
500
ns
ns
ns
CC
CC
CC
400
©1983 Fairchild Semiconductor Corporation
MM74HC08 Rev. 1.4.0
www.fairchildsemi.com
2
(3)
DC Electrical Characteristics
T = –40°C T = –55°C
A
A
T = 25°C
to 85°C
to 125°C
A
Symbol
Parameter
V
(V)
Conditions
Typ.
1.5
Guaranteed Limits
Units
CC
V
Minimum HIGH Level
Input Voltage
2.0
1.5
3.15
4.2
1.5
V
IH
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
4.5
3.15
4.2
3.15
4.2
0.5
1.35
1.8
1.9
4.4
5.9
3.7
V
Maximum LOW Level
Input Voltage
0.5
0.5
V
V
IL
1.35
1.8
1.35
1.8
V
Minimum HIGH Level
Output Voltage
V
|I
= V ,
2.0
4.5
6.0
4.2
1.9
4.4
1.9
OH
IN
IH
| ≤ 20µA
OUT
4.4
5.9
5.9
V
= V ,
3.98
3.84
IN
IH
|I
| ≤ 4.0mA
OUT
6.0
V
= V ,
5.7
5.48
5.34
5.2
IN
IH
|I
| ≤ 5.2mA
OUT
V
Maximum LOW Level
Output Voltage
2.0
4.5
6.0
4.5
V
= V or V ,
| ≤ 20µA
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.4
V
OL
IN
IH
IL
|I
OUT
0
0.1
0.1
V
= V or V ,
0.2
0.26
0.33
IN
IH
IL
|I
| ≤ 4.0mA
OUT
6.0
6.0
6.0
V
= V or V ,
| ≤ 5.2mA
0.2
0.26
0.1
0.33
1.0
20
0.4
1.0
40
IN
IH
IL
|I
OUT
I
Maximum Input
Current
V
= V or GND
µA
µA
IN
IN
CC
I
Maximum Quiescent
Supply Current
V
= V or GND,
2.0
CC
IN
CC
I
= 0µA
OUT
Note:
3. For a power supply of 5V 10ꢀ the worst case output voltages (V , and V ) occur for HC at 4.5V. Thus the 4.5V
OH
OL
values should be used when designing with this supply. Worst case V and V occur at V = 5.5V and 4.5V
IH
IL
CC
respectively. (The V value at 5.5V is 3.85V.) The worst case leakage current (I , I , and I ) occur for CMOS at
IH
IN CC
OZ
the higher voltage and so the 6.0V values should be used.
©1983 Fairchild Semiconductor Corporation
MM74HC08 Rev. 1.4.0
www.fairchildsemi.com
3
AC Electrical Characteristics
V
= 5V, T = 25°C, C = 15pF, t = t = 6ns
CC
A
L
r
f
Guaranteed
Limit
Symbol
Parameter
Conditions
Typ.
Units
t
Maximum Propagation Delay,
Output HIGH-to-LOW
12
20
ns
PHL
t
Maximum Propagation Delay,
Output LOW-to-HIGH
7
15
ns
PLH
AC Electrical Characteristics
V
= 2.0V to 6.0V, C = 50pF, t = t = 6ns (unless otherwise specified)
CC
L
r
f
T = –40°C
A
T = 25°C
to 125°C
A
Symbol
Parameter
V
(V) Conditions
Typ.
77
15
13
30
10
8
Guaranteed Limits Units
CC
t
Maximum Propagation Delay,
Output HIGH-to-LOW
2.0
121
24
20
90
18
15
75
15
13
175
35
ns
ns
ns
PHL
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
30
t
Maximum Propagation Delay,
Output LOW-to-HIGH
134
27
PLH
23
t
, t
Maximum Output Rise and Fall
Time
30
8
110
22
TLH THL
7
19
C
Power Dissipation
Capacitance
(per gate)
38
pF
pF
PD
(4)
C
Maximum Input Capacitance
4
10
10
IN
Note:
4. C determines the no load dynamic power consumption, P = C
2
V
f + I
V
, and the no load dynamic
PD
D
PD CC
CC CC
current consumption, I = C
V
f + I
.
S
PD CC
CC
©1983 Fairchild Semiconductor Corporation
MM74HC08 Rev. 1.4.0
www.fairchildsemi.com
4
Physical Dimensions
8.75
8.50
0.65
A
7.62
14
8
B
5.60
4.00
3.80
6.00
1.70
1.27
1
7
PIN ONE
INDICATOR
0.51
0.35
1.27
(0.33)
LAND PATTERN RECOMMENDATION
M
0.25
C B A
1.75 MAX
1.50
SEE DETAIL A
1.25
0.25
0.19
0.25
0.10
C
0.10
C
NOTES: UNLESS OTHERWISE SPECIFIED
A) THIS PACKAGE CONFORMS TO JEDEC
MS-012, VARIATION AB, ISSUE C,
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE MOLD
FLASH OR BURRS.
0.50
0.25
X 45°
R0.10
R0.10
GAGE PLANE
D) LANDPATTERN STANDARD:
SOIC127P600X145-14M
E) DRAWING CONFORMS TO ASME Y14.5M-1994
F) DRAWING FILE NAME: M14AREV13
0.36
8°
0°
0.90
0.50
SEATING PLANE
(1.04)
DETAIL A
SCALE: 20:1
Figure 1. 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
©1983 Fairchild Semiconductor Corporation
MM74HC08 Rev. 1.4.0
www.fairchildsemi.com
5
Physical Dimensions (Continued)
Figure 2. 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
©1983 Fairchild Semiconductor Corporation
MM74HC08 Rev. 1.4.0
www.fairchildsemi.com
6
Physical Dimensions (Continued)
0.43 TYP
0.65
1.65
6.10
0.45
12.00°
TOP & BOTTOM
R0.09 min
A. CONFORMS TO JEDEC REGISTRATION MO-153,
VARIATION AB, REF NOTE 6
B. DIMENSIONS ARE IN MILLIMETERS
R0.09min
1.00
C. DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH,
AND TIE BAR EXTRUSIONS
D. DIMENSIONING AND TOLERANCES PER ANSI
Y14.5M, 1982
E. LANDPATTERN STANDARD: SOP65P640X110-14M
F. DRAWING FILE NAME: MTC14REV6
Figure 3. 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
©1983 Fairchild Semiconductor Corporation
MM74HC08 Rev. 1.4.0
www.fairchildsemi.com
7
Physical Dimensions (Continued)
19.56
18.80
14
8
6.60
6.09
1
7
(1.74)
1.77
8.12
7.62
1.14
0.35
0.20
3.56
3.30
5.33 MAX
0.38 MIN
3.81
3.17
0.58
0.35
8.82
2.54
NOTES: UNLESS OTHERWISE SPECIFIED
THIS PACKAGE CONFORMS TO
A)
JEDEC MS-001 VARIATION BA
B) ALL DIMENSIONS ARE IN MILLIMETERS.
DIMENSIONS ARE EXCLUSIVE OF BURRS,
MOLD FLASH, AND TIE BAR EXTRUSIONS.
C)
D) DIMENSIONS AND TOLERANCES PER
ASME Y14.5-1994
E) DRAWING FILE NAME: MKT-N14AREV7
Figure 4. 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
©1983 Fairchild Semiconductor Corporation
MM74HC08 Rev. 1.4.0
www.fairchildsemi.com
8
TRADEMARKS
The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global
subsidiaries, and is not intended to be an exhaustive list of all such trademarks.
ACEx®
PDP-SPM™
SupreMOS™
FPS™
Power220®
SyncFET™
Build it Now™
CorePLUS™
CROSSVOLT™
CTL™
Current Transfer Logic™
EcoSPARK®
EZSWITCH™ *
™
FRFET®
POWEREDGE®
Power-SPM™
PowerTrench®
Programmable Active Droop™
QFET®
®
Global Power ResourceSM
Green FPS™
Green FPS™e-Series™
GTO™
i-Lo™
IntelliMAX™
ISOPLANAR™
MegaBuck™
MICROCOUPLER™
MicroFET™
The Power Franchise®
TinyBoost™
TinyBuck™
TinyLogic®
TINYOPTO™
TinyPower™
TinyPWM™
TinyWire™
µSerDes™
UHC®
QS™
QT Optoelectronics™
Quiet Series™
RapidConfigure™
SMART START™
SPM®
STEALTH™
SuperFET™
SuperSOT™-3
SuperSOT™-6
SuperSOT™-8
®
Fairchild®
Fairchild Semiconductor®
FACT Quiet Series™
FACT®
MicroPak™
MillerDrive™
Motion-SPM™
OPTOLOGIC®
FAST®
Ultra FRFET™
UniFET™
VCX™
OPTOPLANAR®
FastvCore™
®
FlashWriter® *
* EZSWITCH™ and FlashWriter® are trademarks of System General Corporation, used under license by Fairchild Semiconductor.
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS
HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE
APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS
PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S
WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR
SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or systems 2. A critical component in any component of a life support,
which, (a) are intended for surgical implant into the body or
(b) support or sustain life, and (c) whose failure to perform
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to
result in a significant injury of the user.
device, or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
This datasheet contains the design specifications for product
development. Specifications may change in any manner without notice.
Advance Information
Formative or In Design
This datasheet contains preliminary data; supplementary data will be
published at a later date. Fairchild Semiconductor reserves the right to
make changes at any time without notice to improve design.
Preliminary
First Production
Full Production
Not In Production
This datasheet contains final specifications. Fairchild Semiconductor
reserves the right to make changes at any time without notice to improve
the design.
No Identification Needed
Obsolete
This datasheet contains specifications on a product that has been
discontinued by Fairchild Semiconductor. The datasheet is printed for
reference information only.
Rev. I33
©1983 Fairchild Semiconductor Corporation
MM74HC08 Rev. 1.4.0
www.fairchildsemi.com
9
相关型号：
MM74HC08MTCX_NL
AND Gate, HC/UH Series, 4-Func, 2-Input, CMOS, PDSO14, 4.40 MM, MO-153, TSSOP-14
FAIRCHILD
MM74HC08M_NL
AND Gate, HC/UH Series, 4-Func, 2-Input, CMOS, PDSO14, 0.150 INCH, MS-012, SOIC-14
FAIRCHILD
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