MM74HC273SJX [ROCHESTER]
HC/UH SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO20, 5.30 MM, EIAJ TYPE2, SOP-20;
| 型号： | MM74HC273SJX |
| 厂家： | 
Rochester Electronics |
| 描述： | HC/UH SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO20, 5.30 MM, EIAJ TYPE2, SOP-20 光电二极管 输出元件 逻辑集成电路 触发器 |
| 文件： | 总9页 (文件大小：787K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
September 1983
Revised May 2005
MM74HC273
Octal D-Type Flip-Flops with Clear
General Description
Features
The MM74HC273 edge triggered flip-flops utilize advanced
silicon-gate CMOS technology to implement D-type flip-
flops. They possess high noise immunity, low power, and
speeds comparable to low power Schottky TTL circuits.
This device contains 8 master-slave flip-flops with a com-
mon clock and common clear. Data on the D input having
the specified setup and hold times is transferred to the Q
output on the LOW-to-HIGH transition of the CLOCK input.
The CLEAR input when LOW, sets all outputs to a low
state.
■ Typical propagation delay: 18 ns
■ Wide operating voltage range
■ Low input current: 1 A maximum
■ Low quiescent current: 80 A (74 Series)
■ Output drive: 10 LS-TTL loads
Each output can drive 10 low power Schottky TTL equiva-
lent loads. The MM74HC273 is functionally as well as pin
compatible to the 74LS273. All inputs are protected from
damage due to static discharge by diodes to VCC and
ground.
Ordering Code:
Order Number Package Number
Package Description
MM74HC273WM
MM74HC273SJ
MM74HC273MTC
MM74HC273N
M20B
M20D
MTC20
N20A
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Top View
© 2005 Fairchild Semiconductor Corporation
DS005331
www.fairchildsemi.com
Truth Table
Logic Diagram
(Each Flip-Flop)
Inputs
Clock
X
Outputs
Clear
D
X
H
L
Q
L
L
H
H
H
H
L
L
X
Q0
H
L
X
HIGH Level (Steady State)
LOW Level (Steady State)
Don’t Care
Transition from LOW-to-HIGH level
Q
The level of Q before the indicated steady state input conditions were
0
established
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2
Absolute Maximum Ratings(Note 1)
(Note 2)
Recommended Operating
Conditions
Supply Voltage (VCC
DC Input Voltage (VIN
DC Output Voltage (VOUT
Clamp Diode Current (IIK, IOK
DC Output Current, per pin (IOUT
DC VCC or GND Current, per pin (ICC
)
0.5 to 7.0V
1.5 to VCC 1.5V
0.5 to VCC 0.5V
20 mA
Min
Max
Units
)
Supply Voltage (VCC
DC Input or Output Voltage
(VIN, VOUT
)
2
6
V
)
)
)
0
VCC
85
V
C
)
25 mA
Operating Temperature Range (TA)
Input Rise or Fall Times
(tr, tf) VCC 2.0V
40
)
50 mA
Storage Temperature Range (TSTG
Power Dissipation (PD)
(Note 3)
)
65 C to 150 C
1000
500
ns
ns
ns
VCC 4.5V
600 mW
500 mW
VCC 6.0V
400
S.O. Package only
Note 1: Absolute Maximum Ratings are those values beyond which dam-
age to the device may occur.
Lead Temperature (TL)
(Soldering 10 seconds)
Note 2: Unless otherwise specified all voltages are referenced to ground.
260 C
Note 3: Power Dissipation temperature derating — plastic “N” package:
12 mW/ C from 65 C to 85 C.
DC Electrical Characteristics (Note 4)
T
25 C
T
40 to 85 C
T
A
55 to 125 C
A
A
V
Symbol
Parameter
Conditions
Units
CC
Typ
Guaranteed Limits
V
Minimum HIGH Level
Input Voltage
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
1.5
1.5
3.15
4.2
1.5
3.15
4.2
V
V
V
V
V
V
IH
3.15
4.2
V
V
Maximum LOW Level
Input Voltage
0.5
0.5
0.5
IL
1.35
1.8
1.35
1.8
1.35
1.8
Minimum HIGH Level
Output Voltage
V
V
or V
IL
OH
IN
IH
|I
|
20
A
2.0V
4.5V
6.0V
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
V
OUT
V
V
V
or V
IL
IN
IH
|I
|I
|
|
4.0 mA
5.2 mA
4.5V
6.0V
4.2
5.7
3.98
5.48
3.84
5.34
3.7
5.2
V
V
OUT
OUT
V
Maximum LOW Level
Output Voltage
V
or V
IL
OL
IN
IH
|I
|
20
A
2.0V
4.5V
6.0V
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
OUT
V
V
or V
IL
IN
IH
|I
|I
|
|
4 mA
5.2 mA
4.5V
6.0V
6.0V
0.2
0.2
0.26
0.26
0.1
0.33
0.33
1.0
0.4
0.4
1.0
V
V
A
OUT
OUT
I
Maximum Input
Current
V
V
V
or GND
IN
IN
CC
I
Maximum Quiescent
Supply Current
V
or GND
6.0V
8
80
160
A
CC
IN
CC
I
0 A
OUT
Note 4: For a power supply of 5V 10% the worst case output voltages (V , and V ) occur for HC at 4.5V. Thus the 4.5V values should be used when
OH
OL
designing with this supply. Worst case V and V occur at V
5.5V and 4.5V respectively. (The V value at 5.5V is 3.85V.) The worst case leakage cur-
IH
IH
IL
CC
rent (I , I , and I ) occur for CMOS at the higher voltage and so the 6.0V values should be used.
IN CC
OZ
3
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AC Electrical Characteristics
V
5V, TA 25 C, CL 15 pF, tr tf 6 ns
CC
Guaranteed
Symbol
Parameter
Conditions
Typ
Units
Limit
30
f
t
Maximum Operating Frequency
Maximum Propagation
Delay, Clock to Output
Maximum Propagation
Delay, Clear to Output
Minimum Removal Time,
Clear to Clock
50
18
MHz
ns
MAX
, t
27
PHL PLH
t
t
t
t
t
18
10
10
2
27
20
20
0
ns
ns
ns
ns
ns
PHL
REM
s
Minimum Setup Time
Data to Clock
Minimum Hold Time
Clock to Data
H
Minimum Pulse Width
Clock or Clear
10
16
W
AC Electrical Characteristics
C
50 pF, tr tf 6 ns (unless otherwise specified)
L
T
25 C
T
40 to 85 C
T
A
55 to 125 C
A
A
V
Symbol
Parameter
Conditions
Units
CC
Typ
16
74
78
38
14
12
42
19
18
0
Guaranteed Limits
f
Maximum Operating
Frequency
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
5
4
21
24
170
34
29
170
34
29
32
6
3
18
20
205
41
35
205
41
35
37
7
MHz
MHz
MHz
ns
MAX
27
31
135
27
23
135
27
23
25
5
t
, t
Maximum Propagation
Delay, Clock to Output
PHL PLH
ns
ns
t
Maximum Propagation
Delay, Clear to Output
ns
PHL
ns
ns
t
Minimum Removal Time
Clear to Clock
ns
REM
0
ns
0
4
5
6
ns
t
Minimum Setup Time
Data to Clock
26
7
100
20
17
0
125
25
21
0
150
30
25
0
ns
s
ns
5
ns
t
Minimum Hold Time
Clock to Data
15
6
ns
H
0
0
0
ns
4
0
0
0
ns
t
Minimum Pulse Width
Clock or Clear
34
11
10
80
16
14
1000
500
400
75
15
13
100
20
18
1000
500
400
95
19
16
120
24
20
1000
500
400
110
22
19
ns
W
ns
ns
t , t
Maximum Input Rise and
Fall Time, Clock
ns
r
f
ns
ns
t
, t
Maximum Output Rise
and Fall Time
28
11
9
ns
THL TLH
ns
ns
C
Power Dissipation
Capacitance (Note 5)
Maximum Input
Capacitance
(per flip-flop)
45
pF
PD
C
7
10
10
10
pF
IN
2
Note 5: C determines the no load dynamic power consumption, P
C
V
f
I
V
, and the no load dynamic current consumption,
PD
D
PD CC
CC CC
I
C
V
f
I
.
S
PD CC
CC
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4
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Package Number M20B
5
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20D
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6
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC20
7
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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8
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