NCP5162D [ROCHESTER]
3 A SWITCHING CONTROLLER, 1000 kHz SWITCHING FREQ-MAX, PDSO16, SOP-16;
| 型号： | NCP5162D |
| 厂家： | 
Rochester Electronics |
| 描述： | 3 A SWITCHING CONTROLLER, 1000 kHz SWITCHING FREQ-MAX, PDSO16, SOP-16 开关 光电二极管 |
| 文件： | 总16页 (文件大小：1224K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NCP5162
General Purpose
Synchronous Buck Controller
The NCP5162 is a synchronous dual N−Channel buck controller
designed to provide unprecedented transient response for today’s
demanding high−density, high−speed logic. It operates using a
proprietary control method which allows a 100 ns response time to
load transients. The NCP5162 is designed to operate over a 9−16 V
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MARKING
range (V ) using 12 V to power the IC and 5.0 V as the main supply
CC
DIAGRAM
16
for conversion.
The NCP5162 is specifically designed for high performance core
SO−16
D SUFFIX
CASE 751B
NCP5162
AWLYWW
logic. It includes the following features: 0.8% output tolerance, V
CC
monitor, and programmable Soft Start capability. The NCP5162 is
available in a 16 pin surface mount package.
1
A
WL, L
YY, Y
= Assembly Location
= Wafer Lot
= Year
Features
• Dual N−Channel Design
• Excess of 1.0 MHz Operation
• 100 ns Transient Response
• 2.0 A Gate Drivers
• 1.02 V Reference Voltage with 0.8% Tolerance
• 5.0 V & 12 V Operation
• Remote Sense
• Programmable Soft Start
• Lossless Short Circuit Protection
WW, W = Work Week
PIN CONNECTIONS
1
16
Disable
NC
V
FB
COMP
LGND
NC
NC
SS
NC
V
V
CC1
GATE(L)
PGND
C
OFF
V
V
GATE(H)
CC2
• V Monitor
V
CC
FFB
2
• V ™ Control Topology
• Overvoltage Protection
ORDERING INFORMATION
Device
Package
Shipping
48 Units/Rail
NCP5162D
SO−16
SO−16
2500 Tape & Reel
NCP5162DR2
©
Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
July, 2006 − Rev. 4
NCP5162/D
NCP5162
12 V
5.0 V
1.0 μH
100 pF
1200 μF/10 V × 3
Sanyo GX
V
V
CC2
CC1
IRF7413
IRF7413
V
GATE(H)
1.6 μH
Disable
V
OUT
NCP5162
IRF7413
IRF7413
C
OFF
V
GATE(L)
270 pF
PGND
SS
V
FB
0.1 μF
2.0 k
3.3 k
COMP
1200 μF/10 V × 3
Sanyo GX
V
FFB
LGND
1.33 k
0.1 μF
100 pF
Figure 1. Application Diagram, 5.0 V to 2.5 V/20 A Core Logic Converter with 12 V Bias
MAXIMUM RATINGS*
Rating
Value
0 to 150
−65 to +150
2.0
Unit
°C
Operating Junction Temperature, T
J
Storage Temperature Range, T
°C
S
ESD Susceptibility (Human Body Model)
kV
Thermal Resistance, Junction−to−Case, R
28
°C/W
°C/W
°C
Θ
JC
Thermal Resistance, Junction−to−Ambient, R
115
Θ
JA
Lead Temperature Soldering:
Reflow: (Note 1)
230 peak
1. 60 second maximum above 183°C.
*The maximum package power dissipation must be observed.
MAXIMUM RATINGS
Pin Name
Max Operating Voltage
Max Current
V
V
16 V/−0.3 V
18 V/−0.3 V
6.0 V/−0.3 V
6.0 V/−0.3 V
6.0 V/−0.3 V
6.0 V/−0.3 V
6.0 V/−0.3 V
6.0 V/−0.3 V
100 mA DC/3.0 A peak
100 mA DC/3.0 A peak
−100 μA
CC1
CC2
SS
COMP
200 μA
V
−0.2 μA
FB
C
V
−0.2 μA
OFF
FFB
−0.2 μA
Disable
−50 μA
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NCP5162
MAXIMUM RATINGS (continued)
Pin Name
Max Operating Voltage
Max Current
100 mA DC/3.0 A peak
100 mA DC/3.0 A peak
25 mA
V
18 V/−0.3 V
16 V/−0.3 V
0 V
GATE(H)
V
GATE(L)
LGND
PGND
0 V
100 mA DC/3.0 A peak
ELECTRICAL CHARACTERISTICS (0°C < T < +70°C; 0°C < T < +125°C; 9.5 V < V
< 14 V; 5.0 V < V
< 16 V;
A
J
CC1
CC2
CV
and CV
= 6.6 nF; C
= 330 pF; C = 0.1 μF, unless otherwise specified.)
GATE(L)
GATE(H)
OFF
SS
Characteristic
Test Conditions
Min
Typ
Max
Unit
Error Amplifier
Reference Voltage
Measure V = COMP
1.012
1.02
0.3
80
1.028
1.0
−
V
FB
V
Bias Current
V
= 0 V
FB
−
−
μA
dB
FB
Open Loop Gain
1.25 V < V
Note 2
, 4.0 V; C
= 0.1 μF;
COMP
COMP
Unity Gain Bandwidth
COMP SINK Current
COMP SOURCE Current
COMP CLAMP Current
COMP High Voltage
COMP Low Voltage
PSRR
C
= 0.1 μF; Note 2
−
30
15
0.4
4.0
−
50
60
−
120
60
kHz
μA
μA
mA
V
COMP
COMP
COMP
COMP
V
V
V
V
V
= 1.5 V; V = 3.0 V; V > 2.0 V
FB SS
= 1.2 V; V = 2.7 V; V = 5.0 V
30
FB
SS
= 0 V; V = 2.7 V
1.0
4.3
1.00
70
1.6
5.0
1.15
−
FB
= 2.7 V; V = 5.0 V
FB
FB
SS
= 3.0 V
V
8.0 V < V
< 14 V @ 1.0 kHz;
−
dB
CC1
C
COMP
= 0.1 μF; Note 2
Transconductance
−
−
33
−
mmho
V
Monitor
CC1
Start Threshold
Stop Threshold
Hysteresis
Output switching
Output not switching
Start−Stop
8.60
8.45
−
8.95
8.80
150
9.30
9.15
−
V
V
mV
Soft Start (SS)
Charge Time
−
−
1.6
25
3.3
100
3.3
5.0
200
6.0
ms
ms
%
V
Pulse Period
Duty Cycle
(Charge Time /Pulse Period) × 100
1.0
0.50
0.9
−
COMP Clamp Voltage
V
V
= 0 V; V = 0
0.95
1.0
1.10
1.1
FB
SS
V
SS Fault Disable
= Low; V
= Low
V
FFB
GATE(H)
GATE(L)
High Threshold
−
2.5
3.0
V
PWM Comparator
Transient Response
V
V
= 0 to 5.0 V to V
= 9.0 V to 1.0 V;
−
−
100
0.3
125
ns
FFB
V
GATE(H)
= V
= 12 V
CC1
CC2
V
Bias Current
= 0 V
−
μA
FFB
FFB
2. Guaranteed by design, not 100% tested in production.
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NCP5162
ELECTRICAL CHARACTERISTICS (continued) (0°C < T < +70°C; 0°C < T < +125°C; 9.5 V < V
< 14 V; 5.0 V < V
< 16 V;
A
J
CC1
CC2
CV
and CV
= 6.6 nF; C
= 330 pF; C = 0.1 μF, unless otherwise specified.)
GATE(L)
GATE(H)
OFF
SS
Characteristic
Test Conditions
Min
Typ
Max
Unit
Disable Input
Threshold Voltage
Pull Down Resistance
Pull Down Voltage
−
−
−
1.00
25
1.25
50
2.40
110
V
kΩ
V
0.00
0.00
0.15
V
and V
GATE(L)
GATE(H)
Out Rise Time
1.0 V < V
< 9.0 V; V
< 9.0 V; 1.0 V < V
−
−
30
30
70
70
50
50
95
95
ns
ns
ns
ns
GATE(H)
GATE(L)
= V
= 12 V
CC1
CC2
Out Fall Time
9.0 V < V
> 1.0 V; 9.0 V > V
GATE(H)
GATE(L)
> 1.0 V; V
= V
= 12 V
CC1
CC2
Delay V
Delay V
to V
V
V
falling to 1.0 V V
= V = 8.0 V
CC2
45
45
GATE(H)
GATE(L)
GATE(L)
GATE(H)
CV
;
CC1
= 6.6 nF; V
rising to 1.0 V
GATE(H)
GATE(L)
to V
falling to 1.0 V; V
= V
= 8.0 V
GATE(H)
GATE(L)
CC1
CC2
CV
= 6.6 nF; V
rising to 1.0 V
GATE(H)
GATE(H)
V
V
V
Resistance
Schottky
Resistor to LGND. Note 3
LGND to V @ 10 mA;
20
50
100
800
kΩ
GATE(H), GATE(L)
V
−
600
mV
GATE(H), GATE(L)
GATE(H)
LGND to V
@ 10 mA
GATE(L)
Supply Current
I
I
No Switching
No Switching
−
−
−
−
−
−
14
11
14
11
17.5
13
mA
mA
mA
mA
CC1
CC2
Operating I
Operating I
V
V
= COMP = V
= COMP = V
17
CC1
CC2
FB
FB
FFB
13.5
FFB
C
OFF
Charge Time
V
= 1.5 V; V = 5.0 V
1.0
5.0
1.6
2.2
μs
FFB
SS
Discharge Current
Time Out Timer
Time Out Time
C
to 5.0 V; V > 1.0 V
−
−
mA
OFF
FB
V
V
= V ; V = 2.0 V;
COMP FFB
10
35
30
50
65
70
μs
FB
Record V
Pulse High Duration
GATE(H)
Fault Mode Duty Cycle
= 0V
%
FFB
3. Guaranteed by design, not 100% tested in production.
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NCP5162
PACKAGE PIN DESCRIPTION
PACKAGE PIN #
PIN SYMBOL
FUNCTION
SO−16
1
Disable
This pin is internally pulled down to ground through a resistor,
providing a logic 0 if left open. When pulled to V , The output gate
CC
drivers are pulled low, powering off the external output stage. At the
same time the Soft Start capacitor is slowly discharged by an internal
2.0 μA current source, setting the time out before the IC is restarted.
2, 3, 4, 6
5
NC
SS
No connection.
Soft Start Pin. A capacitor from this pin to LGND in conjunction with
internal 60 μA current source provides Soft Start function for the
controller. This pin disables fault detect function during Soft Start.
When a fault is detected, the Soft Start capacitor is slowly discharged
by internal 2.0 μA current source setting the time out before trying to
restart the IC. Charge/discharge current ratio of 30 sets the duty cycle
for the IC when the regulator output is shorted.
7
8
C
V
A capacitor from this pin to ground sets the time duration for the on
board one shot, which is used for the constant off time architecture.
OFF
Fast feedback connection to the PWM comparator. This pin is
connected to the regulator output. The inner feedback loop
terminates on time.
FFB
9
V
Boosted power for the high side gate driver.
CC2
10
V
High FET driver pin capable of 3.0 A peak switching current. Internal
GATE(H)
circuit prevents V
simultaneously.
and V
from being in high state
GATE(H)
GATE(L)
11
PGND
High current ground for the IC. The MOSFET drivers are referenced
to this pin. Input capacitor ground and the source of lower FET should
be tied to this pin.
12
13
14
15
V
Low FET driver pin capable of 3.0 A peak switching current.
Input power for the IC and low side gate driver.
GATE(L)
V
CC1
LGND
COMP
Signal ground for the IC. All control circuits are referenced to this pin.
Error amplifier compensation pin. A capacitor to ground should be
provided externally to compensate the amplifier.
16
V
Error amplifier DC feedback input. This is the master voltage
feedback which sets the output voltage. This pin can be connected
directly to the output or a remote sense trace.
FB
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NCP5162
V
CC2
V
Monitor
CC1
Comparator
−
V
CC1
SS
V
GATE(H)
5.0 V
+
SS Low
−
Comparator
FAULT
FAULT
9.05 V
8.90V
Q
R
+
PGND
60 μA
FAULT
Latch
0.7 V
Disable
Q
S
SS High
Comparator
+
V
2.0 μA
CC1
−
V
GATE(L)
Error
Amplifier
2.5 V
Slow Feedback
V
−
FB
PGND
+
PWM
Comparator
−
GATE(H) = ON
GATE(H) = OFF
Maximum
On−Time
Timeout
Q
Q
R
+
REF
S
Normal
Off−Time
Timeout
Extended
Off−Time
Timeout
PMW
Latch
C
COMP
OFF
One Shot
R
C
OFF
Off−Time
Fast Feedback
−
V
FFB
Timeout
Q
S
V
+
CC1
V
Low
FFB
LGND
Comparator
REF
1.0 V
Reference
Time−Out
Timer
(30 μs)
Edge Triggered
REF
Figure 2. Block Diagram
APPLICATIONS INFORMATION
THEORY OF OPERATION
PWM
Comparator
+
V
V2 Control Method
GATE(H)
C
2
V
The V method of control uses a ramp signal that is
generated by the ESR of the output capacitors. This ramp is
proportional to the AC current through the main inductor
and is offset by the value of the DC output voltage. This
control scheme inherently compensates for variation in
either line or load conditions, since the ramp signal is
generated from the output voltage itself. This control
scheme differs from traditional techniques such as voltage
mode, which generates an artificial ramp, and current mode,
which generates a ramp from inductor current.
GATE(L)
−
Ramp
Signal
V
FFB
Output
Voltage
Feedback
V
FB
Error
Amplifier
−
COMP
E
Reference
Voltage
Error
+
Signal
Figure 3. V2 Control Diagram
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NCP5162
2
The V control method is illustrated in Figure 3. The
output voltage is used to generate both the error signal and
the ramp signal. Since the ramp signal is simply the output
voltage, it is affected by any change in the output regardless
of the origin of that change. The ramp signal also contains
the DC portion of the output voltage, which allows the
control circuit to drive the main switch to 0% or 100% duty
cycle as required.
time. The PWM comparator monitors the output voltage
ramp, and terminates the switch on time.
Constant off time provides a number of advantages.
Switch duty cycle can be adjusted from 0 to 100% on a pulse
by pulse basis when responding to transient conditions. Both
0% and 100% duty cycle operation can be maintained for
extended periods of time in response to load or line
transients. PWM slope compensation to avoid
sub−harmonic oscillations at high duty cycles is avoided.
Switch on time is limited by an internal 30 μs timer,
minimizing stress to the power components.
A change in line voltage changes the current ramp in the
inductor, affecting the ramp signal, which causes the V
control scheme to compensate the duty cycle. Since the
change in inductor current modifies the ramp signal, as in
current mode control, the V control scheme has the same
2
Programmable Output
2
The NCP5162 has a 1.0 V reference voltage at the
non−inverting input of the error amplifier, and the output
voltage is programmed by connecting resistor divider
advantages in line transient response.
A change in load current will have an affect on the output
voltage, altering the ramp signal. A load step immediately
changes the state of the comparator output, which controls
the main switch. Load transient response is determined only
by the comparator response time and the transition speed of
the main switch. The reaction time to an output load step has
no relation to the crossover frequency of the error signal
loop, as in traditional control methods.
feedback to the V and V
pins.
FB
FFB
Start Up
Until the voltage on the V
supply pin exceeds the
CC1
8.95 V monitor threshold, the Soft Start and gate pins are
held low. The FAULT latch is reset (no Fault condition). The
output of the error amplifier (COMP) is pulled up to 1.0 V
The error signal loop can have a low crossover frequency,
since transient response is handled by the ramp signal loop.
The main purpose of this ‘slow’ feedback loop is to provide
DC accuracy. Noise immunity is significantly improved,
since the error amplifier bandwidth can be rolled off at a low
frequency. Enhanced noise immunity improves remote
sensing of the output voltage, since the noise associated with
long feedback traces can be effectively filtered.
by the comparator clamp. When the V
pin exceeds the
CC1
monitor threshold, the GATE(H) output is activated, and the
Soft Start capacitor begins charging. The GATE(H) output
will remain on, enabling the NFET switch, until terminated
by either the PWM comparator, or the maximum on time
timer.
If the maximum on time is exceeded before the regulator
output voltage achieves the 1.0 V level, the pulse is
terminated. The GATE(H) pin drives low, and the GATE(L)
pin drives high for the duration of the extended off time. This
time is set by the time out timer and is approximately equal
to the maximum on time, resulting in a 50% duty cycle. The
GATE(L) pin will then drive low, the GATE(H) pin will
drive high, and the cycle repeats.
Line and load regulation are drastically improved because
there are two independent voltage loops. A voltage mode
controller relies on a change in the error signal to
compensate for a deviation in either line or load voltage.
This change in the error signal causes the output voltage to
change corresponding to the gain of the error amplifier,
which is normally specified as line and load regulation. A
current mode controller maintains fixed error signal under
deviation in the line voltage, since the slope of the ramp
signal changes, but still relies on a change in the error signal
When regulator output voltage achieves the 1.0 V level
present at the COMP pin, regulation has been achieved and
normal off time will ensue. The PWM comparator
terminates the switch on time, with off time set by the C
OFF
2
for a deviation in load. The V method of control maintains
2
capacitor. The V control loop will adjust switch duty cycle
as required to ensure the regulator output voltage tracks the
output of the error amplifier.
a fixed error signal for both line and load variation, since the
ramp signal is affected by both line and load.
The Soft Start and COMP capacitors will charge to their
final levels, providing a controlled turn on of the regulator
output. Regulator turn on time is determined by the COMP
capacitor charging to its final value. Its voltage is limited by
the Soft Start COMP clamp and the voltage on the Soft Start
pin (see Figures 4 and 5).
Constant Off Time
To maximize transient response, the NCP5162 uses a
constant off time method to control the rate of output pulses.
During normal operation, the off time of the high side switch
is terminated after a fixed period, set by the C
To maintain regulation, the V control loop varies switch on
capacitor.
OFF
2
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NCP5162
M 250 μs
Trace 1− Regulator Output Voltage (1.0 V/div.)
Trace 2− Inductor Switching Node (2.0 V/div.)
Trace 3− 12 V Input (VCC1 and VCC2) (5.0 V/div.)
Trace 4− 5.0 V Input (1.0 V/div.)
M 10.0 μs
Trace 1− Regulator Output Voltage (5.0 V/div.)
Trace 2− Inductor Switching Node (5.0 V/div.)
Figure 4. NCP5162 Startup in Response to
Increasing 12 V and 5.0 V Input Voltages.
Extended Off Time is Followed by Normal Off
Time Operation when Output Voltage Achieves
Regulation to the Error Amplifier Output
Figure 6. NCP5162 Enable Startup Waveforms
Normal Operation
During normal operation, switch off time is constant and
set by the C
capacitor. Switch on time is adjusted by the
OFF
2
V
control loop to maintain regulation. This results in
changes in regulator switching frequency, duty cycle, and
output ripple in response to changes in load and line. Output
voltage ripple will be determined by inductor ripple current
working into the ESR of the output capacitors (see Figures
7 and 8).
M 2.50 ms
Trace 1− Regulator Output Voltage (1.0 V/div.)
Trace 3− COMP PIn (error amplifier output) (1.0 V/div.)
Trace 4− Soft Start Pin (2.0 V/div.)
Figure 5. NCP5162 Startup Waveforms
If the input voltage rises quickly, or the regulator output
is enabled externally, output voltage will increase to the
level set by the error amplifier output more rapidly, usually
within a couple of cycles (see Figure 6).
M 1.00 μs
Trace 1− Regulator Output Voltage (10 mV/div.)
Trace 2− Inductor Switching Node (5.0 V/div.)
Figure 7. NCP5162 Peak−to−Peak Ripple on
VOUT = 2.8 V, IOUT = 0.5 A (Light Load)
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NCP5162
10 μs/div.
M 1.00 μs
Trace 1− Inductor Switching Node (5.0 V/div.)
Trace 2− Regulator Output Voltage (output set for 1.55 V, 20 mV/div.)
Trace 1− Regulator Output Voltage (10 mV/div.)
Trace 2− Inductor Switching Node (5.0 V/div.)
Figure 10. NCP5162 Output Voltage Response to a
0 to 12 A Load Increase
Figure 8. NCP5162 Peak−to−Peak Ripple on
VOUT = 2.8 V, IOUT = 13 A (Heavy Load)
Transient Response
2
The NCP5162 V control loop’s 100 ns reaction time
provides unprecedented transient response to changes in
input voltage or output current. Pulse by pulse adjustment of
duty cycle is provided to quickly ramp the inductor current
to the required level. Since the inductor current cannot be
changed instantaneously, regulation is maintained by the
output capacitor(s) during the time required to slew the
inductor current.
For best transient response, a combination of a number of
high frequency and bulk output capacitors are usually used.
If the maximum on time is exceeded while responding to
a sudden increase in load current, a normal off time occurs
to prevent saturation of the output inductor.
10 μs/div.
Trace 1− Inductor Switching Node (5 V/div.)
Trace 2− Regulator Output Voltage (output set for 1.55 V, 20 mV/div.)
Figure 11. NCP5162 Output Voltage Response to a
12 to 0 A Load Decrease
PROTECTION AND MONITORING FEATURES
VCC1 Monitor
To maintain predictable startup and shutdown
characteristics an internal V
monitor circuit is used to
CC1
prevent the part from operating below 8.95 V minimum
startup. The V monitor comparator provides hysteresis
CC1
and guarantees a 8.80 V minimum shutdown threshold.
100 μs/div.
Trace 2− Regulator Output Voltage (output set for 1.55 V, 20 mV/div.)
Figure 9. NCP5162 Output Voltage Response to a
12 A Load Pulse
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NCP5162
Short Circuit Protection
A lossless hiccup mode short circuit protection feature is
provided, requiring only the Soft Start capacitor to
implement. If
a
short circuit condition occurs
low comparator sets the FAULT
FFB
(V < 1.0 V), the V
FFB
latch. This causes the top MOSFET to shut off,
disconnecting the regulator from it’s input voltage. The Soft
Start capacitor is then slowly discharged by a 2.0 μA current
source until it reaches it’s lower 0.7 V threshold. The
regulator will then attempt to restart normally, operating in
it’s extended off time mode with a 50% duty cycle, while the
Soft Start capacitor is charged with a 60 μA charge current.
If the short circuit condition persists, the regulator output
M 50.0 μs
will not achieve the 1.0 V low V
comparator threshold
FFB
Trace 4− 5.0 V from PC Power Supply (2.0 V/div.)
Trace 2− Inductor Switching Node (2.0 V/div.)
before the Soft Start capacitor is charged to it’s upper 2.5 V
threshold. If this happens the cycle will repeat itself until the
short is removed. The Soft Start charge/discharge current
ratio sets the duty cycle for the pulses
(2.0 μA/60 μA = 3.3%), while actual duty cycle is half that
due to the extended off time mode (1.65%).
Figure 13. NCP5162 Startup with Regulator
Output Shorted
Overvoltage Protection
Overvoltage protection (OVP) is provided as result of the
2
normal operation of the V control topology and requires no
This protection feature results in less stress to the
regulator components, input power supply, and PC board
traces than occurs with constant current limit protection (see
Figures 12 and 13).
If the short circuit condition is removed, output voltage
will rise above the 1.0 V level, preventing the FAULT latch
from being set, allowing normal operation to resume.
additional external components. The control loop responds
to an overvoltage condition within 100 ns, causing the top
MOSFET to shut off, disconnecting the regulator from it’s
input voltage. The bottom MOSFET is then activated,
resulting in a “crowbar” action to clamp the output voltage
and prevent damage to the load (see Figures 14 and 15). The
regulator will remain in this state until the overvoltage
condition ceases or the input voltage is pulled low. The
bottom FET and board trace must be properly designed to
implement the OVP function.
M 25.0 ms
Trace 4− 5.0 V Supply Voltage (2.0 V/div.)
Trace 3− Soft Start Timing Capacitor (1.0 V/div.)
Trace 2− Inductor Switching Node (2.0 V/div.)
M 10.0 μs
Trace 4− 5.0 V from PC Power Supply (5.0 V/div.)
Trace 1− Regulator Output Voltage (1.0 V/div.)
Trace 2− Inductor Switching Node 5.0 V/div.)
Figure 12. NCP5162 Hiccup Mode Short Circuit
Protection. Gate Pulses are Delivered While
the Soft Start Capacitor Charges, and Cease
During Discharge
Figure 14. NCP5162 OVP Response to an
Input−to−Output Short Circuit by Immediately
Providing 0% Duty Cycle, Crow−Barring the Input
Voltage to Ground
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NCP5162
M 2.50 ms
M 5.00 ms
Trace 4− 5.0 V from PC Power Supply (5.0 V/div.)
Trace 3 − 12 V Input (V ) and (V
CC1
) (10 V/div.)
CC2
Trace 1− Regulator Output Voltage (1.0 V/div.)
Trace 4− 5.0 V Input (2.0 V/div.)
Trace 1− Regulator Output Voltage (1.0 V/div.)
Trace 2− Power Good Signal (2.0 V/div.)
Figure 15. NCP5162 OVP Response to an
Input−to−Output Short Circuit by Pulling the Input
Voltage to Ground
Figure 17. NCP5162 During Power Up. Power
Good Signal is Activated when Output
Voltage Reaches 1.70 V
External Power Good Circuit
An optional Power Good signal can be generated through
the use of four additional external components (see Figure
16). The threshold voltage of the Power Good signal can be
adjusted per the following equation:
Slope Compensation
The V control method uses a ramp signal, generated by
2
the ESR of the output capacitors, that is proportional to the
ripple current through the inductor. To maintain regulation,
2
the V control loop monitors this ramp signal, through the
(R1 ) R2) 0.65 V
V
+
Power Good
PWM comparator, and terminates the switch on−time.
The stringent load transient requirements of modern
microprocessors require the output capacitors to have very
low ESR. The resulting shallow slope presented to the PWM
comparator, due to the very low ESR, can lead to pulse width
jitter and variation caused by both random or synchronous
noise.
Adding slope compensation to the control loop, avoids
erratic operation of the PWM circuit, particularly at lower
duty cycles and higher frequencies, where there is not
enough ramp signal, and provides a more stable switchpoint.
R2
This circuit provides an open collector output that drives
the Power Good output to ground for regulator voltages less
than V
.
Power Good
5.0 V
R3
Power Good
PN3904
10 k
R1
10 k
PN3904
V
OUT
NCP5162
R2
6.2 k
Figure 16. Implementing Power Good
with the NCP5162
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NCP5162
The scheme that prevents that switching noise
supplies when in the high state. In practice, the MOSFET
gates will be driven rail to rail due to overshoot caused by the
capacitive load they present to the controller IC. For the
prematurely triggers the PWM circuit consists of adding a
positive voltage slope to the output of the Error Amplifier
(COMP pin) during an off−time cycle.
typical application where V
= V
= 12 V and 5.0 V is
CC1
CC2
The circuit that implements this function is shown in
Figure 18.
used as the source for the regulator output current, the
following gate drive is provided;
V
+ 12 V * 5.0 V + 7.0 V, V
+ 12 V
GATE(L)
GATE(H)
16
The gate drive waveforms are shown in Figure 19.
COMP
C
COMP
NCP5162
R2
C1
R1
12
GATE(L)
To Synchronous
FET
Figure 18. Small RC Filter Provides the
Proper Voltage Ramp at the Beginning of
each On−Time Cycle
The ramp waveform is generated through a small RC filter
that provides the proper voltage ramp at the beginning of
each on−time cycle. The resistors R1 and R2 in the circuit of
Figure 18 form a voltage divider from the GATE(L) output,
superimposing a small artificial ramp on the output of the
error amplifier. It is important that the series combination
R1/R2 is high enough in resistance not to load down and
negatively affect the slew rate on the GATE(L) pin.
M 1.00 μs
Trace 3 = V
(10 V/div.)
GATE(H)
Math 1 = V
Trace 4 = V
− 5.0 V
IN
GATE(H)
(10 V/div.)
GATE(L)
Trace 2= Inductor Switching Nodes (5.0 V/div.)
Figure 19. NCP5162 Gate Drive Waveforms Depicting
Rail to Rail Swing
The most important aspect of MOSFET performance is
Selecting External Components
The NCP5162 can be used with a wide range of external
power components to optimize the cost and performance of
a particular design. The following information can be used
as general guidelines to assist in their selection.
RDS , which effects regulator efficiency and MOSFET
ON
thermal management requirements.
The power dissipated by the MOSFETs may be estimated
as follows;
NFET Power Transistors
Switching MOSFET:
Both logic level and standard MOSFETs can be used. The
reference designs derive gate drive from the 12 V supply
which is generally available in most computer systems and
utilize logic level MOSFETs. Multiple MOSFETs may be
paralleled to reduce losses and improve efficiency and
thermal management.
Voltage applied to the MOSFET gates depends on the
application circuit used. Both upper and lower gate driver
outputs are specified to drive to within 1.5 V of ground when
in the low state and to within 2.0 V of their respective bias
2
Power + I
RDS duty cycle
ON
LOAD
Synchronous MOSFET:
2
( )
1 * duty cycle
ON
Power + I
RDS
LOAD
Duty Cycle =
V
) (I
RDS
)
OUT
LOAD
RDS )
ON OF SYNCH FET
ON OF SYNCH FET
V
)(I
IN
LOAD
ƪ* (I
ƫ
RDS
)
LOAD
ON OF SWITCH FET
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NCP5162
Off Time Capacitor (COFF
)
THERMAL MANAGEMENT
The C
timing capacitor sets the regulator off time:
OFF
Thermal Considerations for Power
MOSFETs and Diodes
T
+ C 4848.5
OFF
OFF
The preceding equations for duty cycle can also be used
to calculate the regulator switching frequency and select the
In order to maintain good reliability, the junction
temperature of the semiconductor components should be
kept to a maximum of 150°C or lower. The thermal
impedance (junction to ambient) required to meet this
requirement can be calculated as follows:
C
OFF
timing capacitor:
(
)
Perioid 1 * duty cycle
C
OFF
+
4848.5
where:
T
* T
AMBIENT
Power
JUNCTION(MAX)
Thermal Impedance +
1
Period +
switching frequency
A heatsink may be added to TO−220 components to
reduce their thermal impedance. A number of PC board
layout techniques such as thermal vias and additional copper
foil area can be used to improve the power handling
capability of surface mount components.
Schottky Diode for Synchronous MOSFET
A Schottky diode may be placed in parallel with the
synchronous MOSFET to conduct the inductor current upon
turn off of the switching MOSFET to improve efficiency.
For a design operating at 200 kHz or so, the low non−overlap
time combined with Schottky forward recovery time may
make the benefits of this device not worth the additional
expense (see Figure 8, channel 2). The power dissipation in
the synchronous MOSFET due to body diode conduction
can be estimated by the following equation:
EMI Management
As a consequence of large currents being turned on and off
at high frequency, switching regulators generate noise as a
consequence of their normal operation. When designing for
compliance with EMI/EMC regulations, additional
components may be added to reduce noise emissions. These
components are not required for regulator operation and
experimental results may allow them to be eliminated. The
input filter inductor may not be required because bulk filter
and bypass capacitors, as well as other loads located on the
board will tend to reduce regulator di/dt effects on the circuit
board and input power supply. Placement of the power
component to minimize routing distance will also help to
reduce emissions.
Power + V
BD
I
conduction time switching frequency
LOAD
Where V = the forward drop of the MOSFET body
diode. For the NCP5162 demonstration board as shown in
Figure 8;
BD
Power + 1.6 V 13 A 100 ns 233 kHz + 0.48 W
This is only 1.3% of the 36.4 W being delivered to the
load.
Input and Output Capacitors
These components must be selected and placed carefully
to yield optimal results. Capacitors should be chosen to
provide acceptable ripple on the input supply lines and
regulator output voltage. Key specifications for input
capacitors are their ripple rating, while ESR is important for
output capacitors. For best transient response, a combination
of low value/high frequency and bulk capacitors placed
close to the load will be required.
2.0 μH
33 Ω
1000 pF
Output Inductor
Figure 20. Filter Components
The inductor should be selected based on its inductance,
current capability, and DC resistance. Increasing the
inductor value will decrease output voltage ripple, but
degrade transient response.
2.0 μH
+
1200 pF × 3.0/16 V
Figure 21. Input Filter
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NCP5162
To the negative terminal
of the input capacitors
Layout Guidelines
1. Place 12 V filter capacitor next to the IC and connect
capacitor ground to pin 11 (PGND).
2. Connect pin 11 (PGND) with a separate trace to the
ground terminals of the 5.0 V input capacitors.
3. Place fast feedback filter capacitor next to pin 8 (V
V
CC
0.1 μF
15
11
1.0 μF
COMP
)
V
FFB
and connect it’s ground terminal with a separate, wide
trace directly to pin 14 (LGND).
4. Connect the ground terminals of the Compensation
capacitor directly to the ground of the fast feedback
filter capacitor to prevent common mode noise from
effecting the PWM comparator.
8
100 pF
V
FFB
5
SOFT START
5. Place the output filter capacitor(s) as close to the load
as possible and connect the ground terminal to pin 14
(LGND).
OFF TIME
6. Connect the V pin directly to the load with a separate
FB
To the negative terminal of the output capacitors
trace (remote sense).
7. Place 5.0 V input capacitors close to the switching
MOSFET and synchronous MOSFET.
Figure 22. Layout Guidelines
Route gate drive signals V
(pin 10) and
GATE(H)
V
(pin 12 when used) with traces that are a
GATE(L)
minimum of 0.025 inches wide.
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NCP5162
PACKAGE DIMENSIONS
SO−16
D SUFFIX
CASE 751B−05
ISSUE J
−A−
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
16
9
8
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
−B−
P 8 PL
M
S
B
0.25 (0.010)
1
G
MILLIMETERS
INCHES
MIN
DIM MIN
MAX
10.00
4.00
1.75
0.49
1.25
MAX
0.393
0.157
0.068
0.019
0.049
F
A
B
C
D
F
9.80
3.80
1.35
0.35
0.40
0.386
0.150
0.054
0.014
0.016
R X 45
K
_
C
G
J
1.27 BSC
0.050 BSC
−T−
SEATING
PLANE
0.19
0.10
0
0.25
0.25
7
0.008
0.004
0
0.009
0.009
7
J
M
K
M
P
R
D
16 PL
_
_
_
_
5.80
0.25
6.20
0.50
0.229
0.010
0.244
0.019
M
S
S
0.25 (0.010)
T B
A
2
V
is a trademark of Switch Power, Inc.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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NCP5162/D
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