NCP5395MNR2G [ROCHESTER]
DUAL SWITCHING CONTROLLER, 1100kHz SWITCHING FREQ-MAX, QCC48, 7 X 7 MM, LEAD FREE, QFN-48;
| 型号： | NCP5395MNR2G |
| 厂家： | 
Rochester Electronics |
| 描述： | DUAL SWITCHING CONTROLLER, 1100kHz SWITCHING FREQ-MAX, QCC48, 7 X 7 MM, LEAD FREE, QFN-48 开关 |
| 文件： | 总30页 (文件大小：950K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NCP5395
Product Preview
2/3/4-Phase Controller with
On Board Gate Drivers for
CPU Applications
The NCP5395 provides up to a four−phase buck solution which
combines differential voltage sensing, differential phase current
sensing, adaptive voltage positioning, and on board gate drivers.
Dual−edge pulse−width modulation (PWM) combined with inductor
current sensing reduces system cost by providing the fastest initial
response to dynamic load events. Dual−edge multiphase modulation
reduces the total bulk and ceramic output capacitance required to meet
transient regulation specifications.
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1
48
QFN48
CASE 485K
PLASTIC
The on board gate drivers includes adaptive non overlap and power
saving operation. A high performance operational error amplifier is
provided to simplify compensation of the system. Patented Dynamic
Reference Injection further simplifies loop compensation by
eliminating the need to compromise between closed−loop transient
MARKING DIAGRAM
48
response and Dynamic V performance.
1
ID
Features
NCP5395
AWLYYWWG
• Meets Intel’s VR11.1 Specifications
• Meets AMD 6 Bit Code Specifications
• Dual−edge PWM for Fastest Initial Response to Transient Loading
• High Performance Operational Error Amplifier
• Internal Soft Start
A
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
WL
YY
WW
G
• Dynamic Reference Injection (Patent #US07057381)
• DAC Range from 0.5 V to 1.6 V
• DAC Feed Forward Function (Patient Pending)
•
0.5% DAC Voltage Accuracy from 1.0 V to 1.6 V
48
• True Differential Remote Voltage Sensing Amplifier
• Phase−to−Phase Current Balancing
1
BG1
BG3
PSI
G4
VID0
VRRDY
EN
• “Lossless” Differential Inductor Current Sensing
• Differential Current Sense Amplifiers for Each Phase
• Adaptive Voltage Positioning (AVP)
• Oscillator Frequency Range of 125 kHz − 1 MHz
• Latched Over Voltage Protection (OVP)
VID1
CS1N
CS1P
CS2N
CS2P
CS3N
CS3P
CS4N
CS4P
VID2
AGND
Down−bonded to
Exposed Flag
VID3
VID4
VID5
VID6
VID7/AMD
ROSC
ILIM
• Guaranteed Startup into Pre−Charged Loads
• Threshold Sensitive Enable Pin for VTT Sensing
• Power Good Output with Internal Delays
• Thermally Compensated Current Monitoring
• Thermal Shutdown Protection
ORDERING INFORMATION
†
• Adaptive−Non−Overlap Gate Drive Circuit
• Output Disable Control Turn Off of Both Phase Pair MOSFETs
Device
NCP5395MNR2G
Package
Shipping
QFN48
2500/Tape & Reel
• This is a Pb−Free Device
(Pb−Free)
Applications
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
• Desktop Processors
This document contains information on a product under development. ON Semiconductor
reserves the right to change or discontinue this product without notice.
©
Semiconductor Components Industries, LLC, 2008
1
Publication Order Number:
July, 2008 − Rev. P5
NCP5395/D
NCP5395
VID0
VID1
VID2
VID3
VID4
VID5
VID6
VID7/AMD
Flexible DAC
VCCP
Overvoltage
Protection
-
+
PSI
BST1
TG1
+
-
DAC
Phase 1
Gate Driver
with
Adaptive
Non−overlap
VSN
VSP
-
+
SWN1
BG1
Diff Amp
DIFFOUT
1.3 V
Error Amp
+
-
BST2
TG2
VFB
Phase 2
Gate Driver
with
Adaptive
Non−overlap
+
-
COMP
VDRP
SWN2
BG2
+
-
VDFB
CSSUM
+
CS1P
CS1N
+
-
+
Gain = 6
Gain = 6
BST3
TG3
CS2P
CS2N
+
-
+
Phase 3
Gate Driver
with
Adaptive
Non−overlap
+
-
SWN3
CS3P
CS3N
+
-
+
BG3
G4
Gain = 6
Gain = 6
+
-
CS4P
CS4N
+
+
-
Oscillator
IMON
ROSC
ILIM
DRVON
Control,
Fault Logic
and
Monitor
Circuits
+
-
I
Limit
EN
VCC
+
VR_RDY
-
4.25 V
UVLO
GND (FLAG)
Figure 1. NCP5395 Functional Block Diagram
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2
NCP5395
VTT
R226
PSI#_CPU
VID0
VID1
VID2
VID3
VID4
VID5
VID6
VID7
12V_FILTER
D
1
2
12V_FILTER
RLIM7
G
S
IMON
C82
D
S
D
G
PWM3_SENSE_N
PWM3_SENSE_P
R14
G
S
VCCP
48
VBST3
13
14
IMON
VSP
CFB4
RFB7
CH3
47
46
45
44
43
42
TG3
SWN3
DRVON
BST2
15
16
17
18
VSN
DIFFOUT
COMP
VFB
RF3
CF3
RFB6
DRVON
NCP5395
48L 7x7 QFN
FLAG = GND
TG2
RDRP7
2.61K
19
20
21
22
SWN2
VDRP
VDFB
CSSUM
DAC
12V_FILTER
CDFB3
RDFB3
12V_FILTER
BG2 41
R47
40
39
38
37
VCCP
SWN1
TG1
2
1
RISO8
D
G
RISO7
+5.0V
RT8
23
24
GND
VCC
S
BST1
C34
D
S
D
S
PWM1_SENSE_N
PWM1_SENSE_P
C17
G
G
VTT
VCCP
R24
C31
PWM1_SENSE_P
PWM1_SENSE_N
R137
R139
ENABLE
R28
C32
PWM3_SENSE_P
PWM3_SENSE_N
Figure 2. Typical 2 Phase Application
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NCP5395
VTT
R236
PSI#_CPU
12V_FILTER
D
2
1
VID0
VID1
VID2
VID3
VID4
VID5
VID6
VID7
12V_FILTER
G
S
D
S
D
RLIM9
PWM3_SENSE_N
PWM3_SENSE_P
G
G
S
C83
R29
VCCP
12V_FILTER
48
VBST3
IMON
VSP
CFB5 13
2
1
RFB10
14
15
16
17
18
47
46
45
44
43
42
41
TG3
SWN3
DRVON
BST2
TG2
D
VSN
G
S
DIFFOUT
COMP
VFB
DRVON
RF4
RFB8
NCP5395
48L 7x7 QFN
FLAG = GND
CH4
CF4
D
S
D
RDRP10
PWM2_SENSE_N
PWM2_SENSE_P
2.61K
G
S
G
19
VDRP
VDFB
CSSUM
DAC
SWN2
BG2
CDFB4
RDFB4
RT10
20
21
12V_FILTER
R46
VCCP
SWN1
TG1
40
39
12V_FILTER
22
23
RISO4 RISO10
38
37
GND
VCC
2
1
+5.0V
24
D
G
BST1
C48
S
C37
VCCP
D
S
D
S
PWM1_SENSE_N
PWM1_SENSE_P
VTT
G
G
R33
C40
PWM1_SENSE_P
PWM1_SENSE_N
R145
R148
12V_FILTER
R32
C38
PWM2_SENSE_P
ENABLE
PWM2_SENSE_N
PWM3_SENSE_P
R34
C41
PWM3_SENSE_N
Figure 3. Typical 3 Phase Application
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4
NCP5395
VTT
PSI#_CPU
1
2
12V_FILTER
VID0
VID1
VID2
VID3
VID4
VID5
VID6
VID7
12V_FILTER
D
G
S
D
S
D
G
RLIM10
G
PWM3_SENSE_N
PWM3_SENSE_P
S
IMON
VCCP
12V_FILTER
48
47
46
45
VBST3
TG3
13
14
IMON
VSP
2
1
CFB6
RFB9
RFB11
D
G
15
16
17
18
VSN
SWN3
DRVON
BST2
TG2
DRVON
S
DIFFOUT
COMP
VFB
RF5
CF5
NCP5395
48L 7x7 QFN
FLAG = GND
44
43
CH5
D
S
D
RDRP11
PWM2_SENSE_N
PWM2_SENSE_P
G
G
S
19
42
41
VDRP
VDFB
CSSUM
DAC
SWN2
BG2
CDFB5
20
21
12V_FILTER
40
RDFB5
RT12
VCCP
SWN1
TG1
12V_FILTER
39
38
37
22
23
RISO11
RISO12
GND
VCC
2
1
+5.0V
24
D
G
BST1
S
VCCP
D
S
D
PWM1_SENSE_N
PWM1_SENSE_P
VTT
PWM4_GATE
G
G
S
PWM1_SENSE_P
PWM1_SENSE_N
12V_FILTER
12V_FILTER
PWM2_SENSE_P
2
1
ENABLE
D
S
PWM2_SENSE_N
PWM3_SENSE_P
G
BST
VCC
4
1
DRH
SW
DRL
PGND
PWM3_SENSE_N
DRVON
PWM4_GATE
PWM4_SENSE_P
8
OD
IN
7
5
6
3
2
D
S
D
S
PWM4_SENSE_N
PWM4_SENSE_P
NCP5359
G
G
PWM4_SENSE_N
Figure 4. Typical 4 Phase Application
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5
NCP5395
Table 1. Pin Descriptions
Pin No.
Symbol
Description
1
2
BG3
PSI
Low side gate drive #3
Selects DAC Decode.
Voltage ID DAC input
Voltage ID DAC input
Voltage ID DAC input
Voltage ID DAC input
Voltage ID DAC input
Voltage ID DAC input
Voltage ID DAC input
3
VID0
4
VID1
5
VID2
6
VID3
7
VID4
8
VID5
9
VID6
10
11
VID7/AMD
ROSC
Voltage ID DAC input. Pull to V (5 V) to enable AMD 6−bit DAC code.
CC
A resistance from this pin to ground programs the oscillator frequency and provides a 2 V reference
for programming the ILIM voltage.
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
FLAG
ILIM
Over current shutdown threshold setting. ILIM = VDRP − 1.3 V. Resistor divide ROSC to set threshold
0 to 1 Volt analog signal proportional to the output load current. VSN referenced Clamped to 1.1 Vmax
Non−inverting input to the internal differential remote sense amplifier
Inverting input to the internal differential remote sense amplifier
Output of the differential remote sense amplifier
Output of the compensation amplifier
IMON
VSP
VSN
DIFFOUT
COMP
VFB
Compensation amplifier voltage feedback
VDRP
VDFB
CSSUM
DAC
Voltage output signal proportional to current used for current limit and output voltage droop
Droop Amplifier Voltage Feedback
Inverted Sum of the Differential Current Sense inputs
DAC output used to provide feed forward for dynamic VID
Ground
GND
VCC
Power for the internal control circuits with UVLO monitor
Non−inverting input to current sense amplifier #4
Inverting input to current sense amplifier #4
CS4P
CS4N
CS3P
CS3N
CS2P
CS2N
CS1P
CS1N
EN
Non−inverting input to current sense amplifier #3
Inverting input to current sense amplifier #3
Non−inverting input to current sense amplifier #2
Inverting input to current sense amplifier #2
Non−inverting input to current sense amplifier #1
Inverting input to current sense amplifier #1
Threshold sensitive input. High = startup, Low =shutdown.
Open collector output. High indicates that the output is regulating
PWM output pulse to gate driver.
VR_RDY
G4
BG1
Low side gate drive #1
BST1
TG1
Upper MOSFET floating bootstrap supply for driver#1
High side gate drive #1
SWN1
VCCP
BG2
Switch Node #1
Power V for gate drivers with UVLO monitor
CC
Low side gate drive #2
SWN2
TG2
Switch Node #2
High side gate drive #2
BST2
DRVON
SWN3
TG3
Upper MOSFET floating bootstrap supply for driver#2
Bidirectional Gate Drive Enable
Switch Node #3
High side gate drive #3
BST3
GND
Upper MOSFET floating bootstrap supply for driver#3
Power supply return (QFN Flag)
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6
NCP5395
ABSOLUTE MAXIMUM RATINGS
Rating
Symbol
Value
Unit
ELECTRICAL INFORMATION
Controller Power Supply Voltages to GND
Driver Power Supply Voltages to GND
High−Side Gate Driver Supplies: BSTx to SWNx
V
−0.3, 7
V
V
V
CC
V
CCP
−0.3, 15
V
− V
35 V wrt/GND
40 V ≤ 50 ns wrt/GND
−0.3, 15 wrt/SWN
BST
SWN
High−Side FET Gate Driver Voltages: TGx to SWNx
Switch Node: SWNx
V
− V
BOOT + 0.3 V
35 V ≤ 50 ns wrt/GND
−0.3, 15 wrt/SWN
−2 V (200 ns)
V
V
V
TG
SWN
V
SWN
35
40 V ≤ 50 ns wrt/GND
−5 VDC
−10 V (200 ns)
Low−Side Gate Drive: BGx
V
BG
− AGND
V
CC
+ 0.3 V
−0.3 VDC (200 ns)
Logic Inputs
V
−0.3, 6
0
V
V
LOGIC
GND
V
GND
V−
GND 300
1.1
mV
V
Imon Out
V
IMON
All Other Pins
−0.3, 5.5
V
THERMAL INFORMATION
Thermal Characteristic
QFN Package (Note 1)
R
q
JA
TBD
°C/W
Operating Junction Temperature Range (Note 2)
Operating Ambient Temperature Range
Maximum Storage Temperature Range
T
0 to 125
0 to +70
−55 to +150
1
°C
°C
°C
J
T
AMB
T
STG
Moisture Sensitivity Level
QFN Package
MSL
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
*All signals referenced to GND unless noted otherwise.
*The maximum package power dissipation must be observed.
1. JESD 51−5 (1S2P Direct−Attach Method) with 0 LFM
2. Operation at −40°C to 0°C guaranteed by design, not production tested.
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7
NCP5395
ELECTRICAL CHARACTERISTICS
0°C < T < 70°C; 0°C < T < 125°C; 4.75 < V < 5.25 V; All DAC Codes; C
= 0.1 mF unless otherwise noted.
A
J
CC
VCC
Parameter
Test Conditions
Min
Typ
Max
Unit
ERROR AMPLIFIER
Input Bias Current
Open Loop DC Gain
−200
−
200
nA
dB
C = 60 pF to GND,
L
−
100
−
L
R = 10 kW to GND
Open Loop Unity Gain Bandwidth
Open Loop Phase Margin
Slew Rate
C = 60 pF to GND,
L
−
−
−
18
70
10
−
−
−
MHz
°
L
R = 10 kW to GND
C = 60 pF to GND,
L
R = 10 kW to GND
L
DV = 100 mV, G = −10V/V,
V/ms
in
DV = 1.5 V − 2.5 V,
out
C = 60 pF to GND,
L
DC Load = 125 mA to GND
Maximum Output Voltage
Minimum Output Voltage
Output Source Current
Output Sink Current
10 mV of Overdrive,
SOURCE
3.0
−
−
−
−
75
−
V
I
= 2.0 mA
10 mV of Overdrive,
= 500 mA
mV
mA
mA
I
SINK
10 mV of Overdrive,
= 3.5 V
1.5
0.75
2.0
1.0
V
out
10 mV of Overdrive,
= 0.1 V
−
V
out
DIFFERENTIAL SUMMING AMPLIFIER
V+ Input Pull down Resistance
DRVON = low
DRVON = high
−
−
0.6
6.0
−
−
kW
V+ Input Bias Voltage
DRVON = low
DRVON = high
−
−
0.5
0.86
−
−
V
Input Voltage Range (Note 4)
−0.3
−
3.0
V
−3 dB Bandwidth
C = 80 pF to GND,
L
−
15
−
MHz
L
R = 10 kW to GND
Closed Loop DC gain VS to Diffout (Note 4)
Maximum Output Voltage
VS+ to VS− = 0.5 V to 1.6 V
0.98
3.0
1.0
1.02
V/V
V
10 mV of Overdrive,
−
−
I
= 2 mA
SOURCE
Minimum Output Voltage
Output Source Current
10 mV of Overdrive,
= 1 mA
−
−
0.5
−
V
I
SINK
10 mV of Overdrive,
= 3 V
1.5
1.0
2.0
1.5
mA
mA
V
out
Output Sink Current
10 mV of Overdrive,
= 0.2 V
−
V
out
INTERNAL OFFSET VOLTAGE
Offset Voltage to the (+) Pin of the Error Amp & the
VDRP Pin
−2
0
+2
mV
3. Design guaranteed.
4. For propagation delays, “tpdh” refers to the specified signal going high “tpdl” refers to it going low. Reference Gate Timing Diagram.
5. Guaranteed by design; not tested in production.
6. Internal DAC voltage is centered 19 mV below the listed Voltage. For VR11.1/VR11.0/VR10
7. No DAC offset is implemented for AMD operation.
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8
NCP5395
ELECTRICAL CHARACTERISTICS
0°C < T < 70°C; 0°C < T < 125°C; 4.75 < V < 5.25 V; All DAC Codes; C
= 0.1 mF unless otherwise noted.
A
J
CC
VCC
Parameter
Test Conditions
Min
Typ
Max
Unit
VDROOP AMPLIFIER
Input Bias Current
−200
−
200
3.0
−
nA
V
Inverting Voltage Range
Open Loop DC Gain
0
1.3
100
C = 20 pF to GND including ESD
L
−
dB
L
R = 1 kW to GND
Open Loop Unity Gain Bandwidth
Open Loop Phase Margin
Slew Rate
C = 20 pF to GND including ESD
L
−
−
18
70
10
−
−
−
MHz
°
L
R = 1 kW to GND
C = 20 pF to GND including ESD
L
R = 1 kW to GND
L
C = 20 pF to GND including ESD
−
−
V/ms
V
L
R = 1 kW to GND
L
Maximum Output Voltage
Minimum Output Voltage
Output Source Current
Output Sink Current
10 mV of Overdrive,
3.0
−
−
I
= 4.0 mA
SOURCE
10 mV of Overdrive,
= 1.0 mA
−
1.0
−
V
I
SINK
10 mV of Overdrive,
= 3.0 V
4.0
1.0
−
mA
mA
V
out
10 mV of Overdrive,
= 1.0 V
−
−
V
out
CSSUM AMPLIFIER
Current Sense Input to CSSUM Gain
−75 mV < CS < 75 mV
−3.793
−3.70
−3.608
V/V
Current Sense Input to V
−3 dB Bandwidth
C = 10 pF to GND,
L
−
12
−
MHz
DRP
L
R = 10 kW to GND
Current Summing Amp Output Offset Voltage
Maximum CSSUM Output Voltage
CSx − CSNx = 0, CSx = 1 V
CSx − CSxN = −0.2 V
−8.0
−
−
+8.0
mV
V
3.0
−
(all phases) I
= 1 mA
SOURCE
Minimum CSSUM Output Voltage
CSx − CSxN = 0.7 V
(all phases) I = 1 mA
−
−
0.3
V
SINK
Output Source Current
Output Sink Current
PSI
V
= 3.0 V
= 0.3 V
1.0
4.0
−
−
−
−
mA
mA
out
V
out
Enable High Input Leakage Current
Threshold
External 1k Pull−up to 3.3 V
−
450
−
−
1.0
770
−
mA
mV
ns
600
100
Delay
DRVON
Output High Voltage
Output Low Voltage
Delay Time
Sourcing 500 mA
Sinking 500 mA
3.0
−
−
−
−
0.7
−
V
V
Propagation delays
−
10
10
ns
ns
Rise Time
C (PCB) = 20 pF,
−
−
L
DVo = 10% to 90%
Fall Time
C (PCB) = 20 pF,
−
10
−
ns
L
DVo = 10% to 90%
Internal Pull−Down Resistance
35
70
140
2.0
kW
V
CC
Voltage when DRVON Output Valid
−
−
V
3. Design guaranteed.
4. For propagation delays, “tpdh” refers to the specified signal going high “tpdl” refers to it going low. Reference Gate Timing Diagram.
5. Guaranteed by design; not tested in production.
6. Internal DAC voltage is centered 19 mV below the listed Voltage. For VR11.1/VR11.0/VR10
7. No DAC offset is implemented for AMD operation.
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9
NCP5395
ELECTRICAL CHARACTERISTICS
0°C < T < 70°C; 0°C < T < 125°C; 4.75 < V < 5.25 V; All DAC Codes; C
= 0.1 mF unless otherwise noted.
A
J
CC
VCC
Parameter
Test Conditions
Min
Typ
Max
Unit
CURRENT SENSE AMPLIFIERS
Input Bias Current
CSx = CSxN = 1.4 V
−50
−0.3
−
−
50
2.0
nA
V
Common Mode Input Voltage Range
Differential Mode Input Voltage Range
Current Sharing Output Voltage
Current Sense Input to PWM Gain
Current Sense Input to CSSUM Gain
IMON
−120
−TBD
5.4
−
120
mV
mV
V/V
V/V
CSx = CSxN = 1.00 V,
−
TBD
6.0
0 V < CSx − CSxN < 0.1 V,
0 V < CSx − CSxN < 0.1 V
5.7
−3.7
−3.793
−3.608
V
to IMON Gain
1.325 V > V
> 1.75 V
DRP
1.89
2.0
4.0
2.02
V/V
DRP
Current Sense Input to V
−3 dB Bandwidth
C = 30 pF to GND,
−
−
MHz
DRP
L
R = 100 kW to GND
L
V
DRP
to IMON Output Slew Rate
C = 30 pF to GND,
−
TBD
−
V/ms
L
Load = 100k to GND
Output Referred Offset Voltage
Minimum Output Voltage
Maximum Output Voltage
Output Sink Current
V
V
= 1.5 V, I
= 0 mA
SOURCE
−TBD
−
−
−
−
−
−
TBD
0.1
−
mV
V
DRP
DRP
= 1.3 V, I
= 25 mA
SINK
I
= 300 mA
1.0
175
1.1
V
out
V
out
= 0.3 V
−
mA
V
Maximum Clamp Voltage
IMON − VSN V
R
= HIGH
1.15
DRP
= Open
LOAD
OSCILLATOR
Switching Frequency Range
Switching Frequency Accuracy
Switching Frequency Accuracy
Switching Frequency Accuracy (2ph or 4ph)
100
−
−
−
1100
5.0
kHz
%
200 kHz < F
100 kHz < F
< 600 kHz
< 1 MHz
SW
SW
−
−
10
%
kHz
R
OSC
R
OSC
R
OSC
R
OSC
R
OSC
R
OSC
= 69.8k
TBD
475
TBD
TBD
494
TBD
1.93
−
TBD
525
TBD
TBD
546
TBD
2.05
= 16.2k
= 7.5k
−
−
Switching Frequency Accuracy (3ph)
kHz
V
= 69.8k
= 16.2k
= 7.5k
−
−
−
ROSC Output Voltage
2.00
MODULATORS (PWM Comparators)
Minimum Pulse Width
Fsw = 800 kHz
−
30
1.0
150
−
ns
V
Magnitude of the PWM Ramp
0% Duty Cycle
TBD
TBD
TBD
TBD
COMP Voltage when the PWM
Outputs Remain LO
mV
100% Duty Cycle
COMP Voltage when the PWM
Outputs Remain HI
−
1.15
−
V
PWM Phase Angle Error
Between Adjacent Phases
−TBD
−
TBD
°
VR_RDY (Power Good) OUTPUT
VR_RDY Output Saturation Voltage
3. Design guaranteed.
I
= 10 mA
−
−
0.4
V
PGD
4. For propagation delays, “tpdh” refers to the specified signal going high “tpdl” refers to it going low. Reference Gate Timing Diagram.
5. Guaranteed by design; not tested in production.
6. Internal DAC voltage is centered 19 mV below the listed Voltage. For VR11.1/VR11.0/VR10
7. No DAC offset is implemented for AMD operation.
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10
NCP5395
ELECTRICAL CHARACTERISTICS
0°C < T < 70°C; 0°C < T < 125°C; 4.75 < V < 5.25 V; All DAC Codes; C
= 0.1 mF unless otherwise noted.
A
J
CC
VCC
Parameter
Test Conditions
Min
Typ
Max
Unit
VR_RDY (Power Good) OUTPUT
VR_RDY Rise Time
External pull−up of 1 KW to 1.25 V,
TOT
−
−
100
150
1.0
ns
V
C
= 45 pF, DVo = 10% to 90%
VR_RDY Output Voltage at Power−up
VR_RDY pulled up to 5 V via 2 kW,
≤ 3 x t
−
t
R(VCC)
R(5V)
100 ms ≤ t
≤ 20 ms
R(VCC)
VR_RDY High − Output Leakage Current
VR_RDY = 5.5 V via 1 K
−
−
−
0.1
mA
VR_RDY Upper Threshold Voltage (INTEL)
VCore Increasing, DAC = 1.3 V
300
250
mV
(below
DAC)
VR_RDY Lower Threshold Voltage (INTEL)
VR_RDY Lower Threshold Voltage (AMD)
VR_RDY Lower Threshold Voltage (AMD)
VCore Decreasing, DAC = 1.3 V
VCore Increasing, DAC = 1.3 V
VCore Decreasing, DAC = 1.3 V
390
−
350
TBD
TBD
300
TBD
TBD
mV
(below
DAC)
mV
(below
DAC)
TBD
mV
(below
DAC)
VR_RDY Rising Delay
VR_RDY Falling Delay
PWM G4 OUTPUT
Output High Voltage
Mid Output Voltage
Output Low Voltage
Delay + Rise Time
VCore Increasing
VCore Decreasing
−
−
TBD
5.0
−
−
ms
ms
Sourcing 500 mA
Sinking 500 mA
3.0
1.4
−
−
1.5
−
−
V
1.6
0.7
15
V
C (PCB) = 50 pF,
−
10
ns
L
DVo = V to GND
CC
Delay + Fall Time
C (PCB) = 50 pF,
−
10
15
ns
L
DVo = GND to V
CC
Tri−State Output Leakage
Gx = 2.5 V, x = 1−4
−
−
−
1.5
mA
Output Impedance −
HI or LO State
Max Resistance to V (HI) or
GND (LO)
75
150
W
CC
Minimum V for Valid PWM Output Level
−
−
2.0
V
CC
PWM 4 2/3/4 Phase Detection
2 Phase Mode
Note Gate 4 tied to V
3.2
1.2
0
−
−
−
V
V
V
V
CC
CC
4 Phase Mode
Note Gate Driver will pull to 1.5 V
Note Gate 4 tied to GND
2.8
0.8
3 Phase Mode
DIGITAL SOFT−START
Soft−Start Ramp Time
DAC = 0 to DAC = 1.1 V
1.0
−
1.3
ms
VR11 V
time
Not used in Legacy Startup
400
500
600
ms
boot
VID7/VR11/AMD/LEGACY INPUT
VID Threshold
450
600
770
100
mV
nA
VR11 Input Bias Current
−100
−
3. Design guaranteed.
4. For propagation delays, “tpdh” refers to the specified signal going high “tpdl” refers to it going low. Reference Gate Timing Diagram.
5. Guaranteed by design; not tested in production.
6. Internal DAC voltage is centered 19 mV below the listed Voltage. For VR11.1/VR11.0/VR10
7. No DAC offset is implemented for AMD operation.
http://onsemi.com
11
NCP5395
ELECTRICAL CHARACTERISTICS
0°C < T < 70°C; 0°C < T < 125°C; 4.75 < V < 5.25 V; All DAC Codes; C
= 0.1 mF unless otherwise noted.
A
J
CC
VCC
Parameter
Test Conditions
Min
Typ
Max
Unit
VID7/VR11/AMD/LEGACY INPUT
Delay Before Latching VID Change (VID Deskewing)
Measured from the Edge of the 1st
VID Change
200
−
−
300
2.9
ns
V
AMD Upper Threshold
Note: When above this threshold
the controller will ramp directly to
−
VID without stopping at V
boot
AMD Lower Threshold
ENABLE INPUT
2.4
−
−
V
Enable High Input Leakage Current
VR11.1 Threshold
Pull−up to 1.3 V
−
450
−
−
200
770
1.5
−
nA
mV
V
600
1.3
1.1
200
3.5
AMD Upper Threshold
AMD Lower Threshold
AMD Total Hysteresis
Enable Delay Time
0.9
−
V
Rising− Falling Threshold
−
mV
ms
Measure time from Enable
transitioning HI to when SS begins
−
−
CURRENT LIMIT
ILIM to VDRP Gain
0.99
−
1.00
0.25
0.333
0.5
0.1
−
1.01
−
V/V
V/V
V/V
V/V
mA
ILIM to VRDP Gain in PSI 4 Phase
ILIM to VDRP Gain in PSI 3 Phase
ILIM to VDRP Gain in PSI 2 Phase
ILIM Pin Input Bias Current
ILIM Pin Working Voltage Range
ILIM accuracy
−
−
−
−
−
1.0
2.0
10
0.1
−10
V
Measured with respect to the ILIM
setting
−
mV
Delay
−
−
120
ns
OVERVOLTAGE PROTECTION
VR11 Over Voltage Threshold
DAC+
160
DAC+
190
DAC+
210
mV
mV
ns
AMD Over Voltage Threshold
DAC+
210
DAC+
235
DAC+
260
Delay
−
−
100
UNDERVOLTAGE PROTECTION
V
CC
V
CC
V
CC
UVLO Start Threshold
UVLO Stop Threshold
UVLO Hysteresis
4.0
3.8
−
4.25
4.05
200
4.5
4.3
−
V
V
mV
DAC OUTPUT
DAC Output Variation
DAC Output Variation
Output Source Current
Output Sink Current
3. Design guaranteed.
I
I
= 200 mA, All VIDs
−3.0
−3.0
0
0
0
−
−
3.0
3.0
5.0
16
%
%
SOURCE
= 200 mA, All VIDs
= 1.6 V
SINK
V
mA
mA
out
V
= 0.3 V
5.0
out
4. For propagation delays, “tpdh” refers to the specified signal going high “tpdl” refers to it going low. Reference Gate Timing Diagram.
5. Guaranteed by design; not tested in production.
6. Internal DAC voltage is centered 19 mV below the listed Voltage. For VR11.1/VR11.0/VR10
7. No DAC offset is implemented for AMD operation.
http://onsemi.com
12
NCP5395
ELECTRICAL CHARACTERISTICS
0°C < T < 70°C; 0°C < T < 125°C; 4.75 < V < 5.25 V; All DAC Codes; C
= 0.1 mF unless otherwise noted.
A
J
CC
VCC
Parameter
Test Conditions
Min
Typ
Max
Unit
VID INPUTS
Threshold
450
−100
10
600
−
770
100
25
mV
nA
mA
ns
VR11 Mode Leakage
AMD Mode Input Bias Current
−
st
Delay before Latching VID Change
(VID Deskewing)
Measured from the edge of the 1
VID change
200
−
300
Delay Before Responding to Invalid or Shutdown
Codes (Remove Spec)
Note: DAC must hold the last valid
VID during this period
−
−
−
ms
DIGITAL DAC SLEW RATE LIMITER
Slew Rate Limit (Intel Mode)
Slew Rate Limit (AMD Mode)
Soft−Start Slew Rate
12.5
3.125
−
−
−
15
3.75
−
mV/ms
mV/ms
mV/ms
0.84
INPUT SUPPLY CURRENT
V
Operating Current
EN Low, No PWM
CS2 through CS4
20
−
40
mA
mV
CC
PHASE SHEDDING
CS referred ph shed bias
−
66
−
V
SUPPLY VOLTAGE
UVLO Start Threshold
UVLO Stop Threshold
UVLO Hysteresis
POR
CCP
V
V
V
V
8.2
7.2
−
9.0
8.0
1.0
3.2
9.5
8.5
−
V
V
V
CCP
CCP
CCP
CCP
Voltage at which the Driver OVP
becomes active
TBD
TBD
BOOST PIN UVLO
BOOST V UVLO Start Threshold
3.5
3.3
4.0
3.8
V
V
CC
BOOST V UVLO Stop Threshold
CC
BOOST V UVLO Hysteresis
200
mV
CC
BOOST SUPPLY CURRENT
I
Quiescent Supply Current in Normal
EN = V , PWM = OSC, F =
SW
−
−
−
42
40
mA
mA
VCCP_NORM
CC
Operation
100k, C
= 0 p, V
= 12 V
LOAD
CCP
I
Standby Current
EN = GND; No switching,
= 12 V
20
VCC_SBC
V
CCP
I
I
I
I
I
I
Quiescent Supply Current in Normal Operation
Quiescent Supply Current in Normal Operation
Quiescent Supply Current in Normal Operation
IN = V
, V
= 12 V
= 12 V
= 12 V
= 12 V
= 12 V
= 12 V
−
−
−
−
−
−
10
10
TBD
TBD
TBD
−
mA
mA
BST1
CCP CCP
IN = GND, V
IN = GND, V
BST2
CCP
10
BST3
CCP
Standby Current
Standby Current
Standby Current
IN = V
, V
0.25
0.25
0.25
mA
mA
mA
BST1_SD
BST2_SD
BST3_SD
CCP CCP
IN = GND, V
−
CCP
IN = GND, V
−
CCP
st
STARTUP HIGH SIDE SHORT TRIP (Active only during 1 power on)
V
swx
Output Overvoltage Trip Threshold at Startup
Power Startup time, V > 9 V
1.75
−
2.0
V
CC
3. Design guaranteed.
4. For propagation delays, “tpdh” refers to the specified signal going high “tpdl” refers to it going low. Reference Gate Timing Diagram.
5. Guaranteed by design; not tested in production.
6. Internal DAC voltage is centered 19 mV below the listed Voltage. For VR11.1/VR11.0/VR10
7. No DAC offset is implemented for AMD operation.
http://onsemi.com
13
NCP5395
ELECTRICAL CHARACTERISTICS
0°C < T < 70°C; 0°C < T < 125°C; 4.75 < V < 5.25 V; All DAC Codes; C
= 0.1 mF unless otherwise noted.
A
J
CC
VCC
Parameter
Test Conditions
Min
Typ
Max
Unit
HIGH SIDE DRIVER
W
R
R
Output Resistance, Sourcing
Output Resistance, Sinking
Transition Time
V
V
− V
− V
= 12 V
= 12 V
−
−
−
−
−
1.8
1.0
16
11
4.2
2.2
−
H_TG
H_TG
BST
SW
BST
SW
Tr
Tf
C
C
= 3 nF, V
= 3 nF, V
− V
− V
= 12 V
= 12 V
ns
ns
ns
DRVH
DRVH
LOAD
LOAD
BST
BST
SW
Transition Time
−
SW
Tpdh
Propagation Delay (Note 4)
Driving High, C
= 3 nF,
20
−
DRVH
LOAD
V
CCP
= 12 V
Tpdh
Propagation Delay (Note 4)
Driving Low, C
CCP
= 3 nF,
−
20
−
ns
DRVH
LOAD
V
= 12 V
LOW SIDE DRIVER
R
R
Output Resistance, Sourcing
Output Resistance, Sinking
SW = GND
SW = V
−
−
−
−
−
TBD
TBD
16
4.2
2.2
−
W
W
H_BG
L_BG
CC
Tr
Tf
Transition Time
Transition Time
C
LOAD
C
LOAD
= 3 nF
= 3 nF
ns
ns
ns
DRVH
DRVH
11
−
Tpdh
Propagation Delay (Note 4)
Driving High, C
= 3 nF,
= 3 nF,
20
−
DRVH
LOAD
V
CCP
= 12 V
Tpdh
Propagation Delay (Note 4)
Driving Low, C
= 12 V
−
−
20
−
−
ns
DRVH
LOAD
V
CCP
V
NCDT
Negative Current Detector Threshold
(Note 3)
−1.0
mV
THERMAL SHUTDOWN
Tsd Thermal Shutdown (Note 3)
Tsdhys Thermal Shutdown Hysteresis (Note 3)
VRM 11 DAC
150
170
20
−
−
°C
°C
−
System Voltage Accuracy
1.0 V < DAC < 1.6 V
0.8 V < DAC < 1.0 V
0.5 V < DAC < 0.8 V
−
−
−
−
−
−
0.5
5.0
8.0
%
mV
mV
3. Design guaranteed.
4. For propagation delays, “tpdh” refers to the specified signal going high “tpdl” refers to it going low. Reference Gate Timing Diagram.
5. Guaranteed by design; not tested in production.
6. Internal DAC voltage is centered 19 mV below the listed Voltage. For VR11.1/VR11.0/VR10
7. No DAC offset is implemented for AMD operation.
http://onsemi.com
14
NCP5395
IN
tpdl
tf
DRVL
DRVL
DRVL
90%
90%
2V
10%
tpdh
10%
th
tpdl
tf
tr
DRVL
DRVH
DRVH
DRVH
DRVH
90%
90%
10%
2V
10%
tpdh
DRVH−SW
DRVL
SW
Figure 5. Timing Diagram
http://onsemi.com
15
NCP5395
Table 2. VRM11 VID CODES
V
ID7
V
ID6
V
ID5
V
ID4
V
ID3
V
ID2
V
ID1
V
ID0
800 mV
400 mV
200 mV
100 mV
50 mV
25 mV
12.5 mV
6.25 mV
Voltage (V)
HEX
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1.60000
1.59375
1.58750
1.58125
1.57500
1.56875
1.56250
1.55625
1.55000
1.54375
1.53750
1.53125
1.52500
1.51875
1.51250
1.50625
1.50000
1.49375
1.48750
1.48125
1.47500
1.46875
1.46250
1.45625
1.45000
1.44375
1.43750
1.43125
1.42500
1.41875
1.41250
1.40625
1.40000
1.39375
1.38750
1.38125
1.37500
1.36875
1.36250
1.35625
1.35000
1.34375
1.33750
1.33125
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
http://onsemi.com
16
NCP5395
Table 2. VRM11 VID CODES
V
ID7
V
ID6
V
ID5
V
ID4
V
ID3
V
ID2
V
ID1
V
ID0
800 mV
400 mV
200 mV
100 mV
50 mV
25 mV
12.5 mV
6.25 mV
Voltage (V)
1.32500
1.31875
1.31250
1.30625
1.30000
1.29375
1.28750
1.28125
1.27500
1.26875
1.26250
1.25625
1.25000
1.24375
1.23750
1.23125
1.22500
1.21875
1.21250
1.20625
1.20000
1.19375
1.18750
1.18125
1.17500
1.16875
1.16250
1.15625
1.15000
1.14375
1.13750
1.13125
1.12500
1.11875
1.11250
1.10625
1.10000
1.09375
1.08750
1.08125
1.07500
1.06875
1.06250
1.05625
1.05000
1.04375
HEX
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
http://onsemi.com
17
NCP5395
Table 2. VRM11 VID CODES
V
ID7
V
ID6
V
ID5
V
ID4
V
ID3
V
ID2
V
ID1
V
ID0
800 mV
400 mV
200 mV
100 mV
50 mV
25 mV
12.5 mV
6.25 mV
Voltage (V)
1.03750
1.03125
1.02500
1.01875
1.01250
1.00625
1.00000
0.99375
0.98750
0.98125
0.97500
0.96875
0.96250
0.95625
0.95000
0.94375
0.93750
0.93125
0.92500
0.91875
0.91250
0.90625
0.90000
0.89375
0.88750
0.88125
0.87500
0.86875
0.86250
0.85625
0.85000
0.84375
0.83750
0.83125
0.82500
0.81875
0.81250
0.80625
0.80000
0.79375
0.78750
0.78125
0.77500
0.76875
0.76250
0.75625
HEX
5C
5D
5E
5F
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
80
81
82
83
84
85
86
87
88
89
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
http://onsemi.com
18
NCP5395
Table 2. VRM11 VID CODES
V
ID7
V
ID6
V
ID5
V
ID4
V
ID3
V
ID2
V
ID1
V
ID0
800 mV
400 mV
200 mV
100 mV
50 mV
25 mV
12.5 mV
6.25 mV
Voltage (V)
0.75000
0.74375
0.73750
0.73125
0.72500
0.71875
0.71250
0.70625
0.70000
0.69375
0.68750
0.68125
0.67500
0.66875
0.66250
0.65625
0.65000
0.64375
0.63750
0.63125
0.62500
0.61875
0.61250
0.60625
0.60000
0.59375
0.58750
0.58125
0.57500
0.56875
0.56250
0.55625
0.55000
0.54375
0.53750
0.53125
0.52500
0.51875
0.51250
0.50625
0.50000
OFF
HEX
8A
8B
8C
8D
8E
8F
90
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
1
1
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
91
92
93
94
95
96
97
98
99
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
B0
B1
B2
FE
FF
OFF
http://onsemi.com
19
NCP5395
Parameter
Test Condition
TYP
MAX
Units
VR10 DAC
System Voltage Accuracy
1.0 V < DAC < 1.6 V
0. 83125 V < DAC < 1.0 V
−
−
0.5
5
%
mV
8. Internal DAC voltage is centered 19 mV below the listed Voltage. For VR11.1/VR11.0/VR10
No DAC offset is implemented for AMD operation.
V
ID4
V
ID3
V
ID2
V
ID1
V
ID0
V
ID5
V
ID6
400 mV
200 mV
100 mV
50 mV
25 mV
12.5 mV
6.25 mV
Voltage (V)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1.60000
1.59375
1.58750
1.58125
1.57500
1.56875
1.56250
1.55625
1.55000
1.54375
1.53750
1.53125
1.52500
1.51875
1.51250
1.50625
1.50000
1.49375
1.48750
1.48125
1.47500
1.46875
1.46250
1.45625
1.45000
1.44375
1.43750
1.43125
1.42500
1.41875
1.41250
1.40625
1.40000
1.39375
1.38750
1.38125
1.37500
1.36875
1.36250
http://onsemi.com
20
NCP5395
Table 3. DAC CODES FOR VRM 10
V
ID4
V
ID3
V
ID2
V
ID1
V
ID0
V
ID5
V
ID6
400 mV
200 mV
100 mV
50 mV
25 mV
12.5 mV
6.25 mV
Voltage (V)
1.35625
1.35000
1.34375
1.33750
1.33125
1.32500
1.31875
1.31250
1.30625
1.30000
1.29375
1.28750
1.28125
1.27500
1.26875
1.26250
1.25625
1.25000
1.24375
1.23750
1.23125
1.22500
1.21875
1.21250
1.20625
1.20000
1.19375
1.18750
1.18125
1.17500
1.16875
1.16250
1.15625
1.15000
1.14375
1.13750
1.13125
1.12500
1.11875
1.11250
1.10625
1.10000
1.09375
OFF
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
OFF
http://onsemi.com
21
NCP5395
Table 3. DAC CODES FOR VRM 10
V
ID4
V
ID3
V
ID2
V
ID1
V
ID0
V
ID5
V
ID6
400 mV
200 mV
100 mV
50 mV
25 mV
12.5 mV
6.25 mV
Voltage (V)
OFF
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
OFF
1.08750
1.08125
1.07500
1.06875
1.06250
1.05625
1.05000
1.04375
1.03750
1.03125
1.02500
1.01875
1.01250
1.00625
1.00000
0.99375
0.98750
0.98125
0.97500
0.96875
0.96250
0.95625
0.95000
0.94375
0.93750
0.93125
0.92500
0.91875
0.91250
0.90625
0.90000
0.89375
0.88750
0.88125
0.87500
0.86875
0.86250
0.85625
0.85000
0.84375
0.83750
0.83125
http://onsemi.com
22
NCP5395
Parameter
Test Condition
MIN
TYP
MAX
Units
AMD DAC
System Voltage Accuracy
1.0 V < DAC < 1.55V
0.6 V ≤ DAC < 1.0V
0.375 V < DAC < 0.6V
−
−
−
−
−
−
0.5
1.0
2.0
%
%
%
9. NOTE: No DAC offset is implemented for AMD operation. DAC should be equal to the Nominal V shown in the table.
out
Table 4. AMD PROCESSOR 6−BIT VID CODE
(V ) Codes
ID
Nominal
V
V
V
V
V
V
V
Units
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
ID5
ID4
ID3
ID2
ID1
ID0
out
0
0
0
0
0
0
1.550
1.525
1.500
1.475
1.450
1.425
1.400
1.375
1.350
1.325
1.300
1.275
1.250
1.225
1.200
1.175
1.150
1.125
1.100
1.075
1.050
1.025
1.000
0.975
0.950
0.925
0.900
0.875
0.850
0.825
0.800
0.775
0.7625
0.7500
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
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NCP5395
Table 4. AMD PROCESSOR 6−BIT VID CODE
(V ) Codes
ID
Nominal
V
V
V
V
V
V
ID0
V
Units
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
ID5
ID4
ID3
ID2
ID1
out
1
0
0
0
1
0
0.7375
0.7250
0.7125
0.7000
0.6875
0.6750
0.6625
0.6500
0.6375
0.6250
0.6125
0.6000
0.5875
0.5750
0.5625
0.5500
0.5375
0.5250
0.5125
0.5000
0.4875
0.4750
0.4625
0.4500
0.4375
0.4250
0.4125
0.4000
0.3875
0.3750
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
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NCP5395
FUNCTIONAL DESCRIPTIONS
General
voltage with the DAC voltage. The non−inverting input
sums the remote output voltage with a 1.3 V reference. The
resulting voltage at the output of the remote sense amplifier is:
The NCP5395 dual edge modulated multiphase PWM
controller is specifically designed with the necessary
features for a high current CPU system. The IC consists of
the following blocks: Precision Flexible DAC, Differential
Remote Voltage Sense Amplifier, High Performance
Voltage Error Amplifier, Differential Current Feedback
Amplifiers, Precision Oscillator and Saw−tooth Generator,
and PWM Comparators with Hysteresis. The controller also
supports power saving mode as per Intel VR11.1 by
accurately monitoring the current and switching between
multi−phase and single phase operations as requested by the
microprocessor system. Protection features include:
Undervoltage Lockout, Soft−Start, Overcurrent Protection,
Overvoltage Protection, and Power Good Monitor.
VDiffout + Vout ) 1.3 V * Vdac * Voutreturn
This signal then goes through a standard compensation
circuit and into the inverting input of the error amplifier. The
non−inverting input of the error amplifier is also connected
to the 1.3 V reference. The 1.3 V reference then is subtracted
out and the error signal at the comp pin of the error amplifier
is as normally expected:
V
comp + Vdac * Vout
The non−inverting input of the remote sense amplifier is
pulled low through a small current sink during a fault
condition to prevent accidental charging of the regulator
output.
Precision Programmable DAC
A precision flexible DAC is provided. The DAC will
conform to 2 different specifications: AMD or VR11.1. The
VID7/AMD pin is provided to determine which DAC
specification will be used and which soft−start mode the part
will use for power up. There are two soft−start modes. If
VID7/AMD is above it’s threshold the device will soft−start
and ramp directly to the DAC code present on the VID
inputs. The following truth table describes the functionality:
2/3/4 Phase Operation
The part can be configured to 2−, 3−, or 4−phase mode. In
2− or 3−phase mode, the internal drivers will be used. In
4−phase mode, an external driver must be used to drive
phase 4. The NCP5359 driver is suggested to be used with
the controller. The input to G4 pin will decide which phase
mode the system is in operation. Please refer to the
Application Schematics for more information.
High Performance Voltage Error Amplifier
VID7/AMD Pin
VID7
Enable
Soft Start
Mode
Pin Mode
A high performance voltage error amplifier is provided.
The error amplifier’s inverting input is VFB and its output
is COMP. A standard type 3 compensation circuit is used
compensate the system. This involves a 3 pole, 2 zero
compensation network. The comp pin is pulled to ground
before soft−start for smooth start up.
Above AMD
Threshold
Not
active
AMD
Threshol
ds
Ramp to
VID
Below AMD
Threshold
Active
VR11.1
Threshol
ds
Ramp to
Vboot
Differential Current Sense
VID INPUTS
Four differential amplifiers are provided to sense the
output current of each phase. These current sense amplifiers
sense the current through the corresponding phase. A
voltage is generated across a current sense element such as
an inductor or sense resistor. The sense element should be
between 0.5 mW and 1.5 mW. It is possible to sense both
negative and positive going current. The information is used
to create the signal CSSUM and provide feedback for
current sharing.
VID0−VID7 control the target regulation voltage during
normal operation. In AMD mode the VID capture is enabled
just before soft start. In VR11 mode the VID capture is
enabled at the end of the V
waiting period. If the VID
BOOT
is valid the DAC will track to it. If an invalid VID occurs it
will be ignored for 10 ms before the controller shuts down.
Remote Sense Amplifier
A high performance differential amplifier is provided to
accurately sense the output voltage of the regulator. The
non−inverting input should be connected to the regulator’s
output voltage. The inverting input should be connected to
the return line of the regulator. Both connection points are
intended to be at a remote point so that the most accurate
reading of the output voltage can be obtained. The amplifier
is configured in a very unique way. First, the gain of the
amplifier is internally set to unity. Second, both the inverting
and non−inverting inputs of the amplifier are summing
nodes. The inverting input sums the output voltage return
Precision Oscillator
A programmable precision oscillator is provided. This
oscillator is programmed by the summed resistance of an
oscillator resistor and a current limit resistor. The output
voltage of this pin is used as the reference for the current
limit. The oscillator frequency range is 125 KHz/phase to
1000 KHz/phase. The oscillator frequency is proportional to
the current drawn out of the OSC pin.
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25
NCP5395
PWM Comparators
voltage exceeds the DAC voltage by 185 mV, or 285 mV if
in AMD mode, the VR_RDY flag will transition low the
high side gate drivers set to low, and the low side gate drivers
are all brought to high until the voltage falls below the OVP
threshold. If the over voltage trip 8 times the output voltage
will shut down. The OVP will not shut down the controller
if it occurs during soft−start. This is to allow the controller
to pull the output down to the DAC voltage and start up into
a pre−charged output.
Four PWM comparators are incorporated within the IC.
The non−inverting input of the comparators is connected to
the output of the error amplifier. The inverting input is
connected to a summed output of the phase current and the
oscillator ramp voltage with an offset. The output of the
comparator generates the PWM control signals.
During steady state operation, the duty cycle will center
on the valley of the saw−tooth waveform. During a transient
event, the controller will operate somewhat hysteretic, with
the duty cycle climbing along either the down ramp, up
ramp, or both.
VCCP Power ON Reset OVP
The V
power on reset OVP feature is used to protect
CCP
the CPU during start up. When V
is higher than 3.2 V, the
CCP
gate driver will monitor the switching node SW pin. If
SWNx pin higher than 1.9 V, the bottom gate will be forced
to high for discharge of the output capacitor. This works best
Soft−Start
Soft−start is implemented internally. A digital counter
steps the DAC up from zero to the target voltage based on the
predetermined rate in the spec table. There are 2 possible
soft start modes: VR11 and AMD. AMD mode simply ramps
if the 5 volt standby is diode OR’ed into V
with the 12 V
CCP
rail. The fault mode will be latched and the DRVON pin will
be forced to low, unless V
threshold.
is reduced below the UVLO
CCP
V
core
from 0 V directly to the DAC setting. The VR11 mode
ramps DAC to 1.1 V, pauses for 500 ms, reads the DAC
setting, then ramps to the final DAC setting.
Power Saving Mode
The controller is designed to allow power saving mode to
maintain a maximum efficiency. When a low PSI signal
from microcontroller is received, the controller will keep
one phase operating while shedding other phases. The active
one phase will operate in diode emulation mode, minimizing
power losses in light load. When the low PSI signal is
de−asserted, the dropped phases will be pulled back in to be
ready for heavy load.
Digital Slew Rate Limiter / Soft Start Block
The slew rate limiter and the soft−start block are to be
implemented with a digital up/down counter controlled by
an oscillator that is synchronized to VID line changes.
During soft start the DAC will ramp at the soft−start rate,
after soft start is complete the ramp rate will follow either the
Intel or the AMD slew rate depending on the mode.
Under Voltage Lockouts
An under voltage circuit senses the V input of the
Adaptive Non−overlap
CC
The non−overlap dead time control is used to avoid shoot
through damage to the power MOSFETs. When the PWM
signal pull high, DRVL will go low after a propagation
delay, the controller monitors the switching node (SWN) pin
voltage and the gate voltage of the MOSFET to know the
status of the MOSFET. When the low side MOSFET status
is off an internal timer will delay turn on of the high–side
MOSFET. When the PWM pull low, gate DRVH will go low
after the propagation delay (tpdDRVH). The time to turn off
the high side MOSFET is depending on the total gate charge
of the high−side MOSFET. A timer will be triggered once
the high side MOSFET is turn off to delay the turn on the
low−side MOSFET.
controller and the V
input of the driver. During power up
CCP
the input voltage to the controller is monitored. The PWM
outputs and the soft start circuit are disabled until the input
voltage exceeds the threshold voltage of the comparators.
Hysteresis is incorporated within the comparators.
The DRVON is held low until V
threshold during startup. If V
reaches the start
CCP
decreases below the stop
CCP
threshold, the output gate will be forced low unit input
voltage V rises above the startup threshold.
CCP
Over Current Latch
A programmable over current latch is incorporated within
the IC. The oscillator pin provides the reference voltage for
this pin. A resistor divider from the OSC pin generates the
ILIM voltage. The latch is set when the current information
Layout Guidelines
Layout is very important thing for design a DC−DC
on V
exceeds the programmed voltage plus a 1.3 V
converter. Bootstrap capacitor and V capacitor are most
droop
in
offset. DRVON is immediately set low. To recover the part
must be reset by the EN pin or by cycling V
critical items, it should be placed as close as to the controller
IC. Another item is using a GND plane. Ground plane can
provide a good return path for gate drives for reducing the
ground noise. Therefore GND pin should be directly
connected to the ground plane and close to the low−side
MOSFET source pin. Also, the gate drive trace should be
considered. The gate drives has a high di/dt when switching,
therefore a minimized gate drives trace can reduce the di/dv,
raise and fall time for reduce the switching loss.
.
CC
UVLO Monitor
If the output voltage falls greater than 300 mV below the
DAC voltage for more than 5 ms the UVLO comparator will
trip sending the VR_RDY signal low.
Over Voltage Protection
The output voltage is monitored at the input of the
differential amplifier. During normal operation, if the output
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26
NCP5395
1.25 V
1.25 V
ENABLE
VID Captured
VID Valid
VID Not Valid
1 ms − 20 ms
Rise Time
5 V
12 V
12 V
1 ms − 20 ms
Rise Time
5 and 12 Good
VR11 Soft−start
Mode Latched
3.5 ms
Calibration Time
DRVON
Soft−start
Slew Rate
DAC Setting
1.10 V
Soft−start
Slew Rate
500 ms
VOUT/DAC
VR_RDY
500 ms
Figure 6. VR11.1 Start Up Timing Diagram
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NCP5395
ENABLE
5 V
VID7/AMD
1 ms − 20 ms
Rise Time
5 V
1 ms − 20 ms
Rise Time
V
CC
12 V
9.5 V
V
CCP
V
CC
and V
CCP
AMD/Legacy Soft Start
Mode Latched
UVLO
3.5 ms
Calibration Time
DRVON
DAC Setting
SS Slew
Rate
VOUT/DAC
VR_RDY
500 ms
Figure 7. AMD / Legacy Start Up Timing Diagram
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NCP5395
PACKAGE DIMENSIONS
QFN48
CASE 485K−02
ISSUE C
NOTES:
D
A
B
1. DIMENSIONS AND TOLERANCING PER ASME
Y14.5M, 1994.
2. DIMENSIONS IN MILLIMETERS.
3. DIMENSION b APPLIES TO THE PLATED
TERMINAL AND IS MEASURED ABETWEEN
0.25 AND 0.30 MM FROM TERMINAL
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
PIN 1
LOCATION
E
MILLIMETERS
DIM MIN
0.800 0.900 1.000
A1 0.000 0.025 0.050
NOM MAX
A
2 X
A3
b
0.200 REF
0.180 0.250 0.300
7.000 BSC
0.15
C
2 X
D
0.15
C
E
TOP VIEW
(A3)
0.10
C
C
A
0.08
48 X
SIDE VIEW
D2
A1
SEATING
PLANE
C
EXPOSED PAD
L
K
48 X
13
24
4 X
12
25
E2
1
36
48
37
48 X NOTE 3
b
e
0.10 C A B
0.05
C
BOTTOM VIEW
The products described herein (NCP5395), may be covered by one or more of the following U.S. patents; US07057381.There may be other patents pending.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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NCP5395/D
相关型号：
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