NE80546QG0882MM [ROCHESTER]
64-BIT, 3200 MHz, MICROPROCESSOR, CPGA604, FLIP CHIP, MICRO PGA-604;
| 型号： | NE80546QG0882MM |
| 厂家： | 
Rochester Electronics |
| 描述： | 64-BIT, 3200 MHz, MICROPROCESSOR, CPGA604, FLIP CHIP, MICRO PGA-604 时钟 外围集成电路 |
| 文件： | 总107页 (文件大小：5501K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
64-bit Intel Xeon™ Processor
with 2 MB L2 Cache
Datasheet
September 2005
Document Number: 306249-002
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY
ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN
INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS
ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES
RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER
INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
®
The 64-bit Intel Xeon™ Processor with 2 MB L2 Cache may contain design defects or errors known as errata which may cause the product to
deviate from published specifications. Current characterized errata are available on request.
MPEG is an international standard for video compression/decompression promoted by ISO. Implementations of MPEG CODECs, or MPEG enabled
platforms may require licenses from various entities, including Intel Corporation.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling
1-800-548-4725 or by visiting Intel's website at http://www.intel.com.
Intel, Pentium, Intel Xeon, SpeedStep, Intel NetBurst, Intel Extended Memory 64 Technology, and Itanium are trademarks or registered trademarks of
Intel Corporation or its subsidiaries in the United States and other countries.
Intel® Extended Memory 64 Technology (Intel® EM64T) requires a computer system with a processor, chipset, BIOS, OS, device drivers and
applications enabled for Intel EM64T. Processor will not operate (including 32-bit operation) without an Intel EM64T-enabled BIOS. Performance will
vary depending on your hardware and software configurations. Intel EM64T-enabled OS, BIOS, device drivers and applications may not be available.
Check with your vendor for more information.
*Other names and brands may be claimed as the property of others.
Copyright © 2005, Intel Corporation
2
Datasheet
Contents
1
Introduction.......................................................................................................................11
1.1
1.2
1.3
Terminology.........................................................................................................12
References..........................................................................................................14
State of Data .......................................................................................................15
2
Electrical Specifications...................................................................................................17
2.1
2.2
Power and Ground Pins ......................................................................................17
Decoupling Guidelines ........................................................................................17
2.2.1 VCC Decoupling.....................................................................................17
2.2.2 VTT Decoupling......................................................................................17
2.2.3 Front Side Bus AGTL+ Decoupling ........................................................18
Front Side Bus Clock (BCLK[1:0]) and Processor Clocking................................18
2.3.1 Front Side Bus Frequency Select Signals (BSEL[1:0]) ..........................18
2.3.2 Phase Lock Loop (PLL) and Filter..........................................................19
Voltage Identification (VID)..................................................................................20
Reserved Or Unused Pins...................................................................................22
Front Side Bus Signal Groups.............................................................................22
GTL+ Asynchronous and AGTL+ Asynchronous Signals ...................................24
Test Access Port (TAP) Connection....................................................................24
Mixing Processors...............................................................................................25
Absolute Maximum and Minimum Ratings..........................................................25
Processor DC Specifications...............................................................................26
2.11.1 Flexible Motherboard Guidelines (FMB).................................................26
2.11.2 VCC Overshoot Specification.................................................................31
2.11.3 Die Voltage Validation............................................................................32
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
2.11
3
Mechanical Specifications................................................................................................35
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
Package Mechanical Drawings ...........................................................................36
Processor Component Keepout Zones ...............................................................39
Package Loading Specifications .........................................................................39
Package Handling Guidelines .............................................................................40
Package Insertion Specifications ........................................................................40
Processor Mass Specifications ...........................................................................40
Processor Materials.............................................................................................40
Processor Markings.............................................................................................41
Processor Pin-Out Coordinates...........................................................................42
4
5
Signal Definitions..............................................................................................................45
4.1 Signal Definitions.................................................................................................45
Pin Listing.........................................................................................................................55
®
5.1
64-bit Intel Xeon™ Processor with 2 MB L2 Cache Pin Assignments ..............55
5.1.1 Pin Listing by Pin Name .........................................................................55
5.1.2 Pin Listing by Pin Number......................................................................63
6
Thermal Specifications....................................................................................................71
6.1
Package Thermal Specifications.........................................................................71
6.1.1 Thermal Specifications...........................................................................71
Datasheet
3
6.1.2 Thermal Metrology .................................................................................78
Processor Thermal Features...............................................................................79
6.2.1 Thermal Monitor .....................................................................................79
6.2.2 Thermal Monitor 2 ..................................................................................79
6.2.3 On-Demand Mode..................................................................................81
6.2.4 PROCHOT# Signal Pin ..........................................................................81
6.2.5 FORCEPR# Signal Pin ..........................................................................81
6.2.6 THERMTRIP# Signal Pin .......................................................................82
6.2.7 TCONTROL and Fan Speed Reduction.................................................82
6.2.8 Thermal Diode........................................................................................82
6.2
7
Features...........................................................................................................................85
7.1
7.2
Power-On Configuration Options ........................................................................85
Clock Control and Low Power States..................................................................85
7.2.1 Normal State ..........................................................................................86
7.2.2 HALT or Enhanced HALT Power Down States......................................86
7.2.3 Stop Grant State ....................................................................................87
7.2.4 Enhanced HALT Snoop or HALT Snoop State, Stop Grant
Snoop State ...........................................................................................88
7.2.5 Sleep State.............................................................................................88
Demand Based Switching (DBS) with Enhanced Intel
7.3
®
SpeedStep Technology.....................................................................................89
8
Boxed Processor Specifications.......................................................................................91
8.1
8.2
Introduction .........................................................................................................91
Mechanical Specifications...................................................................................93
8.2.1 Boxed Processor Heatsink Dimensions (CEK) ......................................93
8.2.2 Boxed Processor Heatsink Weight.......................................................101
8.2.3 Boxed Processor Retention Mechanism and
Heatsink Support (CEK).......................................................................101
Electrical Requirements ....................................................................................101
8.3.1 Fan Power Supply (Active CEK) ..........................................................101
8.3.2 Boxed Processor Cooling Requirements .............................................103
Boxed Processor Contents ...............................................................................104
8.3
8.4
9
Debug Tools Specifications............................................................................................105
9.1
9.2
Debug Port System Requirements....................................................................105
Target System Implementation .........................................................................105
9.2.1 System Implementation........................................................................105
Logic Analyzer Interface (LAI)..........................................................................105
9.3.1 Mechanical Considerations ..................................................................106
9.3.2 Electrical Considerations......................................................................106
9.3
Figures
2-1
2-2
Phase Lock Loop (PLL) Filter Requirements ......................................................19
64-bit Intel Xeon™ Processor and 64-bit Intel Xeon™
®
®
MV 3.20 GHz Processor Load Current Vs. Time ................................................29
®
2-3
2-4
2-5
3-1
64-bit Intel Xeon™ LV 3 GHz Processor Load Current Vs. Time .....................29
VCC Static and Transient Tolerance...................................................................31
VCC Overshoot Example Waveform...................................................................32
Processor Package Assembly Sketch ................................................................35
4
Datasheet
3-2
3-3
3-4
3-5
3-6
3-7
6-1
Processor Package Drawing (Sheet 1 of 2) ........................................................37
Processor Package Drawing (Sheet 2 of 2) ........................................................38
Processor Top-Side Markings (Example)............................................................41
Processor Bottom-Side Markings (Example) ......................................................41
Processor Pin-out Coordinates, Top View ..........................................................42
Processor Pin-out Coordinates, Bottom View .....................................................43
®
64-bit Intel Xeon™ Processor with 2 MB L2 Cache Thermal Profiles
A and B (PRB = 1)...............................................................................................73
®
6-2
64-bit Intel Xeon™ MV 3.20 GHz Processor Thermal Profiles
A and B (PRB = 1)...............................................................................................75
®
6-3
6-4
6-5
7-1
8-1
8-2
8-3
8-4
64-bit Intel Xeon™ LV Processor Thermal Profiles A and B (PRB = 0)............77
Case Temperature (TCASE) Measurement Location .........................................78
Demand Based Switching Frequency and Voltage Ordering..............................80
Stop Clock State Machine...................................................................................87
1U Passive CEK Heatsink...................................................................................91
2U Passive CEK Heatsink...................................................................................92
Active CEK Heatsink (Representation Only).......................................................92
®
Passive 64-bit Intel Xeon™ Processor with 2 MB L2 Cache Thermal
Solution (2U and Larger).....................................................................................93
Top-Side Board Keepout Zones (Part 1).............................................................94
Top-Side Board Keepout Zones (Part 2).............................................................95
Bottom-Side Board Keepout Zones.....................................................................96
Board Mounting Hole Keepout Zones .................................................................97
Volumetric Height Keep-Ins.................................................................................98
4-Pin Fan Cable Connector (For Active CEK Heatsink)......................................99
4-Pin Base Board Fan Header (For Active CEK Heatsink) ...............................100
Fan Cable Connector Pin Out for 4-Pin Active CEK Thermal Solution .............102
8-5
8-6
8-7
8-8
8-9
8-10
8-11
8-12
Tables
®
1-1
Features of the 64-bit Intel Xeon™ Processor with 2 MB L2 Cache.................12
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
Core Frequency to Front Side Bus Multiplier Configuration................................18
BSEL[1:0] Frequency Table ................................................................................19
Voltage Identification Definition 2, 3....................................................................21
Front Side Bus Signal Groups.............................................................................23
Signal Description Table .....................................................................................24
Signal Reference Voltages..................................................................................24
Absolute Maximum and Minimum Ratings..........................................................25
Voltage and Current Specifications.....................................................................27
VCC Static and Transient Tolerance...................................................................30
VCC Overshoot Specifications............................................................................31
BSEL[1:0] and VID[5:0] Signal Group DC Specifications....................................32
AGTL+ Signal Group DC Specifications .............................................................33
PWRGOOD Input and TAP Signal Group DC Specifications..............................33
GTL+ Asynchronous and AGTL+ Asynchronous Signal Group DC
2-9
2-10
2-11
2-12
2-13
2-14
Specifications ......................................................................................................34
VIDPWRGD DC Specifications ...........................................................................34
Processor Loading Specifications .......................................................................39
Package Handling Guidelines .............................................................................40
Processor Materials.............................................................................................40
Signal Definitions.................................................................................................45
Pin Listing by Pin Name ......................................................................................55
2-15
3-1
3-2
3-3
4-1
5-1
Datasheet
5
5-2
6-1
Pin Listing by Pin Number...................................................................................63
64-bit Intel Xeon™ Processor with 2 MB L2 Cache
®
Thermal Specifications........................................................................................72
®
6-2
6-3
64-bit Intel Xeon™ Processor with 2 MB L2 Cache
Thermal Profile A
(PRB = 1) ............................................................................................................74
®
64-bit Intel Xeon™ Processor with 2 MB L2 Cache
Thermal Profile B
(PRB = 1) ............................................................................................................74
®
6-4
6-5
64-bit Intel Xeon™ MV 3.20 GHz Processor Thermal Specifications ...............75
®
64-bit Intel Xeon™ MV 3.20 GHz Processor Thermal Profile A
(PRB = 1) ............................................................................................................76
®
6-6
64-bit Intel Xeon™ MV 3.20 GHz Processor Thermal Profile B
(PRB = 1) ............................................................................................................76
®
6-7
6-8
6-9
6-10
7-1
8-1
64-bit Intel Xeon™ LV 3 GHz Processor Thermal Specifications .....................77
®
64-bit Intel Xeon™ LV 3 GHz Processor Thermal Profile (PRB = 0) ................78
Thermal Diode Parameters .................................................................................82
Thermal Diode Interface......................................................................................83
Power-On Configuration Option Pins..................................................................85
PWM Fan Frequency Specifications for 4-Pin Active CEK
Thermal Solution...............................................................................................102
Fan Specifications for 4-pin Active CEK Thermal Solution ...............................102
Fan Cable Connector Pin Out for 4-Pin Active CEK Thermal Solution.............102
Fan Cable Connector Supplier and Part Number .............................................103
8-2
8-3
8-4
6
Datasheet
Revision History
Version
Number
Description
Date
-001
-002
Initial release of the document.
February 2005
Updated to include 2.8 GHz, 3.8 GHz, and power-optimized versions.
September 2005
Datasheet
7
8
Datasheet
64-bit Intel® Xeon™ Processor with 2 MB L2
Cache
Product Features
Available at 2.80, 3, 3.20, 3.40, 3.60, and 3.80 GHz Execute Disable Bit
Available in power-optimized configurations with
LV 3 GHz (55 W TDP) and MV 3.2 GHz (90 W
TDP) processors
90 nm process technology
Dual processing server/workstation support
Includes 16-KB Level 1 data cache
®
®
Intel Extended Memory 64 Technology (Intel
EM64T)
2 MB Advanced Transfer Cache (On-die, full speed
Level 2 (L2) Cache) with 8-way associativity and
Error Correcting Code (ECC)
Binary compatible with applications running on
previous members of Intel’s IA-32 microprocessor
line
Enables system support of up to 64 GB of physical
memory
®
Intel NetBurst microarchitecture
144 Streaming SIMD Extensions 2 (SSE2)
instructions
Hyper-Threading Technology
Hardware support for multithreaded applications
Fast 800 MHz system bus
13 Streaming SIMD Extensions 3 (SSE3)
instructions
Enhanced floating-point and multimedia unit for
enhanced video, audio, encryption, and 3D
performance
Rapid Execution Engine: Arithmetic Logic Units
(ALUs) run at twice the processor core frequency
Hyper Pipelined Technology
Advanced Dynamic Execution
Very deep out-of-order execution
Enhanced branch prediction
System Management mode
Thermal Monitor
Machine Check Architecture (MCA)
Demand Based Switching (DBS) with Enhanced
®
Intel SpeedStep Technology
®
The 64-bit Intel Xeon™ processor with 2 MB L2 cache is designed for high-performance dual-processor
workstation and server applications. Based on the Intel NetBurst microarchitecture and the Hyper-Threading
Technology, it is binary compatible with previous Intel Architecture (IA-32) processors. The 64-bit Intel Xeon
processor with 2 MB L2 cache is scalable to two processors in a multiprocessor system providing exceptional
performance for applications running on advanced operating systems such as Windows XP*, Windows Server*
2003, Linux*, and UNIX*.
The 64-bit Intel Xeon processor with 2 MB L2 cache delivers compute power at
unparalleled value and flexibility for powerful workstations, internet infrastructure,
and departmental server applications. The Intel NetBurst micro-architecture and
Hyper-Threading Technology deliver outstanding performance and headroom for
peak internet server workloads, resulting in faster response times, support for more
users, and improved scalability.
Datasheet
9
10
Datasheet
1 Introduction
®
This document details specifications and features of the 64-bit Intel Xeon™ processor with 2 MB
L2 cache, including new processors in LV (55 W TDP) and MV (90 W TDP) configurations. In this
document, “processor” and “64-bit Intel Xeon processor with 2 MB L2 cache” are generic terms
for all of these processors. Details specific to a particular processor will be specifically called out in
the applicable text, table or figure.
®
®
The 64-bit Intel Xeon™ processor with 2 MB L2 cache, 64-bit Intel Xeon™ LV 3 GHz
®
processor and 64-bit Intel Xeon™ MV 3.20 GHz processor are server / workstation processors
based on improvements to the Intel NetBurst microarchitecture. They maintain the tradition of
compatibility with IA-32 software and include features found in the Intel Xeon processor such as
Hyper Pipelined Technology, a Rapid Execution Engine, and an Execution Trace Cache. Hyper
Pipelined Technology includes a multi-stage pipeline, allowing the processor to reach much higher
core frequencies. The 800 MHz system bus is a quad-pumped bus running off a 200 MHz system
clock making 6.4 GB per second data transfer rates possible. The Execution Trace Cache is a level
1 cache that stores decoded micro-operations, which removes the decoder from the main execution
path, thereby increasing performance.
In addition, enhanced thermal and power management capabilities are implemented including
Thermal Monitor and Thermal Monitor 2. These capabilities are targeted for dual processor (DP)
servers and workstations in data center and office environments. Thermal Monitor and Thermal
Monitor 2 provide efficient and effective cooling in high temperature situations. Demand Based
Switching (DBS) with Enhanced Intel SpeedStep allows trade-offs to be made between
performance and power consumption. This may lower average power consumption (in conjunction
with OS support). [Note: Not all processors are capable of supporting Thermal Monitor 2 or
Enhanced Intel SpeedStep technology. More details on which processor frequencies support this
®
feature are provided in the 64-bit Intel Xeon™ Processor with 800 MHz System Bus (1 MB and 2
MB L2 Cache Versions) Specification Update.
The 64-bit Intel Xeon processor with 2 MB L2 cache supports Hyper-Threading Technology. This
feature allows a single, physical processor to function as two logical processors. While some
execution resources such as caches, execution units, and buses are shared, each logical processor
has its own architecture state with its own set of general-purpose registers, control registers to
provide increased system responsiveness in multitasking environments, and headroom for next
generation multithreaded applications. More information on Hyper-Threading Technology can be
found at http://www.intel.com/technology/hyperthread.
The 64-bit Intel Xeon processor with 2 MB L2 cache also includes the Execute Disable Bit
®
®
capability previously available in Intel Itanium processors. This feature, when combined with a
supported operating system, allows memory to be marked as executable or non-executable. If code
attempts to run in non-executable memory, the processor raises an error to the operating system.
This feature can prevent some classes of viruses or worms that exploit buffer overrun
®
vulnerabilities and can thus help improve the overall security of the system. See the Intel
Architecture Software Developer’s Manual for more detailed information.
Other features within the Intel NetBurst microarchitecture include Advanced Dynamic Execution,
Advanced Transfer Cache, enhanced floating point and multi-media unit, Streaming SIMD
Extensions 2 (SSE2) and Streaming SIMD Extensions 3 (SSE3). Advanced Dynamic Execution
improves speculative execution and branch prediction internal to the processor. The Advanced
Transfer Cache is a 2 MB, on-die, level 2 (L2) cache with increased bandwidth. The floating point
and multi-media units include 128-bit wide registers and a separate register for data movement.
Streaming SIMD2 (SSE2) instructions provide highly efficient double-precision floating point,
Datasheet
11
Introduction
SIMD integer, and memory management operations. In addition, SSE3 instructions have been
added to further extend the capabilities of Intel processor technology. Other processor
enhancements include core frequency improvements and microarchitectural improvements.
64-bit Intel Xeon processors with 2 MB L2 cache supports Intel Extended Memory 64 Technology
(Intel EM64T) as an enhancement to Intel's IA-32 architecture. This enhancement allows the
processor to execute operating systems and applications written to take advantage of the 64-bit
extension technology. Further details on Intel Extended Memory 64 Technology and its
®
programming model can be found in the 64-bit Intel Extended Memory 64 Technology Software
Developer's Guide at http://developer.intel.com/technology/64bitextensions/.
64-bit Intel Xeon processors with 2 MB L2 cache are intended for high performance workstation
and server systems with up to two processors on one system bus. The 64-bit Intel Xeon MV 3.20
GHz processor is a mid-voltage processor intended for volumetrically constrained platforms. The
64-bit Intel Xeon LV 3 GHz processor is a low-voltage, low-power processor intended for
embedded and volumetrically constrained platforms. These processors are packaged in a 604-pin
Flip Chip Micro Pin Grid Array (FC-mPGA4) package and use a surface mount Zero Insertion
Force (ZIF) socket (mPGA604).
®
Table 1-1. Features of the 64-bit Intel Xeon™ Processor with 2 MB L2 Cache
# of Supported
Symmetric
Agents
L2 Advanced
Transfer
Front Side
Bus
Frequency
Package
Cache
64-bit Intel® Xeon™ processor
with 2 MB L2 cache
64-bit Intel® Xeon™ MV 3.20
GHz processor
604-pin FC-
mPGA4
1 - 2
2 MB
800 MHz
64-bit Intel® Xeon™ LV 3 GHz
processor
64-bit Intel Xeon processor with 2 MB L2 cache-based platforms implement independent power
planes for each system bus agent. As a result, the processor core voltage (V ) and system bus
CC
termination voltage (V ) must connect to separate supplies. The processor core voltage utilizes
TT
power delivery guidelines denoted by VRM 10.1 and the associated load line (see Voltage
Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 10.1 Design
Guidelines for further details). Implementation details can be obtained by referring to the
applicable platform design guidelines. Cost-reduced power delivery systems may be possible for
mid-voltage (MV) and low-voltage (LV) processors.
The 64-bit Intel Xeon processor with 2 MB L2 cache uses a scalable system bus protocol referred
to as the “system bus” in this document. The system bus utilizes a split-transaction, deferred reply
protocol. The system bus uses Source-Synchronous Transfer (SST) of address and data to improve
performance. The processor transfers data four times per bus clock (4X data transfer rate, as in
AGP 4X). Along with the 4X data bus, the address bus can deliver addresses two times per bus
clock and is referred to as a ‘double-clocked’ or the 2X address bus. In addition, the Request Phase
completes in one clock cycle. Working together, the 4X data bus and 2X address bus provide a data
bus bandwidth of up to 6.4 GBytes/second (6400 MBytes/second). Finally, the system bus is also
used to deliver interrupts.
1.1
Terminology
A ‘#’ symbol after a signal name refers to an active low signal, indicating a signal is in the asserted
state when driven to a low level. For example, when RESET# is low, a reset has been requested.
Conversely, when NMI is high, a nonmaskable interrupt has occurred. In the case of signals where
12
Datasheet
Introduction
the name does not imply an active state but describes part of a binary sequence (such as address or
data), the ‘#’ symbol implies that the signal is inverted. For example, D[3:0] = ‘HLHL’ refers to a
hex ‘A’, and D[3:0]# = ‘LHLH’ also refers to a hex ‘A’ (H= High logic level, L= Low logic level).
“Front side bus” or “System bus” refers to the interface between the processor, system core logic
(a.k.a. the chipset components), and other bus agents. The system bus is a multiprocessing interface
to processors, memory, and I/O. For this document, “front side bus” or “system bus” are used as
generic terms for the “64-bit Intel Xeon processor with 2 MB L2 cache system bus”.
Commonly used terms are explained here for clarification:
• 64-bit Intel Xeon processor with 2 MB L2 cache — Intel 64-bit microprocessor intended for
dual processor servers and workstations. The 64-bit Intel Xeon processor with 2 MB L2 cache
is based on Intel’s 90 nanometer process and includes a larger 2 MB, on-die, level 2 (L2)
cache. The processor uses the mPGA604 socket. For this document, “processor” is used as the
generic term for the “64-bit Intel Xeon processor with 2 MB L2 cache”.
• 64-bit Intel Xeon MV 3.20 GHz processor — Mid-voltage (MV), low-power Intel 64-bit
microprocessor targeted for volumetrically constrained platforms. Unless otherwise noted,
“processor” and “64-bit Intel Xeon processor with 2 MB L2 cache” are used as generic terms
for the “64-bit Intel Xeon MV 3.20 GHz processor”.
• 64-bit Intel Xeon LV 3 GHz processor — Low-voltage (LV), low-power Intel 64-bit
microprocessor targeted for embedded and volumetrically constrained platforms. Unless
otherwise noted, “processor” and “64-bit Intel Xeon processor with 2 MB L2 cache” are used
as generic terms for the “64-bit Intel Xeon LV 3 GHz processor”.
• Central Agent — The central agent is the host bridge to the processor and is typically known
as the chipset.
• Demand Based Switching (DBS) with Enhanced Intel SpeedStep Technology — Demand
Based Switching with Enhanced Intel SpeedStep technology is the next generation
implementation of Geyserville technology which extends power management capabilities of
servers and workstations.
• Enterprise Voltage Regulator Down (EVRD) — DC-DC converter integrated onto the
system board that provide the correct voltage and current for the processor based on the logic
stat of the VID bits.
• Flip Chip Micro Pin Grid Array (FC-mPGA4) Package — The processor package is a Flip
Chip Micro Pin Grid Array (FC-mPGA4), consisting of a processor core mounted on a pinned
substrate with an integrated heat spreader (IHS). This package technology employs a 1.27 mm
[0.05 in.] pitch for the processor pins.
• Front Side Bus (FSB) — The electrical interface that connects the processor to the chipset.
Also referred to as the processor system bus or the system bus. All memory and I/O
transactions as well as interrupt messages pass between the processor and the chipset over the
FSB.
• Functional Operation — Refers to the normal operating conditions in which all processor
specifications, including DC, AC, system bus, signal quality, mechanical and thermal are
satisfied.
• Integrated Heat Spreader (IHS) — A component of the processor package used to enhance
the thermal performance of the package. Component thermal solutions interface with the
processor at the IHS surface.
• mPGA604 Socket — The 64-bit Intel Xeon processor with 2 MB L2 cache mates with the
baseboard through this surface mount, 604-pin, zero insertion force (ZIF) socket. See the
mPGA604 Socket Design Guidelines for details regarding this socket.
Datasheet
13
Introduction
• Platform Requirement Bit — Bit 18 of the processor’s IA32_FLEX_BRVID_SEL register is
the Platform Requirement Bit (PRB) that indicates that the processor has specific platform
requirements.
• Processor Core — The processor’s execution engine.
• Storage Conditions — Refers to a non-operational state. The processor may be installed in a
platform, in a tray, or loose. Processors may be sealed in packaging or exposed to free air.
Under these conditions, processor pins should not be connected to any supply voltages, have
any I/Os biased or receive any clocks.
• Symmetric Agent — A symmetric agent is a processor which shares the same I/O subsystem
and memory array, and runs the same operating system as another processor in a system.
Systems using symmetric agents are known as Symmetric Multiprocessor (SMP) systems. 64-
bit Intel Xeon processors with 2 MB L2 cache should only be used in SMP systems which
have two or fewer agents.
• Thermal Design Power — Processor/chipset thermal solution should be designed to this
target. It is the highest expected sustainable power while running known power-intensive real
applications. TDP is not the maximum power that the processor/chipset can dissipate.
• Voltage Regulator Module (VRM)— DC-DC converter built onto a module that interfaces
with an appropriate card edge socket that supplies the correct voltage and current to the
processor.
• V — The processor core power supply.
CC
• V — The processor ground.
SS
• V — The system bus termination voltage.
TT
1.2
References
Material and concepts available in the following documents may be beneficial when reading this
document:
Document
Intel Order Number
64-bit Intel® Xeon™ Processor with 800 MHz System Bus (1 MB and 2 MB L2
302402
Cache Versions) Specification Update
64-bit Intel® Xeon™ Processor with 2 MB L2 Cache Boundary Scan Descriptive
Language (BSDL) Model (V2.0) and Cell Descriptor File (V2.0)
http://developer.intel.com
http://developer.intel.com
64-bit Intel® Xeon™ Processor with 2 MB L2 Cache Cooling Solution Mechanical
Models
64-bit Intel® Xeon™ Processor with 2 MB L2 Cache Cooling Solution Thermal
Models
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64-bit Intel® Xeon™ Processor with 2 MB L2 Cache Mechanical Models
64-bit Intel® Xeon™ Processor with 2 MB L2 Cache Thermal Models
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http://developer.intel.com
64-bit Intel® Xeon™ Processor with 2 MB L2 Cache Thermal/Mechanical Design
Guidelines
298348
AP-485, Intel® Processor Identification and CPUID Instruction
241618
ATX12V Power Supply Design Guidelines
http://formfactors.org
Entry-Level Electronics-Bay Specifications: A Server System Infrastructure (SSI)
Specification for Entry Pedestal Servers and Workstations
http://www.ssiforum.org
14
Datasheet
Introduction
Document
Intel Order Number
EPS12V Power Supply Design Guide: A Server System Infrastructure (SSI)
Specification for Entry Chassis Power Supplies
http://www.ssiforum.org
248966
IA-32 Intel® Architecture Optimization Reference Manual
IA-32 Intel® Architecture Software Developer's Manual
•
•
•
•
Volume I: Basic Architecture
253665
253666
253667
253668
Volume 2A: Instruction Set Reference, A-M
Volume 2B: Instruction Set Reference, N-Z
Volume 3: System Programming Guide
Intel® Extended Memory 64 Technology Software Developer's Manual, Volume 1
Intel® Extended Memory 64 Technology Software Developer's Manual, Volume 2
300834
300835
ITP700 Debug Port Design Guide
mPGA604 Socket Design Guidelines
249679
254239
Thin Electronics Bay Specification (A Server System Infrastructure (SSI)
Specification for Rack Optimized Servers)
http://www.ssiforum.org
302732
Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down
(EVRD) 10.1 Design Guidelines
NOTE: Contact your Intel representative for the latest revision of documents without document numbers.
1.3
State of Data
The data contained within this document is subject to change. It is the most accurate information
available by the publication date of this document.
Datasheet
15
Introduction
16
Datasheet
2 Electrical Specifications
2.1
Power and Ground Pins
For clean on-chip power distribution, the processor has 181 VCC (power) and 185 VSS (ground)
inputs. All VCC pins must be connected to the processor power plane, while all VSS pins must be
connected to the system ground plane. The processor VCC pins must be supplied with the voltage
determined by the processor Voltage IDentification (VID) pins.
Eleven signals are denoted as VTT, which provide termination for the front side bus and power to
the I/O buffers. The platform must implement a separate supply for these pins, which meets the VTT
specifications outlined in Table 2-8.
2.2
Decoupling Guidelines
Due to its large number of transistors and high internal clock speeds, the 64-bit
Intel Xeon processor with 2 MB L2 cache is capable of generating large average current swings
between low and full power states. This may cause voltages on power planes to sag below their
minimum values if bulk decoupling is not adequate. Larger bulk storage (CBULK), such as
electrolytic or aluminum-polymer capacitors, supply current during longer lasting changes in
current demand by the component, such as coming out of an idle condition. Similarly, they act as a
storage well for current when entering an idle condition from a running condition. Care must be
taken in the baseboard design to ensure that the voltage provided to the processor remains within
the specifications listed in Table 2-8. Failure to do so can result in timing violations or reduced
lifetime of the component.
2.2.1
2.2.2
VCC Decoupling
Regulator solutions need to provide bulk capacitance with a low Effective Series Resistance (ESR)
and the baseboard designer must assure a low interconnect resistance from the voltage regulator
(VRD or VRM pins) to the mPGA604 socket. The power delivery solution must insure the voltage
and current specifications are met (defined in Table 2-8).
VTT Decoupling
Decoupling must be provided on the baseboard. Decoupling solutions must be sized to meet the
expected load. To insure optimal performance, various factors associated with the power delivery
solution must be considered including regulator type, power plane and trace sizing, and component
placement. A conservative decoupling solution would consist of a combination of low ESR bulk
capacitors and high frequency ceramic capacitors.
Datasheet
17
Electrical Specifications
2.2.3
Front Side Bus AGTL+ Decoupling
The 64-bit Intel Xeon processor with 2 MB L2 cache integrates signal termination on the die, as
well as part of the required high frequency decoupling capacitance on the processor package.
However, additional high frequency capacitance must be added to the baseboard to properly
decouple the return currents from the front side bus. Bulk decoupling must also be provided by the
baseboard for proper AGTL+ bus operation.
2.3
Front Side Bus Clock (BCLK[1:0]) and Processor
Clocking
BCLK[1:0] directly controls the front side bus interface speed as well as the core frequency of the
processor. As in previous processor generations, the 64-bit Intel Xeon processor with 2 MB L2
cache core frequency is a multiple of the BCLK[1:0] frequency. The processor bus ratio multiplier
is set during manufacturing. The Platform Requirement Bit (PRB) is set for all 64-bit Intel Xeon
processors with 2 MB L2 cache and 64-bit Intel Xeon MV processors with 2 MB L2 cache, which
means the default setting will be the minimum speed for the processor. Software must override this
setting to permit operation at the designated processor frequency. The PRB will NOT be set for 64-
bit Intel Xeon LV processors with 2 MB L2 cache. As a result, these processors will begin
operation at their default maximum speed. It is possible to override this setting using software,
permitting operation at a speed lower than the processors’ tested frequency.
The BCLK[1:0] inputs directly control the operating speed of the front side bus interface. The
processor core frequency is configured during reset by using values stored internally during
manufacturing. The stored value sets the highest bus fraction at which the particular processor can
operate. If lower speeds are desired, the appropriate ratio can be configured by setting bits [15:8] of
the IA32_FLEX_BRVID_SEL MSR.
Clock multiplying within the processor is provided by the internal phase locked loop (PLL), which
requires a constant frequency BCLK[1:0] input, with exceptions for spread spectrum clocking. The
64-bit Intel Xeon processor with 2 MB L2 cache uses differential clocks. Table 2-1 contains core
frequency to front side bus multipliers and their corresponding core frequencies.
Table 2-1. Core Frequency to Front Side Bus Multiplier Configuration
Core Frequency to Front Side Bus Multiplier
Core Frequency with 200 MHz Front Side Bus Clock
1/14
1/15
1/16
1/17
1/18
1/19
2.80 GHz
3 GHz
3.20 GHz
3.40 GHz
3.60 GHz
3.80 GHz
NOTE: Individual processors operate only at or below the frequency marked on the package.
2.3.1
Front Side Bus Frequency Select Signals (BSEL[1:0])
BSEL[1:0] are open-drain outputs, which must be pulled up to V , and are used to select the front
TT
side bus frequency. Please refer to Table 2-11 for DC specifications. Table 2-2 defines the possible
combinations of the signals and the frequency associated with each combination. The frequency is
18
Datasheet
Electrical Specifications
determined by the processor(s), chipset, and clock synthesizer. All front side bus agents must
operate at the same core and front side bus frequencies. Individual processors will only operate at
their specified front side bus clock frequency.
Table 2-2. BSEL[1:0] Frequency Table
BSEL1
BSEL0
Bus Clock Frequency
0
0
1
1
0
1
0
1
Reserved
Reserved
200 MHz
Reserved
2.3.2
Phase Lock Loop (PLL) and Filter
VCCA and VCCIOPLL are power sources required by the PLL clock generators on the processor. Since
these PLLs are analog in nature, they require quiet power supplies for minimum jitter. Jitter is
detrimental to the system: it degrades external I/O timings as well as internal core timings (i.e.,
maximum frequency). To prevent this degradation, these supplies must be low pass filtered from
VTT.
The AC low-pass requirements are as follows:
• < 0.2 dB gain in pass band
• < 0.5 dB attenuation in pass band < 1 Hz
• > 34 dB attenuation from 1 MHz to 66 MHz
• > 28 dB attenuation from 66 MHz to core frequency
The filter requirements are illustrated in Figure 2-1.
Figure 2-1. Phase Lock Loop (PLL) Filter Requirements
0.2 dB
0 dB
-0.5 dB
forbidden
zone
-28 dB
forbidden
zone
-34 dB
DC
passband
1 Hz
fpeak
1 MHz
66 MHz
fcore
high frequency
band
Datasheet
19
Electrical Specifications
NOTES:
1. Diagram not to scale.
2. No specifications for frequencies beyond fcore (core frequency).
3. fpeak, if existent, should be less than 0.05 MHz.
4. fcore represents the maximum core frequency supported by the platform.
2.4
Voltage Identification (VID)
The Voltage Identification (VID) specification for the 64-bit Intel Xeon processor with 2 MB L2
cache is defined by the Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down
(EVRD) 10.1 Design Guidelines. The voltage set by the VID signals is the maximum voltage
allowed by the processor (please see Section 2.11.2 for V overshoot specifications). VID signals
CC
are open drain outputs, which must be pulled up to V . Please refer to Table 2-11 for the DC
TT
specifications for these signals. A minimum voltage is provided in Table 2-8 and changes with
frequency. This allows processors running at a higher frequency to have a relaxed minimum
voltage specification. The specifications have been set such that one voltage regulator can operate
with all supported frequencies.
Individual processor VID values may be calibrated during manufacturing such that two devices at
the same core speed may have different default VID settings. This is reflected by the VID range
®
values provided in Table 2-8. Refer to the 64-bit Intel Xeon™ Processor with 800 MHz System
Bus (1 MB and 2 MB L2 Cache Versions) Specification Update for further details on specific valid
core frequency and VID values of the processor.
The processor uses six voltage identification signals, VID[5:0], to support automatic selection of
power supply voltages. Table 2-3 specifies the voltage level corresponding to the state of VID[5:0].
A ‘1’ in this table refers to a high voltage level and a ‘0’ refers to a low voltage level. If the
processor socket is empty (VID[5:0] = x11111), or the voltage regulation circuit cannot supply the
voltage that is requested, it must disable itself. See the Voltage Regulator Module (VRM) and
Enterprise Voltage Regulator-Down (EVRD) 10.1 Design Guidelines for further details.
The 64-bit Intel Xeon processor with 2 MB L2 cache provides the ability to operate while
transitioning to an adjacent VID and its associated processor core voltage (V ). This will
CC
represent a DC shift in the load line. It should be noted that a low-to-high or high-to-low voltage
state change may result in as many VID transitions as necessary to reach the target core voltage.
Transitions above the specified VID are not permitted. Table 2-8 includes VID step sizes and DC
shift ranges. Minimum and maximum voltages must be maintained as shown in Table 2-9 and
Figure 2-4.
The VRM or VRD used must be capable of regulating its output to the value defined by the new
VID. DC specifications for dynamic VID transitions are included in Table 2-8 and Table 2-9.
Please refer to the Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down
(EVRD) 10.1 Design Guidelines for further details.
Power source characteristics must be guaranteed to be stable whenever the supply to the voltage
regulator is stable.
20
Datasheet
Electrical Specifications
2, 3
Table 2-3. Voltage Identification Definition
VID5
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
VID4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
VID3
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
VID2
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
VID1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
VID0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
VCC_MAX
VID5
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
VID4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
VID3
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
VID2
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
VID1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
VID0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
VCC_MAX
1.2125
1.2250
1.2375
1.2500
1.2625
1.2750
1.2875
1.3000
1.3125
1.3250
1.3375
1.3500
1.3625
1.3750
1.3875
1.4000
1.4125
1.4250
1.4375
1.4500
1.4625
1.4750
1.4875
1.5000
1.5125
1.5250
1.5375
1.5500
1.5625
1.5750
1.5875
1.6000
0.8375
0.8500
0.8625
0.8750
0.8875
0.9000
0.9125
0.9250
0.9375
0.9500
0.9625
0.9750
0.9875
1.0000
1.0125
1.0250
1.0375
1.0500
1.0625
1.0750
1.0875
OFF1
OFF1
1.1000
1.1125
1.1250
1.1375
1.1500
1.1625
1.1750
1.1875
1.2000
NOTES:
1. When this VID pattern is observed, the voltage regulator output should be disabled.
2. Shading denotes the expected default VID range during normal operation for the 64-bit Intel Xeon processor with 2 MB L2
cache [1.2875 V -1.3875 V], 64-bit Intel Xeon MV 3.20 GHz processor [1.2125 V - 1.3875 V] and 64-bit Intel Xeon LV 3 GHz
processor [1.0500 V - 1.2000 V]. Please note this is subject to change.
3. Shaded areas do not represent the entire range of VIDs that may be driven by the processor. Events causing dynamic VID
transitions (see Section 2.4) may result in a more broad range of VID values.
Datasheet
21
Electrical Specifications
2.5
Reserved Or Unused Pins
All Reserved pins must remain unconnected. Connection of these pins to V , V , V , or to any
CC
TT SS
other signal (including each other) can result in component malfunction or incompatibility with
future processors. See Section 5 for a pin listing of the processor and the location of all Reserved
pins.
For reliable operation, always connect unused inputs or bidirectional signals to an appropriate
signal level. In a system level design, on-die termination has been included by the processor to
allow end agents to be terminated within the processor silicon for most signals. In this context, end
agent refers to the bus agent that resides on either end of the daisy-chained front side bus interface
while a middle agent is any bus agent in between the two end agents. For end agents, most unused
AGTL+ inputs should be left as no connects as AGTL+ termination is provided on the processor
silicon. However, see Table 2-5 for details on AGTL+ signals that do not include on-die
termination. For middle agents, the on-die termination must be disabled, so the platform must
ensure that unused AGTL+ input signals which do not connect to end agents are connected to V
TT
via a pull-up resistor. Unused active high inputs, should be connected through a resistor to ground
(V ). Unused outputs can be left unconnected, however this may interfere with some TAP
SS
functions, complicate debug probing, and prevent boundary scan testing. A resistor must be used
when tying bidirectional signals to power or ground. When tying any signal to power or ground, a
resistor will also allow for system testability. Resistor values should be within ± 20% of the
impedance of the baseboard trace for front side bus signals. For unused AGTL+ input or I/O
signals, use pull-up resistors of the same value as the on-die termination resistors (R ).
TT
TAP, Asynchronous GTL+ inputs, and Asynchronous GTL+ outputs do not include on-die
termination. Inputs and utilized outputs must be terminated on the baseboard. Unused outputs may
be terminated on the baseboard or left unconnected. Note that leaving unused outputs unterminated
may interfere with some TAP functions, complicate debug probing, and prevent boundary scan
testing. Signal termination for these signal types is discussed in the ITP700 Debug Port Design
Guide (See Section 1.2).
All TESTHI[6:0] pins should be individually connected to V via a pull-up resistor which
TT
matches the nominal trace impedance. TESTHI[3:0] and TESTHI[6:5] may be tied together and
pulled up to V with a single resistor if desired. However, utilization of boundary scan test will
TT
not be functional if these pins are connected together. TESTHI4 must always be pulled up
independently from the other TESTHI pins. For optimum noise margin, all pull-up resistor values
used for TESTHI[6:0] pins should have a resistance value within ± 20 % of the impedance of the
board transmission line traces. For example, if the nominal trace impedance is 50 Ω, then a value
between 40 Ωand 60 Ωshould be used.
N/C (no connect) pins of the processor are not utilized by the processor. There is no connection
from the pin to the die. These pins may perform functions in future processors intended for
platforms using the 64-bit Intel Xeon processor with 2 MB L2 cache.
2.6
Front Side Bus Signal Groups
The front side bus signals have been combined into groups by buffer type. AGTL+ input signals
have differential input buffers, which use GTLREF as a reference level. In this document, the term
“AGTL+ Input” refers to the AGTL+ input group as well as the AGTL+ I/O group when receiving.
Similarly, “AGTL+ Output” refers to the AGTL+ output group as well as the AGTL+ I/O group
when driving. AGTL+ asynchronous outputs can become active anytime and include an active
pMOS pull-up transistor to assist during the first clock of a low-to-high voltage transition.
22
Datasheet
Electrical Specifications
With the implementation of a source synchronous data bus comes the need to specify two sets of
timing parameters. One set is for common clock signals whose timings are specified with respect to
rising edge of BCLK0 (ADS#, HIT#, HITM#, etc.) and the second set is for the source
synchronous signals which are relative to their respective strobe lines (data and address) as well as
rising edge of BCLK0. Asynchronous signals are still present (A20M#, IGNNE#, etc.) and can
become active at any time during the clock cycle. Table 2-4 identifies which signals are common
clock, source synchronous and asynchronous.
Table 2-4. Front Side Bus Signal Groups
Signal Group
Type
Signals1
AGTL+ Common Clock Input
Synchronous to BCLK[1:0] BPRI#, BR[3:1]#2,3, DEFER#, RESET#,
RS[2:0]#, RSP#, TRDY#
AGTL+ Common Clock I/O
Synchronous to BCLK[1:0] ADS#, AP[1:0]#, BINIT#4, BNR#4, BPM[5:0]#,
BR0#2,3, DBSY#, DP[3:0]#, DRDY#, HIT#4,
HITM#4, LOCK#, MCERR#4
AGTL+ Source Synchronous I/O Synchronous to assoc.
strobe
Signals
Associated Strobe
REQ[4:0]#,A[16:3]#3 ADSTB0#
A[35:17]#3
ADSTB1#
D[15:0]#, DBI0#
D[31:16]#, DBI1#
D[47:32]#, DBI2#
D[63:48]#, DBI3#
DSTBP0#, DSTBN0#
DSTBP1#, DSTBN1#
DSTBP2#, DSTBN2#
DSTBP3#, DSTBN3#
AGTL+ Strobe I/O
Synchronous to BCLK[1:0] ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]#
AGTL Asynchronous Output
GTL+ Asynchronous Input
Asynchronous
Asynchronous
FERR#/PBE#, IERR#, PROCHOT#
A20M#, FORCEPR#, IGNNE#, INIT#3, LINT0/
INTR, LINT1/NMI, SMI#3, SLP#, STPCLK#
GTL+ Asynchronous Output
Front Side Bus Clock
TAP Input
Asynchronous
Clock
THERMTRIP#
BCLK1, BCLK0
tck, tdi, tms, trst#
TDO
Synchronous to TCK
Synchronous to TCK
Power/Other
TAP Output
Power/Other
BOOT_SELECT, BSEL[1:0], COMP[1:0],
GTLREF[3:0], ODTEN, OPTIMIZED/
COMPAT#, PWRGOOD, Reserved,
SKTOCC#, SLEW_CTRL, SMB_PRT,
TEST_BUS, TESTHI[6:0], THERMDA,
THERMDC, VCC, VCCA, VCCIOPLL, VCCPLL
VCCSENSE, VID[5:0], VSS, VSSA
VSSSENSE, VTT, VIDPWRGD, VTTEN
,
,
NOTES:
1. Refer to Section 4 for signal descriptions.
2. The 64-bit Intel® Xeon™ processor with 2 MB L2 cache only uses BR0# and BR1#. BR2# and BR3# must be
terminated to VTT. For additional details regarding the BR[3:0]# signals, see Section 4 and Section 7.1.
3. The value of these pins during the active-to-inactive edge of RESET# defines the processor configuration
options. See Section 7.1 for details.
4. These signals may be driven simultaneously by multiple agents (wired-OR).
Table 2-5 outlines the signals which include on-die termination (R ) and lists signals which
TT
include additional on-die resistance (R ). Table 2-6 provides signal reference voltages.
L
Datasheet
23
Electrical Specifications
Table 2-5. Signal Description Table
Signals with RTT
A[35:3]#, ADS#, ADSTB[1:0]#, AP[1:0]#, BINIT#, BNR#, BOOT_SELECT2, BPRI#, D[63:0]#, DBI[3:0]#,
DBSY#, DEFER#, DP[3:0]#, DRDY#, DSTBN[3:0]#, DSTBP[3:0]#, FORCEPR#, HIT#, HITM#, LOCK#,
MCERR#, OPTIMIZED/COMPAT#2, REQ[4:0]#, RS[2:0]#, RSP#, SLEW_CTRL, TEST_BUS, TRDY#
Signals with RL
BINIT#, BNR#, HIT#, HITM#, MCERR#
NOTES:
1. Signals that do not have RTT, nor are actively driven to their high voltage level.
2. The termination for these signals is not RTT. The OPTIMIZED/COMPAT# and BOOT_SELECT pins have a
500 - 5000 Ω pull-up to VTT
.
Table 2-6. Signal Reference Voltages
GTLREF
0.5 * VTT
A20M#, A[35:3]#, ADS#, ADSTB[1:0]#, AP[1:0]#,
BOOT_SELECT, OPTIMIZED/COMPAT#, PWRGOOD1,
TCK1, TDI1, TMS1, TRST#1, VIDPWRGD
BINIT#, BNR#, BPM[5:0]#, BPRI#, BR[3:0]#,
D[63:0]#, DBI[3:0]#, DBSY#, DEFER#, DP[3:0]#,
DRDY#, DSTBN[3:0]#, DSTBP[3:0]#, FORCEPR#,
HIT#, HITM#, IGNNE#, INIT#, LINT0/INTR, LINT1/
NMI, LOCK#, MCERR#, ODTEN, RESET#,
REQ[4:0]#, RS[2:0]#, RSP#, SLEW_CTRL, SLP#,
SMI#, STPCLK#, TRDY#
NOTES:
1. These signals also have hysteresis added to the reference voltage. See Table 2-13 for more information.
2.7
GTL+ Asynchronous and AGTL+ Asynchronous
Signals
The 64-bit Intel Xeon processor with 2 MB L2 cache does not use CMOS voltage levels on any
signals that connect to the processor silicon. As a result, input signals such as A20M#,
FORCEPR#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, SMI#, SLP#, and STPCLK# utilize
GTL input buffers. Legacy output THERMTRIP# utilizes a GTL+ output buffers. All of these
Asynchronous GTL+ signals follow the same DC requirements as GTL+ signals, however the
outputs are not driven high (during the logical 0-to-1 transition) by the processor. FERR#/PBE#,
IERR#, and IGNNE# have now been defined as AGTL+ asynchrnous signals as they include an
active p-MOS device. GTL+ asynchronous and AGTL+ asynchronous signals do not have setup or
hold time specifications in relation to BCLK[1:0]. However, all of the GTL+ asynchronous and
AGTL+ asynchronous signals are required to be asserted/deasserted for at least six BCLKs in order
for the processor to recognize them. See Table 2-14 for the DC specifications for the asynchronous
GTL+ signal groups.
2.8
Test Access Port (TAP) Connection
Due to the voltage levels supported by other components in the Test Access Port (TAP) logic, it is
recommended that the processor(s) be first in the TAP chain and followed by any other components
within the system. A translation buffer should be used to connect to the rest of the chain unless one
24
Datasheet
Electrical Specifications
of the other components is capable of accepting an input of the appropriate voltage. Similar
considerations must be made for TCK, TMS, and TRST#. Two copies of each signal may be
required with each driving a different voltage level.
2.9
Mixing Processors
Intel only supports and validates dual processor configurations in which both processors operate
with the same front side bus frequency, core frequency, VID range, and have the same internal
cache sizes. Mixing components operating at different internal clock frequencies is not supported
and will not be validated by Intel [Note: Processors within a system must operate at the same
frequency per bits [15:8] of the IA32_FLEX_BRVID_SEL MSR; however this does not apply to
frequency transitions initiated due to thermal events, Enhanced Intel SpeedStep technology
transitions, or assertion of the FORCEPR# signal (see Chapter 6)]. Not all operating systems can
support dual processors with mixed frequencies. Intel does not support or validate operation of
processors with different cache sizes. Mixing processors of different steppings but the same model
®
(as per CPUID instruction) is supported. Please see the 64-bit Intel Xeon™ Processor with 800
MHz System Bus (1 MB and 2 MB L2 Cache Versions) Specification Update (see Section 1.2) for
the applicable mixed stepping table. Details regarding the CPUID instruction are provided in the
Intel® Processor Identification and the CPUID Instruction application note. Low-voltage (LV),
mid-voltage (MV), and full power 64-bit Intel Xeon processors with 2 MB L2 cache should not be
mixed within a system.
2.10
Absolute Maximum and Minimum Ratings
Table 2-7 specifies absolute maximum and minimum ratings. Within functional operation limits,
functionality and long-term reliability can be expected.
At conditions outside functional operation condition limits, but within absolute maximum and
minimum ratings, neither functionality nor long term reliability can be expected. If a device is
returned to conditions within functional operation limits after having been subjected to conditions
outside these limits, but within the absolute maximum and minimum ratings, the device may be
functional, but with its lifetime degraded depending on exposure to conditions exceeding the
functional operation condition limits.
At conditions exceeding absolute maximum and minimum ratings, neither functionality nor long-
term reliability can be expected. Moreover, if a device is subjected to these conditions for any
length of time then, when returned to conditions within the functional operating condition limits, it
will either not function, or its reliability will be severely degraded.
Although the processor contains protective circuitry to resist damage from static electric discharge,
precautions should always be taken to avoid high static voltages or electric fields.
Table 2-7. Absolute Maximum and Minimum Ratings
Symbol
VCC
Parameter
Min
Max
Unit
Notes1,2
Core voltage with respect to VSS
-0.30
1.55
V
VTT
System bus termination voltage with
respect to VSS
-0.30
1.55
V
TCASE
Processor case temperature
Storage temperature
See Chapter 6 See Chapter 6
-40 85
°C
°C
TSTORAGE
3,4
Datasheet
25
Electrical Specifications
NOTES:
1. For functional operation, all processor electrical, signal quality, mechanical and thermal specifications must
be satisfied.
2. Overshoot and undershoot voltage guidelines for input, output, and I/O signals are outlined in Chapter 3.
Excessive overshoot or undershoot on any signal will likely result in permanent damage to the processor.
3. Storage temperature is applicable to storage conditions only. In this scenario, the processor must not receive
a clock, and no pins can be connected to a voltage bias. Storage within these limits will not affect the long-
term reliability of the device. For functional operation, please refer to the processor case temperature
specifications.
4. This rating applies to the processor and does not include any tray or packaging.
2.11
Processor DC Specifications
The processor DC specifications in this section are defined at the processor core (pads) unless
noted otherwise. See Section 5.1 for the processor pin listings and Chapter 4 for signal definitions.
Voltage and current specifications are detailed in Table 2-8. For platform power delivery planning
refer to Table 2-9, which provides V static and transient tolerances. This same information is
CC
presented graphically in Figure 2-4.
BSEL[1:0] and VID[5:0] signals are specified in Table 2-11. The DC specifications for the AGTL+
signals are listed in Table 2-12. The DC specifications for the PWRGOOD input and TAP signal
group are listed in Table 2-13 and the Asynchronous GTL+ signal group is listed in Table 2-14. The
VIDPWRGD signal is detailed in Table 2-15.
Table 2-8 through Table 2-15 list the DC specifications for the processor and are valid only while
meeting specifications for case temperature (TCASE as specified in Chapter 6), clock frequency, and
input voltages. Care should be taken to read all notes associated with each parameter.
IA32_FLEX_BRVID_SEL bit 18 is the Platform Requirement Bit (PRB) that indicates that the
processor has specific platform requirements.
2.11.1
Flexible Motherboard Guidelines (FMB)
The Flexible Motherboard (FMB) guidelines are estimates of the maximum values the 64-bit
Intel Xeon processor with 2 MB L2 cache will have over certain time periods. The values are only
estimates and actual specifications for future processors may differ. Processors may or may not
have specifications equal to the FMB value in the foreseeable future. System designers should meet
the FMB values to ensure their systems will be compatible with future Intel Xeon processors.
26
Datasheet
Electrical Specifications
Table 2-8. Voltage and Current Specifications
Symbol
Parameter
Min
Typ
Max
Unit
Notes 1
VID range
VID range for 64-bit
Intel® Xeon™ processor with 2
MB L2 cache
1.2875
1.3875
V
2,3
VID range for 64-bit
Intel® Xeon™ MV 3.20 GHz
processor
1.2125
1.0500
1.3875
1.2000
V
V
V
2,3
2,3
VID range for 64-bit
Intel® Xeon™ LV 3 GHz
processor
VCC
VCC for 64-bit Intel Xeon
processors with 2 MB L2 cache
with multiple VIDs (PRB = 1)
See Table 2-9, Figure 2-2 and Figure 2-4
3,4,5,6,7
VID
Transition
VID step size during a transition
12.5
450
mV
mV
8
9
Total allowable DC load line shift
from VID steps
VTT
Front Side Bus
termination voltage
(DC specification)
1.176 1.20
1.140 1.20
1.224
1.260
V
V
10
Front Side Bus
termination voltage
(DC & AC specification)
10,11
ICC
ICC for 64-bit Intel Xeon
processor with 2 MB L2 cache
and 64-bit Intel Xeon MV 3.20
GHz processor (PRB = 1)
120
A
6,7
I
CC for 64-bit Intel Xeon LV 3 GHz
60
4.8
1.5
120
A
A
6,7
12
13
14
processor (PRB = 0)
ITT
Front Side Bus
end-agent VTT current
Front Side Bus
mid-agent VTT current
A
ICC_VCCA
ICC for
PLL power pins
mA
ICC_VCCIOPLL ICC for
PLL power pins
100
200
mA
14
15
ICC_GTLREF
ICC for GTLREF pins
µA
ISGNT
ISLP
ICC Stop Grant for 64-bit Intel
Xeon processor with 2 MB L2
cache and 64-bit Intel Xeon MV
3.20 GHz processor (PRB = 1)
56
A
16
I
CC Stop Grant for 64-bit Intel
Xeon LV 3 GHz processor (PRB =
0)
35.8
ICC
A
A
16
17
ITCC
ICC TCC Active
ICC_TDC
Thermal Design Current for 64-bit
Intel Xeon processor with 2 MB
L2 cache and 64-bit Intel Xeon
MV 3.20 GHz processor
105
56
A
A
18
18
Thermal Design Current for 64-bit
Intel Xeon LV 3 GHz processor
Datasheet
27
Electrical Specifications
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processors. These specifications are based
on silicon characterization, however they may be updated as further data becomes available.
2. Each processor is programmed with a maximum valid voltage identification (VID) values, which is set at
manufacturing and can not be altered. Individual maximum VID values are calibrated during manufacturing
such that two processors at the same frequency may have different settings within the VID range. Please
note this differs from the VID employed by the processor during a power management event (Thermal
Monitor 2, Enhanced Intel SpeedStep® Technology, or Enhanced HALT Power Down State).
3. These voltages are targets only. A variable voltage source should exist on systems in the event that a
different voltage is required. See Section 2.4 for more information.
4. The voltage specification requirements are measured across vias on the platform for the VCCSENSE and
VSSSENSE pins close to the socket with a 100 MHz bandwidth oscilloscope, 1.5 pF maximum probe
capacitance, and 1 MΩ minimum impedance. The maximum length of ground wire on the probe should be
less than 5 mm. Ensure external noise from the system is not coupled in the scope probe.
5. Refer to Table 2-9 and corresponding Figure 2-4. The processor should not be subjected to any static VCC
level that exceeds the VCC_MAX associated with any particular current. Failure to adhere to this specification
can shorten processor lifetime.
6. Minimum VCC and maximum ICC are specified at the maximum processor case temperature (TCASE) shown
in Table 6-1. ICC_MAX is specified at the relative VCC_MAX point on the VCC load line. The processor is capable
of drawing ICC_MAX for up to 10 ms. Refer to Figure 2-2 for further details on the average processor current
draw over various time durations.
7. FMB is the flexible motherboard guideline. These guidelines are for estimation purposes only. See
Section 2.11.1 for further details on FMB guidelines.
8. This specification represents the VCC reduction due to each VID transition. See Section 2.4.
9. This specification refers to the potential total reduction of the load line due to VID transitions below the
specified VID.
10.VTT must be provided via a separate voltage source and must not be connected to VCC. This specification is
measured at the pin.
11.Baseboard bandwidth is limited to 20 MHz.
12.This specification refers to a single processor with RTT enabled. Please note the end agent and middle agent
may not require ITT(max) simultaneously. This parameter is based on design characterization and not tested.
13.This specification refers to a single processor with RTT disabled. Please note the end agent and middle agent
may not require ITT(max) simultaneously.
14.These specifications apply to the PLL power pins VCCA, VCCIOPLL, and VSSA. See Section 2.3.2 for
details. These parameters are based on design characterization and are not tested.
15.This specification represents a total current for all GTLREF pins.
16.The current specified is also for HALT State.
17.The maximum instantaneous current the processor will draw while the thermal control circuit is active as
indicated by the assertion of the PROCHOT# signal is the maximum ICC for the processor.
18.ICC_TDC (Thermal Design Current) is the sustained (DC equivalent) current that the processor is capable of
drawing indefinitely and should be used for the voltage regulator temperature assessment. The voltage
regulator is responsible for monitoring its temperature and asserting the necessary signal to inform the
processor of a thermal excursion. Please see the applicable design guidelines for further details. The
processor is capable of drawing ICC_TDC indefinitely. Refer to Figure 2-2 for further details on the average
processor craw over various time durations. This parameter is based on design characterization and is not
tested.
28
Datasheet
Electrical Specifications
®
®
Figure 2-2. 64-bit Intel Xeon™ Processor and 64-bit Intel Xeon™ MV 3.20 GHz Processor
Load Current Vs. Time
VRM 10.1 Current
125
120
115
110
105
100
0.01
0.1
1
10
Time Duration (s)
100
1000
NOTES:
1. Processor /voltage regulator thermal protection circuitry should not trip for load currents greater than ICC_TDC
2. Not 100% tested. Specified by design characterization.
.
®
Figure 2-3. 64-bit Intel Xeon™ LV 3 GHz Processor Load Current Vs. Time
6 2
6 0
5 8
5 6
5 4
0 .0 1
0 .1
1
1 0
1 0 0
1 0 0 0
Tim e Dura tion (s )
NOTES:
1. Processor /voltage regulator thermal protection circuitry should not trip for load currents greater than ICC_TDC
2. Not 100% tested. Specified by design characterization.
.
Datasheet
29
Electrical Specifications
Table 2-9. V Static and Transient Tolerance
CC
Voltage Deviation from VID Setting (V) 1,2,3,4
ICC
VCC_Max
VCC_Typ
VCC_Min
0
5
VID - 0.000
VID - 0.006
VID - 0.013
VID - 0.019
VID - 0.025
VID - 0.031
VID - 0.038
VID - 0.044
VID - 0.050
VID - 0.056
VID - 0.063
VID - 0.069
VID - 0.075
VID - 0.081
VID - 0.087
VID - 0.094
VID - 0.100
VID - 0.106
VID - 0.113
VID - 0.119
VID - 0.125
VID - 0.131
VID - 0.138
VID - 0.020
VID - 0.026
VID - 0.033
VID - 0.039
VID - 0.045
VID - 0.051
VID - 0.058
VID - 0.064
VID - 0.070
VID - 0.076
VID - 0.083
VID - 0.089
VID - 0.095
VID - 0.101
VID - 0.108
VID - 0.114
VID - 0.120
VID - 0.126
VID - 0.133
VID - 0.139
VID - 0.145
VID - 0.151
VID - 0.158
VID - 0.040
VID - 0.046
VID - 0.052
VID - 0.059
VID - 0.065
VID - 0.071
VID - 0.077
VID - 0.084
VID - 0.090
VID - 0.096
VID - 0.103
VID - 0.109
VID - 0.115
VID - 0.121
VID - 0.128
VID - 0.134
VID - 0.140
VID - 0.146
VID - 0.153
VID - 0.159
VID - 0.165
VID - 0.171
VID - 0.178
10
15
20
25
30
35
40
45
50
55
60
65
70
75
80
85
90
95
100
105
110
NOTES:
1. The VCC_MIN and VCC_MAX loadlines represent static and transient limits. Please see Section 2.11.2 for VCC
overshoot specifications.
2. This table is intended to aid in reading discrete points on Figure 2-4.
3. The loadlines specify voltage limits at the die measured at the VCCSENSE and VSSSENSE pins. Voltage
regulation feedback for voltage regulator circuits must be taken from processor VCC and VSS pins. Refer to
the Enterprise Voltage Regulator Down (EVRD) 10.1 Design Guidelines for socket loadline guidelines and
VR implementation.
4. The 64-bit Intel Xeon LV processor has a maximum ICC specification of 60 A. As a result, this processor will
only use a portion of this table.
30
Datasheet
Electrical Specifications
Figure 2-4. V Static and Transient Tolerance
CC
Icc [A]
0
5
10
15
20
25
30
35
40
45
50
55
60
65
70
75
80
85
90
95 100 105 110 115 120
VID - 0.000
VID - 0.020
VID - 0.040
VID - 0.060
VID - 0.080
VID - 0.100
VID - 0.120
VID - 0.140
VID - 0.160
VID - 0.180
VID - 0.200
VCC
Maximum
VCC
Typical
VCC
Minimum
NOTES:
1. The VCC_MIN and VCC_MAX loadlines represent static and transient limits. Please see Section 2.11.2 for VCC
overshoot specifications.
2. The VCC_MIN and VCC_MAX loadlines are plots of the discrete point found in Table 2-9.
3. Refer to Table 2-8 for processor VID information.
4. The loadlines specify voltage limits at the die measured at the VCCSENSE and VSSSENSE pins. Voltage
regulation feedback for voltage regulator circuits must be taken from processor VCC and VSS pins. Refer to
the Enterprise Voltage Regulator Down (EVRD) 10.1 Design Guidelines for socket loadline guidelines and
VR implementation.
5. The 64-bit Intel Xeon LV processor has a maximum ICC specification of 60 A. As a result, this processor will
only use a portion of this table.
2.11.2
VCC Overshoot Specification
The processor can tolerate short transient overshoot events where V exceeds the VID voltage
CC
when transitioning from a high-to-low current load condition. This overshoot cannot exceed VID +
V
. (V
is the maximum allowable overshoot above VID). These specifications
OS_MAX
OS_MAX
apply to the processor die voltage as measured across the VCCSENSE and VSSSENSE pins.
Table 2-10. V Overshoot Specifications
CC
Symbol
Parameter
Min
Max
Units
Figure
Notes
Magnitude of VCC
overshoot above VID
VOS_MAX
0.050
V
2-5
Time duration of VCC
overshoot above VID
TOS_MAX
25
µs
2-5
Datasheet
31
Electrical Specifications
Figure 2-5. V Overshoot Example Waveform
CC
Example Overshoot Waveform
VOS
VID + 0.050
VID - 0.000
TOS
0
5
10
15
20
25
Time [us]
TOS: Overshoot time above VID
OS: Overshoot above VID
V
NOTES:
1. VOS is measured overshoot voltage.
2. TOS is measured time duration above VID.
2.11.3
Die Voltage Validation
Overshoot events from application testing on processor must meet the specifications in Table 2-10
when measured across the VCCSENSE and VSSSENSE pins. Overshoot events that are < 10 ns in
duration may be ignored. These measurement of processor die level overshoot should be taken with
a 100 MHz bandwidth limited oscilloscope.
Table 2-11. BSEL[1:0] and VID[5:0] Signal Group DC Specifications
Symbol
Parameter
Min
Typ
Max
Units Notes1
RON
BSEL[1:0] and VID[5:0]
Buffer On Resistance
N/A
60
Ω
2
IOL
ILO
Maximum Pin Current
N/A
N/A
8
mA
µA
Ω
2
Output Leakage Current
200
2,3
RPULL_UP Pull-Up Resistor
500
VTT
VTOL
Voltage Tolerance
0.95 * VTT
1.05 * VTT
V
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. These parameters are based on design characterization and are not tested.
3. Leakage to VSS with pin held at VTT
.
32
Datasheet
Electrical Specifications
Table 2-12. AGTL+ Signal Group DC Specifications
Symbol
Parameter
Min
Max
Unit
Notes1
VIL
Input Low Voltage
Input High Voltage
Output High Voltage
Output Low Current
0.0
GTLREF - (0.10 * VTT
)
V
V
V
2,3
2,4,5
2,5
VIH
VOH
IOL
GTLREF + (0.10 * VTT
0.90 * VTT
)
VTT
VTT
V
/
TT
(0.50 * R
+ [R
||
N/A
mA
2,6
TT_MIN
R ])
ON_MIN
L
ILI
Input Leakage Current
Output Leakage Current
Buffer On Resistance
N/A
N/A
7
± 200
± 200
11
µA
µA
Ω
7,8
7,8
ILO
RON
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. The VTT represented in these specifications refers to instantaneous VTT
.
3. VIL is defined as the voltage range at a receiving agent that will be interpreted as a logical low value.
4. VIH is defined as the voltage range at a receiving agent that will be interpreted as a logical high value.
5. VIH and VOH may experience excursions above VTT
6. Refer to Table 2-5 to determine which signals include additional on-die termination resistance (RL).
7. Leakage to VSS with pin held at VTT
.
.
8. Leakage to VTT with pin held at 300 mV.
Table 2-13. PWRGOOD Input and TAP Signal Group DC Specifications
Notes
Symbol
Parameter
Min
Max
Unit
1,2,5
VHYS
Vt+
Input Hysteresis
200
350
mV
V
3
4
Input Low to High
Threshold Voltage
0.5 * (VTT + VHYS_MIN
)
)
0.5 * (VTT + VHYS_MAX)
Vt-
Input High to Low
Threshold Voltage
0.5 * (VTT - VHYS_MAX
N/A
0.5 * (VTT - VHYS_MIN
)
V
4
VOH
IOL
Output High Voltage
Output Low Current
Input Leakage Current
Output Leakage Current
Buffer On Resistance
VTT
45
V
mA
µA
µA
Ω
4
6
ILI
N/A
N/A
7
± 200
± 200
11
ILO
RON
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. All outputs are open drain.
3. VHYS represents the amount of hysteresis, nominally centered about 0.5 * VTT for all PWRGOOD and TAP
inputs.
4. The VTT represented in these specifications refers to instantaneous VTT
.
5. PWRGOOD input and the TAP signal group must meet system signal quality specification in Chapter 2.
6. The maximum output current is based on maximum current handling capability of the buffer and is not
specified into the test load.
Datasheet
33
Electrical Specifications
Table 2-14. GTL+ Asynchronous and AGTL+ Asynchronous Signal Group DC
Specifications
Symbol
Parameter
Min
Max
Unit
Notes1
VIL
Input Low Voltage
Input High Voltage
Output High Voltage
Output Low Current
0.0
GTLREF - (0.10 * VTT
)
V
V
V
2,3
2,4,5
2,5
VIH
VOH
IOL
GTLREF + (0.10 * VTT
0.90 * VTT
)
VTT
VTT
V
/
TT
N/A
mA
2,6
(0.50 * R
+ [R
|| R ])
ON_MIN L
TT_MIN
ILI
Input Leakage Current
Output Leakage Current
Buffer On Resistance
N/A
N/A
7
± 200
± 200
11
µA
µA
Ω
7,8
7,8
ILO
Ron
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. The VTT represented in these specifications refers to instantaneous VTT
3. VIL is defined as the voltage range at a receiving agent that will be interpreted as a logical low value.
4. VIH is defined as the voltage range at a receiving agent that will be interpreted as a logical high value.
5. VIH and VOH may experience excursions above VTT
6. Refer to Table 2-5 to determine which signals include additional on-die termination resistance (RL).
7. Leakage to VSS with pin held at VTT
.
.
.
8. Leakage to VTT with pin held at 300 mV.
Table 2-15. VIDPWRGD DC Specifications
Symbol
Parameter
Input Low Voltage
Input High Voltage
Min
0.0
Max
0.30
VTT
Unit
V
Notes1
VIL
VIH
0.90
V
34
Datasheet
3 Mechanical Specifications
The 64-bit Intel Xeon processor with 2 MB L2 cache is packaged in Flip Chip Micro Pin Grid
Array (FC-mPGA4) package that interfaces to the baseboard via an mPGA604 socket. The
package consists of a processor core mounted on a substrate pin-carrier. An integrated heat
spreader (IHS) is attached to the package substrate and core and serves as the mating surface for
processor component thermal solutions, such as a heatsink. Figure 3-1 shows a sketch of the
processor package components and how they are assembled together. Refer to the mPGA604
Socket Design Guidelines for complete details on the mPGA604 socket.
The package components shown in Figure 3-1 include the following:
1. Integrated Heat Spreader (IHS)
2. Processor die
3. Substrate
4. Pin side capacitors
5. Package pin
6. Die Side Capacitors
Figure 3-1. Processor Package Assembly Sketch
6
1
2
3
5
4
Note: This drawing is not to scale and is for reference only. The mPGA604 socket is not shown.
Datasheet
35
Mechanical Specifications
3.1
Package Mechanical Drawings
The package mechanical drawings are shown in Figure 3-2 and Figure 3-3. The drawings include
dimensions necessary to design a thermal solution for the processor. These dimensions include:
1. Package reference and tolerance dimensions (total height, length, width, etc.)
2. IHS parallelism and tilt
3. Pin dimensions
4. Top-side and back-side component keepout dimensions
5. Reference datums
All drawing dimensions are in mm [in.].
36
Datasheet
Mechanical Specifications
Figure 3-2. Processor Package Drawing (Sheet 1 of 2)
Datasheet
37
Mechanical Specifications
Figure 3-3. Processor Package Drawing (Sheet 2 of 2)
38
Datasheet
Mechanical Specifications
3.2
3.3
Processor Component Keepout Zones
The processor may contain components on the substrate that define component keepout zone
requirements. A thermal and mechanical solution design must not intrude into the required keepout
zones. Decoupling capacitors are typically mounted to either the topside or pin-side of the package
substrate. See Figure 3-3 for keepout zones.
Package Loading Specifications
Table 3-1 provides dynamic and static load specifications for the processor package. These
mechanical load limits should not be exceeded during heatsink assembly, mechanical stress testing
or standard drop and shipping conditions. The heatsink attach solutions must not include
continuous stress onto the processor with the exception of a uniform load to maintain the heatsink-
to-processor thermal interface. Also, any mechanical system or component testing should not
exceed these limits. The processor package substrate should not be used as a mechanical reference
or load-bearing surface for thermal or mechanical solutions.
Table 3-1. Processor Loading Specifications
Parameter
Min
Max
Unit
Notes
Static
Compressive Load
44
10
222
50
N
lbf
1,2,3,4
44
10
288
65
N
lbf
1,2,3,5
1,3,4,6,7
1,3,5,6,7
1,3,8
Dynamic
Compressive Load
NA
NA
222 N + 0.45 kg *100 G
50 lbf (static) + 1 lbm * 100 G
N
lbf
NA
NA
288 N + 0.45 kg * 100 G
65 lbf (static) + 1 lbm * 100 G
N
lbf
Transient
NA
445
100
N
lbf
NOTES:
1. These specifications apply to uniform compressive loading in a direction perpendicular to the IHS top
surface.
2. This is the minimum and maximum static force that can be applied by the heatsink and retention solution to
maintain the heatsink and processor interface.
3. These specifications are based on limited testing for design characterization. Loading limits are for the
package only and do not include the limits of the processor socket.
4. This specification applies for thermal retention solutions that allow baseboard deflection.
5. This specification applies either for thermal retention solutions that prevent baseboard deflection or for the
Intel enabled reference solution (CEK).
6. Dynamic loading is defined as an 11 ms duration average load superimposed on the static load requirement.
7. Experimentally validated test condition used a heatsink mass of 1 lbm (~0.45 kg) with 100 G acceleration
measured at heatsink mass. The dynamic portion of this specification in the product application can have
flexibility in specific values, but the ultimate product of mass times acceleration should not exceed this
validated dynamic load (1 lbm x 100 G = 100 lb). Allowable strain in the dynamic compressive load
specification is in addition to the strain allowed in static loading.
8. Transient loading is defined as a 2 second duration peak load superimposed on the static load requirement,
representative of loads experienced by the package during heatsink installation.
Datasheet
39
Mechanical Specifications
3.4
Package Handling Guidelines
Table 3-2 includes a list of guidelines on a package handling in terms of recommended maximum
loading on the processor IHS relative to a fixed substrate. These package handling loads may be
experienced during heatsink removal.
Table 3-2. Package Handling Guidelines
Parameter
Maximum Recommended
Notes
Shear
356 N
80 lbf
1,4,5
Tensile
Torque
156 N
35 lbf
2,4,5
3,4,5
8 N-m
70 lbf-in
NOTES:
1. A shear load is defined as a load applied to the IHS in a direction parallel to the IHS top surface.
2. A tensile load is defined as a pulling load applied to the IHS in a direction normal to the IHS surface.
3. A torque load is defined as a twisting load applied to the IHS in an axis of rotation normal to the IHS top
surface.
4. These guidelines are based on limited testing for design characterization and incidental applications (one
time only).
5. Handling guidelines are for the package only and do not include the limits of the processor socket.
3.5
3.6
3.7
Package Insertion Specifications
The processor can be inserted and removed 15 times from an mPGA604 socket, which meets the
criteria outlined in the mPGA604 Socket Design Guidelines.
Processor Mass Specifications
The typical mass of the 64-bit Intel Xeon processor with 2 MB L2 cache is 25 grams [0.88 oz.].
This mass [weight] includes all components which make up the entire processor product.
Processor Materials
The processor is assembled from several components. The basic material properties are described
in Table 3-3.
Table 3-3. Processor Materials
Component
Material
Integrated Heat Spreader (IHS)
Substrate
Nickel over copper
Fiber-reinforced resin
Gold over nickel
Substrate Pins
40
Datasheet
Mechanical Specifications
3.8
Processor Markings
Figure 3-4 shows the topside markings and Figure 3-5 shows the bottom-side markings on the
processor. These diagrams are to aid in the identification of the processor.
Figure 3-4. Processor Top-Side Markings (Example)
2D M atrix
Includes ATPO and Serial
Num ber (front end m ark)
Processor Nam e
i(m ) ©’04
ATPO
Serial Num ber
Pin 1 Indicator
NOTES:
1. All characters will be in upper case.
2. Drawing is not to scale.
Figure 3-5. Processor Bottom-Side Markings (Example)
Pin 1 Indicator
Speed / Cache / Bus / Voltage
Pin Field
4000DP/2MB/800/1.350V
SL6NY COSTA RICA
C0096109-0021
S-Spec
Country of Assy
Cavity
with
Components
FPO – Serial #
(13 Characters)
Text Line1
Text Line2
Text Line3
NOTES:
3. All characters will be in upper case.
4. Drawing is not to scale.
Datasheet
41
Mechanical Specifications
3.9
Processor Pin-Out Coordinates
Figure 3-6 and Figure 3-7 show the top and bottom view of the processor pin coordinates,
respectively. The coordinates are referred to throughout the document to identify processor pins.
Figure 3-6. Processor Pin-out Coordinates, Top View
COMMON
ADDRESS
COMMON
CLOCK
Async /
JTAG
CLOCK
1
3
5
7
9
11 13
15 17 19
21 23 25
27
29
31
A
B
A
B
C
D
C
D
E
E
F
F
G
H
J
G
H
J
K
L
M
N
P
R
K
L
64-bit
Intel® Xeon™ Processor
M
N
P
with 2 MB L2 Cache
(Top View)
R
T
T
U
V
W
Y
U
V
W
Y
AA
AA
AB
AC
AD
AB
AC
AD
AE
AE
2
4
6
8
10 12 14
16 18
20 22
24 26 28
30
CLOCKS
DATA
= Signal
= Power
= Ground
= GTLREF
= Reserved/No Connect
= VTT
42
Datasheet
Mechanical Specifications
Figure 3-7. Processor Pin-out Coordinates, Bottom View
Async /
JTAG
COMMON
CLOCK
COMMON
CLOCK
ADDRESS
31 29 27 25
23 21 19 17 15
13 11
9
7
5
3
1
A
B
A
B
C
D
C
D
E
E
F
F
G
H
J
G
H
J
K
L
M
N
P
R
K
L
M
64-bit
Intel® Xeon™ Processor
with 2 MB L2 Cache
N
P
R
T
(Bottom View)
T
U
V
W
Y
U
V
W
Y
AA
AA
AB
AC
AB
AC
AD
AE
AD
AE
30
28 26
24 22
20 18
16 14 12
10
8
6
4
2
CLOCKS
DATA
= Signal
= Power
= Ground
= GTLREF
= Reserved/No Connect
= VTT
Datasheet
43
Mechanical Specifications
44
Datasheet
4 Signal Definitions
4.1
Signal Definitions
Table 4-1. Signal Definitions (Sheet 1 of 10)
Name
Type
Description
Notes
A[35:3]# (Address) define a 236-byte physical memory address space. In
sub-phase 1 of the address phase, these pins transmit the address of a
transaction. In sub-phase 2, these pins transmit transaction type
information. These signals must connect the appropriate pins of all agents
on the front side bus. A[35:3]# are protected by parity signals AP[1:0]#.
A[35:3]# are source synchronous signals and are latched into the receiving
buffers by ADSTB[1:0]#.
A[35:3]#
I/O
4
On the active-to-inactive transition of RESET#, the processors sample a
subset of the A[35:3]# pins to determine their power-on configuration. See
Section 7.1.
If A20M# (Address-20 Mask) is asserted, the processor masks physical
address bit 20 (A20#) before looking up a line in any internal cache and
before driving a read/write transaction on the bus. Asserting A20M#
emulates the 8086 processor's address wrap-around at the 1 MB
boundary. Assertion of A20M# is only supported in real mode.
A20M#
I
3
4
4
A20M# is an asynchronous signal. However, to ensure recognition of this
signal following an I/O write instruction, it must be valid along with the
TRDY# assertion of the corresponding I/O write bus transaction.
ADS# (Address Strobe) is asserted to indicate the validity of the
transaction address on the A[35:3]# pins. All bus agents observe the ADS#
activation to begin parity checking, protocol checking, address decode,
internal snoop, or deferred reply ID match operations associated with the
new transaction. This signal must connect the appropriate pins on all (800
MHz) front side bus agents.
ADS#
I/O
I/O
Address strobes are used to latch A[35:3]# and REQ[4:0]# on their rising
and falling edge. Strobes are associated with signals as shown below.
Signals
Associated Strobes
ADSTB[1:0]#
REQ[4:0]#, A[16:3]#
A[35:17]#
ADSTB0#
ADSTB1#
AP[1:0]# (Address Parity) are driven by the request initiator along with
ADS#, A[35:3]#, and the transaction type on the REQ[4:0]# pins. A correct
parity signal is high if an even number of covered signals are low and low if
an odd number of covered signals are low. This allows parity to be high
when all the covered signals are high. AP[1:0]# should connect the
appropriate pins of all system bus agents. The following table defines the
coverage model of these signals.
AP[1:0]#
I/O
4
Request Signals
Subphase 1
Subphase 2
A[35:24]#
A[23:3]#
AP0#
AP1#
AP1#
AP1#
AP0#
AP0#
REQ[4:0]#
Datasheet
45
Signal Definitions
Table 4-1. Signal Definitions (Sheet 2 of 10)
Name
Type
Description
Notes
The differential bus clock pair BCLK[1:0] determines the front side bus
frequency. All processor front side bus agents must receive these signals
to drive their outputs and latch their inputs.
BCLK[1:0]
I
4
All external timing parameters are specified with respect to the rising edge
of BCLK0 crossing VCROSS
.
BINIT# (Bus Initialization) may be observed and driven by all processor
front side bus agents and if used, must connect the appropriate pins of all
such agents. If the BINIT# driver is enabled during power on configuration,
BINIT# is asserted to signal any bus condition that prevents reliable future
information.
If BINIT# observation is enabled during power-on configuration (see
Figure 7.1) and BINIT# is sampled asserted, symmetric agents reset their
bus LOCK# activity and bus request arbitration state machines. The bus
agents do not reset their I/O Queue (IOQ) and transaction tracking state
machines upon observation of BINIT# assertion. Once the BINIT#
assertion has been observed, the bus agents will re-arbitrate for the front
side bus and attempt completion of their bus queue and IOQ entries.
BINIT#
I/O
4
If BINIT# observation is disabled during power-on configuration, a central
agent may handle an assertion of BINIT# as appropriate to the error
handling architecture of the system.
Since multiple agents may drive this signal at the same time, BINIT# is a
wired-OR signal which must connect the appropriate pins of all processor
front side bus agents. In order to avoid wired-OR glitches associated with
simultaneous edge transitions driven by multiple drivers, BINIT# is
activated on specific clock edges and sampled on specific clock edges
BNR# (Block Next Request) is used to assert a bus stall by any bus agent
who is unable to accept new bus transactions. During a bus stall, the
current bus owner cannot issue any new transactions.
Since multiple agents might need to request a bus stall at the same time,
BNR# is a wired-OR signal which must connect the appropriate pins of all
processor front side bus agents. In order to avoid wired-OR glitches
associated with simultaneous edge transitions driven by multiple drivers,
BNR# is activated on specific clock edges and sampled on specific clock
edges.
BNR#
I/O
4
The BOOT_SELECT input informs the processor whether the platform
supports the 64-bit Intel Xeon processor with 2 MB L2 cache. The
processor will not operate if this signal is low. This input has a weak pull-up
BOOT_
SELECT
I
to VTT
.
BPM[5:0]# (Breakpoint Monitor) are breakpoint and performance monitor
signals. They are outputs from the processor which indicate the status of
breakpoints and programmable counters used for monitoring processor
performance. BPM[5:0]# should connect the appropriate pins of all front
side bus agents.
BPM4# provides PRDY# (Probe Ready) functionality for the TAP port.
PRDY# is a processor output used by debug tools to determine processor
debug readiness.
BPM[5:0]#
I/O
3
BPM5# provides PREQ# (Probe Request) functionality for the TAP port.
PREQ# is used by debug tools to request debug operation of the
processors.
BPM[5:4]# must be bussed to all bus agents. Please refer to the
appropriate platform design guidelines for more detailed information.
These signals do not have on-die termination and must be terminated
at the end agent.
46
Datasheet
Signal Definitions
Table 4-1. Signal Definitions (Sheet 3 of 10)
Name
Type
Description
Notes
BPRI# (Bus Priority Request) is used to arbitrate for ownership of the
processor front side bus. It must connect the appropriate pins of all
processor front side bus agents. Observing BPRI# active (as asserted by
the priority agent) causes all other agents to stop issuing new requests,
unless such requests are part of an ongoing locked operation. The priority
agent keeps BPRI# asserted until all of its requests are completed, then
releases the bus by deasserting BPRI#.
BPRI#
I
4
BR[3:0]# (Bus Request) drive the BREQ[3:0]# signals in the system. The
BREQ[3:0]# signals are interconnected in a rotating manner to individual
processor pins. The tables below provide the rotating interconnect
between the processor and bus signals for 2-way systems.
BR[1:0]# Signals Rotating Interconnect, 2-way system
Bus Signal Agent 0 Pins Agent 1 Pins
BREQ0#
BREQ1#
BR0#
BR1#
BR1#
BR0#
BR0#
BR[1:3]#1
I/O
I
1,4
BR2# and BR3# must not be utilized in 2-way platform designs. However,
they must still be terminated.
During power-on configuration, the central agent must assert the BR0# bus
signal. All symmetric agents sample their BR[3:0]# pins on the active-to-
inactive transition of RESET#. The pin which the agent samples asserted
determines it’s agent ID.
These signals do not have on-die termination and must be terminated
at the end agent.
The BCLK[1:0] frequency select signals BSEL[1:0] are used to select the
processor input clock frequency. Table defines the possible combinations
of the signals and the frequency associated with each combination. The
required frequency is determined by the processors, chipset, and clock
synthesizer. All front side bus agents must operate at the same frequency.
The 64-bit Intel Xeon processor with 2 MB L2 cache currently operates at a
800 MHz front side bus frequency (200 MHz BCLK[1:0] frequency). For
more information about these pins, including termination
BSEL[1:0]
COMP[1:0]
O
recommendations, refer to the appropriate platform design guideline.
COMP[1:0] must be terminated to VSS on the baseboard using precision
resistors. These inputs configure the GTL+ drivers of the processor. Refer
to the appropriate platform design guidelines for implementation details.
I
Datasheet
47
Signal Definitions
Table 4-1. Signal Definitions (Sheet 4 of 10)
Name
Type
Description
Notes
D[63:0]# (Data) are the data signals. These signals provide a 64-bit data
path between the processor front side bus agents, and must connect the
appropriate pins on all such agents. The data driver asserts DRDY# to
indicate a valid data transfer.
D[63:0]# are quad-pumped signals, and will thus be driven four times in a
common clock period. D[63:0]# are latched off the falling edge of both
DSTBP[3:0]# and DSTBN[3:0]#. Each group of 16 data signals correspond
to a pair of one DSTBP# and one DSTBN#. The following table shows the
grouping of data signals to strobes and DBI#.
DSTBN#/
DSTBP#
Data Group
DBI#
D[63:0]#
I/O
4
D[15:0]#
D[31:16]#
D[47:32]#
D[63:48]#
0
1
2
3
0
1
2
3
Furthermore, the DBI# pins determine the polarity of the data signals. Each
group of 16 data signals corresponds to one DBI# signal. When the DBI#
signal is active, the corresponding data group is inverted and therefore
sampled active high.
DBI[3:0]# are source synchronous and indicate the polarity of the D[63:0]#
signals. The DBI[3:0]# signals are activated when the data on the data bus
is inverted. If more than half the data bits, within a 16-bit group, would have
been asserted electronically low, the bus agent may invert the data bus
signals for that particular sub-phase for that 16-bit group.
DBI[3:0] Assignment To Data Bus
DBI[3:0]#
I/O
4
Bus Signal
Data Bus Signals
DBI0#
DBI1#
DBI2#
DBI3#
D[15:0]#
D[31:16]#
D[47:32]#
D[63:48]#
DBSY# (Data Bus Busy) is asserted by the agent responsible for driving
data on the processor front side bus to indicate that the data bus is in use.
The data bus is released after DBSY# is deasserted. This signal must
connect the appropriate pins on all processor front side bus agents.
DBSY#
I/O
4
DEFER# is asserted by an agent to indicate that a transaction cannot be
guaranteed in-order completion. Assertion of DEFER# is normally the
responsibility of the addressed memory or I/O agent. This signal must
connect the appropriate pins of all processor front side bus agents.
DEFER#
DP[3:0]#
DRDY#
I
4
4
4
DP[3:0]# (Data Parity) provide parity protection for the D[63:0]# signals.
They are driven by the agent responsible for driving D[63:0]#, and must
connect the appropriate pins of all processor front side bus agents.
I/O
I/O
DRDY# (Data Ready) is asserted by the data driver on each data transfer,
indicating valid data on the data bus. In a multi-common clock data
transfer, DRDY# may be deasserted to insert idle clocks. This signal must
connect the appropriate pins of all processor front side bus agents.
48
Datasheet
Signal Definitions
Table 4-1. Signal Definitions (Sheet 5 of 10)
Name
Type
Description
Data strobe used to latch in D[63:0]#.
Notes
Signals
Associated Strobes
D[15:0]#, DBI0#
D[31:16]#, DBI1#
D[47:32]#, DBI2#
D[63:48]#, DBI3#
DSTBN0#
DSTBN1#
DSTBN2#
DSTBN3#
DSTBN[3:0]#
I/O
4
Data strobe used to latch in D[63:0]#.
Signals
Associated Strobes
D[15:0]#, DBI0#
D[31:16]#, DBI1#
D[47:32]#, DBI2#
D[63:48]#, DBI3#
DSTBP0#
DSTBP1#
DSTBP2#
DSTBP3#
DSTBP[3:0]#
I/O
4
FERR#/PBE# (floating-point error/pending break event) is a multiplexed
signal and its meaning is qualified by STPCLK#. When STPCLK# is not
asserted, FERR#/PBE# indicates a floating-point error and will be asserted
when the processor detects an unmasked floating-point error. When
STPCLK# is not asserted, FERR#/PBE# is similar to the ERROR# signal
on the Intel 387 coprocessor, and is included for compatibility with systems
using MS-DOS*-type floating-point error reporting. When STPCLK# is
asserted, an assertion of FERR#/PBE# indicates that the processor has a
pending break event waiting for service. The assertion of FERR#/PBE#
indicates that the processor should be returned to the Normal state. For
additional information on the pending break event functionality, including
the identification of support of the feature and enable/disable information,
refer to Vol. 3 of the IA-32 Intel® Architecture Software Developer’s Manual
and the Intel Processor Identification and the CPUID Instruction application
note.
FERR#/PBE#
O
3
This signal does not have on-die termination and must be terminated
at the end agent.
The FORCEPR# input can be used by the platform to force the processor
to activate the Thermal Control Circuit (TCC). The TCC will remain active
until the system deasserts FORCEPR#.
FORCEPR#
GTLREF
I
I
GTLREF determines the signal reference level for GTL+ input pins.
GTLREF is used by the GTL+ receivers to determine if a signal is a logical
0 or a logical 1.
HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction snoop
operation results. Any front side bus agent may assert both HIT# and
HITM# together to indicate that it requires a snoop stall, which can be
continued by reasserting HIT# and HITM# together.
HIT#
I/O
I/O
Since multiple agents may deliver snoop results at the same time, HIT#
and HITM# are wired-OR signals which must connect the appropriate pins
of all processor front side bus agents. In order to avoid wired-OR glitches
associated with simultaneous edge transitions driven by multiple drivers,
HIT# and HITM# are activated on specific clock edges and sampled on
specific clock edges.
4
HITM#
Datasheet
49
Signal Definitions
Table 4-1. Signal Definitions (Sheet 6 of 10)
Name
Type
Description
Notes
IERR# (Internal Error) is asserted by a processor as the result of an
internal error. Assertion of IERR# is usually accompanied by a
SHUTDOWN transaction on the processor front side bus. This transaction
may optionally be converted to an external error signal (e.g., NMI) by
system core logic. The processor will keep IERR# asserted until the
assertion of RESET#.
IERR#
O
3
This signal does not have on-die termination and must be terminated
at the end agent.
IGNNE# (Ignore Numeric Error) is asserted to force the processor to ignore
a numeric error and continue to execute noncontrol floating-point
instructions. If IGNNE# is deasserted, the processor generates an
exception on a noncontrol floating-point instruction if a previous floating-
point instruction caused an error. IGNNE# has no effect when the NE bit in
control register 0 (CR0) is set.
IGNNE#
I
3
IGNNE# is an asynchronous signal. However, to ensure recognition of this
signal following an I/O write instruction, it must be valid along with the
TRDY# assertion of the corresponding I/O write bus transaction.
INIT# (Initialization), when asserted, resets integer registers inside all
processors without affecting their internal caches or floating-point registers.
Each processor then begins execution at the power-on Reset vector
configured during power-on configuration. The processor continues to
handle snoop requests during INIT# assertion. INIT# is an asynchronous
signal and must connect the appropriate pins of all processor front side bus
agents.
INIT#
I
3
If INIT# is sampled active on the active to inactive transition of RESET#,
then the processor executes its Built-in Self-Test (BIST).
LINT[1:0] (Local APIC Interrupt) must connect the appropriate pins of all
front side bus agents. When the APIC functionality is disabled, the LINT0/
INTR signal becomes INTR, a maskable interrupt request signal, and
LINT1/NMI becomes NMI, a nonmaskable interrupt. INTR and NMI are
backward compatible with the signals of those names on the Pentium®
processor. Both signals are asynchronous.
LINT[1:0]
I
3
These signals must be software configured via BIOS programming of the
APIC register space to be used either as NMI/INTR or LINT[1:0]. Because
the APIC is enabled by default after Reset, operation of these pins as
LINT[1:0] is the default configuration.
LOCK# indicates to the system that a transaction must occur atomically.
This signal must connect the appropriate pins of all processor front side
bus agents. For a locked sequence of transactions, LOCK# is asserted
from the beginning of the first transaction to the end of the last transaction.
LOCK#
I/O
4
When the priority agent asserts BPRI# to arbitrate for ownership of the
processor front side bus, it will wait until it observes LOCK# deasserted.
This enables symmetric agents to retain ownership of the processor front
side bus throughout the bus locked operation and ensure the atomicity of
lock.
50
Datasheet
Signal Definitions
Table 4-1. Signal Definitions (Sheet 7 of 10)
Name
Type
Description
Notes
MCERR# (Machine Check Error) is asserted to indicate an unrecoverable
error without a bus protocol violation. It may be driven by all processor front
side bus agents.
MCERR# assertion conditions are configurable at a system level.
Assertion options are defined by the following options:
•
•
•
Enabled or disabled.
Asserted, if configured, for internal errors along with IERR#.
Asserted, if configured, by the request initiator of a bus transaction
after it observes an error.
MCERR#
I/O
•
Asserted by any bus agent when it observes an error in a bus
transaction.
For more details regarding machine check architecture, refer to the IA-32
Intel® Architecture Software Developer’s Manual, Volume 3: System
Programming Guide.
Since multiple agents may drive this signal at the same time, MCERR# is a
wired-OR signal which must connect the appropriate pins of all processor
front side bus agents. In order to avoid wired-OR glitches associated with
simultaneous edge transitions driven by multiple drivers, MCERR# is
activated on specific clock edges and sampled on specific clock edges.
ODTEN (On-die termination enable) should be connected to VTT to enable
on-die termination for end bus agents. For middle bus agents, pull this
signal down via a resistor to ground to disable on-die termination.
Whenever ODTEN is high, on-die termination will be active, regardless of
other states of the bus.
ODTEN
I
I
This is an input pin to the processor to determine if the processor is in an
optimized platform or a compatible platform. This signal does includes a
OPTIMIZED/
COMPAT#
weak on-die pull-up to VTT
.
PROCHOT# (Processor Hot) will go active when the processor
temperature monitoring sensor detects that the processor die temperature
has reached its factory configured trip point. This indicates that the
processor Thermal Control Circuit (TCC) has been activated, if enabled.
See Section 6.2.4 for more details.
PROCHOT#
PWRGOOD
REQ[4:0]#
O
PWRGOOD (Power Good) is an input. The processor requires this signal
to be a clean indication that all processor clocks and power supplies are
stable and within their specifications. “Clean” implies that the signal will
remain low (capable of sinking leakage current), without glitches, from the
time that the power supplies are turned on until they come within
specification. The signal must then transition monotonically to a high state.
PWRGOOD can be driven inactive at any time, but clocks and power must
again be stable before a subsequent rising edge of PWRGOOD. It must
also meet the minimum pulse width specification in Table 2-14, and be
followed by a 1-10 ms RESET# pulse.
I
3
The PWRGOOD signal must be supplied to the processor; it is used to
protect internal circuits against voltage sequencing issues. It should be
driven high throughout boundary scan operation.
REQ[4:0]# (Request Command) must connect the appropriate pins of all
processor front side bus agents. They are asserted by the current bus
owner to define the currently active transaction type. These signals are
source synchronous to ADSTB[1:0]#. Refer to the AP[1:0]# signal
description for details on parity checking of these signals.
I/O
4
Datasheet
51
Signal Definitions
Table 4-1. Signal Definitions (Sheet 8 of 10)
Name
Type
Description
Notes
Asserting the RESET# signal resets all processors to known states and
invalidates their internal caches without writing back any of their contents.
For a power-on Reset, RESET# must stay active for at least 1 ms after VCC
and BCLK have reached their proper specifications. On observing active
RESET#, all front side bus agents will deassert their outputs within two
clocks. RESET# must not be kept asserted for more than 10 ms while
PWRGOOD is asserted.
RESET#
I
4
A number of bus signals are sampled at the active-to-inactive transition of
RESET# for power-on configuration. These configuration options are
described in the Section 7.1.
This signal does not have on-die termination and must be terminated
at the end agent.
RS[2:0]# (Response Status) are driven by the response agent (the agent
responsible for completion of the current transaction), and must connect
the appropriate pins of all processor front side bus agents.
RS[2:0]#
RSP#
I
I
4
4
RSP# (Response Parity) is driven by the response agent (the agent
responsible for completion of the current transaction) during assertion of
RS[2:0]#, the signals for which RSP# provides parity protection. It must
connect to the appropriate pins of all processor front side bus agents.
A correct parity signal is high if an even number of covered signals are low
and low if an odd number of covered signals are low. While RS[2:0]# = 000,
RSP# is also high, since this indicates it is not being driven by any agent
guaranteeing correct parity.
SKTOCC# (Socket occupied) will be pulled to ground by the processor to
indicate that the processor is present. There is no connection to the
processor silicon for this signal.
SKTOCC#
O
I
The front side bus slew rate control input, SLEW_CTRL, is used to
establish distinct edge rates for middle and end agents.
SLEW_CTRL
SLP# (Sleep), when asserted in Stop-Grant state, causes processors to
enter the Sleep state. During Sleep state, the processor stops providing
internal clock signals to all units, leaving only the Phase-Lock Loop (PLL)
still operating. Processors in this state will not recognize snoops or
interrupts. The processor will only recognize the assertion of the RESET#
signal, deassertion of SLP#, and removal of the BCLK input while in Sleep
state. If SLP# is deasserted, the processor exits Sleep state and returns to
Stop-Grant state, restarting its internal clock signals to the bus and
processor core units.
SLP#
I
3
The SMBus present (SMB_PRT) pin is defined to inform the platform if the
installed processor includes SMBus components such as the integrated
thermal sensor and the processor information ROM (PIROM). This pin is
tied to VSS by the processor if these features are not present. Platforms
utilizing this pin should use a pull up resistor to the appropriate voltage
level for the logic tied to this pin. Because this pin does not connect to the
processor silicon, any platform voltage and termination value is acceptable.
SMB_PRT
O
SMI# (System Management Interrupt) is asserted asynchronously by
system logic. On accepting a System Management Interrupt, processors
save the current state and enter System Management Mode (SMM). An
SMI Acknowledge transaction is issued, and the processor begins program
execution from the SMM handler.
SMI#
I
3
If SMI# is asserted during the deassertion of RESET# the processor will tri-
state its outputs.
52
Datasheet
Signal Definitions
Table 4-1. Signal Definitions (Sheet 9 of 10)
Name
Type
Description
Notes
STPCLK# (Stop Clock), when asserted, causes processors to enter a low
power Stop-Grant state. The processor issues a Stop-Grant Acknowledge
transaction, and stops providing internal clock signals to all processor core
units except the front side bus and APIC units. The processor continues to
snoop bus transactions and service interrupts while in Stop-Grant state.
When STPCLK# is deasserted, the processor restarts its internal clock to
all units and resumes execution. The assertion of STPCLK# has no effect
on the bus clock; STPCLK# is an asynchronous input.
STPCLK#
I
3
TCK (Test Clock) provides the clock input for the processor Test Bus (also
known as the Test Access Port).
TCK
I
I
TDI (Test Data In) transfers serial test data into the processor. TDI provides
the serial input needed for JTAG specification support.
TDI
TDO (Test Data Out) transfers serial test data out of the processor. TDO
provides the serial output needed for JTAG specification support.
TDO
O
I
Must be connected to all other processor TEST_BUS signals in the
system.
TEST_BUS
All TESTHI inputs should be individually connected to VTT via a pull-up
resistor which matches the trace impedance. TESTHI[3:0] and
TESTHI[6:5] may all be tied together and pulled up to VTT with a single
resistor if desired. However, utilization of boundary scan test will not be
functional if these pins are connected together. TESTHI4 must always be
pulled up independently from the other TESTHI pins. For optimum noise
margin, all pull-up resistor values used for TESTHI[6:0] should have a
resistance value within 20% of the impedance of the baseboard
transmission line traces. For example, if the trace impedance is 50 Ω, than
a value between 40 Ω and 60 Ω should be used.
TESTHI[6:0]
I
THERMDA
THERMDC
Other Thermal Diode Anode. See Section 6.2.8.
Other Thermal Diode Cathode. See Section 6.2.8.
Assertion of THERMTRIP# (Thermal Trip) indicates the processor junction
temperature has reached a temperature beyond which permanent silicon
damage may occur. Measurement of the temperature is accomplished
through an internal thermal sensor. Upon assertion of THERMTRIP#, the
processor will shut off its internal clocks (thus halting program execution) in
an attempt to reduce the processor junction temperature. To protect the
processor its core voltage (VCC) must be removed following the assertion
of THERMTRIP#.
THERMTRIP#
O
2
Driving of the THERMTRIP# signals is enabled within 10 ms of the
assertion of PWRGOOD and is disabled on de-assertion of PWRGOOD.
Once activated, THERMTRIP# remains latched until PWRGOOD is de-
asserted. While the de-assertion of the PWRGOOD signal will de-assert
THERMTRIP#, if the processor’s junction temperature remains at or above
the trip level, THERMTRIP# will again be asserted within 10 ms of the
assertion of PWRGOOD.
TMS (Test Mode Select) is a JTAG specification support signal used by
debug tools.
TMS
I
This signal does not have on-die termination and must be terminated
at the end agent.
TRDY# (Target Ready) is asserted by the target to indicate that it is ready
to receive a write or implicit writeback data transfer. TRDY# must connect
the appropriate pins of all front side bus agents.
TRDY#
TRST#
VCCA
I
I
I
TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST# must
be driven low during power on Reset.
VCCA provides isolated power for the analog portion of the internal
processor core PLL’s. Refer to the appropriate platform design guidelines
for complete implementation details.
Datasheet
53
Signal Definitions
Table 4-1. Signal Definitions (Sheet 10 of 10)
Name
Type
Description
Notes
VCCIOPLL provides isolated power for digital portion of the internal
processor core PLL’s. Refer to the appropriate platform design guidelines
for complete implementation details.
VCCIOPLL
I
The on-die PLL filter solution will not be implemented on this
VCCPLL
I
platform. The V
input should be left unconnected.
CCPLL
VCCSENSE and VSSSENSE provide an isolated, low impedance
connection to the processor core power and ground. They can be
used to sense or measure power near the silicon with little noise.
VCCSENSE
VSSSENSE
O
VID[5:0] (Voltage ID) pins are used to support automatic selection of power
supply voltages (VCC). These are open drain signals that are driven by the
processor and must be pulled up through a resistor. Conversely, the VR
output must be disabled prior to the voltage supply for these pins becomes
invalid. The VID pins are needed to support processor voltage specification
variations. See Table 2-3 for definitions of these pins. The VR must supply
the voltage that is requested by these pins, or disable itself.
VID[5:0]
O
The processor requires this input to determine that the supply voltage for
BSEL[1:0] and VID[5:0] is stable and within specification.
VIDPWRGD
VSSA
I
I
VSSA provides an isolated, internal ground for internal PLL’s. Do not
connect directly to ground. This pin is to be connected to VCCA and
V
CCIOPLL through a discrete filter circuit.
The front side bus termination voltage input pins. Refer to Table 2-8 for
further details.
VTT
P
The VTTEN can be used as an output enable for the VTT regulator in the
event an incompatible processor is inserted into the platform. There is no
connection to the processor silicon for this signal and it must be pulled up
through a resistor. Refer to the appropriate platform design guidelines for
implementation details.
VTTEN
O
NOTES:
1. The 64-bit Intel® Xeon™ processor with 2 MB L2 cache only supports BR0# and BR1#. However, platforms
must terminate BR2# and BR3# to VTT
.
2. For this pin on the 64-bit Intel Xeon processor with 2 MB L2 cache, the maximum number of symmetric
agents is one. Maximum number of central agents is zero.
3. For this pin on the 64-bit Intel Xeon processor with 2 MB L2 cache, the maximum number of symmetric
agents is two. Maximum number of central agents is zero.
4. For this pin on the 64-bit Intel Xeon processor with 2 MB L2 cache, the maximum number of symmetric
agents is two. Maximum number of central agents is one.
54
Datasheet
5 Pin Listing
®
5.1
64-bit Intel Xeon™ Processor with 2 MB L2 Cache
Pin Assignments
This section provides sorted pin lists in Table 5-1 and Table 5-2. Table 5-1 is a listing of all processor pins ordered
alphabetically by pin name. Table 5-2 is a listing of all processor pins ordered by pin number.
5.1.1
Pin Listing by Pin Name
Table 5-1. Pin Listing by Pin Name (Cont’d)
Table 5-1. Pin Listing by Pin Name
Signal
Buffer Type
Signal
Buffer Type
Pin Name
Pin No.
Direction
Pin Name
Pin No.
Direction
A31#
A32#
B7
A6
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Async GTL+
Common Clk
Source Sync
Source Sync
Common Clk
Common Clk
Sys Bus Clk
Sys Bus Clk
Common Clk
Common Clk
Power/Other
Common Clk
Common Clk
Common Clk
Common Clk
Common Clk
Common Clk
Common Clk
Common Clk
Common Clk
Common Clk
Common Clk
Power/Other
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input
A3#
A4#
A22
A20
B18
C18
A19
C17
D17
A13
B16
B14
B13
A12
C15
C14
D16
D15
F15
A10
B10
B11
C12
E14
D13
A9
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
A33#
A7
A5#
A34#
C9
A6#
A35#
C8
A7#
A20M#
ADS#
F27
D19
F17
F14
E10
D9
A8#
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input
A9#
ADSTB0#
ADSTB1#
AP0#
A10#
A11#
A12#
A13#
A14#
A15#
A16#
A17#
A18#
A19#
A20#
A21#
A22#
A23#
A24#
A25#
A26#
A27#
A28#
A29#
A30#
AP1#
BCLK0
BCLK1
BINIT#
BNR#
Y4
W5
F11
F20
G7
Input
Input/Output
Input/Output
Input
BOOT_SELECT
BPM0#
BPM1#
BPM2#
BPM3#
BPM4#
BPM5#
BPRI#
F6
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input
F8
E7
F5
E8
E4
D23
D20
F12
E11
D10
AA3
BR0#
Input/Output
Input
BR1#
B8
BR2# 1
BR3# 1
BSEL0
Input
E13
D12
C11
Input
Output
Datasheet
55
Pin Listing
Table 5-1. Pin Listing by Pin Name (Cont’d)
Table 5-1. Pin Listing by Pin Name (Cont’d)
Signal
Buffer Type
Signal
Buffer Type
Pin Name
Pin No.
Direction
Pin Name
Pin No.
Direction
BSEL1
COMP0
COMP1
D0#
AB3
AD16
E16
Power/Other
Power/Other
Power/Other
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Output
D38#
D39#
AD13
AD14
AD11
AC12
AE10
AC11
AE9
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Common Clk
Common Clk
Source Sync
Source Sync
Source Sync
Source Sync
Common Clk
Common Clk
Common Clk
Common Clk
Common Clk
Source Sync
Source Sync
Source Sync
Source Sync
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input
Input
Input
D40#
Y26
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
D41#
D1#
AA27
Y24
D42#
D2#
D43#
D3#
AA25
AD27
Y23
D44#
D4#
D45#
AD10
AD8
D5#
D46#
D6#
AA24
AB26
AB25
AB23
AA22
AA21
AB20
AB22
AB19
AA19
AE26
AC26
AD25
AE25
AC24
AD24
AE23
AC23
AA18
AC20
AC21
AE22
AE20
AD21
AD19
AB17
AB16
AA16
AC17
AE13
AD18
AB15
D47#
AC9
D7#
D48#
AA13
AA14
AC14
AB12
AB13
AA11
AA10
AB10
AC8
D8#
D49#
D9#
D50#
D10#
D11#
D12#
D13#
D14#
D15#
D16#
D17#
D18#
D19#
D20#
D21#
D22#
D23#
D24#
D25#
D26#
D27#
D28#
D29#
D30#
D31#
D32#
D33#
D34#
D35#
D36#
D37#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
AD7
D58#
AE7
D59#
AC6
D60#
AC5
D61#
AA8
D62#
Y9
D63#
AB6
DBSY#
DEFER#
DBI0#
DBI1#
DBI2#
DBI3#
DP0#
DP1#
DP2#
DP3#
DRDY#
DSTBN0#
DSTBN1#
DSTBN2#
DSTBN3#
F18
C23
AC27
AD22
AE12
AB9
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
AC18
AE19
AC15
AE17
E18
Y21
Y18
Y15
Y12
56
Datasheet
Pin Listing
Table 5-1. Pin Listing by Pin Name (Cont’d)
Table 5-1. Pin Listing by Pin Name (Cont’d)
Signal
Buffer Type
Signal
Buffer Type
Pin Name
Pin No.
Direction
Pin Name
Pin No.
Direction
DSTBP0#
DSTBP1#
DSTBP2#
DSTBP3#
FERR#/PBE#
FORCEPR#
GTLREF
GTLREF
GTLREF
GTLREF
HIT#
Y20
Y17
Y14
Y11
Source Sync
Source Sync
Source Sync
Source Sync
Async GTL+
Async GTL+
Power/Other
Power/Other
Power/Other
Power/Other
Common Clk
Common Clk
Async GTL+
Async GTL+
Async GTL+
Async GTL+
Async GTL+
Common Clk
Common Clk
N/C
Input/Output
Input/Output
Input/Output
Input/Output
Output
Input
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
RESET#
RS0#
Y3
AC1
AE15
AE16
AE28
AE29
Y8
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Input
Reserved
Reserved
E27
A15
W23
W9
Reserved
Reserved
Input
Common Clk
Common Clk
Common Clk
Common Clk
Common Clk
Power/Other
Async GTL+
Power/Other
Power/Other
Async GTL+
Async GTL+
TAP
Input
E21
D22
F21
C6
Input
F23
F9
Input
RS1#
Input
Input
RS2#
Input
E22
A23
E5
Input/Output
Input/Output
Output
Input
RSP#
Input
HITM#
IERR#
SKTOCC#
SLP#
A3
Output
Input
AE6
AC30
AE4
C27
D4
IGNNE#
INIT#
C26
D6
SLEW_CTRL
SMB_PRT
SMI#
Input
Input
Output
Input
LINT0/INTR
LINT1/NMI
LOCK#
MCERR#
N/C
B24
G23
A17
D7
Input
Input
STPCLK#
TCK
Input
Input/Output
Input/Output
N/C
E24
C24
E25
A16
W6
Input
TDI
TAP
Input
Y29
AA28
AA29
AB28
AB29
AC28
AC29
AD28
AD29
AE30
B5
TDO
TAP
Output
Input
N/C
N/C
N/C
TEST_BUS
TESTHI0
TESTHI1
TESTHI2
TESTHI3
TESTHI4
TESTHI5
TESTHI6
THERMDA
THERMDC
THERMTRIP#
TMS
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Async GTL+
TAP
N/C
N/C
N/C
Input
N/C
N/C
N/C
W7
Input
N/C
N/C
N/C
W8
Input
N/C
N/C
N/C
Y6
Input
N/C
N/C
N/C
AA7
AD5
AE5
Y27
Y28
F26
A25
E19
F24
A2
Input
N/C
N/C
N/C
Input
N/C
N/C
N/C
Input
N/C
N/C
N/C
Output
Output
Output
Input
ODTEN
Power/Other
Power/Other
Input
OPTIMIZED/
COMPAT#
C1
Input
PROCHOT#
PWRGOOD
REQ0#
B25
AB7
B19
B21
C21
C20
B22
A26
D25
W3
Async GTL+
Async GTL+
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Reserved
Output
TRDY#
TRST#
Common Clk
TAP
Input
Input
Input
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Reserved
Reserved
Reserved
VCC
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
REQ1#
VCC
A8
REQ2#
VCC
A14
A18
A24
A28
A30
REQ3#
VCC
REQ4#
VCC
Reserved
Reserved
Reserved
VCC
Reserved
VCC
Reserved
Datasheet
57
Pin Listing
Table 5-1. Pin Listing by Pin Name (Cont’d)
Table 5-1. Pin Listing by Pin Name (Cont’d)
Signal
Buffer Type
Signal
Buffer Type
Pin Name
Pin No.
Direction
Pin Name
Pin No.
Direction
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
B6
B20
B26
B29
B31
C2
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
H7
H9
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
H23
H25
H27
H29
H31
J2
C4
C16
C22
C28
C30
D1
J4
J6
J8
J24
J26
J28
J30
K1
D8
D14
D18
D24
D29
D31
E2
K3
K5
K7
E6
K9
E20
E26
E28
E30
F1
K23
K25
K27
K29
K31
L2
F4
F16
F22
F29
F31
G2
L4
L6
L8
L24
L26
L28
L30
M1
M3
M5
M7
M9
M23
M25
M27
G4
G6
G8
G24
G26
G28
G30
H1
H3
H5
58
Datasheet
Pin Listing
Table 5-1. Pin Listing by Pin Name (Cont’d)
Table 5-1. Pin Listing by Pin Name (Cont’d)
Signal
Buffer Type
Signal
Buffer Type
Pin Name
Pin No.
Direction
Pin Name
Pin No.
Direction
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
M29
M31
N1
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
U7
U9
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
U23
U25
U27
U29
U31
V2
N3
N5
N7
N9
N23
N25
N27
N29
N31
P2
V4
V6
V8
V24
V26
V28
V30
W1
P4
P6
P8
P24
P26
P28
P30
R1
W25
W27
W29
W31
Y2
R3
Y16
Y22
Y30
AA1
AA4
AA6
AA20
AA26
AA31
AB2
AB8
AB14
AB18
AB24
AB30
AC3
AC4
AC16
AC22
AC31
R5
R7
R9
R23
R25
R27
R29
R31
T2
T4
T6
T8
T24
T26
T28
T30
U1
U3
U5
Datasheet
59
Pin Listing
Table 5-1. Pin Listing by Pin Name (Cont’d)
Table 5-1. Pin Listing by Pin Name (Cont’d)
Signal
Buffer Type
Signal
Buffer Type
Pin Name
Pin No.
Direction
Pin Name
Pin No.
Direction
VCC
VCC
AD2
AD6
AD20
AD26
AD30
AE3
AE8
AE14
AE18
AE24
AB4
AD4
AD1
B27
F3
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
D5
D11
D21
D27
D28
D30
E9
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
VCC
VCC
VCC
VCC
VCC
VCC
E15
E17
E23
E29
E31
F2
VCC
VCC
VCCA
VCCIOPLL
VCCPLL
VCCSENSE
VID0
VID1
VID2
VID3
VID4
VID5
VIDPWRGD
VSS
Input
Input
Input
Output
Output
Output
Output
Output
Output
Output
Input
F7
F13
F19
F25
F28
F30
G1
E3
D3
C3
B3
A1
B1
G3
A5
G5
VSS
A11
A21
A27
A29
A31
B2
G9
VSS
G25
G27
G29
G31
H2
VSS
VSS
VSS
VSS
VSS
B9
H4
VSS
B15
B17
B23
B28
B30
C7
H6
VSS
H8
VSS
H24
H26
H28
H30
J1
VSS
VSS
VSS
VSS
C13
C19
C25
C29
C31
D2
VSS
J3
VSS
J5
VSS
J7
VSS
J9
VSS
J23
60
Datasheet
Pin Listing
Table 5-1. Pin Listing by Pin Name (Cont’d)
Table 5-1. Pin Listing by Pin Name (Cont’d)
Signal
Buffer Type
Signal
Buffer Type
Pin Name
Pin No.
Direction
Pin Name
Pin No.
Direction
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
J25
J27
J29
J31
K2
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
P7
P9
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
P23
P25
P27
P29
P31
R2
K4
K6
K8
K24
K26
K28
K30
L1
R4
R6
R8
R24
R26
R28
R30
T1
L3
L5
L7
L9
T3
L23
L25
L27
L29
L31
M2
M4
M6
M8
M24
M26
M28
M30
N2
T5
T7
T9
T23
T25
T27
T29
T31
U2
U4
U6
U8
U24
U26
U28
U30
V1
N4
N6
N8
N24
N26
N28
N30
P1
V3
V5
V7
V9
V23
V25
V27
P3
P5
Datasheet
61
Pin Listing
Table 5-1. Pin Listing by Pin Name (Cont’d)
Table 5-1. Pin Listing by Pin Name (Cont’d)
Signal
Buffer Type
Signal
Buffer Type
Pin Name
Pin No.
Direction
Pin Name
Pin No.
Direction
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
V29
V31
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
VSS
VSSA
VSSSENSE
VTT
AE27
AA5
D26
A4
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Input
W2
Output
W4
W24
W26
W28
W30
Y1
VTT
B4
VTT
C5
VTT
B12
C10
E12
F10
Y10
AA12
AC10
AD12
E1
VTT
VTT
Y5
VTT
Y7
VTT
Y13
VTT
Y19
VTT
Y25
VTT
Y31
VTTEN
Output
AA2
AA9
AA15
AA17
AA23
AA30
AB1
AB5
AB11
AB21
AB27
AB31
AC2
AC7
AC13
AC19
AC25
AD3
AD9
AD15
AD17
AD23
AD31
AE2
AE11
AE21
NOTES:
1. In systems using the 64-bit Intel Xeon processor with 2 MB
L2 cache, the system designer must pull-up these signals
to the processor VTT
.
62
Datasheet
Pin Listing
5.1.2
Pin Listing by Pin Number
Table 5-2. Pin Listing by Pin Number (Cont’d)
Table 5-2. Pin Listing by Pin Number
Pin
Number
Signal Buffer
Type
Pin
Number
Signal Buffer
Type
Pin Name
Direction
Pin Name
Direction
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
C1
A21#
A22#
Source Sync Input/Output
Source Sync Input/Output
Power/Other
A1
A2
VID5
VCC
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Output
VTT
A3
SKTOCC#
VTT
Output
A13#
Source Sync Input/Output
Source Sync Input/Output
Power/Other
A4
A12#
A5
VSS
VSS
A6
A32#
Source Sync Input/Output
Source Sync Input/Output
Power/Other
A11#
Source Sync Input/Output
Power/Other
A7
A33#
VSS
A8
VCC
A5#
Source Sync Input/Output
Source Sync Input/Output
Power/Other
A9
A26#
Source Sync Input/Output
Source Sync Input/Output
Power/Other
REQ0#
VCC
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
B1
A20#
VSS
REQ1#
REQ4#
VSS
Source Sync Input/Output
Source Sync Input/Output
Power/Other
A14#
Source Sync Input/Output
Source Sync Input/Output
Power/Other
A10#
VCC
LINT0/INTR
PROCHOT#
VCC
Async GTL+
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Input
FORCEPR#
TEST_BUS
LOCK#
VCC
Async GTL+
Power/Other
Input
Input
Output
Common Clk Input/Output
Power/Other
VCCSENSE
VSS
Output
A7#
Source Sync Input/Output
Source Sync Input/Output
Power/Other
VCC
A4#
VSS
VSS
VCC
A3#
Source Sync Input/Output
Common Clk Input/Output
Power/Other
OPTIMIZED/
COMPAT#
Input
HITM#
VCC
C2
C3
VCC
VID3
VCC
VTT
Power/Other
Power/Other
Power/Other
Power/Other
Common Clk
Power/Other
TMS
TAP
Input
Output
Reserved
VSS
Reserved
Reserved
C4
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
C5
VCC
C6
RSP#
VSS
A35#
A34#
VTT
Input
VSS
C7
VCC
C8
Source Sync Input/Output
Source Sync Input/Output
Power/Other
VSS
C9
VIDPWRGD
VSS
Input
Output
Input
C10
C11
C12
C13
C14
C15
C16
C17
B2
A30#
A23#
VSS
A16#
A15#
VCC
A8#
Source Sync Input/Output
Source Sync Input/Output
Power/Other
B3
VID4
B4
VTT
B5
OTDEN
VCC
Source Sync Input/Output
Source Sync Input/Output
Power/Other
B6
B7
A31#
Source Sync Input/Output
Source Sync Input/Output
Power/Other
B8
A27#
Source Sync Input/Output
B9
VSS
Datasheet
63
Pin Listing
Table 5-2. Pin Listing by Pin Number (Cont’d)
Table 5-2. Pin Listing by Pin Number (Cont’d)
Pin
Number
Signal Buffer
Type
Pin
Number
Signal Buffer
Type
Pin Name
Direction
Pin Name
Direction
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
C30
C31
D1
A6#
VSS
Source Sync Input/Output
Power/Other
D29
D30
D31
E1
VCC
VSS
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
REQ3#
REQ2#
VCC
Source Sync Input/Output
Source Sync Input/Output
Power/Other
VCC
VTTEN
VCC
Output
Output
E2
DEFER#
TDI
Common Clk
TAP
Input
Input
E3
VID1
E4
BPM5#
IERR#
VCC
Common Clk Input/Output
VSS
Power/Other
Async GTL+
Async GTL+
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Async GTL+
Power/Other
Async GTL+
E5
Async GTL+
Power/Other
Output
IGNNE#
SMI#
Input
Input
E6
E7
BPM2#
BPM4#
VSS
Common Clk Input/Output
Common Clk Input/Output
Power/Other
VCC
E8
VSS
E9
VCC
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
E20
E21
E22
E23
E24
E25
E26
E27
E28
E29
E30
E31
F1
AP0#
BR2#1
VTT
Common Clk Input/Output
VSS
Common Clk
Power/Other
Input
VCC
D2
VSS
A28#
Source Sync Input/Output
Source Sync Input/Output
Power/Other
D3
VID2
Output
Input
A24#
D4
STPCLK#
VSS
VSS
D5
COMP1
VSS
Power/Other
Power/Other
Input
D6
INIT#
MCERR#
VCC
Input
D7
Common Clk Input/Output
Power/Other
DRDY#
TRDY#
VCC
Common Clk Input/Output
D8
Common Clk
Power/Other
Common Clk
Input
D9
AP1#
BR3# 1
VSS
Common Clk Input/Output
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
Common Clk
Power/Other
Input
RS0#
HIT#
Input
Common Clk Input/Output
Power/Other
A29#
Source Sync Input/Output
Source Sync Input/Output
Power/Other
VSS
A25#
TCK
TAP
Input
VCC
TDO
TAP
Output
A18#
Source Sync Input/Output
Source Sync Input/Output
Source Sync Input/Output
Power/Other
VCC
Power/Other
Async GTL+
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
A17#
FERR#/PBE#
VCC
Output
A9#
VCC
VSS
ADS#
BR0#
VSS
Common Clk Input/Output
Common Clk Input/Output
Power/Other
VCC
VSS
VCC
RS1#
BPRI#
VCC
Common Clk
Common Clk
Power/Other
Reserved
Input
Input
F2
VSS
F3
VID0
Output
F4
VCC
Reserved
VSSSENSE
VSS
Reserved
Output
F5
BPM3#
BPM0#
VSS
Common Clk Input/Output
Common Clk Input/Output
Power/Other
Power/Other
Power/Other
Power/Other
F6
F7
VSS
F8
BPM1#
Common Clk Input/Output
64
Datasheet
Pin Listing
Table 5-2. Pin Listing by Pin Number (Cont’d)
Table 5-2. Pin Listing by Pin Number (Cont’d)
Pin
Number
Signal Buffer
Type
Pin
Number
Signal Buffer
Type
Pin Name
Direction
Pin Name
Direction
F9
F10
F11
F12
F13
F14
F15
F16
F17
F18
F19
F20
F21
F22
F23
F24
F25
F26
F27
F28
F29
F30
F31
G1
GTLREF
VTT
Power/Other
Power/Other
Input
H2
H3
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
BINIT#
BR1#
VSS
Common Clk Input/Output
H4
Common Clk
Power/Other
Input
H5
H6
ADSTB1#
A19#
Source Sync Input/Output
Source Sync Input/Output
Power/Other
H7
H8
VCC
H9
ADSTB0#
DBSY#
VSS
Source Sync Input/Output
Common Clk Input/Output
Power/Other
H23
H24
H25
H26
H27
H28
H29
H30
H31
J1
BNR#
RS2#
VCC
Common Clk Input/Output
Common Clk
Power/Other
Power/Other
TAP
Input
GTLREF
TRST#
VSS
Input
Input
Power/Other
Async GTL+
Async GTL+
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Async GTL+
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
THERMTRIP#
A20M#
VSS
Output
Input
J2
J3
VCC
J4
VSS
J5
VCC
J6
VSS
J7
G2
VCC
J8
G3
VSS
J9
G4
VCC
J23
J24
J25
J26
J27
J28
J29
J30
J31
K1
G5
VSS
G6
VCC
G7
BOOT_SELECT
VCC
Input
Input
G8
G9
VSS
G23
G24
G25
G26
G27
G28
G29
G30
G31
H1
LINT1/NMI
VCC
VSS
VCC
VSS
K2
VCC
K3
VSS
K4
VCC
K5
VSS
K6
VCC
K7
Datasheet
65
Pin Listing
Table 5-2. Pin Listing by Pin Number (Cont’d)
Table 5-2. Pin Listing by Pin Number (Cont’d)
Pin
Number
Signal Buffer
Type
Pin
Number
Signal Buffer
Type
Pin Name
Direction
Pin Name
Direction
K8
K9
VSS
VCC
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VCC
VSS
VCC
VSS
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
M27
M28
M29
M30
M31
N1
VCC
VSS
VCC
VSS
VCC
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
K23
K24
K25
K26
K27
K28
K29
K30
K31
L1
N2
N3
N4
N5
N6
N7
L2
N8
L3
N9
L4
N23
N24
N25
N26
N27
N28
N29
N30
N31
P1
L5
L6
L7
L8
L9
L23
L24
L25
L26
L27
L28
L29
L30
L31
M1
P2
P3
P4
P5
P6
P7
M2
P8
M3
P9
M4
P23
P24
P25
P26
P27
P28
P29
P30
P31
R1
M5
M6
M7
M8
M9
M23
M24
M25
M26
66
Datasheet
Pin Listing
Table 5-2. Pin Listing by Pin Number (Cont’d)
Table 5-2. Pin Listing by Pin Number (Cont’d)
Pin
Number
Signal Buffer
Type
Pin
Number
Signal Buffer
Type
Pin Name
Direction
Pin Name
Direction
R2
R3
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
U8
U9
VSS
VCC
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Reserved
R4
U23
U24
U25
U26
U27
U28
U29
U30
U31
V1
VCC
R5
VSS
R6
VCC
R7
VSS
R8
VCC
R9
VSS
R23
R24
R25
R26
R27
R28
R29
R30
R31
T1
VCC
VSS
VCC
VSS
V2
VCC
V3
VSS
V4
VCC
V5
VSS
V6
VCC
V7
VSS
T2
V8
VCC
T3
V9
VSS
T4
V23
V24
V25
V26
V27
V28
V29
V30
V31
W1
W2
W3
W4
W5
W6
W7
W8
W9
W23
W24
W25
W26
VSS
T5
VCC
T6
VSS
T7
VCC
T8
VSS
T9
VCC
T23
T24
T25
T26
T27
T28
T29
T30
T31
U1
VSS
VCC
VSS
VCC
VSS
Reserved
VSS
Reserved
Power/Other
Sys Bus Clk
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
BCLK1
TESTHI0
TESTHI1
TESTHI2
GTLREF
GTLREF
VSS
Input
Input
Input
Input
Input
Input
U2
U3
U4
U5
U6
VCC
U7
VSS
Datasheet
67
Pin Listing
Table 5-2. Pin Listing by Pin Number (Cont’d)
Table 5-2. Pin Listing by Pin Number (Cont’d)
Pin
Number
Signal Buffer
Type
Pin
Number
Signal Buffer
Type
Pin Name
Direction
Pin Name
Direction
W27
W28
W29
W30
W31
Y1
VCC
VSS
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Reserved
AA7
AA8
TESTHI4
D61#
VSS
Power/Other
Input
Source Sync Input/Output
Power/Other
VCC
AA9
VSS
AA10
AA11
AA12
AA13
AA14
AA15
AA16
AA17
AA18
AA19
AA20
AA21
AA22
AA23
AA24
AA25
AA26
AA27
AA28
AA29
AA30
AA31
AB1
D54#
D53#
VTT
Source Sync Input/Output
Source Sync Input/Output
Power/Other
VCC
VSS
Y2
VCC
D48#
D49#
VSS
Source Sync Input/Output
Source Sync Input/Output
Power/Other
Y3
Reserved
BCLK0
VSS
Reserved
Input
Y4
Sys Bus Clk
Power/Other
Power/Other
Power/Other
Common Clk
Y5
D33#
VSS
Source Sync Input/Output
Power/Other
Y6
TESTHI3
VSS
Input
Y7
D24#
D15#
VCC
Source Sync Input/Output
Source Sync Input/Output
Power/Other
Y8
RESET#
D62#
Input
Y9
Source Sync Input/Output
Power/Other
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y17
Y18
Y19
Y20
Y21
Y22
Y23
Y24
Y25
Y26
Y27
Y28
Y29
Y30
Y31
AA1
AA2
AA3
AA4
AA5
AA6
VTT
D11#
D10#
VSS
Source Sync Input/Output
Source Sync Input/Output
Power/Other
DSTBP3#
DSTBN3#
VSS
Source Sync Input/Output
Source Sync Input/Output
Power/Other
D6#
Source Sync Input/Output
Source Sync Input/Output
Power/Other
DSTBP2#
DSTBN2#
VCC
Source Sync Input/Output
Source Sync Input/Output
Power/Other
D3#
VCC
D1#
Source Sync Input/Output
DSTBP1#
DSTBN1#
VSS
Source Sync Input/Output
Source Sync Input/Output
Power/Other
N/C
N/C
N/C
N/C
N/C
N/C
VSS
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
DSTBP0#
DSTBN0#
VCC
Source Sync Input/Output
Source Sync Input/Output
Power/Other
VCC
VSS
AB2
VCC
D5#
Source Sync Input/Output
Source Sync Input/Output
Power/Other
AB3
BSEL1
VCCA
VSS
Output
Input
D2#
AB4
VSS
AB5
D0#
Source Sync Input/Output
AB6
D63#
PWRGOOD
VCC
Source Sync Input/Output
THERMDA
THERMDC
N/C
Power/Other
Power/Other
N/C
Output
Output
N/C
AB7
Async GTL+
Power/Other
Input
AB8
AB9
DBI3#
D55#
VSS
Source Sync Input/Output
Source Sync Input/Output
Power/Other
VCC
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
AB10
AB11
AB12
AB13
AB14
AB15
AB16
AB17
VSS
VCC
D51#
D52#
VCC
Source Sync Input/Output
Source Sync Input/Output
Power/Other
VSS
BSEL0
VCC
Output
Input
D37#
D32#
D31#
Source Sync Input/Output
Source Sync Input/Output
Source Sync Input/Output
VSSA
VCC
68
Datasheet
Pin Listing
Table 5-2. Pin Listing by Pin Number (Cont’d)
Table 5-2. Pin Listing by Pin Number (Cont’d)
Pin
Number
Signal Buffer
Type
Pin
Number
Signal Buffer
Type
Pin Name
Direction
Pin Name
Direction
AB18
AB19
AB20
AB21
AB22
AB23
AB24
AB25
AB26
AB27
AB28
AB29
AB30
AB31
AC1
VCC
D14#
D12#
VSS
Power/Other
AC29
AC30
AC31
AD1
N/C
SLEW_CTRL
VCC
N/C
N/C
Source Sync Input/Output
Source Sync Input/Output
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Input
VCCPLL
VCC
Input
D13#
D9#
Source Sync Input/Output
Source Sync Input/Output
Power/Other
AD2
AD3
VSS
VCC
D8#
AD4
VCCIOPLL
TESTHI5
VCC
Input
Input
Source Sync Input/Output
Source Sync Input/Output
Power/Other
AD5
D7#
AD6
VSS
AD7
D57#
D46#
VSS
Source Sync Input/Output
Source Sync Input/Output
Power/Other
N/C
N/C
N/C
N/C
AD8
N/C
N/C
AD9
VCC
VSS
Power/Other
Power/Other
Reserved
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
AE2
D45#
D40#
VTT
Source Sync Input/Output
Source Sync Input/Output
Power/Other
Reserved
VSS
Reserved
AC2
Power/Other
Power/Other
Power/Other
D38#
D39#
VSS
Source Sync Input/Output
Source Sync Input/Output
Power/Other
AC3
VCC
VCC
D60#
D59#
VSS
AC4
AC5
Source Sync Input/Output
Source Sync Input/Output
Power/Other
COMP0
VSS
Power/Other
Power/Other
Input
AC6
AC7
D36#
D30#
VCC
Source Sync Input/Output
Source Sync Input/Output
Power/Other
AC8
D56#
D47#
VTT
Source Sync Input/Output
Source Sync Input/Output
Power/Other
AC9
AC10
AC11
AC12
AC13
AC14
AC15
AC16
AC17
AC18
AC19
AC20
AC21
AC22
AC23
AC24
AC25
AC26
AC27
AC28
D29#
DBI1#
VSS
Source Sync Input/Output
Source Sync Input/Output
Power/Other
D43#
D41#
VSS
Source Sync Input/Output
Source Sync Input/Output
Power/Other
D21#
D18#
VCC
Source Sync Input/Output
Source Sync Input/Output
Power/Other
D50#
DP2#
VCC
D34#
DP0#
VSS
Source Sync Input/Output
Common Clk Input/Output
Power/Other
D4#
Source Sync Input/Output
Source Sync Input/Output
Common Clk Input/Output
Power/Other
N/C
N/C
N/C
N/C
N/C
N/C
VCC
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Async GTL+
D25#
D26#
VCC
D23#
D20#
VSS
Source Sync Input/Output
Source Sync Input/Output
Power/Other
VSS
VSS
AE3
VCC
Source Sync Input/Output
Source Sync Input/Output
Power/Other
AE4
SMB_PRT
TESTHI6
SLP#
D58#
VCC
Output
Input
AE5
AE6
Input
D17#
DBI0#
N/C
Source Sync Input/Output
Source Sync Input/Output
AE7
Source Sync Input/Output
Power/Other
AE8
N/C
N/C
AE9
D44#
Source Sync Input/Output
Datasheet
69
Pin Listing
Table 5-2. Pin Listing by Pin Number (Cont’d)
Pin
Number
Signal Buffer
Type
Pin Name
Direction
AE10
AE11
AE12
AE13
AE14
AE15
AE16
AE17
AE18
AE19
AE20
AE21
AE22
AE23
AE24
AE25
AE26
AE27
AE28
AE29
AE30
D42#
VSS
Source Sync Input/Output
Power/Other
DBI2#
D35#
Source Sync Input/Output
Source Sync Input/Output
Power/Other
VCC
Reserved
Reserved
DP3#
VCC
Reserved
Reserved
Reserved
Reserved
Common Clk Input/Output
Power/Other
DP1#
D28#
Common Clk Input/Output
Source Sync Input/Output
Power/Other
VSS
D27#
Source Sync Input/Output
Source Sync Input/Output
Power/Other
D22#
VCC
D19#
Source Sync Input/Output
Source Sync Input/Output
Power/Other
D16#
VSS
Reserved
Reserved
N/C
Reserved
Reserved
N/C
Reserved
Reserved
N/C
NOTES:
1. In systems using the 64-bit Intel Xeon processor with 2 MB
L2 cache, the system designer must pull-up these signals
to the processor VTT
.
70
Datasheet
6 Thermal Specifications
6.1
Package Thermal Specifications
The 64-bit Intel Xeon processor with 2 MB L2 cache requires a thermal solution to maintain
temperatures within operating limits. Any attempt to operate the processor outside these operating
limits may result in permanent damage to the processor and potentially other components within
the system. As processor technology changes, thermal management becomes increasingly crucial
when building computer systems. Maintaining the proper thermal environment is key to reliable,
long-term system operation.
A complete solution includes both component and system level thermal management features.
Component level thermal solutions can include active or passive heatsinks attached to the
processor Integrated Heat Spreader (IHS). Typical system level thermal solutions may consist of
system fans combined with ducting and venting.
®
For more information on designing a component level thermal solution, refer to the 64-bit Intel
Xeon™ Processor with 2 MB L2 Cache Thermal/Mechanical Design Guidelines.
Note: The boxed processor will ship with a component thermal solution. Refer to Chapter 8 for details on
the boxed processor.
6.1.1
Thermal Specifications
To allow the optimal operation and long-term reliability of Intel processor-based systems, the
processor must remain within the minimum and maximum case temperature (T
) specifications
CASE
as defined by the applicable thermal profile (see Figure 6-1, Table 6-2 and Table 6-3). Thermal
solutions not designed to provide this level of thermal capability may affect the long-term
reliability of the processor and system. For more details on thermal solution design, please refer to
the appropriate processor thermal/mechanical design guideline.
The 64-bit Intel Xeon processor with 2 MB L2 cache uses a methodology for managing processor
temperatures which is intended to support acoustic noise reduction through fan speed control and
assure processor reliability. Selection of the appropriate fan speed will be based on the temperature
reported by the processor’s Thermal Diode. If the diode temperature is greater than or equal to
Tcontrol (see Section 6.2.7), then the processor case temperature must remain at or below the
temperature as specified by the thermal profile (see Figure 6-1). If the diode temperature is less
than Tcontrol, then the case temperature is permitted to exceed the thermal profile, but the diode
temperature must remain at or below Tcontrol. Systems that implement fan speed control must be
designed to take these conditions into account. Systems that do not alter the fan speed only need to
guarantee the case temperature meets the thermal profile specifications.
Intel has developed two thermal profiles, either of which can be implemented with the 64-bit Intel
Xeon processor with 2 MB L2 cache. Both ensure adherence to Intel reliability requirements.
Thermal Profile A is representative of a volumetrically unconstrained thermal solution (i.e.
industry enabled 2U heatsink). In this scenario, it is expected that the Thermal Control Circuit
(TCC) would only be activated for very brief periods of time when running the most power
intensive applications. Thermal Profile B is indicative of a constrained thermal environment (i.e.
1U). Because of the reduced cooling capability represented by this thermal solution, the probability
of TCC activation and performance loss is increased. Additionally, utilization of a thermal solution
that does not meet Thermal Profile B will violate the thermal specifications and may result in
Datasheet
71
Thermal Specifications
permanent damage to the processor. Intel has developed these thermal profiles to allow OEMs to
choose the thermal solution and environmental parameters that best suit their platform
implementation. Refer to the appropriate thermal/mechanical design guide for details on system
thermal solution design, thermal profiles, and environmental considerations.
The upper point of the thermal profile consists of the Thermal Design Power (TDP) defined in
Table 6-1 and the associated T
Thermal Profile B (x = TDP and y = T
value. It should be noted that the upper point associated with
CASE
@ TDP) represents a thermal solution design
CASE_MAX_B
point. In actuality the processor case temperature will never reach this value due to TCC activation
(see Figure 6-1). The lower point of the thermal profile consists of x = P and y =
CONTROL_BASE
T
@ P
. Pcontrol is defined as the processor power at which T
,
CASE_MAX
CONTROL_BASE
CASE
calculated from the thermal profile, corresponds to the lowest possible value of Tcontrol. This point
is associated with the Tcontrol value (see Section 6.2.7) However, because Tcontrol represents a
diode temperature, it is necessary to define the associated case temperature. This is T
@
CASE_MAX
P
. Please see Section 6.2.7 and the appropriate thermal/mechanical design guide for
CONTROL_BASE
proper usage of the Tcontrol specification.
The case temperature is defined at the geometric top center of the processor IHS. Analysis
indicates that real applications are unlikely to cause the processor to consume maximum power
dissipation for sustained time periods. Intel recommends that complete thermal solution designs
target the Thermal Design Power (TDP) indicated in Table 6-1, instead of the maximum processor
power consumption. The Thermal Monitor feature is intended to help protect the processor in the
event that an application exceeds the TDP recommendation for a sustained time period. For more
details on this feature, refer to Section 6.2. To ensure maximum flexibility for future requirements,
systems should be designed to the Flexible Motherboard (FMB) guidelines, even if a processor
with a lower thermal dissipation is currently planned. Thermal Monitor or Thermal Monitor 2
feature must be enabled for the processor to remain within specification.
®
Table 6-1. 64-bit Intel Xeon™ Processor with 2 MB L2 Cache Thermal Specifications
Core
Frequency
(GHz)
Maximum
Power
(W)
Thermal
DesignPower
(W)
Minimum
TCASE
(°C)
Maximum
TCASE
Notes
(°C)
2.80 GHz - FMB
(PRB = 1)
See Figure 6-1, Table 6-2
or Table 6-3
120
110
5
1,2,3,4,5,6,7
NOTES:
1. These values are specified at VCC_MAX for all processor frequencies. Systems must be designed to ensure
the processor is not to be subjected to any static VCC and ICC combination wherein VCC exceeds VCC_MAX at
specified ICC. Please refer to the VCC static and transient tolerance specifications in Chapter 2.
2. Listed frequencies are not necessarily committed production frequencies.
3. Maximum Power is the maximum thermal power that can be dissipated by the processor through the
integrated heat spreader (IHS). Maximum Power is measured at maximum TCASE
.
4. Thermal Design Power (TDP) should be used for processor/chipset thermal solution design targets. TDP is
not the maximum power that the processor can dissipate. TDP is measured at maximum TCASE
5. These specifications are based on final silicon characterization.
.
6. Power specifications are defined at all VIDs found in Table 2-8. The 64-bit Intel® Xeon™ processor with 2 MB
L2 cache may be shipped under multiple VIDs listed for each frequency.
7. FMB, or Flexible Motherboard, guidelines provide a design target for meeting all planned processor
frequency requirements. FMB is a design target that is sequential in time.
72
Datasheet
Thermal Specifications
®
Figure 6-1. 64-bit Intel Xeon™ Processor with 2 MB L2 Cache Thermal Profiles
A and B (PRB = 1)
90
80
70
60
50
40
30
20
10
0
TCASE MAX_B
TDP
TCASE MAX_A
TDP
@
@
Thermal Profile B
y = 0.320 * x +43.4
TCASE_MAX_B is a thermal
solution design point. In
actuality, units will not
exceed TCASE_MAX_A due to
TCC activation.
TCASE MAX
@
Thermal Profile A
y = 0.270 * x +43.1
PCONTROL_BASE
0
10
20
30
40
50
60
70
80
90
100
110
120
PCONTROL_BASE_B
TDP
Power [W]
PCONTROL_BASE_A
NOTES:
1. Thermal Profile A is representative of a volumetrically unconstrained platform. Please refer to Table 6-2 for
discrete points that constitute the thermal profile.
2. Implementation of Thermal Profile A should result in virtually no TCC activation. Furthermore, utilization of
thermal solutions that do not meet processor Thermal Profile A will result in increased probability of TCC
activation and may incur measurable performance loss. (See Section 6.2 for details on TCC activation).
3. Thermal Profile B is representative of a volumetrically constrained platform. Please refer to Table 6-3 for
discrete points that constitute the thermal profile.
4. Implementation of Thermal Profile B will result in increased probability of TCC activation and may incur
measurable performance loss. Furthermore, utilization of thermal solutions that do not meet Thermal Profile
B do not meet the processor’s thermal specifications and may result in permanent damage to the processor.
5. Refer to the 64-bit Intel® Xeon™ Processor with 2 MB L2 Cache Thermal/Mechanical Design Guidelines for
system and environmental implementation details.
Datasheet
73
Thermal Specifications
®
Table 6-2. 64-bit Intel Xeon™ Processor with 2 MB L2 Cache Thermal Profile A
(PRB = 1)
Power [W]
CONTROL_BASE_A = 27
TCASE_MAX [deg C]
Power [W]
68
TCASE_MAX [deg C]
P
50
51
51
52
52
53
53
54
54
55
56
56
57
57
58
58
59
59
60
60
60
61
61
62
63
63
64
64
65
65
66
66
67
67
68
68
69
70
70
71
71
72
72
73
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
64
66
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
®
Table 6-3. 64-bit Intel Xeon™ Processor with 2 MB L2 Cache Thermal Profile B
(PRB = 1)
Power [W]
CONTROL_BASE_B = 22
TCASE_MAX [deg C]
Power [W]
66
TCASE_MAX [deg C]
P
50
51
52
52
53
54
54
55
56
56
57
57
58
59
59
60
61
61
62
63
63
64
65
65
66
66
67
68
68
69
70
70
71
72
72
73
73
74
75
75
76
77
77
78
79
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
74
Datasheet
Thermal Specifications
®
Table 6-4. 64-bit Intel Xeon™ MV 3.20 GHz Processor Thermal Specifications
Core
Frequency
(GHz)
Maximum
Power
(W)
Thermal
Design Power
(W)
Minimum
TCASE
(°C)
Maximum
TCASE
Notes
(°C)
3.20 GHz
(PRB = 1)
See Figure 6-2,
Table 6-5 or Table 6-6
97
90
5
1,2,3,4,5,6
NOTES:
1. These values are specified at VCC_MAX for all processor frequencies. Systems must be designed to ensure
the processor is not to be subjected to any static VCC and ICC combination wherein VCC exceeds VCC_MAX at
specified ICC. Please refer to the VCC static and transient tolerance specifications in Section 2.
2. Listed frequencies are not necessarily committed production frequencies.
3. Maximum Power is the maximum thermal power that can be dissipated by the processor through the
integrated heat spreader (IHS). Maximum Power is measured at maximum TCASE
.
4. Thermal Design Power (TDP) should be used for processor/chipset thermal solution design targets. TDP is
not the maximum power that the processor can dissipate. TDP is measured at maximum TCASE
5. These specifications are based on pre-silicon estimates.
.
6. Power specifications are defined at all VIDs found in Table 2-3. The 64-bit Intel® Xeon™MV processor may
be shipped under multiple VIDs listed for each frequency.
®
Figure 6-2. 64-bit Intel Xeon™ MV 3.20 GHz Processor Thermal Profiles A and B (PRB = 1)
80
TCASE MAX_B
TDP
@
70
TCASE MAX_A
TDP
@
Thermal Profile B
y = 0.320 * x +42.8
60
TCASE MAX
PCONTROL_BASE
@
TCASE_MAX_B is a thermal
solution design point. In
actuality, units will not
exceed TCASE_MAX_A due to
TCC activation.
50
40
Thermal Profile A
y = 0.270 * x +42.5
30
20
10
0
0
10
20
PCONTROL_BASE_B
30
40
50
60
70
80
90
100
TDP
Power [W]
PCONTROL_BASE_A
NOTES:
1. Thermal Profile A is representative of a volumetrically unconstrained platform. Please refer to Table 6-5 for
discrete points that constitute the thermal profile.
2. Implementation of Thermal Profile A should result in virtually no TCC activation. Furthermore, utilization of
thermal solutions that do not meet processor Thermal Profile A will result in increased probability of TCC
activation and may incur measurable performance loss. (See Section 6.2 for details on TCC activation).
3. Thermal Profile B is representative of a volumetrically constrained platform. Please refer to Table 6-6 for
discrete points that constitute the thermal profile.
4. Implementation of Thermal Profile B will result in increased probability of TCC activation and may incur
measurable performance loss. Furthermore, utilization of thermal solutions that do not meet Thermal Profile
B do not meet the processor’s thermal specifications and may result in permanent damage to the processor.
Datasheet
75
Thermal Specifications
®
Table 6-5. 64-bit Intel Xeon™ MV 3.20 GHz Processor Thermal Profile A (PRB = 1)
Power [W]
TCASE_MAX [deg C]
Power [W]
TCASE_MAX [deg C]
PCONTROL_BASE_A = 27
50
50
51
51
52
52
53
53
54
54
55
55
56
57
57
58
58
60
62
64
64
66
68
70
72
74
76
78
80
82
84
86
88
90
59
59
60
60
60
61
61
62
62
63
64
64
65
65
66
66
67
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
®
Table 6-6. 64-bit Intel Xeon™ MV 3.20 GHz Processor Thermal Profile B (PRB = 1)
Power [W]
CONTROL_BASE_B = 22
TCASE_MAX [deg C]
Power [W]
56
TCASE_MAX [deg C]
P
50
50
51
52
52
53
54
54
55
56
56
57
58
58
59
59
60
61
61
62
63
63
64
65
65
66
66
67
68
68
69
70
70
71
72
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
76
Datasheet
Thermal Specifications
®
Table 6-7. 64-bit Intel Xeon™ LV 3 GHz Processor Thermal Specifications
Core
Frequency
(GHz)
Maximum
Power
(W)
Thermal
Design Power
(W)
Minimum
TCASE
(°C)
Maximum
TCASE
Notes
(°C)
3 GHz
(PRB = 1)
See Figure 6-3
and Table 6-8
60
55
5
1,2,3,4,5,6
NOTES:
1. These values are specified at VCC_MAX for all processor frequencies. Systems must be designed to ensure
the processor is not to be subjected to any static VCC and ICC combination wherein VCC exceeds VCC_MAX at
specified ICC. Please refer to the VCC static and transient tolerance specifications in Section 2.
2. Listed frequencies are not necessarily committed production frequencies.
3. Maximum Power is the maximum thermal power that can be dissipated by the processor through the
integrated heat spreader (IHS). Maximum Power is measured at maximum TCASE
.
4. Thermal Design Power (TDP) should be used for processor/chipset thermal solution design targets. TDP is
not the maximum power that the processor can dissipate. TDP is measured at maximum TCASE
5. These specifications are based on pre-silicon estimates.
.
6. Power specifications are defined at all VIDs found in Table 2-3. The 64-bit Intel® Xeon™ LV processor may
be shipped under multiple VIDs listed for each frequency.
®
Figure 6-3. 64-bit Intel Xeon™ LV Processor Thermal Profiles A and B (PRB = 0)
90
TCASE MAX
TDP
@
80
70
60
50
40
30
20
10
0
Thermal Profile
Y = 0.55 * x +55
0
5
10
15
20
25
30
35
40
45
50
55
60
TDP
Power [W]
NOTES:
1. Please refer to Table 6-8 for discrete points that constitute the thermal profile.
2. Utilization of thermal solutions that do not meet the Thermal Profile do not meet the processor’s thermal
specifications and may result in permanent damage to the processor.
Datasheet
77
Thermal Specifications
®
Table 6-8. 64-bit Intel Xeon™ LV 3 GHz Processor Thermal Profile (PRB = 0)
Pow er [W ]
TCASE_MAX [deg C]
Pow er [W ]
TCASE_M AX [deg C]
0
2
4
6
55
56
57
58
59
61
62
63
64
65
66
67
68
70
71
30
32
34
36
38
40
42
44
46
48
50
52
54
55
72
73
74
75
76
77
79
80
81
82
83
84
85
86
8
10
12
14
16
18
20
22
24
26
28
6.1.2
Thermal Metrology
The maximum case temperatures (T
) are specified in Table 6-2, Table 6-3, Table 6-5,
CASE
Table 6-6, and Table 6-8 measured at the geometric top center of the processor integrated heat
spreader (IHS). Figure 6-4 illustrates the location where T temperature measurements should
CASE
be made. For detailed guidelines on temperature measurement methodology, refer to the
appropriate thermal/mechanical design guide.
Figure 6-4. Case Temperature (T
) Measurement Location
CASE
Measure from Edge of Processor
21.25 mm
[0.837 in.
21.25 mm
[0.837 in.
Measure TCASE at
this point.
42.5 mm FC-mPGA4 Package
Note: Figure is not to scale and is for reference only.
78
Datasheet
Thermal Specifications
6.2
Processor Thermal Features
6.2.1
Thermal Monitor
The Thermal Monitor feature helps control the processor temperature by activating the Thermal
Control Circuit (TCC) when the processor silicon reaches its maximum operating temperature. The
TCC reduces processor power consumption as needed by modulating (starting and stopping) the
internal processor core clocks. The Thermal Monitor (or Thermal Monitor 2) feature must be
enabled for the processor to be operating within specifications. The temperature at which Thermal
Monitor activates the thermal control circuit is not user configurable and is not software visible.
Bus traffic is snooped in the normal manner, and interrupt requests are latched (and serviced during
the time that the clocks are on) while the TCC is active.
When the Thermal Monitor is enabled, and a high temperature situation exists (i.e. TCC is active),
the clocks will be modulated by alternately turning the clocks off and on at a duty cycle specific to
the processor (typically 30 -50%). Clocks will not be off for more than 3 microseconds when the
TCC is active. Cycle times are processor speed dependent and will decrease as processor core
frequencies increase. A small amount of hysteresis has been included to prevent rapid active/
inactive transitions of the TCC when the processor temperature is near its maximum operating
temperature. Once the temperature has dropped below the maximum operating temperature, and
the hysteresis timer has expired, the TCC goes inactive and clock modulation ceases.
With a thermal solution designed to meet Thermal Profile A, it is anticipated that the TCC would
only be activated for very short periods of time when running the most power intensive
applications. The processor performance impact due to these brief periods of TCC activation is
expected to be so minor that it would be immeasurable. A thermal solution that is designed to
Thermal Profile B may cause a noticeable performance loss due to increased TCC activation.
Thermal Solutions that exceed Thermal Profile B will exceed the maximum temperature
specification and affect the long-term reliability of the processor. In addition, a thermal solution
that is significantly under designed may not be capable of cooling the processor even when the
TCC is active continuously. Refer to the appropriate thermal/mechanical design guide for
information on designing a thermal solution.
The duty cycle for the TCC, when activated by the Thermal Monitor, is factory configured and
cannot be modified. The Thermal Monitor does not require any additional hardware, software
drivers, or interrupt handling routines.
6.2.2
Thermal Monitor 2
The 64-bit Intel Xeon processor with 2 MB L2 cache also supports an additional power reduction
capability known as Thermal Monitor 2. This mechanism provides an efficient means for limiting
the processor temperature by reducing the power consumption within the processor. The Thermal
Monitor (or Thermal Monitor 2) feature must be enabled for the processor to be operating within
specifications.
Note: Not all Intel Xeon processors may be capable of supporting Thermal Monitor 2. Details on
®
which processor frequencies support Thermal Monitor 2 are provided in the 64-bit Intel Xeon™
Processor with 800 MHz System Bus (1 MB and 2 MB L2 Cache Versions) Specification Update.
When Thermal Monitor 2 is enabled, and a high temperature situation is detected, the Thermal
Control Circuit (TCC) will be activated. The TCC causes the processor to adjust its operating
frequency (via the bus multiplier) and input voltage (via the VID signals). This combination of
reduced frequency and VID results in a reduction to the processor power consumption.
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79
Thermal Specifications
A processor enabled for Thermal Monitor 2 includes two operating points, each consisting of a
specific operating frequency and voltage. The first operating point represents the normal operating
condition for the processor. Under this condition, the core-frequency-to-system-bus multiple
utilized by the processor is that contained in the IA32_FLEX_BRVID_SEL MSR and the VID is
that specified in Table 2-8. These parameters represent normal system operation.
The second operating point consists of both a lower operating frequency and voltage. When the
TCC is activated, the processor automatically transitions to the new frequency. This transition
occurs very rapidly (on the order of 5 µs). During the frequency transition, the processor is unable
to service any bus requests, and consequently, all bus traffic is blocked. Edge-triggered interrupts
will be latched and kept pending until the processor resumes operation at the new frequency.
Once the new operating frequency is engaged, the processor will transition to the new core
operating voltage by issuing a new VID code to the voltage regulator. The voltage regulator must
support dynamic VID steps in order to support Thermal Monitor 2. During the voltage change, it
will be necessary to transition through multiple VID codes to reach the target operating voltage.
Each step will be one VID table entry (see Table 2-8). The processor continues to execute
instructions during the voltage transition. Operation at the lower voltage reduces the power
consumption of the processor.
A small amount of hysteresis has been included to prevent rapid active/inactive transitions of the
TCC when the processor temperature is near its maximum operating temperature. Once the
temperature has dropped below the maximum operating temperature, and the hysteresis timer has
expired, the operating frequency and voltage transition back to the normal system operating point.
Transition of the VID code will occur first, in order to insure proper operation once the processor
reaches its normal operating frequency. Refer to Figure 6-5 for an illustration of this ordering.
Figure 6-5. Demand Based Switching Frequency and Voltage Ordering
TTM2
Temperature
fMAX
fTM2
Frequency
VNOM
VTM2
Vcc
Time
T(hysterisis)
The PROCHOT# signal is asserted when a high temperature situation is detected, regardless of
whether Thermal Monitor or Thermal Monitor 2 is enabled.
If a processor has its Thermal Control Circuit activated via a Thermal Monitor 2 event, and an
Enhanced Intel SpeedStep technology transition to a higher target frequency (through the
applicable MSR write) is attempted, the frequency transition will be delayed until the TCC is
deactivated and the Thermal Monitor 2 event is complete.
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Datasheet
Thermal Specifications
6.2.3
On-Demand Mode
The processor provides an auxiliary mechanism that allows system software to force the processor
to reduce its power consumption. This mechanism is referred to as “On-Demand” mode and is
distinct from the Thermal Monitor and Thermal Monitor 2 features. On-Demand mode is intended
as a means to reduce system level power consumption. Systems using the 64-bit
Intel Xeon processor with 2 MB L2 cache must not rely on software usage of this mechanism to
limit the processor temperature.
If bit 4 of the IA32_CLOCK_MODULATION MSR is written to a ‘1’, the processor will
immediately reduce its power consumption via modulation (starting and stopping) of the internal
core clock, independent of the processor temperature. When using On-Demand mode, the duty
cycle of the clock modulation is programmable via bits 3:1 of the same
IA32_CLOCK_MODULATION MSR. In On-Demand mode, the duty cycle can be programmed
from 12.5% on/ 87.5% off to 87.5% on/12.5% off in 12.5% increments. On-Demand mode may be
used in conjunction with the Thermal Monitor. If the system tries to enable On-Demand mode at
the same time the TCC is engaged, the factory configured duty cycle of the TCC will override the
duty cycle selected by the On-Demand mode.
6.2.4
PROCHOT# Signal Pin
An external signal, PROCHOT# (processor hot) is asserted when the processor die temperature has
reached its factory configured trip point. If Thermal Monitor is enabled (note that Thermal Monitor
must be enabled for the processor to be operating within specification), the TCC will be active
when PROCHOT# is asserted. The processor can be configured to generate an interrupt upon the
assertion or de-assertion of PROCHOT#. Refer to the Intel Architecture Software Developer’s
Manual(s) for specific register and programming details.
PROCHOT# is designed to assert at or a few degrees higher than maximum T
(as specified by
CASE
Thermal Profile A) when dissipating TDP power, and cannot be interpreted as an indication of
processor case temperature. This temperature delta accounts for processor package, lifetime and
manufacturing variations and attempts to ensure the Thermal Control Circuit is not activated below
maximum T
when dissipating TDP power. There is no defined or fixed correlation between
CASE
the PROCHOT# trip temperature, the case temperature or the thermal diode temperature. Thermal
solutions must be designed to the processor specifications and cannot be adjusted based on
experimental measurements of T
, PROCHOT#, or Tdiode on random processor samples.
CASE
6.2.5
FORCEPR# Signal Pin
The FORCEPR# (force power reduction) input can be used by the platform to cause the processor
to activate the TCC. If the Thermal Monitor is enabled, the TCC will be activated upon the
assertion of the FORCEPR# signal. The TCC will remain active until the system deasserts
FORCEPR#. FORCEPR# is an asynchronous input. FORCEPR# can be used to thermally protect
other system components. To use the VR as an example, when the FORCEPR# pin is asserted, the
TCC circuit in the processor will activate, reducing the current consumption of the processor and
the corresponding temperature of the VR.
If should be noted that assertion of the FORCEPR# does not automatically assert PROCHOT#. As
mentioned previously, the PROCHOT# signal is asserted when a high temperature situation is
detected. A minimum pulse width of 500 µs is recommend when the FORCEPR# is asserted by the
system. Sustained activation of the FORCEPR# pin may cause noticeable platform performance
degradation.
Datasheet
81
Thermal Specifications
Refer to the appropriate platform design guidelines for details on implementing the FORCEPR#
signal feature.
6.2.6
6.2.7
THERMTRIP# Signal Pin
Regardless of whether or not Thermal Monitor or Thermal Monitor 2 is enabled, in the event of a
catastrophic cooling failure, the processor will automatically shut down when the silicon has
reached an elevated temperature (refer to the THERMTRIP# definition in Table 4-1). At this point,
the system bus signal THERMTRIP# will go active and stay active as described in Table 4-1.
THERMTRIP# activation is independent of processor activity and does not generate any bus
cycles.
TCONTROL and Fan Speed Reduction
Tcontrol is a temperature specification based on a temperature reading from the thermal diode. The
value for Tcontrol will be calibrated in manufacturing and configured for each processor. The
Tcontrol temperature for a given processor can be obtained by reading the
IA32_TEMPERATURE_TARGET MSR in the processor. The Tcontrol value that is read from the
IA32_TEMPERATURE_TARGET MSR must be converted from Hexadecimal to Decimal and
added to a base value. The base value is 50 ° C for the 64-bit Intel Xeon processor with 2 MB L2
cache.
The value of Tcontrol may vary from 0x00h to 0x1Eh. Systems that support the 64-bit
Intel Xeon processor with 2 MB L2 cache must implement BIOS changes to detect which
processor is present, and then select from the appropriate Tcontrol_base value.
When Tdiode is above Tcontrol, then T
must be at or below T
as defined by the
CASE_MAX
CASE
thermal profile. (See Figure 6-1; Table 6-2 and Table 6-3). Otherwise, the processor temperature
can be maintained at Tcontrol.
6.2.8
Thermal Diode
The processor incorporates an on-die thermal diode. A thermal sensor located on the system board
may monitor the die temperature of the processor for thermal management/long term die
temperature change purposes. Table 6-9 and Table 6-10 provide the diode parameter and interface
specifications. This thermal diode is separate from the Thermal Monitor’s thermal sensor and
cannot be used to predict the behavior of the Thermal Monitor.
Table 6-9. Thermal Diode Parameters
Symbol
IFW
Symbol
Forward Bias Current
Min
Typ
Max
Unit
Notes
11
187
µA
1
n
Diode ideality factor
Series Resistance
1.0083
3.242
1.011
3.33
1.0183
3.594
2,3,4
2,3,5
RT
Ω
NOTES:
1. Intel does not support or recommend operation of the thermal diode under reverse bias.
2. Characterized at 75°C.
3. Not 100% tested. Specified by design characterization.
4. The ideality factor, n, represents the deviation from ideal diode behavior as exemplified by the diode
equation: IFW = IS * (eqVD/nkT - 1)
Where IS = saturation current, q = electronic charge, VD = voltage across the diode, k = Boltzmann Constant,
and T = absolute temperature (Kelvin).
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Datasheet
Thermal Specifications
5. The series resistance, RT, is provided to allow for a more accurate measurement of the junction temperature.
RT, as defined, includes the pins of the processor but does not include any socket resistance or board trace
resistance between the socket and external remote diode thermal sensor. RT can be used by remote diode
thermal sensors with automatic series resistance cancellation to calibrate out this error term. Another
application that a temperature offset can be manually calculated and programmed into an offset register in
the remote diode thermal sensors as exemplified by the equation: Terror = [RT * (N-1) * IFW_min] / [nk/q *ln N]
Where Terror = sensor temperature error, N =sensor current ratio, k = Boltzmann Constant, q= electronic
charge.
Table 6-10. Thermal Diode Interface
Pin Name
Pin Number
Pin Description
THERMDA
THERMDC
Y27
Y28
diode anode
diode cathode
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83
Thermal Specifications
84
Datasheet
7 Features
7.1
Power-On Configuration Options
Several configuration options can be configured by hardware. The processor samples its hardware
configuration at reset, on the active-to-inactive transition of RESET#. For specifics on these
options, please refer to Table 7-1.
The sampled information configures the processor for subsequent operation. These configuration
options cannot be changed except by another reset. All resets reconfigure the processor, for reset
purposes, the processor does not distinguish between a “warm” reset and a “power-on” reset.
Table 7-1. Power-On Configuration Option Pins
Configuration Option
Pin
Notes
Output tri state
SMI#
INIT#
A7#
1,2
1,2
Execute BIST (Built-In Self Test)
In Order Queue de-pipelining (set IOQ depth to 1)
Disable MCERR# observation
Disable BINIT# observation
Disable bus parking
1,2
A9#
1,2
A10#
A15#
BR[3:0]#
A31#
1,2
1,2
Symmetric agent arbitration ID
Disable Hyper-Threading Technology
1,2,3
1,2
NOTES:
1. Asserting this signal during RESET# will select the corresponding option.
2. Address pins not identified in this table as configuration options should not be asserted during RESET#.
3. The 64-bit Intel® Xeon™ processor with 2 MB L2 cache only uses the BR0# and BR1# signals. Platforms
must not utilize BR2# and BR3# signals.
7.2
Clock Control and Low Power States
The processor allows the use of HALT, Stop Grant and Sleep states to reduce power consumption
by stopping the clock to internal sections of the processor, depending on each particular state. See
Figure 7-1 for a visual representation of the processor low power states.
The 64-bit Intel Xeon processor with 2 MB L2 cache supports the Enhanced HALT Power Down
state. Refer to Figure 7-1 and the following sections. Note: Not all Intel Xeon processors are
capable of supporting the Enhanced HALT state. More details on which processor frequencies
®
support the Enhanced HALT state are provided in the 64-bit Intel Xeon™ Processor with 800
MHz System Bus (1 MB and 2 MB L2 Cache Versions) Specification Update.
The Stop Grant state requires chipset and BIOS support on multiprocessor systems. In a
multiprocessor system, all the STPCLK# signals are bussed together, thus all processors are
affected in unison. The Hyper-Threading Technology feature adds the conditions that all logical
processors share the same STPCLK# signal internally. When the STPCLK# signal is asserted, the
processor enters the Stop Grant state, issuing a Stop Grant Special Bus Cycle (SBC) for each
processor or logical processor. The chipset needs to account for a variable number of processors
Datasheet
85
Features
asserting the Stop Grant SBC on the bus before allowing the processor to be transitioned into one
of the lower processor power states. Refer to the applicable chipset specification for more
information.
Due to the inability of processors to recognize bus transactions during the Sleep state,
multiprocessor systems are not allowed to simultaneously have one processor in Sleep state and the
other processors in Normal or Stop Grant state.
7.2.1
7.2.2
Normal State
This is the normal operating state for the processor.
HALT or Enhanced HALT Power Down States
The Enhanced HALT Power Down state is configured and enabled via the BIOS. If the Enhanced
HALT state is not enabled, the default Power Down state entered will be HALT. Refer to the
sections below for details on HALT and Enhanced HALT states.
7.2.2.1
HALT Power Down State
HALT is a low power state entered when the processor executes the HALT or MWAIT instruction.
When one of the logical processors executes the HALT or MWAIT instruction, that logical
processor is halted; however, the other processor continues normal operation. The processor will
transition to the Normal state upon the occurrence of SMI#, BINIT#, INIT#, LINT[1:0] (NMI,
INTR), or an interrupt delivered over the front side bus. RESET# will cause the processor to
immediately initialize itself.
The return from a System Management Interrupt (SMI) handler can be to either Normal Mode or
the HALT Power Down state. See the IA-32 Intel® Architecture Software Developer's Manual,
Volume 3: System Programmer's Guide for more information.
The system can generate a STPCLK# while the processor is in the HALT Power Down state. When
the system deasserts the STPCLK# interrupt, the processor will return execution to the HALT state.
While in HALT Power Down state, the processor will process front side bus snoops and interrupts.
7.2.2.2
Enhanced HALT Power Down State
Enhanced HALT state is a low power state entered when all logical processors have executed the
HALT or MWAIT instructions and Enhanced HALT state has been enabled via the BIOS. When
one of the logical processors executes the HALT instruction, that logical processor is halted;
however, the other processor continues normal operation. The Enhanced HALT state is generally a
lower power state than the Stop Grant state.
The processor will automatically transition to a lower core frequency and voltage operating point
before entering the Enhanced HALT state. Note that the processor FSB frequency is not altered;
only the internal core frequency is changed. When entering the low power state, the processor will
first switch to the lower bus ratio and then transition to the lower VID.
While in the Enhanced HALT state, the processor will process bus snoops.
The processor exits the Enhanced HALT state when a break event occurs. When the processor
exists the Enhanced HALT state, it will first transition the VID to the original value and then
change the bus ratio back to the original value.
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Datasheet
Features
Figure 7-1. Stop Clock State Machine
HALT or MWAIT Instruction and
HALT Bus Cycle Generated
Enhanced HALT or HALT State
Normal State
INIT#, BINIT#, INTR, NMI, SMI#,
RESET#, FSB interrupts
BCLK running
Snoops and interrupts allowed
Normal execution
Snoop
Event
Occurs
Snoop
Event
Serviced
STPCLK#
Asserted
STPCLK#
De-asserted
Enhanced HALT Snoop or HALT
Snoop State
BCLK running
Service snoops to caches
Snoop Event Occurs
Snoop Event Serviced
Stop Grant State
Stop Grant Snoop State
BCLK running
BCLK running
Snoops and interrupts allowed
Service snoops to caches
SLP#
SLP#
Asserted
De-asserted
Sleep State
BCLK running
No snoops or interrupts
allowed
7.2.3
Stop Grant State
When the STPCLK# pin is asserted, the Stop Grant state of the processor is entered 20 bus clocks
after the response phase of the processor-issued Stop Grant Acknowledge special bus cycle. Once
the STPCLK# pin has been asserted, it may only be deasserted once the processor is in the Stop
Grant state. For the 64-bit Intel Xeon processor with 2 MB L2 cache, both logical processors must
be in the Stop Grant state before the deassertion of STPCLK#.
Since the AGTL+ signal pins receive power from the front side bus, these pins should not be driven
(allowing the level to return to VTT) for minimum power drawn by the termination resistors in this
state. In addition, all other input pins on the front side bus should be driven to the inactive state.
BINIT# will not be serviced while the processor is in Stop Grant state. The event will be latched
and can be serviced by software upon exit from the Stop Grant state.
RESET# will cause the processor to immediately initialize itself, but the processor will stay in Stop
Grant state. A transition back to the Normal state will occur with the de-assertion of the STPCLK#
signal. When re-entering the Stop Grant state from the Sleep state, STPCLK# should only be
deasserted one or more bus clocks after the deassertion of SLP#.
Datasheet
87
Features
A transition to the Grant Snoop state will occur when the processor detects a snoop on the front
side bus (see Section 7.2.4). A transition to the Sleep state (see Section 7.2.5) will occur with the
assertion of the SLP# signal.
While in the Stop Grant state, SMI#, INIT#, BINIT# and LINT[1:0] will be latched by the
processor, and only serviced when the processor returns to the Normal state. Only one occurrence
of each event will be recognized upon return to the Normal state.
While in Stop Grant state, the processor will process snoops on the front side bus and it will latch
interrupts delivered on the front side bus.
The PBE# signal can be driven when the processor is in Stop Grant state. PBE# will be asserted if
there is any pending interrupt latched within the processor. Pending interrupts that are blocked by
the EFLAGS.IF bit being clear will still cause assertion of PBE#. Assertion of PBE# indicates to
system logic that it should return the processor to the Normal state.
7.2.4
Enhanced HALT Snoop or HALT Snoop State, Stop Grant
Snoop State
The Enhanced HALT Snoop state is used in conjunction with the Enhanced HALT state. If
Enhanced HALT state is not enabled in the BIOS, the default Snoop state entered will be the HALT
Snoop state. Refer to the sections below for details on HALT Snoop state, Grant Snoop state and
Enhanced HALT Snoop state.
7.2.4.1
HALT Snoop State, Stop Grant Snoop State
The processor will respond to snoop or interrupt transactions on the front side bus while in Stop
Grant state or in HALT Power Down state. During a snoop or interrupt transaction, the processor
enters the HALT/Grant Snoop state. The processor will stay in this state until the snoop on the front
side bus has been serviced (whether by the processor or another agent on the front side bus) or the
interrupt has been latched. After the snoop is serviced or the interrupt is latched, the processor will
return to the Stop Grant state or HALT Power Down state, as appropriate.
7.2.4.2
Enhanced HALT Snoop State
The Enhanced HALT Snoop state is the default Snoop state when the Enhanced HALT state is
enabled via the BIOS. The processor will remain in the lower bus ratio and VID operating point of
the Enhanced HALT state.
While in the Enhanced HALT Snoop state, snoops and interrupt transactions are handled the same
way as in the HALT Snoop state. After the snoop is serviced or the interrupt is latched, the
processor will return to the Enhanced HALT state.
7.2.5
Sleep State
The Sleep state is a very low power state in which each processor maintains its context, maintains
the phase-locked loop (PLL), and has stopped most of internal clocks. The Sleep state can only be
entered from Stop Grant state. Once in the Stop Grant state, the processor will enter the Sleep state
upon the assertion of the SLP# signal. The SLP# pin has a minimum assertion of one BCLK
period. The SLP# pin should only be asserted when the processor is in the Stop Grant state. For 64-
bit Intel Xeon processors with 2 MB L2 cache, the SLP# pin may only be asserted when all logical
processors are in the Stop Grant state. SLP# assertions while the processors are not in the Stop
Grant state are out of specification and may results in illegal operation.
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Snoop events that occur while in Sleep state or during a transition into or out of Sleep state will
cause unpredictable behavior.
In the Sleep state, the processor is incapable of responding to snoop transactions or latching
interrupt signals. No transitions or assertions of signals (with the exception of SLP# or RESET#)
are allowed on the front side bus while the processor is in Sleep state. Any transition on an input
signal before the processor has returned to Stop Grant state will result in unpredictable behavior.
If RESET# is driven active while the processor is in the Sleep state, and held active as specified in
the RESET# pin specification, then the processor will reset itself, ignoring the transition through
Stop Grant state. If RESET# is driven active while the processor is in the Sleep state, the SLP# and
STPCLK# signals should be deasserted immediately after RESET# is asserted to ensure the
processor correctly executes the reset sequence.
When the processor is in Sleep state, it will not respond to interrupts or snoop transactions.
7.3
Demand Based Switching (DBS) with Enhanced
Intel SpeedStep Technology
®
®
Demand Based Switching (DBS) with Enhanced Intel SpeedStep technology enables the
processor to switch between multiple frequency and voltage points, which may result in platform
power savings. In order to support this technology, the system must support dynamic VID
transitions. Switching between voltage / frequency states is software controlled.
Note: Not all processors are capable of supporting Enhanced Intel SpeedStep technology. More
®
details on which processor frequencies support this feature are provided in the 64-bit Intel Xeon™
Processor with 800 MHz System Bus (1 MB and 2 MB L2 Cache Versions) Specification Update.
Enhanced Intel SpeedStep technology is a technology that creates processor performance states (P-
states). P-states are power consumption and capability states within the Normal state. Enhanced
Intel SpeedStep technology enables real-time dynamic switching between frequency and voltage
points. It alters the performance of the processor by changing the bus to core frequency ratio and
voltage. This allows the processor to run at different core frequencies and voltages to best serve the
performance and power requirements of the processor and system. Note that the front side bus is
not altered; only the internal core frequency is changed. In order to run at reduced power
consumption, the voltage is altered in step with the bus ratio.
The following are key features of Enhanced Intel SpeedStep technology:
1. Multiple voltage / frequency operating points provide optimal performance at reduced power
consumption.
2. Voltage / Frequency selection is software controlled by writing to processor MSR’s (Model
Specific Registers), thus eliminating chipset dependency.
If the target frequency is higher than the current frequency, V is incremented in steps (+12.5
CC
mV) by placing a new value on the VID signals. The Phase Lock Loop (PLL) then locks to the new
frequency. Note that the top frequency for the processor can not be exceeded.
If the target frequency is lower than the current frequency, the PLL locks to the new frequency. The
V
is then decremented in step (-12.5 mV) by changing the target VID through the VID signals.
CC
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8 Boxed Processor Specifications
8.1
Introduction
Intel boxed processors are intended for system integrators who build systems from components
available through distribution channels. The 64-bit Intel Xeon processor with 2 MB L2 cache and
64-bit Intel Xeon LV 3 GHz processor will be offered as Intel boxed processors.
Intel will offer boxed 64-bit Intel Xeon processors with 2 MB L2 cache and 64-bit Intel Xeon LV
3 GHz processors in three product configurations available for each processor frequency: 1U
passive, 2U passive and 2U+ active. Although the active thermal solution mechanically fits into a
2U keepout, additional design considerations may need to be addressed to provide sufficient
airflow to the fan inlet.
The active thermal solution is primarily designed to be used in a pedestal chassis where sufficient
air inlet space is present and side directional airflow is not an issue. The 1U and 2U passive thermal
solutions require the use of chassis ducting and are targeted for use in rack mount servers. The
retention solution used for these products is called the Common Enabling Kit, or CEK. The CEK
base is compatible with all three thermal solutions.
The active heatsink solution for the boxed 64-bit Intel Xeon processor with 2 MB L2 cache will be
a 4-pin pulse width modulated (PWM) T-diode controlled solution. Use of a 4-pin PWM T-diode
controlled active thermal solution helps customers meet acoustic targets in pedestal platforms
through the platform’s ability to directly control the active thermal solution. It may be necessary to
modify existing baseboard designs with 4-pin CPU fan headers and other required circuitry for
PWM operation. If a 4-pin PWM T-diode controlled active thermal solution is connected to an
older 3-pin CPU fan header, the thermal solution will revert back to a thermistor controlled mode.
Please see the Section 8.3, “Electrical Requirements” on page 8-101 for more details.
Figure 8-1 through Figure 8-3 are representations of the three heatsink solutions that will be
offered as part of a boxed processor. Figure 8-4 shows an exploded view of the boxed processor
thermal solution and the other CEK retention components.
Figure 8-1. 1U Passive CEK Heatsink
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Figure 8-2. 2U Passive CEK Heatsink
Figure 8-3. Active CEK Heatsink (Representation Only)
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®
Figure 8-4. Passive 64-bit Intel Xeon™ Processor with 2 MB L2 Cache Thermal
Solution (2U and Larger)
Heat sink screw
springs
Heat sink
screws
Heat sink
Heat sink standoffs
Thermal Interface
Material
Motherboard
and
processor
Protective Tape
CEK spring
Chassis pan
NOTE:
1. The heatsink in this image is for reference only, and may not represent any of the actual boxed processor
heatsinks.
2. The screws, springs, and standoffs will be captive to the heatsink. This image shows all of the components in
an exploded view.
3. It is intended that the CEK spring will ship with the base board and be pre-attached prior to shipping.
8.2
Mechanical Specifications
This section documents the mechanical specifications of the boxed processor.
8.2.1
Boxed Processor Heatsink Dimensions (CEK)
The boxed processor will be shipped with an unattached thermal solution. Clearance is required
around the thermal solution to ensure unimpeded airflow for proper cooling. The physical space
requirements and dimensions for the boxed processor and assembled heatsink are shown in
Figure 8-5 through Figure 8-9. Figure 8-10 through Figure 8-11 are the mechanical drawings for
the 4-pin server board fan header and 4-pin connector used for the active CEK fan heatsink
solution.
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Boxed Processor Specifications
Figure 8-5. Top-Side Board Keepout Zones (Part 1)
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Figure 8-6. Top-Side Board Keepout Zones (Part 2)
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Figure 8-7. Bottom-Side Board Keepout Zones
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Figure 8-8. Board Mounting Hole Keepout Zones
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Figure 8-9. Volumetric Height Keep-Ins
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Figure 8-10. 4-Pin Fan Cable Connector (For Active CEK Heatsink)
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Figure 8-11. 4-Pin Base Board Fan Header (For Active CEK Heatsink)
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8.2.2
Boxed Processor Heatsink Weight
8.2.2.1
Thermal Solution Weight
The 2U passive and 2U+ active heatsink solutions will not exceed a mass of 1050 grams. Note that
this is per processor, so a dual processor system will have up to 2100 grams total mass in the
heatsinks. The 1U CEK heatsink will not exceed a mass of 700 grams, for a total of 1400 grams in
a dual processor system. This large mass will require a minimum chassis stiffness to be met in
order to withstand force during shock and vibration.
See Section 3 for details on the processor weight.
8.2.3
Boxed Processor Retention Mechanism and Heatsink
Support (CEK)
Baseboards and chassis designed for use by a system integrator should include holes that are in
proper alignment with each other to support the boxed processor. Refer to the Server System
Infrastructure Specification (SSI-EEB 3.51) or see http://www.ssiforum.org for details on the hole
locations.
Figure 8-4 illustrates the new Common Enabling Kit (CEK) retention solution. The CEK is
designed to extend air-cooling capability through the use of larger heatsinks with minimal airflow
blockage and bypass. CEK retention mechanisms can allow the use of much heavier heatsink
masses compared to legacy limits by using a load path directly attached to the chassis pan. The
CEK spring on the secondary side of the baseboard provides the necessary compressive load for
the thermal interface material. The baseboard is intended to be isolated such that the dynamic loads
from the heatsink are transferred to the chassis pan via the stiff screws and standoffs. The retention
scheme reduces the risk of package pullout and solder joint failures.
The baseboard mounting holes for the CEK solution are the same location as the legacy server
processor hole locations, as specified by the SSI EEB 3.5. However, the CEK assembly requires
larger diameter holes to compensate for the CEK spring embosses. The holes now need to be 10.2
mm [0.402 in.] in diameter.
All components of the CEK heatsink solution will be captive to the heatsink and will only require a
Phillips screwdriver to attach to the chassis pan. When installing the CEK, the CEK screws should
be tightened until they will no longer turn easily. This should represent approximately 8 inch-
pounds of torque. Avoid applying more than 10 inch-pounds of torque; otherwise, damage may
occur to retention mechanism components.
®
For further details on the CEK thermal solution, refer to the 64-bit Intel Xeon™ Processor with 2
MB L2 Cache Thermal/Mechanical Design Guidelines (see Section 1.2).
8.3
Electrical Requirements
8.3.1
Fan Power Supply (Active CEK)
The 4-pin PWM/T-diode-controlled active thermal solution is being offered to help provide better
control over pedestal chassis acoustics. This is achieved though more accurate measurement of
processor die temperature through the processor’s temperature diode (T-diode). Fan RPM is
modulated through the use of an ASIC located on the baseboard, that sends out a PWM control
signal to the 4th pin of the connector labeled as Control. This thermal solution requires a constant
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Boxed Processor Specifications
+12 V supplied to pin 2 of the active thermal solution and does not support variable voltage control
or 3-pin PWM control. See Table 8-2 for details on the 3- and 4-pin active heatsink solution
connectors.
If the new 4-pin active fan heatsink solution is connected to an older 3-pin baseboard CPU fan
header it will default back to a thermistor controlled mode, allowing compatibility with existing
designs. When operating in thermistor controlled mode, fan RPM is automatically varied based on
the T
temperature measured by a thermistor located at the fan inlet. It may be necessary to
INLET
change existing baseboard designs to support the new 4-pin active heatsink solution if PWM/T-
diode control is desired. It may also be necessary to verify that the larger 4-pin fan connector will
not interfere with other components installed on the baseboard.
The fan power header on the baseboard must be positioned to allow the fan heatsink power cable to
reach it. The fan power header identification and location must be documented in the suppliers
platform documentation, or on the baseboard itself. The baseboard fan power header should be
positioned within 177.8 mm [7 in.] from the center of the processor socket.
Table 8-1. PWM Fan Frequency Specifications for 4-Pin Active CEK Thermal Solution
Min
Frequency
Nominal
Frequency
Max
Frequency
Description
Unit
PWM Control Frequency Range 21,000
25,000
28,000
Hz
Table 8-2. Fan Specifications for 4-pin Active CEK Thermal Solution
Typ
Steady
Max
Steady
Max
Startup
Description
Min
Unit
+12 V: 12 volt fan power supply
IC: Fan Current Draw
10.8
N/A
2
12
1
12
1.25
2
13.2
1.5
2
V
A
SENSE: SENSE frequency
2
Pulses per fan
revolution
Figure 8-12. Fan Cable Connector Pin Out for 4-Pin Active CEK Thermal Solution
Table 8-3. Fan Cable Connector Pin Out for 4-Pin Active CEK Thermal Solution
Pin Number
Signal
Color
1
2
3
4
Ground
Black
Yellow
Green
Blue
Power: (+12 V)
Sense: 2 pulses per revolution
Control: 21 KHz-28 KHz
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Table 8-4. Fan Cable Connector Supplier and Part Number
Vendor
3-Pin Connector Part Number
4-Pin Connector Part Number
AMP*
Fan Connector: 643815-3
Header: 640456-3
N/A
Walden*
Molex*
Fan Connector: 22-01-3037
Header: 22-23-2031
Fan Connector: 47054-1000
Header: 47053-1000
Wieson*
N/A
Fan Connector: 2510C888-001
Header: 2366C888-007
Foxconn*
N/A
Fan Connector: N/A
Header: HF27040-M1
This section describes the cooling requirements of the heatsink solution utilized by the boxed
processor.
8.3.2
Boxed Processor Cooling Requirements
As previously stated the boxed processor will be available in three product configurations. Each
configuration will require unique design considerations. Meeting the processor’s temperature
specifications is also the function of the thermal design of the entire system, and ultimately the
responsibility of the system integrator. The processor temperature specifications are found in
Section 6 of this document.
8.3.2.1
1U Passive CEK Heatsink (1U Form Factor)
In the 1U configuration it is assumed that a chassis duct will be implemented to provide 15 CFM of
airflow to pass through the heatsink fins. The duct should be designed as precisely as possible and
should not allow any air to bypass the heatsink (0” bypass) and a back pressure of 0.38 in. H O. It
2
is assumed that a 40 °C T is met. This requires a superior chassis design to limit the T
at or
LA
RISE
below 5 ° C with an external ambient temperature of 35 ° C. Following these guidelines will allow
the designer to meet Thermal Profile B and conform to the thermal requirements of the processor.
8.3.2.2
8.3.2.3
2U Passive CEK Heatsink (2U and above Form Factor)
Once again a chassis duct is required for the 2U passive heatsink. In this configuration Thermal
Profile A (see Chapter 6) should be followed by supplying 22 CFM of airflow through the fins of
the heatsink with a 0” or no duct bypass and a back pressure of 0.14 in. H O. The T temperature
2
LA
of 40 °C should be met. This may require the use of superior design techniques to keep T
at or
RISE
below 5 °C based on an ambient external temperature of 35 ° C.
2U+ Active CEK Thermal Solution (2U+ and above Pedestal)
This thermal solution was designed to help pedestal chassis users to meet the thermal processor
requirements without the use of chassis ducting. It may be necessary to implement some form of
chassis air guide or air duct to meet the T temperature of 40 ° C depending on the pedestal
LA
chassis layout. Also, while the active thermal solution is designed to mechanically fit into a 2U
chassis, it may require additional space at the top of the thermal solution to allow sufficient airflow
into the heatsink fan. Therefore, additional design criteria may need to be considered if this thermal
solution is used in a 2U rack mount chassis, or in a chassis that has drive bay obstructions above the
inlet to the fan heatsink.
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Boxed Processor Specifications
Thermal Profile A should be used to help determine the thermal performance of the platform.
Once again it is recommended that the ambient air temperature outside of the chassis be kept at or
below 35 ° C. The air passing directly over the processor thermal solution should not be preheated
by other system components. Meeting the processor’s temperature specification is the
responsibility of the system integrator.
8.4
Boxed Processor Contents
A direct chassis attach method must be used to avoid problems related to shock and vibration, due
to the weight of the thermal solution required to cool the processor. The board must not bend
beyond specification in order to avoid damage. The boxed processor contains the components
necessary to solve both issues. The boxed processor will include the following items:
• 64-bit Intel Xeon processor with 2 MB L2 cache or 64-bit Intel Xeon LV 3 GHz processor
• Unattached (Active or Passive) Thermal Solution
• Four screws, four springs, and four heatsink standoffs (all captive to the heatsink)
• Thermal Interface Material (pre-applied on heatsink)
• Installation Manual
®
• Intel Inside Logo
The other items listed in Figure 8-4 that are required to compete this solution will be shipped with
either the chassis or boards. They are as follows:
• CEK Spring (supplied by baseboard vendors)
• Heatsink Standoffs (supplied by chassis vendors)
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9 Debug Tools Specifications
Please refer to the ITP700 Debug Port Design Guide for information regarding debug tool
specifications. Section 1.2 provides collateral details.
9.1
Debug Port System Requirements
The 64-bit Intel Xeon processor with 2 MB L2 cache debug port is the command and control
interface for the In-Target Probe (ITP) debugger. The ITP enables run-time control of the
processors for system debug. The debug port, which is connected to the front side bus, is a
combination of the system, JTAG and execution signals. There are several mechanical, electrical
and functional constraints on the debug port that must be followed. The mechanical constraint
requires the debug port connector to be installed in the system with adequate physical clearance.
Electrical constraints exist due to the mixed high and low speed signals of the debug port for the
processor. While the JTAG signals operate at a maximum of 75 MHz, the execution signals operate
at the common clock front side bus frequency (200 MHz). The functional constraint requires the
debug port to use the JTAG system via a handshake and multiplexing scheme.
In general, the information in this chapter may be used as a basis for including all run-control tools
in 64-bit Intel Xeon processor with 2 MB L2 cache-based system designs, including tools from
vendors other than Intel.
Note: The debug port and JTAG signal chain must be designed into the processor board to utilize the ITP
for debug purposes.
9.2
Target System Implementation
9.2.1
System Implementation
Specific connectivity and layout guidelines for the Debug Port are provided in the ITP700 Debug
Port Design Guide.
9.3
Logic Analyzer Interface (LAI)
Intel is working with two logic analyzer vendors to provide logic analyzer interfaces (LAIs) for use
in debugging 64-bit Intel Xeon processor with 2 MB L2 cache-based systems. Tektronix* and
Agilent* should be contacted to obtain specific information about their logic analyzer interfaces.
The following information is general in nature. Specific information must be obtained from the
logic analyzer vendor.
Due to the complexity of 64-bit Intel Xeon processor with 2 MB L2 cache-based multiprocessor
systems, the LAI is critical in providing the ability to probe and capture front side bus signals.
There are two sets of considerations to keep in mind when designing a 64-bit Intel Xeon processor
with 2 MB L2 cache-based system that can make use of an LAI: mechanical and electrical.
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Debug Tools Specifications
9.3.1
Mechanical Considerations
The LAI is installed between the processor socket and the processor. The LAI pins plug into the
socket, while the processor pins plug into a socket on the LAI. Cabling that is part of the LAI
egresses the system to allow an electrical connection between the processor and a logic analyzer.
The maximum volume occupied by the LAI, known as the keepout volume, as well as the cable
egress restrictions, should be obtained from the logic analyzer vendor. System designers must
make sure that the keepout volume remains unobstructed inside the system. Note that it is possible
that the keepout volume reserved for the LAI may include differerent requirements from the space
normally occupied by the heatsink. If this is the case, the logic analyzer vendor will provide a
cooling solution as part of the LAI.
9.3.2
Electrical Considerations
The LAI will also affect the electrical performance of the front side bus, therefore it is critical to
obtain electrical load models from each of the logic analyzer vendors to be able to run system level
simulations to prove that their tool will work in the system. Contact the logic analyzer vendor for
electrical specifications and load models for the LAI solution they provide.
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