S3014D-1 [ROCHESTER]
Clock Recovery Circuit, 1-Func, PQCC44, PLASTIC, LCC-44;
| 型号： | S3014D-1 |
| 厂家： | 
Rochester Electronics |
| 描述： | Clock Recovery Circuit, 1-Func, PQCC44, PLASTIC, LCC-44 ATM 异步传输模式 电信 电信集成电路 |
| 文件： | 总10页 (文件大小：99K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
DEVICE SPECIFICATION
SONET/SDH CLOCK RECOVERY AND SYNTHESIS UNIT
S3014
GENERAL DESCRIPTION
FEATURES
• Complies with ANSI, Bellcore, and CCITT
specifications for jitter tolerance
• On-chip high frequency PLL with internal loop
filter for clock generation or clock recovery
• Supports clock generation for STS-3/STM-1
(155.52 MHz)
• Supports clock recovery for STS-3/STM-1
(155.52 Mbit/s) or STS-12/STM-4
(622.08 Mbit/s) NRZ data
• Selectable 19.44 MHz, 51.84 MHz, or
155.52 MHz reference frequency
• Lock detect—monitors transition density
and run length
The function of the S3014 clock synthesis and recov-
ery unit is to derive high speed timing signals for
SONET/SDH-based equipment. The S3014 is imple-
mented using AMCC’s proven Phase Locked Loop
(PLL) technology.
In Clock Recovery mode, the S3014 receives either
an STS-3/STM-1 or STS-12/STM-4 scrambled NRZ
signal and recovers the clock from the data. The chip
outputs a differential ECL bit clock and retimed data.
In Clock Synthesis mode, the S3014 receives a
19.44, 51.84, or 155.52 MHz reference clock and out-
puts an STS-3/STM-1 or STS-12/STM-4 differential
ECL clock.
• Low power
• Low-jitter ECL interface
• Small 44 PLCC or CLCC package
• TTL reference clock output
The S3014 utilizes an on-chip PLL which consists of
a phase detector, a loop filter, and a voltage con-
trolled oscillator (VCO). The phase detector
compares the phase relationship between the VCO
output and the REFCLK input, a loop filter converts
the phase detector output into a smooth DC voltage,
and the DC voltage is input to the VCO whose fre-
quency is varied by this voltage. A block diagram is
shown in Figure 1.
Figure 1. System Block Diagram
CAP1
LOOP
VCO
FILTER
CAP2
2
3
REFCKINP/N
TSTCLKEN
SEL(2:0)
REFCKOUT
2
SERCLKOP/N
CLOCK
DIVIDER
LOCK
DETECTOR
LOCKDET
RST
PHASE DETECTOR
2
SERDATOP/N
LOS
2
SERDATIP/N
1
S3014
SONET/SDH CLOCK RECOVERY AND SYNTHESIS UNIT
CHARACTERISTICS
S3014 OVERVIEW
Performance
Clock Recovery Mode
The S3014 PLL complies with the minimum jitter toler-
ance for clock recovery proposed for SONET/SDH
equipment defined by the T1X1.6/91-022 document,
when used with differential inputs and outputs as
shown in Figure 2.
In the Clock Recovery mode, the S3014 supports
clock recovery for the STS-3/STM-1 and STS-12/
STM-4 rates. In this mode, ECL differential serial data is
input to the chip at the rate specified by the three SEL
pins, and clock recovery is performed on the incoming
data stream. An external ECL differential reference
clock (19.44, 51.84, or 155.52 MHz) is required to
minimize the PLL lock time and provide a stable output
clock source in the absence of serial input data.
Retimed data and clock are output from the S3014.
Input Jitter Tolerance
Input jitter tolerance is defined as the peak to peak
amplitude of sinusoidal jitter applied on the input sig-
nal that causes an equivalent 1 dB optical/electrical
power penalty. SONET input jitter tolerance require-
ments are shown in Figure 2. The measurement
condition is the input jitter amplitude which causes an
equivalent of 1 dB power penalty.
Clock Synthesis Mode
In the Clock Synthesis mode, the S3014 synthesizes up
to the STS-3/STM-1 and STS-12/STM-4 clock rates
from either a 19.44 MHz, 51.84 MHz, or 155.52 MHz
input reference frequency. STS-3/STM-1 jitter generation
is compliant with the SONET/SDH requirement for
0.01 U.I. (rms) maximum, given 14.1 ps (rms) jitter on
REFCLK in the 12 KHz to 1 MHz frequency band.
Jitter Generation
Jitter generation is defined as the amount of jitter at
the OC-N/STS-N output of a SONET equipment.
Jitter generation shall not exceed 0.01 UI rms in OC-3
mode and 0.03 UI rms in OC-12 mode when measured
using a highpass filter with a 12 kHz cutoff frequency.
In this mode, a crystal oscillator is connected to the
ECL differential reference input and synthesized up to
the output frequency selected using the three SEL
pins. The Clock Synthesis mode is recognized by the
absence of data on the SERDATIP/N input pins. In
this mode, tie the SERDATIP pin to ground and tie the
SERDATIN pin to VTT (-2.0v) or to an ECL low level.
A programmable internal divider outputs a TTL clock
at the same frequency as the reference clock input via
the REFCKOUT output. The lock detect output will
remain consistently low in the Clock Synthesis mode.
Serial Data Output Set-up and Hold Time
The output set-up and hold times are represented by
the waveforms shown in Figure 3.
Reference Clock Input
The required characteristics of the reference clock
are outlined below. Unless otherwise noted, specifi-
cations refer to both Clock Recovery and Clock
Synthesis modes of operation. While a single-ended
ECL reference clock may be used, additional jitter
due to edge movement related to threshold variations
from DC offsets may be induced.
Figure 2. Input Jitter Tolerance Specification
Sinusoidal
Input Jitter
Amplitude
Figure 3. Clock Output to Data Transition Delay
15
(UI p-p)
SERCLKOP/N
SERDATOP/N
1.5
0.15
t
h
t
su
f0
f2
f3
ft
f1
Frequency
Output Frequency
OC/STS
Level
f0
(Hz)
f1
(Hz)
f2
f3
ft
155.52 MHz
2.5 ns
622.08 MHz
450 ps
(Hz) (kHz) (kHz)
SERDATOP/N Setup Time
SERDATOP/N Hold Time
3
10
10
30
30
300
300
6.5
25
75
2.5 ns
650 ps
12
250
2
S3014
SONET/SDH CLOCK RECOVERY AND SYNTHESIS UNIT
Pin Assignment and Descriptions
Pin Name
Level I/O
Pin # Description
REFCKINP
REFCKINN
Diff.
ECL
I
41
43
Reference clock. Input used as the reference for the internal bit
clock in frequency synthesis mode. Used as standby clock in the
absence of data or during reset in clock recovery mode.
SERDATIP
SERDATIN
Diff.
ECL
I
I
I
4
6
Serial data in. When the S3014 is used in the Clock Recovery
mode, clock is recovered from the transitions on these inputs.
TSTCLKEN
TTL
36
Test clock enable, active high. Used during production test to
bypass the VCO in the PLL. Tie to ground for normal operation.
SEL2
SEL1
SEL0
TTL
26
24
23
Mode select, used to select output and input frequencies. Refer
to Table 1 for explanation.
RST
LOS
TTL
ECL
I
33
32
Reset, active low. Initializes the device to a known state and
forces the PLL to acquire to the reference clock. RST, when held
low, also forces the REFCKOUT and LOCKDET outputs to the
Hi-Z state. A reset of at least 16 ms should be applied at power-
up and whenever it is necessary to reacquire to the reference
clock. The S3014 will also reacquire to the reference clock if the
serial data is held quiescent (constant ones or constant zeros)
for at least 16 ms.
I
Loss of signal, active low. A single-ended 10K ECL input to be
driven by the external optical receiver module to indicate a loss
of received optical power. When LOS is low, the data on the
Serial Data In (SERDATIP/N) pins will be internally forced to a
constant zero, LOCKDET forced low, and the PLL forced to lock
to the REFCKINP/N inputs. This signal must be used to assure
correct automatic reacquisition to serial data following an
interruption and subsequent reconnection of the optical path.
This will assure that the PLL does not "wander" out of
reacquisition range by tracking the random phase/frequency
content of the optical detector's noise floor while monitoring
"dark" fiber. When LOS is high, data on the SERDATIP/N pins
will be processed normally.
CAP1, CAP2
LOCKDET
–
I
39
40
Loop filter capacitor, connected to these pins. The capacitor
value should be 0.1 µf ±10% tolerance, X7R dielectric ceramic
chip capacitor. 50V is recommended.
TTL
O
11
Lock detect, active high. Clock recovery indicator. Set high when
the internal clock recovery has locked onto the incoming
datastream. LOCKDET is an asynchronous output. This output
is deasserted when there is no incoming serial data input; in
which case the PLL locks to the reference clock.
3
S3014
SONET/SDH CLOCK RECOVERY AND SYNTHESIS UNIT
Pin Assignment and Descriptions (Continued)
Pin Name
Level I/O
Pin # Description
SERDATOP
SERDATON
Diff.
ECL
O
20
21
Serial data out signal. In the Clock Recovery mode, this signal is
the delayed version of the incoming data stream (SERDATI)
updated on the falling edge of Serial Clock Out (SERCLKOP).
SERCLKOP
SERCLKON
Diff.
ECL
O
15
14
Serial clock out signal that is phase aligned with Serial Data Out
(SERDATO) when Lock Detect (LOCKDET) is high. When Lock
Detect is low, the signal is synchronous with Reference Clock
(REFCKINP/N).
REFCKOUT
AVEE
TTL
O
31
Single-ended TTL reference clock output. See Table 1.
Analog power (-5.2V)
-5.2V
–
2, 5, 7,
38, 44
AGND
GND
GND
GND
–
–
1, 3, 8, Analog ground (0V)
37, 42
9, 16, 17, Ground
19, 22,
27, 29,
30, 35
-5.2V
+5V
NC
-5.2V
+5V
–
–
–
–
10, 13, -5.2V
25, 34
18, 28
+5V
12
No Connection
4
S3014
SONET/SDH CLOCK RECOVERY AND SYNTHESIS UNIT
Figure 4. 44 PLCC Pinout
6
5
4
3
44 43
41 40
42
2
1
CAP1
39
7
8
*
*
AVEE1
AGND1
GND
38
AVEE3*
AGND3*
TSTCLKEN
GND
37
36
35
9
TOP
VIEW
10
11
-5.2V
LOCKDET
N/C
34
33
-5.2V
12
13
RST
-5.2V
LOS
SERCLKON
SERCLKOP
32
31
30
29
14
15
16
17
REFCKOUT
GND
GND
GND
GND
24
23
22
25 26 27 28
21
18 19 20
* Analog Power & GND
AVEE = -5.2V
AGND = 0V
Figure 5. 44 PLCC Package
0.692 ±.005
0.029 ±.003
0.649 ±.005
TOP
VIEW
0.050 ±.002
0.152 ±.005
0.172 ±.005
0.620 ±.010
All dimensions nominal in inches
5
S3014
SONET/SDH CLOCK RECOVERY AND SYNTHESIS UNIT
Performance Specifications
Parameter
Min
Typ
Max
Units
Condition
Given REFCLK = SERCLK ÷ 4,
12 or SERCLK ÷ 32 per SEL
<2:0> settings
Nominal VCO
Center Frequency
622.08
MHz
Clock Synthesis Output
Jitter
In CSU mode, given :
OC-3/STS-3
.005
.015
.01
64
UI(rms)
ps (rms)
•
56ps rms jitter on REFCLK
in 12 KHz to 1 MHz band
1
OC-12/STS-12
.03
48
UI(rms) • 14.1 ps rms jitter on REFCLK
ps (rms) in 12 KHz to 1 MHz band
Clock Recovery Output
Jitter
.01
UI(rms) rms jitter, in lock
Reference Clock
Frequency Tolerance
Clock Synthesis
2,3
Required to meet SONET output
-20
-100
20
100
ppm
ppm
frequency specification
Clock Recovery
OC-3/STS-3
OC-12/STS-12
Capture Range
±200
ppm
%
With respect to fixed reference
frequency
Lock Range
Clock Output
Duty Cycle
+8,-12
Minimum transition density of
20%
45
30
55
%
3
Acquisition Lock Time
OC-3/STS-3
OC-12/STS-12
64
16
With device already powered up
and valid REFCLK.
µsec
Reference Clock
Input Duty Cycle
% of
period
70
Reference Clock Rise &
Fall Times
2.0
ns
ps
10% to 90% of amplitude
ECL Output Rise & Fall
Times
10% to 90%, 50Ω to -2V
equivalent load, 5 pf cap
850
1. These specs can be achieved with either a 51.84 MHz or a 155.52 MHz Reference Clock.
2. Noise on REFCLK should be less than 14.1 ps rms in a jitter frequency band from 12 KHz to 1 MHz.
3. Specifications based on design values. Not tested.
Table 1. Mode Select
SEL2 SEL1 SEL0
SERCLKO
REFCKOUT
REFCKIN
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
622.08 MHz
622.08 MHz
622.08 MHz
622.08 MHz
155.52 MHz
155.52 MHz
51.84 MHz
19.44 MHz
19.44 MHz
—
51.84 MHz
19.44 MHz
51.84 MHz
19.44 MHz
19.44 MHz
155.52 MHz
51.84 MHz
19.44 MHz
6
S3014
SONET/SDH CLOCK RECOVERY AND SYNTHESIS UNIT
Absolute Maximum Ratings
Parameter
Min
-55
Typ
Max
125
150
150
7.0
Unit
°C
°C
°C
V
Case Temperature under Bias
Junction Temperature under Bias
Storage Temperature
-55
-65
Voltage on VCC with Respect to GND
Voltage on VEE with Respect to GND
Voltage on Any TTL Input Pin
Voltage on Any ECL Input Pin
TTL Output Sink Current
-0.5
-8.0
-0.5
-3.0
0.5
V
+5.5
0.0
V
V
20
mA
mA
mA
V
TTL Output Source Current
10
High Speed ECL Output Source Current
Static Discharge Voltage
50
500
Recommended Operating Conditions
Parameter
Ambient Temperature under Bias (industrial)
Ambient Temperature under Bias (commercial)
Junction Temperature under Bias
Voltage on VCC with Respect to GND
Voltage on VEE with Respect to GND
Voltage on Any TTL Input Pin
Min
-40
0
Typ
Max
85
Unit
°C
°C
°C
V
70
-10
4.75
-4.2
0.0
130
5.25
-5.46
VCC
0
5.0
-4.5/-5.2
V
V
Voltage on Any ECL Input Pin
-2.0
V
TTL/CMOS Output Sink Current
8
mA
mA
mA
mA
mA
TTL/CMOS Output Source Current
ECL Output Source Current (50Ω to -2V)
1
14
10
25
ICC
IEE
17
Supply Current
170
210
VEE (min) = -4.2V for Ambient Temperature ≥ 0˚C, -4.5V for Ambient Temperature <0˚C.
7
S3014
SONET/SDH CLOCK RECOVERY AND SYNTHESIS UNIT
TTL Input/Output DC Characteristics1
(TA = -40°C to +85°C, VCC = 5 V ±5%, VEE = -4.5 V ±7% or -5.2 ± 5%)
Symbol
Parameter
Test Conditions
Min
Max
Unit
Volts
Volts
2
IL
V
Input LOW Voltage
Guaranteed Input LOW Voltage for all inputs
Guaranteed Input HIGH Voltage for all inputs
0.8
2
V
Input HIGH Voltage
2.0
IH
I
Input LOW Current
-400.0
uA
uA
mA
V
V
V
V
V
V
= MAX, V = 0.5V
IN
IL
CC
CC
CC
CC
CC
CC
I
Input HIGH Current
= MAX, V = 2.7V
IN
50.0
1.0
IH
I
I
Input HIGH Current at Max VCC
= MAX, V = 5.25V
IN
I
Output Short Circuit Current
Input Clamp Diode Voltage
TTL Output LOW Voltage
= MAX, V
= 0.5V
-100.0
-1.2
-25.0
mA
Volts
Volts
Volts
OS
OUT
= MIN, I = -18.0mA
V
IK
IN
V
= MIN, I
= MIN, I
= 8mA
0.5
OL
OL
V
TTL Output HIGH Voltage
2.4
V
= -1.0mA
OH
CC
OH
1. These conditions will be met with an airflow of 400 LFPM.
2. These input levels provide a zero–noise immunity and should only be tested in a static, noise-free environment.
ECL Input/Output DC Characteristics3
(TA = -40°C to +85°C, VCC = 5 V ±5%, VEE = -4.5 V ±7% or -5.2 ± 5%)
Symbol
Parameter
Test Conditions
Signal Name
Min
Max
Unit
Guaranteed Input LOW Voltage
for all single ended inputs
1
V
Input LOW Voltage
-2.00
-1.47
Volts
IL
Guaranteed Input HIGH Voltage
for all single ended inputs
1
V
Input HIGH Voltage
Input LOW Voltage
Input HIGH Voltage
Input DIFF Voltage
-1.18
-2.00
-1.75
0.25
-0.80
-0.70
-0.45
1.40
Volts
Volts
Volts
Volts
IH
Guaranteed Input LOW Voltage
for all differential inputs
2
V
IL
Guaranteed Input HIGH Voltage
for all differential inputs
2
V
IH
Guaranteed Input DIFF Voltage
for all differential inputs
2,4
V
ID
20.00
20.00
20.00
20.00
uA
uA
uA
uA
V
= MAX, V = -1.95V
IL
LOS
-0.50
-1.0
EE
I
Input LOW Current
Input HIGH Current
IL
SERDATIP,SERDATIN,
REFCLKP, REFCLKN
LOS
V
V
= MAX, V
= 0.5V
EE
DIFF
= MAX, V = -0.80V
-0.50
-1.0
EE
EE
IH
I
IH
SERDATIP,SERDATIN,
REFCLKP, REFCLKN
V
= MAX, V
= 0.5V
DIFF
50Ω to -2V termination
50Ω to -2V termination
V
Output LOW Voltage
Output HIGH Voltage
-2.00
-1.11
-1.50
-0.62
Volts
Volts
OL
V
OH
1. Single Ended Inputs
2. Differential ECL Inputs
3. These conditions will be met with an airflow of 400 LFPM.
4. When not used, tie the negative differential input to ground (OV), and tie the positive differential input to -2.0V.
8
S3014
SONET/SDH CLOCK RECOVERY AND SYNTHESIS UNIT
Figure 6. Differential ECL Input and Output Applications
S3014
50Ω Transmission Lines
330 Ω
330 Ω
Differential output to
SERDATIP/N
VEE
Ω
termination
External 100
S3014
Ω
Ω
50
50
-2V
SERCLKOP/N
and SERDATOP/N output to
ECL-compatible input
S3014
330 Ω
330 Ω
VEE
Ω
termination
ECL driver to
REFCLK input
External 100
S3014
Optical to
electrical
330 Ω
330 Ω
Ω
termination
External 100
ECL-compatible
VEE
output to SERDATIP/N
differential input
S3014
100 Ω
50Ω
transmission line
–2V
0.1 µF
Unbalanced ECL
signal to SERDATIP/N
differential input
Ω
termination
External 100
9
S3014
SONET/SDH CLOCK RECOVERY AND SYNTHESIS UNIT
Ordering Information
GRADE
PART
PACKAGE
SPEED GRADE
S-commercial/
Industrial
3014
A-44 PLCC (com only)
D-44 PLCC TEP
1 – 155 Mbit/s
6 – 622 Mbit/s
X
Grade
XXXX
Part number
X
Package
X
–
Speed Grade
I
I
Applied Micro Circuits Corporation • 6290 Sequence Dr., San Diego, CA 92121
Phone: (619) 450-9333 • (800)755-2622 • Fax: (619) 450-9885
http://www.amcc.com
AMCC reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and
advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied
on is current.
AMCC does not assume any liability arising out of the application or use of any product or circuit described herein, neither does it
convey any license under its patent rights nor the rights of others.
AMCC reserves the right to ship devices of higher grade in place of those of lower grade.
AMCC SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR
USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS.
AMCC is a registered trademark of Applied Micro Circuits Corporation.
Copyright ® 1997 Applied Micro Circuits Corporation
June 2, 1997
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