S80960SA16 [ROCHESTER]

32-BIT, 16MHz, RISC PROCESSOR, PQFP80, EIAJ, QFP-80;


型号：	S80960SA16
厂家：	Rochester Electronics
描述：	32-BIT, 16MHz, RISC PROCESSOR, PQFP80, EIAJ, QFP-80 时钟外围集成电路
文件：	总40页 (文件大小：3061K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

80960SA

EMBEDDED 32-BIT MICROPROCESSOR

WITH 16-BIT BURST DATA BUS

■

High-Performance Embedded

Architecture

— 20 MIPS* Burst Execution at 20 MHz

— 7.5 MIPS Sustained Execution

at 20 MHz

■

Pin Compatible with 80960SB

Built-in Interrupt Controller

— 4 Direct Interrupt Pins

— 31 Priority Levels, 256 Vectors

■

Easy to Use, High Bandwidth 16-Bit Bus

— 32 Mbytes/s Burst

— Up to 16 Bytes Transferred per Burst

■

512-Byte On-Chip Instruction Cache

— Direct Mapped

— Parallel Load/Decode for Uncached

Instructions

■

32-Bit Address Space, 4 Gigabytes

Multiple Register Sets

80-Lead Quad Flat Pack (EIAJ QFP)

— 84-Lead Plastic Leaded Chip Carrier

(PLCC)

— Sixteen Global 32-Bit Registers

— Sixteen Local 32-Bit Registers

— Four Local Register Sets Stored

On-Chip

■

Software Compatible with

80960KA/KB/CA/CF Processors

— Register Scoreboarding

The 80960SA is a member of Intel’s i960^®32-bit processor family, which is designed especially for low cost

embedded applications. It includes a 512-byte instruction cache and a built-in interrupt controller. The 80960SA

has a large register set, multiple parallel execution units and a 16-bit burst bus. Using advanced RISC

technology, this high performance processor is capable of execution rates in excess of 7.5 million instructions

per second^*. The 80960SA is well-suited for a wide range of cost sensitive embedded applications including

non-impact printers, network adapters and I/O controllers.

64- BY 32-BIT

LOCAL

CACHE

32-BIT

INSTRUCTION

EXECUTION

UNIT

SIXTEEN

32-BIT GLOBAL

REGISTERS

32-BIT

BUS

CONTROL

LOGIC

512-BYTE

INSTRUCTION

CACHE

MICRO-

INSTRUCTION

SEQUENCER

MICRO-

INSTRUCTION

ROM

32-BIT

ADDRESS

16-BIT

INSTRUCTION

FETCH UNIT

INSTRUCTION

DECODER

BURST

BUS

Figure 1. The 80960SA Processor’s Highly Parallel Architecture

Relative to Digital Equipment Corporation’s VAX-11/780 at 1 MIPS (VAX-11™ is a trademark of Digital Equipment

Corporation)

Intel Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in an Intel product. No other circuit patent

licenses are implied. Information contained herein supersedes previously published specifications on these devices from Intel.

August 2004

Order Number: 272206-003

80960SA

EMBEDDED 32-BIT MICROPROCESSOR

WITH 16-BIT BURST DATA BUS

CONTENTS

PAGE

1.0 THE i960^®PROCESSOR ...........................................................................................................................1

1.1 Key Performance Features .................................................................................................................2

1.1.1 Memory Space And Addressing Modes ...................................................................................4

1.1.2 Data Types ...............................................................................................................................4

1.1.3 Large Register Set ...................................................................................................................4

1.1.4 Multiple Register Sets ..............................................................................................................5

1.1.5 Instruction Cache .....................................................................................................................6

1.1.6 Register Scoreboarding ...........................................................................................................6

1.1.7 High Bandwidth Bus ................................................................................................................6

1.1.8 Interrupt Handling ....................................................................................................................6

1.1.9 Debug Features .......................................................................................................................6

1.1.10 Fault Detection .......................................................................................................................7

1.1.11 Built-in Testability ....................................................................................................................7

1.1.12 CHMOS ..................................................................................................................................7

2.0 ELECTRICAL SPECIFICATIONS............................................................................................................. 11

2.1 Power and Grounding ....................................................................................................................... 11

2.2 Power Decoupling Recommendations .............................................................................................. 11

2.3 Connection Recommendations ......................................................................................................... 11

2.4 Characteristic Curves ....................................................................................................................... 11

2.5 Test Load Circuit ...............................................................................................................................13

2.6 ABSOLUTE MAXIMUM RATINGS* ..................................................................................................14

2.7 DC Characteristics ............................................................................................................................14

2.8 AC Specifications ..............................................................................................................................15

3.0 MECHANICAL DATA................................................................................................................................21

3.1 Packaging .........................................................................................................................................21

3.2 Pin Assignment .................................................................................................................................21

3.3 Pinout ................................................................................................................................................23

3.4 Package Thermal Specifications ......................................................................................................27

3.5 Stepping Register Information ..........................................................................................................27

4.0 WAVEFORMS...........................................................................................................................................28

5.0 REVISION HISTORY ................................................................................................................................34

LIST OF FIGURES

PAGE

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

Figure 13

Figure 14

Figure 15

Figure 16

Figure 17

Figure 18

Figure 19

Figure 20

The 80960SA Processor’s Highly Parallel Architecture ................................................................0

80960SA Programming Environment ...........................................................................................1

Instruction Formats ......................................................................................................................4

Multiple Register Sets Are Stored On-Chip ..................................................................................5

Connection Recommendation for LOCK .................................................................................... 11

Typical Supply Current vs. Case Temperature ........................................................................... 12

Typical Current vs. Frequency (Room Temp) ............................................................................. 12

Typical Current vs. Frequency (Hot Temp) ................................................................................. 13

Capacitive Derating Curve ......................................................................................................... 13

Test Load Circuit for Three-State Output Pins ............................................................................ 13

Drive Levels and Timing Relationships for 80960SA Signals ..................................................... 15

Processor Clock Pulse (CLK2) ................................................................................................... 19

RESET Signal Timing ................................................................................................................. 19

HOLD Timing .............................................................................................................................. 20

80-Lead EIAJ Quad Flat Pack (QFP) Package .......................................................................... 21

84-Lead Plastic Leaded Chip Carrier (PLCC) Package ............................................................. 22

Non-Burst Read and Write Transactions Without Wait States .................................................... 28

Quad Word Burst Read Transaction With 1, 0, 0, 0, 0, 0, 0, 0 Wait States ................................ 29

Burst Write Transaction With 2, 1, 1, 1 Wait States (6-8 Bytes Transferred) .............................. 30

Accesses Generated by Quad Word Read Bus Request,

Misaligned One Byte from Quad Word Boundary 1, 0, 0, 0, 0, 0, 0, 0 Wait States..................... 31

Figure 21

Figure 22

Interrupt Acknowledge Cycle ...................................................................................................... 32

Cold Reset Waveform ................................................................................................................ 33

LIST OF TABLES

Table 1

Table 2

Table 3

Table 4

Table 5

Table 6

Table 7

Table 8

Table 9

Table 10

Table 11

Table 12

Table 13

Table 14

Table 15

80960SA Instruction Set ..............................................................................................................3

Memory Addressing Modes .........................................................................................................4

80960SA Pin Description: Bus Signals ........................................................................................8

80960SA Pin Description: Support Signals ................................................................................ 10

DC Characteristics ..................................................................................................................... 14

80960SA AC Characteristics (10 MHz) ...................................................................................... 16

80960SA AC Characteristics (16 MHz) ...................................................................................... 17

80960SA AC Characteristics (20 MHz) ...................................................................................... 18

80960SA QFP Pinout — In Pin Order ........................................................................................ 23

80960SA QFP Pinout — In Signal Order ................................................................................... 24

80960SA PLCC Pinout — In Pin Order ...................................................................................... 25

80960SA PLCC Pinout — In Signal Order ................................................................................. 26

80960SA QFP Package Thermal Characteristics ...................................................................... 27

80960SA PLCC Package Thermal Characteristics .................................................................... 27

Die Stepping Cross Reference ................................................................................................... 27

iii

80960SA

Since time to market is critical, embedded micropro-

cessors need to be easy to use in both hardware and

software designs.

1.0 THE i960 PROCESSOR

The 80960SA is a member of the 32-bit architecture

from Intel known as the i960 processor family. These

microprocessors were especially designed to serve

the needs of embedded applications. The embedded

market includes applications as diverse as industrial

automation, avionics, image processing, graphics

and networking. These types of applications require

high integration, low power consumption, quick

interrupt response times and high performance.

All members of the i960 processor family share a

common core architecture which utilizes RISC

technology so that, except for special functions, the

family members are object-code compatible. Each

new processor in the family adds its own special set

of functions to the core to satisfy the needs of a

specific application or range of applications in the

embedded market.

FFFF FFFFH

0000 0000H

ADDRESS SPACE

ARCHITECTURALLY

DEFINED

DATA STRUCTURES

LOAD

STORE

FETCH

INSTRUCTION

CACHE

INSTRUCTION

STREAM

INSTRUCTION

EXECUTION

g15

SIXTEEN 32-BIT

GLOBAL REGISTERS

PROCESSOR STATE

REGISTERS

r15

SIXTEEN 32-BIT

LOCAL REGISTERS

INSTRUCTION

POINTER

ARITHMETIC

CONTROLS

FOUR 80-BIT

FLOATING POINT REGISTERS

CONTROL REGISTERS

PROCESS

CONTROLS

TRACE

CONTROLS

Figure 2. 80960SA Programming Environment

80960SA

5. Overlapped Instruction Execution. Load

operations allow execution of subsequent

instructions to continue before the data has

been returned from memory, so that these

instructions can overlap the load. The

80960SA manages this process transparently

to software through the use of a register score-

board. Conditional instructions also make use

of a scoreboard so that subsequent unrelated

instructions may be executed while the condi-

tional instruction is pending.

1.1 Key Performance Features

The 80960SA architecture is based on the most

recent advances in microprocessor technology and

is grounded in Intel’s long experience in the design

and manufacture of embedded microprocessors.

Many features contribute to the 80960SA’s excep-

tional performance:

1. Large Register Set. Having a large number of

registers reduces the number of times that a

processor needs to access memory. Modern

compilers can take advantage of this feature to

optimize execution speed. For maximum flexi-

bility, the 80960SA provides thirty-two 32-bit

registers. (See Figure 2.)

6. Integer Execution Optimization. When the

result of an arithmetic execution is used as an

operand in a subsequent calculation, the value

is sent immediately to its destination register.

At the same time, the value is put on a bypass

path to the ALU, thereby saving the time that

otherwise would be required to retrieve the

value for the next operation.

2. Fast Instruction Execution. Simple functions

make up the bulk of instructions in most

programs so that execution speed can be

improved by ensuring that these core instruc-

tions are executed as quickly as possible. The

most frequently executed instructions — such

as register-register moves, add/subtract,

logical operations and shifts — execute in one

to two cycles. (Table 1 contains a list of instruc-

tions.)

7. Bandwidth Optimizations. The 80960SA gets

optimal use of its memory bus bandwidth

because the bus is tuned for use with the on-

chip instruction cache: instruction cache line

size matches the maximum burst size for

instruction fetches. The 80960SA automatically

fetches four words in a burst and stores them

directly in the cache. Due to the size of the

cache and the fact that it is continually filled in

anticipation of needed instructions in the

program flow, the 80960SA is relatively insen-

sitive to memory wait states. The benefit is that

the 80960SA delivers outstanding performance

even with a low cost memory system.

3. Load/Store Architecture. One way to improve

execution speed is to reduce the number of

times that the processor must access memory

to perform an operation. As with other

processors based on RISC technology, the

80960SA has a Load/Store architecture. As

such, only the LOAD and STORE instructions

reference memory; all other instructions

operate on registers. This type of architecture

simplifies instruction decoding and is used in

combination with other techniques to increase

parallelism.

8. Cache Bypass. If a cache miss occurs, the

processor fetches the needed instruction then

sends it on to the instruction decoder at the

same time it updates the cache. Thus, no extra

time is spent to load and read the cache.

4. Simple Instruction Formats. All instructions

in the 80960SA are 32 bits long and must be

aligned on word boundaries. This alignment

makes it possible to eliminate the instruction

alignment stage in the pipeline. To simplify the

instruction decoder, there are only five

instruction formats; each instruction uses only

one format. (See Figure 3.)

80960SA

Table 1. 80960SA Instruction Set

Arithmetic Logical

Data Movement

Load

Bit and Bit Field

Set Bit

Add

And

Store

Subtract

Not And

And Not

Clear Bit

Not Bit

Move

Multiply

Load Address

Divide

Check Bit

Alter Bit

Remainder

Modulo

Exclusive Or

Not Or

Scan For Bit

Scan Over Bit

Extract

Shift

Or Not

Extended Multiply

Extended Divide

Nor

Exclusive Nor

Not

Modify

Nand

Rotate

Comparison

Branch

Call/Return

Fault

Compare

Unconditional Branch

Conditional Branch

Call

Conditional Fault

Conditional Compare

Call Extended

Call System

Return

Synchronize Faults

Compare and Increment Compare and Branch

Compare and Decrement

Branch and Link

Debug

Miscellaneous

Atomic Add

Decimal

Modify Trace Controls

Mark

Move

Atomic Modify

Add with Carry

Subtract with Carry

Force Mark

Flush Local Registers

Modify Arithmetic

Controls

Scan Byte for Equal

Test Condition Code

Synchronous

Synchronous Load

Synchronous Move

80960SA

Control

Opcode

Displacement

Compare and

Branch

Reg/Lit

Reg

Displacement

Ext’d Op

Opcode

Reg/Lit

Base

Modes

Reg/Lit

Offset

Memory Access---

Short

Reg

Offset

Memory Access---

Long

Opcode

Reg

Base

Mode

Scale

Displacement

Figure 3. Instruction Formats

1.1.1 Memory Space And Addressing Modes 1.1.2 Data Types

The 80960SA offers

linear programming

The 80960SA recognizes the following data types:

Numeric:

environment so that all programs running on the

processor are contained in a single address space.

Maximum address space size is 4 Gigabytes (2³²

bytes).

•

8-, 16-, 32- and 64-bit ordinals

8-, 16-, 32- and 64-bit integers

For ease of use the 80960SA has a small number of

addressing modes, but includes all those necessary

to ensure efficient execution of high-level languages

such as C. Table 2 lists the memory addressing

modes.

Non-Numeric:

•

Bit

Bit Field

Triple Word (96 bits)

Quad-Word (128 bits)

Table 2. Memory Addressing Modes

•

12-Bit Offset

1.1.3 Large Register Set

32-Bit Offset

The 80960SA programming environment includes a

large number of registers. In fact, 32 registers are

available at any time. The availability of this many

registers greatly reduces the number of memory

accesses required to perform algorithms, which

leads to greater instruction processing speed.

Bit Displacement

There are two types of general-purpose register:

local and global. The global registers consist of

sixteen 32-bit registers (g0 though g15). These

registers perform the same function as the general-

Scale-Factor is 1, 2, 4, 8 or 16

80960SA

purpose registers provided in other popular micro-

processors. The term global refers to the fact that

these registers retain their contents across

procedure calls.

Although programs may have procedure calls nested

many calls deep, a program typically oscillates back

and forth between only two to three levels. As a

result, with four stack frames in the cache, the proba-

bility of having a free frame available on the cache

when a call is made is very high. In fact, runs of

representative C-language programs show that 80%

of the calls are handled without needing to access

memory.

The local registers, on the other hand, are procedure

specific. For each procedure call, the 80960SA

allocates 16 local registers (r0 through r15). Each

local register is 32 bits wide.

If four or more procedures are active and a new

procedure is called, the 80960SA moves the oldest

local register set in the stack-frame cache to a

procedure stack in memory to make room for a new

set of registers. Global register g15 is the frame

pointer (FP) to the procedure stack.

1.1.4 Multiple Register Sets

To further increase the efficiency of the register set,

multiple sets of local registers are stored on-chip

(See Figure 4). This cache holds up to four local

procedure calls can be made without having to

access the procedure stack resident in memory.

Global registers are not exchanged on a procedure

call, but retain their contents, making them available

to all procedures for fast parameter passing.

CACHE

ONE OF FOUR

LOCAL

LOCAL REGISTER SET

r₀

r₁₅

Figure 4. Multiple Register Sets Are Stored On-Chip

80960SA

1.1.5 Instruction Cache

In essence, the two unrelated instructions between

LOAD and ADD are executed “for free” (i.e., take no

apparent time to execute) because they are

executed while the register is being loaded. Up to

three load instructions can be pending at one time

with three corresponding scoreboard bits set. By

exploiting this feature, system programmers and

compiler writers have a useful tool for optimizing

execution speed.

To further reduce memory accesses, the 80960SA

includes a 512-byte on-chip instruction cache. The

instruction cache is based on the concept of locality

of reference; most programs are not usually

executed in a steady stream but consist of many

branches, loops and procedure calls that lead to

jumping back and forth in the same small section of

code. Thus, by maintaining a block of instructions in

cache, the number of memory references required to

read instructions into the processor is greatly

reduced.

1.1.7

High Bandwidth Bus

The 80960SA CPU resides on a high-bandwidth

address/data bus. The bus provides a direct commu-

nication path between the processor and the

memory and I/O subsystem interfaces. The

processor uses the bus to fetch instructions,

manipulate memory and respond to interrupts. Bus

features include:

To load the instruction cache, instructions are

fetched in 16-byte blocks; up to four instructions can

be fetched at one time. An efficient prefetch

algorithm increases the probability that an instruction

will already be in the cache when it is needed.

•

16-bit data path multiplexed onto the lower bits of

the 32-bit address path

Code for small loops often fits entirely within the

cache, leading to a great increase in processing

speed since further memory references might not be

necessary until the program exits the loop. Similarly,

when calling short procedures, the code for the

calling procedure is likely to remain in the cache so it

will be there on the procedure’s return.

Eight 16-bit half-word burst capability which

allows transfers from 1 to 16 bytes at a time

High bandwidth reads and writes with 32

Mbytes/s burst (at 20 MHz)

Table 3 defines bus signal names and functions;

Table 4 defines other component-support signals

such as interrupt lines.

1.1.6 Register Scoreboarding

The instruction decoder is optimized in several ways.

One optimization method is the ability to overlap

instructions by using register scoreboarding.

1.1.8 Interrupt Handling

The 80960SA can be interrupted in one of two ways:

by the activation of one of four interrupt pins or by

sending a message on the processor’s data bus.

a variable from memory into a register. When the

instruction initiates, a scoreboard bit on the target

reset. In between, any reference to the register

contents is accompanied by a test of the scoreboard

bit to ensure that the load has completed before

processing continues. Since the processor does not

need to wait for the LOAD to complete, it can execute

additional instructions placed between the LOAD

and the instruction that uses the register contents, as

shown in the following example:

The 80960SA is unusual in that it automatically

handles interrupts on a priority basis and can keep

track of pending interrupts through its on-chip

interrupt controller. Two of the interrupt pins can be

configured to provide 8259A-style handshaking for

expansion beyond four interrupt lines.

1.1.9 Debug Features

The 80960SA has built-in debug capabilities. There

are two types of breakpoints and six trace modes.

Debug features are controlled by two internal 32-bit

registers, the Process-Controls Word and the Trace-

Controls Word. By setting bits in these control words,

a software debug monitor can closely control how

the processor responds during program execution.

ld data_2, r4

ld data_2, r5

Unrelated instruction

add r4, r5, r6

80960SA

The 80960SA provides two hardware breakpoint

registers on-chip which, by using special

command, can be set to any value. When the

instruction pointer matches either breakpoint register

value, the breakpoint handling routine is automati-

cally called.

For each of the fault types, there are numerous

subtypes that provide specific information about a

fault. The fault handler can use this specific infor-

mation to respond correctly to the fault.

1.1.11 Built-in Testability

The 80960SA also provides software breakpoints

through the use of two instructions: MARK and

FMARK. These can be placed at any point in a

program and cause the processor to halt execution

at that point and call the breakpoint handling routine.

The breakpoint mechanism is easy to use and

provides a powerful debugging tool.

Upon reset, the 80960SA automatically conducts an

exhaustive internal test of its major blocks of logic.

Then, before executing its first instruction, it does a

zero check sum on the first eight words in memory to

ensure that the memory image was programmed

correctly. If a problem is discovered at any point

during the self-test, the 80960SA asserts its FAIL pin

and will not begin program execution. Self test takes

approximately 24,000 cycles to complete.

Tracing is available for instructions (single step

execution), calls and returns and branching. Each

trace type may be enabled separately by a special

debug instruction. In each case, the 80960SA

executes the instruction first and then calls a trace

handling routine (usually part of a software debug

monitor). Further program execution is halted until

the routine completes, at which time execution

resumes at the next instruction. The 80960SA’s

tracing mechanisms, implemented completely in

hardware, greatly simplify the task of software test

and debug.

System manufacturers can use the 80960SA’s self-

test feature during incoming parts inspection. No

special diagnostic programs need to be written. The

test is both thorough and fast. The self-test capability

helps ensure that defective parts are discovered

before systems are shipped and, once in the field,

the self-test makes it easier to distinguish between

problems caused by processor failure and problems

resulting from other causes.

1.1.12 CHMOS

1.1.10 Fault Detection

The 80960SA is fabricated using Intel’s CHMOS IV

(Complementary High Speed Metal Oxide Semicon-

ductor) process. The 80960SA is available at 10 and

16 MHz in the QFP package and at 10, 16 and 20

MHz in the PLCC package.

The 80960SA has an automatic mechanism to

handle faults. Fault types include trace and

arithmetic faults. When the processor detects a fault,

it automatically calls the appropriate fault handling

routine and saves the current instruction pointer and

necessary state information to make efficient

recovery possible. Like interrupt handling routines,

fault handling routines are usually written to meet the

needs of specific applications and are often included

as part of the operating system or kernel.

80960SA

Table 3. 80960SA Pin Description: Bus Signals (Sheet 1 of 2)

NAME

CLK2

TYPE

DESCRIPTION

SYSTEM CLOCK provides the fundamental timing for 80960SA systems. It is

divided by two inside the 80960SA to generate the internal processor clock.

A31:16

ADDRESS BUS carries the upper 16 bits of the 32-bit physical address to memory.

T.S.

It is valid throughout the burst cycle; no latch is required.

AD15:1, D0

I/O

T.S.

ADDRESS/DATA BUS carries the low order 32-bit addresses and 16-bit data to

and from memory. AD15:4 must be latched since the cycle following the address

cycle carries data on the bus.

A3:1

ALE

T.S.

ADDRESS BUS carries the word addresses of the 32-bit address to memory.

These three bits are incremented during a burst access indicating the next word

address of the burst access. Note that A3:1 are duplicated with AD3:1 during the

address cycle.

T.S.

ADDRESS LATCH ENABLE indicates the transfer of a physical address. ALE is

asserted during a T_acycle and deasserted before the beginning of the T_dstate. It is

active HIGH and floats to a high impedance state during a hold cycle (T_h).

ADDRESS STATUS indicates an address state. AS is asserted every T_astate and

T.S.

deasserted during the following T_dstate. AS is driven HIGH during reset.

W/R

DEN

T.S.

WRITE/READ specifies, during a T_acycle, whether the operation is a write or read.

It is latched on-chip and remains valid during T_dcycles.

T.S.

DATA ENABLE is asserted during T_dcycles and indicates transfer of data on the

AD lines. The AD lines should not be driven by an external source unless DEN is

asserted. When DEN is asserted, outputs from the previous cycle are guaranteed

to be three-stated. In addition, DEN deasserted indicates inputs have been

captured; therefore input hold times can be disregarded. DEN is driven HIGH

during reset.

DT/R

T.S.

DATA TRANSMIT / RECEIVE indicates the direction of data transfer to and from

the bus. It is low during T_aand T_dcycles for a read or interrupt acknowledgment; it

is high during T_aand T_dcycles for a write. DT/R never changes state when DEN is

asserted. DT/R is driven HIGH during reset.

READY

READY indicates that data on AD lines can be sampled or removed. If READY is

not asserted during a T_dcycle, the T_dcycle is extended to the next cycle by

inserting a wait state (T_w).

I/O = Input/Output, O = Output, I = Input, O.D. = Open Drain, T.S. = Three-state

80960SA

Table 3. 80960SA Pin Description: Bus Signals (Sheet 2 of 2)

NAME

LOCK

TYPE

I/O

DESCRIPTION

BUS LOCK prevents bus masters from gaining control of the bus during

O.D. Read/Modify/Write (RMW) cycles. The processor or any bus agent may assert

LOCK.

At the start of a RMW operation, the processor examines the LOCK pin. If the pin is

already asserted, the processor waits until it is not asserted. If the pin is not

asserted, the processor asserts LOCK during the T_acycle of the read transaction.

The processor deasserts LOCK in the T_acycle of the write transaction. While LOCK

is asserted, a bus agent can perform a normal read or write but not a RMW

operation. The processor also asserts LOCK during interrupt-acknowledge transac-

tions.

Do not leave LOCK unconnected. It must be pulled high for the processor to

function properly.

ONCE MODE: The LOCK pin is sampled during reset. If it is asserted LOW at the

end of reset, all outputs will be three-stated until the part is reset again. ONCE

mode is used in conjunction with an in-circuit emulator.

BE1:0

BYTE ENABLE LINES specify which data bytes (up to two) on the bus take part in

T.S.

the current bus cycle. BE1 corresponds to AD15:8; BE0 corresponds to AD7:1, D0.

The byte enable lines are asserted appropriately during each data cycle.

INITIALIZATION FAILURE indicates that the processor has failed to initialize

correctly. The failure state is indicated by a combination of BLAST asserted and

BE1:0 not asserted. This condition occurs after RESET is deasserted and before

the first bus transaction begins. FAIL is asserted while the processor performs a

self-test. If the self-test completes successfully, FAIL is deasserted. The processor

then performs a zero checksum on the first eight words of memory, If it fails, FAIL is

asserted for a second time and remains asserted; if it passes, system initialization

continues and FAIL remains deasserted.

HOLD

HOLD indicates a request from an external bus master to acquire the bus. When

the processor receives HOLD and grants bus control to another master, it floats its

three-state bus lines, then asserts HLDA and enters the T_hstate. When HOLD is

deasserted, the processor deasserts HLDA and enters the T_ior T_astate.

HLDA

T.S.

HOLD ACKNOWLEDGE notifies an external bus master that the processor has

relinquished control of the bus. This signal is always driven. At reset it is driven

LOW.

BLAST/FAIL

BURST LAST indicates the last data cycle (T_d) of a burst access. It is asserted low

T.S.

during the last T_dand associated with T_wcycles in a burst access.

INITIALIZATION FAILURE indicates that the processor has failed to initialize

correctly. The failure state is indicated by a combination of BLAST asserted and

BE1:0 not asserted. This condition occurs after RESET is deasserted and before

the first bus transaction begins. FAIL is asserted while the processor performs a

self-test. If the self-test completes successfully, FAIL is deasserted. The processor

then performs a zero checksum on the first eight words of memory, If it fails, FAIL is

asserted for a second time and remains asserted; if it passes, system initialization

continues and FAIL remains deasserted.

I/O = Input/Output, O = Output, I = Input, O.D. = Open Drain, T.S. = Three-state

80960SA

Table 4. 80960SA Pin Description: Support Signals

NAME

TYPE

DESCRIPTION

RESET

RESET clears the processor’s internal logic and causes it to reinitialize.

During RESET assertion, the input pins are ignored (except for INT0, INT1, INT3,

LOCK), the three-state output pins are placed in a HIGH impedance state (except

for DT/R, DEN, and AS) and other output pins are placed in their non-asserted

states.

RESET must be asserted for at least 41 CLK2 cycles for a predictable reset.

Optionally, for a synchronous reset, the LOW and HIGH transition of RESET

should occur after the rising edge of both CLK2 and the external bus CLK and

before the next rising edge of CLK2.

The interrupt pins indicate the initialization sequence executed. Typical initial-

ization requires driving only INT0 and INT3 to a HIGH state. The reset conditions

follow:

INT0

INT1

INT3

LOCK

Action Taken

Run self test (core initialization)

Disable self-test

Reserved

ONCE mode (see LOCK pin)

INT0

INTERRUPT 0 indicates a pending interrupt. To signal an interrupt in a

synchronous system, this pin — as well as the other interrupt pins — must be

enabled by being deasserted for at least one bus cycle and then asserted for at

least one additional bus cycle. In an asynchronous system, the pin must remain

deasserted for at least two system clock cycles and then asserted for at least two

more system clock cycles. The interrupt control register must be programmed with

an interrupt vector before using this pin.

INT0 is sampled during reset to determine if the self-test sequence is to be

executed.

INT1

INTERRUPT 1, like INT0, provides direct interrupt signaling. INT1 is sampled

during reset to determine if the self-test sequence is to be executed.

INT2/INTR

INTERRUPT2/INTERRUPT REQUEST: The interrupt control register determines

how this pin is interpreted. If INT2, it has the same interpretation as the INT0 and

INT1 pins. If INTR, it is used to receive an interrupt request from an external

interrupt controller.

INT3/INTA

I/O

INTERRUPT3/INTERRUPT ACKNOWLEDGE: The interrupt control register

determines how this pin is interpreted. If INT3, it has the same interpretation as

the INT0 and INT1 pins. If INTA, it is used as an output to control interrupt

acknowledge transactions. The INTA output is latched on-chip and remains valid

during T_dcycles; as an output, it is open-drain. INT3 must be pulled HIGH during

reset.

T.S.

N/A

NOT CONNECTED indicates pins should not be connected. Never connect any

pin marked NC; these pins may be reserved for factory use.

I/O = Input/Output, O = Output, I = Input, O.D. = Open Drain, T.S. = Three-state

80960SA

The LOCK open-drain pin requires a pullup resistor

whether or not the pin is used as an output. Figure 5

shows the recommended resistor value.

2.0 ELECTRICAL SPECIFICATIONS

2.1 Power and Grounding

Do not connect external logic to pins marked NC.

The 80960SA is implemented in CHMOS IV

technology and therefore has modest power require-

ments. Its high clock frequency and numerous output

buffers (address/data, control, error and arbitration

signals) can cause power surges as multiple output

buffers simultaneously drive new signal levels. For

clean on-chip power distribution, V_CCand V_SSpins

separately feed the device’s functional units. Power

and ground connections must be made to all

80960SA power and ground pins. On the circuit

board, all V_CCpins must be strapped closely

together, preferably on a power plane; all V_SSpins

should be strapped together, preferably on a ground

plane.

OPEN-DRAIN

OUTPUT

910Ω

Figure 5. Connection Recommendation

for LOCK

2.4 Characteristic Curves

Figure 6 shows typical supply current requirements

over the operating temperature range of the

processor at supply voltage (V_CC) of 5V. Figure 7

shows the typical power supply current (I_CC) that the

80960SA requires at various operating frequencies

when measured at three input voltage (V_CC) levels.

2.2 Power Decoupling

Recommendations

Place a liberal amount of decoupling capacitance

near the 80960SA. When driving the bus the

processor can cause transient power surges, partic-

ularly when connected to a large capacitive load.

For a given output current (I_OL) the curve in Figure 8

shows the worst case output low voltage (V_OL).

Figure 9 shows the typical capacitive derating curve

for the 80960SA measured from 1.5V on the system

clock (CLK) to 0.8V on the falling edge and 2.0V on

the rising edge of the bus address/data (AD) signals.

Low inductance capacitors and interconnects are

recommended for best high frequency electrical

performance. Inductance is reduced by shortening

board traces between the processor and decoupling

capacitors as much as possible.

2.3 Connection Recommendations

For reliable operation, always connect unused inputs

to an appropriate signal level. In particular, if one or

more interrupt lines are not used, they should be

pulled up. No inputs should ever be left floating.

80960SA

350

300

= 5.0V

250

200

150

100

20 MHz

16 MHz

10 MHz

-10

10 20 30 40 50 60 70 80 90 100 110

CASE TEMPERATURE (°C)

Figure 6. Typical Supply Current vs. Case Temperature

TEMP = +22°C

4.5V

5.0V

5.5V

250

225

200

175

150

125

100

OPERATING FREQUENCY (MHz)

Figure 7. Typical Current vs. Frequency (Room Temp)

80960SA

(TEMP = +85°C, V

= 4.5V)

TEMP = +85°C

FALLING

300

250

200

150

100

4.5V

5.0V

5.5V

RISING

20 40 60 80 100

OPERATING FREQUENCY (MHz)

CAPACITIVE LOAD (pF)

Figure 8. Typical Current vs. Frequency

(Hot Temp)

Figure 9. Capacitive Derating Curve

2.5 Test Load Circuit

Figure 10 illustrates the load circuit used to test the 80960SA’s output pins.

THREE-STATE OUTPUT

= 50 pF for all signals

Figure 10. Test Load Circuit for Three-State Output Pins

80960SA

2.6 ABSOLUTE MAXIMUM RATINGS*

NOTICE: This is a production data sheet. The

specifications are subject to change without notice.

Parameter

Maximum Rating

Operating Temperature (PLCC) ........... 0°C to +85°C Case

Operating Temperature (QFP) ............ 0°C to +100°C Case

Storage Temperature .............................. –65°C to +150°C

Voltage on Any Pin (PLCC)................. –0.5V to VCC +0.5V

Voltage on Any Pin (QFP)............... –0.25V to VCC +0.25V

Power Dissipation ....................................... 1.9W (20 MHz)

*WARNING: Stressing the device beyond the

“Absolute

Maximum

Ratings”

may

cause

permanent damage. These are stress ratings only.

Operation beyond the “Operating Conditions” is not

recommended and extended exposure beyond the

“Operating Conditions” may affect device reliability.

2.7 DC Characteristics

80960SA (10 and 16 MHz QFP)

80960SA (10 and 16 MHz PLCC)

80960SA (20 MHz PLCC)

T_CASE= 0°C to +100°C, V_CC= 5V ± 5%

T_CASE= 0°C to +85°C, V_CC= 5V ± 10%

T_CASE= 0°C to +85°C, V_CC= 5V ± 5%

Table 5. DC Characteristics

Symbol

V_IL

Parameter

Input Low Voltage

Min

–0.3

Max

+0.8

Units

Notes

V_IH

Input High Voltage

2.0

–0.3

V_CC+ 0.3

+0.8

V_CL

V_CH

V_OL

CLK2 Input Low Voltage

CLK2 Input High Voltage

Output Low Voltage

0.7 V_CC

V_CC+ 0.3

0.45

I_OL= 4.0 mA

I_OL= 6 mA, LOCK Pin

All TS, -2.5 mA (1)

V_OH

I_CC

Output High Voltage

2.4

Power Supply Current:

10 MHz-QFP

10 MHz-PLCC

16 MHz-PLCC

20 MHz-PLCC

240

300

340

T_CASE= 0 C

I_LI1

I_LI2

Input Leakage Current,

Except INT0, LOCK

±15

µA

0 ≤ V_IN≤ V_CC

Input Leakage Current,

INT0, LOCK

–300

µA

V_IN= 0.45V (2)

I_OL

Output Leakage Current

Input Capacitance

±15

µA

C_IN

f_C= 1 MHz (3)

C_O

Output Capacitance

Clock Capacitance

C_CLK

NOTES:

1. Not measured for open-drain output.

2. INT0 and LOCK have internal pullup devices.

3. Input, output and clock capacitance are not tested.

80960SA

crosses 1.5V (for output delay and input setup). All

AC testing should be done with input voltages of

0.4V and 2.4V, except for the clock (CLK2) which

should be tested with input voltages of 0.45V and 0.7

x V_CC. See Figure 11 and Tables 6, 7 and 8 for timing

relationships for the 80960SA signals.

2.8 AC Specifications

This section describes the AC specifications for the

80960SA pins. All input and output timings are

specified relative to the 1.5V level of the rising edge

of CLK2 and refer to the time at which the signal

EDGE

CLK2

1.5V

OUTPUTS:

AD15:1, A3:1, D0,

A 31:16, BE1:0,

W/R, DEN, BLAST,

HLDA, LOCK, INTA

1.5V VALID OUTPUT1.5V

6AS

1.5V

ALE

1.5V

VALID OUTPUT

DT/R

INPUTS:

2.0V 2.0V

0.8V 0.8V

AD15:1, D0,

INT0, INT1,

INT2, INT3

VALID INPUT

HOLD

LOCK

READY

2.0V 2.0V

0.8V 0.8V

Figure 11. Drive Levels and Timing Relationships for 80960SA Signals

80960SA

Table 6. 80960SA AC Characteristics (10 MHz)

Symbol

Parameter

Min

Max

Units

Notes

Input Clock

T₁

T₂

Processor Clock Period (CLK2)

125

V_IN= 1.5V

V_T= 10% Point

= V_CL+ (V_CH– V_CL) x 0.1

V_T= 90% Point

= V_CL+ (V_CH– V_CL) x 0.9

Processor Clock Low Time (CLK2)

T₃

Processor Clock High Time

(CLK2)

T₄

T₅

Processor Clock Fall Time (CLK2)

Processor Clock Rise Time (CLK2)

V_T= 90% to 10% Point (1)

V_T= 10% to 90% Point (1)

Synchronous Outputs

T₆

Output Valid Delay

T_6AS

T₇

AS Output Valid Delay

ALE Width

T₁- 11

T₈

ALE Output Valid Delay

Output Float Delay

T₉

(2)

Synchronous Inputs

T₁₀

Input Setup 1

T₁₁

Input Hold

T₁₂

Input Setup 2

T₁₃

Setup to ALE Inactive

Hold after ALE Inactive

RESET Hold

T₁₄

T₁₅

(3)

T₁₆

RESET Setup

RESET Width

(3)

T₁₇

2050

41 CLK2 Periods Minimum

NOTES:

1. Processor clock (CLK2) rise time and fall time are not tested.

2. A float condition occurs when the maximum output current becomes less than I . Float delay is not tested, but should be

no longer than the valid delay.

3. Meeting RESET setup and hold times is an optional method of synchronizing your clocks. If you decide to use an asyn-

chronous reset, synchronizing the clock can be accomplished by using AS.

80960SA

Table 7. 80960SA AC Characteristics (16 MHz)

Symbol

Parameter

Min

Max

Units

Notes

Input Clock

T₁

T₂

Processor Clock Period (CLK2)

31.25

125

V_IN

V_T

1.5V

10% Point

Processor Clock Low Time (CLK2)

V_CL+ (V_CH– V_CL) x 0.1

T₃

Processor Clock High Time

(CLK2)

V_T

90% Point

V_CL+ (V_CH– V_CL) x 0.9

T₄

T₅

Processor Clock Fall Time (CLK2)

Processor Clock Rise Time (CLK2)

V_T

90% to 10% Point (1)

10% to 90% Point (1)

Synchronous Outputs

T₆

Output Valid Delay

T_6AS

T₇

AS Output Valid Delay

ALE Width

T₁- 11

T₈

ALE Output Valid Delay

Output Float Delay

T₉

(2)

Synchronous Inputs

T₁₀

Input Setup 1

T₁₁

Input Hold

T₁₂

Input Setup 2

T₁₃

Setup to ALE Inactive

Hold after ALE Inactive

RESET Hold

T₁₄

T₁₅

(3)

T₁₆

RESET Setup

RESET Width

T₁₇

1281

41 CLK2 Periods Minimum

NOTES:

1. Processor clock (CLK2) rise time and fall time are not tested.

2. A float condition occurs when the maximum output current becomes less than I . Float delay is not tested, but should be

no longer than the valid delay.

3. Meeting RESET setup and hold times is an optional method of synchronizing your clocks. If you decide to use an asyn-

chronous reset, synchronizing the clock can be accomplished by using AS.

80960SA

Table 8. 80960SA AC Characteristics (20 MHz)

Symbol

Parameter

Min

Max

Units

Notes

Input Clock

T₁

T₂

Processor Clock Period (CLK2)

125

V_IN

V_T

= 1.5V

Processor Clock Low Time (CLK2)

10% Point

V_CL+ (V_CH– V_CL) x 0.1

T₃

Processor Clock High Time (CLK2)

V_T

90% Point

V_CL+ (V_CH– V_CL) x 0.9

T₄

T₅

Processor Clock Fall Time (CLK2)

Processor Clock Rise Time (CLK2)

V_T

90% to 10% Point (1)

10% to 90% Point (1)

Synchronous Outputs

T₆

Output Valid Delay

T_6AS

T₇

AS Output Valid Delay

ALE Width

T₁- 11

T₈

ALE Output Valid Delay

Output Float Delay

T₉

(2)

Synchronous Inputs

T₁₀

Input Setup 1

T₁₁

Input Hold

T₁₂

Input Setup 2

T₁₃

Setup to ALE Inactive

Hold after ALE Inactive

RESET Hold

T₁₄

T₁₅

(3)

T₁₆

RESET Setup

RESET Width

T₁₇

1025

41 CLK2 Periods Minimum

NOTES:

1. Processor clock (CLK2) rise time and fall time are not tested.

2. A float condition occurs when the maximum output current becomes less than I . Float delay is not tested, but should be

no longer than the valid delay.

3. Meeting RESET setup and hold times is an optional method of synchronizing your clocks. If you decide to use an asyn-

chronous reset, synchronizing the clock can be accomplished by using AS.

80960SA

HIGH LEVEL (MIN) 0.7V

90%

1.5 V

LOW LEVEL (MAX) 0.8V

10%

Figure 12. Processor Clock Pulse (CLK2)

CLK2

CLK

OUTPUTS

RESET

INT0, INT1,

INT3, LOCK

INITIALIZATION PARAMETERS

NOTE: Initialization parameters must be set up at least four CLK2 periods before the first CLK2 “A” edge.

Figure 13. RESET Signal Timing

80960SA

CLK2

CLK

HOLD

HLDA

Figure 14. HOLD Timing

80960SA

3.0 MECHANICAL DATA

3.2 Pin Assignment

The QFP and PLCC have different pin assignments.

The QFP pins are numbered in order from 1 to 80

around the package perimeter. The PLCC pins are

numbered in order from 1 to 84 around the package

perimeter. Tables 9 and 10 list the function of each

QFP pin; Tables 11 and 12 list the function of each

PLCC pin.

3.1 Packaging

The 80960SA is available in two package types:

•

80-lead quad flat pack (EIAJ QFP). Shown in

Figure 15.

•

84-lead plastic leaded chip carrier (PLCC).

Shown in Figure 16.

V_CCand GND connections must be made to multiple

V_CCand GND pins. Each V_CCand GND pin must be

connected to the appropriate voltage or ground and

externally strapped close to the package. It is recom-

mended that you include separate power and ground

planes in your circuit board for power distribution.

Dimensions for both package types are given in the

Intel Packaging handbook (Order #240800).

Pins identified as NC (No Connect) should never be

connected.

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41

V_SS

BE1

ALE

READY

A31

V_SS

V_CC

A30

A29

A28

V_SS

x80960SA-20

XXXXXXXX

XXXXXX

V_CC

V_SS

V_CC

XXXXXX

A27

A26

A25

V_CC

AD1

AD2

AD3

AD4

AD5

V_SS

A24

A23

AD6

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Figure 15. 80-Lead EIAJ Quad Flat Pack (QFP) Package

NOTE: To address the fact that many of the package prefix variables have changed, all

package prefix variables in this document are now indicated with an "x".

80960SA

11 10

84 83 82 81 80 79 78 77 76 75

A20

A19

V_SS

V_CC

V_SS

V_CC

A18

A17

A16

LOCK

BLAST

DT/R

V_CC

V_SS

AD15

DEN

W/R

AD14

V_CC

x80960SA-20

XXXXXXXX

XXXXXX

V_SS

HOLD

V_SS

XXXXXX

AD13

V_CC

AD12

AD11

HLDA

INT3/INTA

INT2/INTR

INT1

AD10

AD9

INT0

AD8

AD7

V_CC

RESET

CLK2

V_SS

33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53

Figure 16. 84-Lead Plastic Leaded Chip Carrier (PLCC) Package

NOTE: To address the fact that many of the package prefix variables have changed, all

package prefix variables in this document are now indicated with an "x".

80960SA

3.3 Pinout

Table 9. 80960SA QFP Pinout — In Pin Order

Signal

BE0

Signal

A22

V_CC

V_SS

V_CC

V_SS

V_CC

V_SS

A21

V_CC

A20

V_SS

A19

CLK2

RESET

INT0

A18

AD6

AD5

AD4

AD3

AD2

AD1

V_SS

A17

ALE

READY

A31

A30

A29

A28

V_SS

A16

INT1

V_CC

INT2/INTR

INT3/INTA

HLDA

V_CC

V_SS

NOTES:

AD15

AD14

V_CC

V_SS

V_CC

V_SS

HOLD

W/R

V_CC

A27

A26

A25

V_CC

V_SS

AD13

AD12

AD11

AD10

AD9

AD8

AD7

DEN

V_CC

V_SS

DT/R

BLAST

LOCK

V_CC

A24

A23

BE1

V_SS

Do not connect any external logic to any pins marked NC.

80960SA

Table 10. 80960SA QFP Pinout — In Signal Order

Signal

A18

A19

A20

A21

A22

A23

A24

A25

A26

A27

A28

A29

A30

A31

V_CC

V_SS

DEN

DT/R

HLDA

HOLD

INT0

AD1

AD2

AD3

AD4

AD5

AD6

AD7

AD8

AD9

AD10

AD11

AD12

AD13

AD14

AD15

A16

INT1

INT2/INTR

INT3/INTA

LOCK

READY

RESET

V_CC

ALE

V_CC

BE0

V_CC

BE1

V_CC

BLAST

CLK2

V_CC

A17

V_CC

W/R

NOTES:

Do not connect any external logic to any pins marked N.C.

80960SA

Signal

Table 11. 80960SA PLCC Pinout — In Pin Order

Signal

V_CC

Signal

V_SS

Signal

V_SS

HOLD

V_CC

A27

A26

A25

V_CC

V_SS

A24

A23

A22

A21

A20

A19

A18

A17

A16

V_CC

V_SS

AD15

AD14

V_CC

AD13

AD12

AD11

AD10

AD9

AD8

AD7

V_CC

V_SS

W/R

DEN

DT/R

BLAST

LOCK

V_CC

V_SS

BE1

V_SS

NOTES:

BE0

V_CC

V_SS

V_CC

V_SS

CLK2

RESET

INT0

INT1

INT2/INTR

INT3/INTA

HLDA

V_CC

AD6

AD5

AD4

AD3

V_SS

ALE

READY

A31

A30

A29

A28

V_SS

Do not connect any external logic to any pins marked NC.

80960SA

Table 12. 80960SA PLCC Pinout — In Signal Order

Signal

DT/R

Signal

A18

A19

A20

A21

A22

A23

A24

A25

A26

A27

A28

A29

A30

A31

ALE

V_CC

V_SS

HLDA

HOLD

INT0

INT1

INT2/INTR

INT3/INTA

LOCK

AD1

AD2

AD3

AD4

AD5

AD6

AD7

AD8

AD9

AD10

AD11

AD12

AD13

AD14

AD15

AD16

A17

READY

RESET

V_CC

BE0

BE1

V_CC

BLAST

CLK2

DEN

V_CC

W/R

NOTES:

Do not connect any external logic to any pins marked NC.

80960SA

Compute P by multiplying the maximum voltage by

the typical current at maximum temperature. Values

for θ_JAand θ_JCfor various airflows are given in Table

13 for the QFP package and in Table 14 for the

PLCC package. I_CCat maximum temperature is

typically 80 percent of specified I_CCmaximum (cold).

3.4 Package Thermal Specifications

The 80960SA is specified for operation when case

temperature is within the range 0°C to +85°C (PLCC)

or 0°C to 100°C (QFP). Measure case temperature

at the top center of the package. Ambient temper-

ature can be calculated from:

T_J= T_C+ P*θ_JC

T_A= T_J- P*θ_JA

T_C= T_A+ P*[θ_JA−θ_JC

]

Table 13. 80960SA QFP Package Thermal Characteristics

Thermal Resistance — °C/Watt

Airflow — ft./min (m/sec)

Parameter

100

200

400

600

800

θ Junction-to-Ambient (Case

measured in the middle of the

top of the package)

(No Heatsink)

θ Junction-to-Case

NOTES:

This table applies to 80960SA QFP soldered directly to board.

Table 14. 80960SA PLCC Package Thermal Characteristics

Thermal Resistance — °C/Watt

Airflow — ft./min (m/sec)

Parameter

100

200

400

600

800

1000

θ Junction-to-Ambient

(No Heatsink)

29.5

20.5

θ Junction-to-Case

NOTES:

This table applies to 80960SA PLCC soldered directly to board.

Table 15. Die Stepping Cross Reference

3.5 Stepping Register Information

Die Stepping

Upon reset, register g0 contains die stepping infor-

mation. Table 15 shows the relationship between the

number in g0 and the current die stepping

01010101H

C-1

The current numbering pattern in g0 may not be

consistent with past or future steppings of this

product.

80960SA

4.0 WAVEFORMS

Figures 17, 18, 19, 20 and 21 show waveforms for various transactions on the 80960SA’s bus. Figure 22 shows

a cold reset functional waveform.

CLK2

CLK

ALE

A31:16

VALID

A15:4,

D15:0

ADDR

DATA

INVALID

VALID

A3:1

BE1:0

BLAST

W/R

DT/R

DEN

READY

Figure 17. Non-Burst Read and Write Transactions Without Wait States

80960SA

CLK2

CLK

ALE

VALID

A31:16

A15:4,

D15:0

ADDR

A3:1

000

001

010

011

100

101

110

111

BE1:0

BLAST

W/R

DT/R

DEN

READY

Figure 18. Quad Word Burst Read Transaction With 1, 0, 0, 0, 0, 0, 0, 0 Wait States

80960SA

CLK2

CLK

ALE

VALID

A31:16

A15:4,

D15:0

ADDR

DATA

A3:1

VALID

BE1:0

BLAST

W/R

DT/R

DEN

READY

Figure 19. Burst Write Transaction With 2, 1, 1, 1 Wait States (6-8 Bytes Transferred)

80960SA

Figure 20. Accesses Generated by Quad Word Read Bus Request,

Misaligned One Byte from Quad Word Boundary 1, 0, 0, 0, 0, 0, 0, 0 Wait States

80960SA

CLK2

CLK

ALE

A31:16

A15:4,

D15:0

ADD

ADDR

DATA

A3:1

1 1 0

BE1:0

INTA

1 0

BLAST

W/R

DT/R

DEN

LOCK

READY

Figure 21. Interrupt Acknowledge Cycle

A B C D

A B C D A B C D

A B C D

CLK2

CLK

AS, DT/R,

DEN,

LOCK (O)

HLDA

BLAST/FAIL

ALE, A31:16,

A15:4, A3:1,

D15:0,

BE1:0, W/R

RESET

INT0, INT1,

INT3,

VALID

LOCK (I)

Internal self-test,

approximately 9448,,000000CLK2

periods (if selected)

First

Bus

Initialization parameters

set up to first A edge,

minimum 4 CLK2 periods

Activity

and CLK2 stable to RESET high, minimum 41 CLK2 periods

80960SA

5.0 REVISION HISTORY

This data sheet supersedes data sheet 272206-001 and applies only to those devices identified as the current

stepping in section 3.5. The sections significantly changed since the previous revision are:

Last

Rev.

Section

Description

To address the fact that many of the package prefix

variables have changed, all package prefix variables

in this document are now indicated with an "x".

Overall

-003

2.3 Connection Recommendations (pg. 11) -001 Removed two LOCK pin Connection Recommendation

figures and added Figure 5 to reflect the new LOCK pin

connection recommendation of a single 910Ω pullup

resistor.

2.5 Test Load Circuit (pg. 13)

-001 Obsolete figure (Test Load Circuit for Open-Drain

Output Pins) removed to reflect current test conditions.

2.7 DC Characteristics (pg. 14)

-001 I_OLvalue at 0.45V improved.

WAS:

LOCK pin I_OLvalue at 0.45V relaxed.

WAS: 12 mA IS:

LOCK pin I_OLvalue at 0.60V deleted.

80960SA 16 MHz QFP added to product list.

-001 New section added.

2.5 mA

IS:

4.0 mA

6 mA

3.5 Stepping Register Information (pg. 27)

Data sheet 270917-004 applied to both the 80960SA and the 80960SB. The 80960SA was then documented

alone in data sheet 272206-001. The sections significantly changed between revisions -004 of the SA/SB data

sheet and 272206-001 of the SA data sheet were:

Last

Rev.

Section

Description

2.3 Connection Recommendations

(pg. 11)

-004

Deleted corresponding graph of open drain voltage vs. out-

put current.

Figure 6. Typical Supply Current vs.

Case Temperature (pg. 11)

-004

Regraphed new data in three graphs instead of two.

Figure 7. Typical Current vs. Fre-

quency (Room Temp) (pg. 12)

Figure 8. Typical Current vs. Fre-

quency (Hot Temp) (pg. 12)

Table 5. DC Characteristics (pg. 15)

Input Leakage Current (I_LI2) Specification added to accu-

rately describe leakage of INT0 and LOCK as inputs.

I_CCmax reduced:

Power Supply Current:

10 MHz

Was:

280

Is:

240

300

16 MHz

350

NOTES:

Page numbers refer to 80960SA data sheet number 272206-001.

80960SA

Last

Rev.

Section

Description

Table 6. 80960SA AC Characteristics

(10 MHz) (pg. 17)

-004

T₇minimum specification improved:

Power Supply Current:

10 MHz

Was:

24 ns

15 ns

Is:

Table 7. 80960SA AC Characteristics

(16 MHz) (pg. 18).

T₁- 11 ns

16 MHZ

Table 8. 80960SA AC Characteristics

(20 MHz) (pg. 19)

-004

New 20 MHz specification table added for 80960SA C-step.

Table 11. 80960SA PLCC Pinout — In -004

Pin Order (pg. 26)

θ_JAincreased to reflect smaller die size and lower I_CC

Table 11. 80960SA PLCC Pinout — In -004

Pin Order (pg. 26)

θ_JAand θ_JCincreased to reflect smaller die size and lower

I_CC

NOTES:

Page numbers refer to 80960SA data sheet number 272206-001.

The sections significantly changed between revisions -003 and -004 of the 80960SA/SB Data Sheet were:

Last

Rev.

Section

DC Characteristics

Description

-003

Operating temperature for PLCC package changed:

WAS:

IS:

T_CASE= 0°C to +100°C

T_CASE= 0°C to +85°C

The test program has not changed.

Table 9. 80960SA and 80960SB QFP

Pinout — In Pin Order

-003

Signal A12 incorrectly shown as Pin 28; is now cor-

rectly shown as Pin 38. Note added to clarify No Con-

nect Pins.

S80960SA16 [ROCHESTER]

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