S80C51FA_技术文档

REI Datasheet

8XC51FX

CHMOS Single-Chip 8-Bit Microcontrollers

The Intel 87C51FA/8XC51FB/8XC51FC is a single-chip control oriented microcontroller

which is fabricated on Intel’s reliable CHMOS III-E technology. The Intel 83C51FA/80C51FA

is fabricated on CHMOS III technology. Being a member of the MCS 51 controller family,

the 8XC51FA/8XC51FB/8XC51FC uses the same powerful instruction set, has the same

architecture, and is pin-for-pin compatible with the existing MCS 51 controller products. The

8XC51FA/8XC51FB/8XC51FC is an enhanced version of the 8XC52/8XC54/8XC58. Its added

features make it an even more powerful microcontroller for applications that require Pulse Width

Modulation, High Speed I/O and up/down counting capabilities such as motor control.

Quality Overview

Rochester Electronics

Manufactured Components

•

ꢀ

•

ꢀ

ISO-9001

AS9120ꢀcertiﬁcation

QualiﬁedꢀManufacturersꢀListꢀ(QML)ꢀMIL-PRF-38535

Rochesterꢀ brandedꢀ componentsꢀ areꢀ

manufactured using either die/wafers

purchased from the original suppliers

orꢀRochesterꢀwafersꢀrecreatedꢀfromꢀtheꢀ

original IP. All recreations are done with

the approval of the OCM.

•

Class Q Military

ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀClassꢀVꢀSpaceꢀLevel

QualiﬁedꢀSuppliersꢀListꢀofꢀDistributorsꢀ(QSLD)

ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀRochesterꢀisꢀaꢀcriticalꢀsupplierꢀtoꢀDLAꢀand

ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀmeetsꢀallꢀindustryꢀandꢀDLAꢀstandards.

Parts are tested using original factory

testꢀprogramsꢀorꢀRochesterꢀdevelopedꢀ

test solutions to guarantee product

meets or exceeds the OCM data sheet.

RochesterꢀElectronics,ꢀLLCꢀisꢀcommittedꢀtoꢀsupplyingꢀ

products that satisfy customer expectations for

quality and are equal to those originally supplied by

industry manufacturers.

The original manufacturer’s datasheet accompanying this document reﬂects the performance

and speciﬁcations of the Rochester manufactured version of this device. Rochester Electronics

guarantees the performance of its semiconductor products to the original OEM speciﬁcations.

‘Typical’ values are for reference purposes only. Certain minimum or maximum ratings may be

based on product characterization, design, simulation, or sample testing.

To learn more, please visit www.rocelec.com

8XC51FX

CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLERS

Commercial/Express

87C51FA/83C51FA/80C51FA/87C51FB/83C51FB/87C51FC/83C51FC

ꢀSee Table 1 for Proliferation Options

Y

High Performance CHMOS

EPROM/ROM/CPU

32 Programmable I/O Lines

7 Interrupt Sources

Y

12/24/33 MHz Operation

Four Level Interrupt Priority

Three 16-Bit Timer/Counters

Programmable Serial Channel with:

- Framing Error Detection

- Automatic Address Recognition

Programmable Counter Array with:

- High Speed Output,

- Compare/Capture,

- Pulse Width Modulator,

- Watchdog Timer Capabilities

Y

TTL Compatible Logic Levels

64K External Program Memory Space

64K External Data Memory Space

Y

Up/Down Timer/Counter

MCS 51 Controller Compatible

ꢁ

Three Level Program Lock System

8K/16K/32K On-Chip Program Memory

256 Bytes of On-Chip Data RAM

Instruction Set

Y

Power Saving Idle and Power Down

Modes

Improved Quick Pulse Programming

Algorithm

Y

ONCE (On-Circuit Emulation) Mode

Extended Temperature Range Except

Y

Boolean Processor

b

a

for 33 MHz Offering ( 40 C to 85 C)

ꢂ

MEMORY ORGANIZATION

ROM/

EPROM

Bytes

ROM

Device

EPROM

Version

ROMLESS

Version

RAM

Bytes

83C51FA

83C51FB

83C51FC

87C51FA

87C51FB

87C51FC

80C51FA

8K

16K

32K

256

These devices can address up to 64 Kbytes of external program/data memory.

The Intel 87C51FA/8XC51FB/8XC51FC is a single-chip control oriented microcontroller which is fabricated on

Intel's reliable CHMOS III-E technology. The Intel 83C51FA/80C51FA is fabricated on CHMOS III technology.

Being a member of the MCS 51 controller family, the 8XC51FA/8XC51FB/8XC51FC uses the same powerful

ꢁ

instruction set, has the same architecture, and is pin-for-pin compatible with the existing MCS 51 controller

products. The 8XC51FA/8XC51FB/8XC51FC is an enhanced version of the 8XC52/8XC54/8XC58. Its added

features make it an even more powerful microcontroller for applications that require Pulse Width Modulation,

High Speed I/O and up/down counting capabilities such as motor control.

For the remainder of this document, the 8XC51FA, 8XC51FB, 8XC51FC will be referred to as the 8XC51FX,

unless information applies to a specific device.

ꢀOther brands and names are the property of their respective owners.

Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or

copyright, for sale and use of Intel products except as provided in Intel's Terms and Conditions of Sale for such products. Intel retains the right to make

changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata.

ꢀ

COPYRIGHT

INTEL CORPORATION,2004

July 2004

Order Number: 272322-005

8XC51FX

Table 1. Proliferation Options

ꢀ1

Standard

-1

X

-2

X

-24

X

-33

X

80C51FA

X

83C51FA

87C51FA

83C51FB

87C51FB

83C51FC

87C51FC

X

NOTES:

g

ꢀ1

3.5 MHz to 12 MHz; 5V 20%

3.5 MHz to 16 MHz; 5V 20%

-1

g

-2

0.5 MHz to 12 MHz; 5V 20%

g

3.5 MHz to 24 MHz; 5V 20%

-24

-33

g

3.5 MHz to 33 MHz; 5V 10%

272322±1

Figure 1. 8XC51FX Block Diagram

2

8XC51FX

PROCESS INFORMATION

PACKAGES

Part

Package Type

The 87C51FA/8XC51FB/8XC51FC is manufactured

on P629.0, a CHMOS III-E process. Additional pro-

cess and reliability information is available in the

8XC51FX

40-Pin Plastic DIP

40-Pin CERDIP

44-Pin PLCC

®

Intel Quality System Handbook:

http://developer.intel.com/design/quality/quality.htm

44-Pin QFP

272322–23

PLCC

272322–2

DIP

272322–24

*Do not connect Reserved Pins.

QFP

Figure 2. Pin Connections

3

8XC51FX

In addition, Port 1 serves the functions of the follow-

ing special features of the 8XC51FX:

PIN DESCRIPTIONS

V

: Supply voltage.

CC

Port Pin

Alternate Function

: Circuit ground.

SS

P1.0

T2 (External Count Input to Timer/

Counter 2), Clock Out

: Secondary ground (not on DIP devices or any

SS1

P1.1

T2EX (Timer/Counter 2 Capture/

Reload Trigger and Direction Control)

83C51FA/80C51FA device). Provided to reduce

ground bounce and improve power supply by-pass-

ing.

P1.2

P1.3

ECI (External Count Input to the PCA)

CEX0 (External I/O for Compare/

Capture Module 0)

NOTE:

This pin is not a substitution for the V pin. (Con-

nection not necessary for proper operation.)

SS

P1.4

P1.5

P1.6

P1.7

CEX1 (External I/O for Compare/

Capture Module 1)

Port 0: Port 0 is an 8-bit, open drain, bidirectional

I/O port. As an output port each pin can sink several

LS TTL inputs. Port 0 pins that have 1's written to

them float, and in that state can be used as high-im-

pedance inputs.

CEX2 (External I/O for Compare/

Capture Module 2)

CEX3 (External I/O for Compare/

Capture Module 3)

CEX4 (External I/O for Compare/

Capture Module 4)

Port 0 is also the multiplexed low-order address and

data bus during accesses to external Program and

Data Memory. In this application it uses strong inter-

nal pullups when emitting 1's, and can source and

sink several LS TTL inputs.

Port 1 receives the low-order address bytes during

EPROM programming and verifying.

Port 2: Port 2 is an 8-bit bidirectional I/O port with

internal pullups. The Port 2 output buffers can drive

LS TTL inputs. Port 2 pins that have 1's written to

them are pulled high by the internal pullups, and in

that state can be used as inputs. As inputs, Port 2

pins that are externally pulled low will source current

Port 0 also receives the code bytes during EPROM

programming, and outputs the code bytes during

program verification. External pullup resistors are re-

quired during program verification.

Port 1: Port 1 is an 8-bit bidirectional I/O port with

internal pullups. The Port 1 output buffers can drive

LS TTL inputs. Port 1 pins that have 1's written to

them are pulled high by the internal pullups, and in

that state can be used as inputs. As inputs, Port 1

pins that are externally pulled low will source current

(I , on the data sheet) because of the internal pull-

IL

ups.

Port 2 emits the high-order address byte during

fetches from external Program Memory and during

accesses to external Data Memory that use 16-bit

addresses (MOVX ^ꢃDPTR). In this application it

uses strong internal pullups when emitting 1's. Dur-

ing accesses to external Data Memory that use 8-bit

addresses (MOVX ^ꢃRi), Port 2 emits the contents of

the P2 Special Function Register.

(I , on the data sheet) because of the internal pull-

IL

ups.

Some Port 2 pins receive the high-order address bits

during EPROM programming and program verifica-

tion.

Port 3: Port 3 is an 8-bit bidirectional I/O port with

internal pullups. The Port 3 output buffers can drive

LS TTL inputs. Port 3 pins that have 1's written to

them are pulled high by the internal pullups, and in

that state can be used as inputs. As inputs, Port 3

pins that are externally pulled low will source current

(I , on the data sheet) because of the pullups.

IL

4

8XC51FX

Port 3 also serves the functions of various special

features of the MCS-51 Family, as listed below:

When the 8XC51FX is executing code from external

Program Memory, PSEN is activated twice each ma-

chine cycle, except that two PSEN activations are

skipped during each access to external Data Memo-

ry.

Port Pin

Alternate Function

RXD (serial input port)

P3.0

P3.1

P3.2

P3.3

P3.4

P3.5

P3.6

P3.7

EA/V : External Access enable. EA must be

TXD (serial output port)

PP

strapped to VSS in order to enable the device to

fetch code from external Program Memory locations

0000H to 0FFFH. Note, however, that if either of the

Program Lock bits are programmed, EA will be inter-

nally latched on reset.

INT0 (external interrupt 0)

INT1 (external interrupt 1)

T0 (Timer 0 external input)

T1 (Timer 1 external input)

WR (external data memory write strobe)

RD (external data memory read strobe)

EA should be strapped to V

for internal program

CC

executions.

RST: Reset input. A high on this pin for two machine

cycles while the oscillator is running resets the de-

vice. The port pins will be driven to their reset condi-

This pin also receives the programming supply volt-

age (V ) during EPROM programming.

PP

tion when a minimum V

er the oscillator is running or not. An internal pull-

down resistor permits a power-on reset with only a

voltage is applied wheth-

IH1

XTAL1: Input to the inverting oscillator amplifier.

XTAL2: Output from the inverting oscillator amplifi-

er.

capacitor connected to V

.

CC

ALE: Address Latch Enable output pulse for latching

the low byte of the address during accesses to ex-

ternal memory. This pin (ALE/PROG) is also the

program pulse input during EPROM programming for

the 87C51FX.

OSCILLATOR CHARACTERISTICS

XTAL1 and XTAL2 are the input and output, respec-

tively, of a inverting amplifier which can be config-

ured for use as an on-chip oscillator, as shown in

Figure 3. Either a quartz crystal or ceramic resonator

may be used. More detailed information concerning

the use of the on-chip oscillator is available in Appli-

cation Note AP-155, ``Oscillators for Microcontrol-

lers.''

In normal operation ALE is emitted at a constant

rate of ꢀꢁꢂ the oscillator frequency, and may be used

for external timing or clocking purposes. Note, how-

ever, that one ALE pulse is skipped during each ac-

cess to external Data Memory.

If desired, ALE operation can be disabled by setting

bit 0 of SFR location 8EH. With this bit set, the pin is

weakly pulled high. However, the ALE disable fea-

ture will be suspended during a MOVX or MOVC in-

struction, idle mode, power down mode and ICE

mode. The ALE disable feature will be terminated by

reset. When the ALE disable feature is suspended or

terminated, the ALE pin will no longer be pulled up

weakly. Setting the ALE-disable bit has no affect if

the microcontroller is in external execution mode.

To drive the device from an external clock source,

XTAL1 should be driven, while XTAL2 floats, as

shown in Figure 4. There are no requirements on the

duty cycle of the external clock signal, since the in-

put to the internal clocking circuitry is through a

divide-by-two flip-flop, but minimum and maximum

high and low times specified on the data sheet must

be observed.

An external oscillator may encounter as much as a

100 pF load at XTAL1 when it starts up. This is due

to interaction between the amplifier and its feedback

Throughout the remainder of this data sheet, ALE

will refer to the signal coming out of the ALE/PROG

pin, and the pin will be referred to as the ALE/PROG

pin.

capacitance. Once the external signal meets the V

IL

and V specifications the capacitance will not ex-

IH

ceed 20 pF.

PSEN: Program Store Enable is the read strobe to

external Program Memory.

5

8XC51FX

Down is the last instruction executed. The on-chip

RAM and Special Function Registers retain their val-

ues until the Power Down mode is terminated.

On the 8XC51FX either hardware reset or external

interrupt can cause an exit from Power Down. Reset

redefines all the SFRs but does not change the on-

chip RAM. An external interrupt allows both the

SFRs and the on-chip RAM to retain their values.

272322±3

e

g

30 pF 10 pF for Crystals

C1, C2

For Ceramic Resonators, contact resonator manufacturer.

To properly terminate Power Down the reset or ex-

ternal interrupt should not be executed before V is

CC

Figure 3. Oscillator Connections

restored to its normal operating level and must be

held active long enough for the oscillator to restart

and stabilize (normally less than 10 ms).

With an external interrupt, INT0 or INT1 must be en-

abled and configured as level-sensitive. Holding the

pin low restarts the oscillator but bringing the pin

back high completes the exit. Once the interrupt is

serviced, the next instruction to be executed after

RETI will be the one following the instruction that put

the device into Power Down.

272322±4

Figure 4. External Clock Drive Configuration

DESIGN CONSIDERATION

Ambient light is known to affect the internal RAM

contents during operation. If the 87C51FX appli-

cation requires the part to be run under ambient

lighting, an opaque label should be placed over

the window to exclude light.

#

IDLE MODE

The user's software can invoke the Idle Mode. When

the microcontroller is in this mode, power consump-

tion is reduced. The Special Function Registers and

the onboard RAM retain their values during Idle, but

the processor stops executing instructions. Idle

Mode will be exited if the chip is reset or if an en-

abled interrupt occurs. The PCA timer/counter can

optionally be left running or paused during Idle

Mode.

When the idle mode is terminated by a hardware

reset, the device normally resumes program exe-

cution, from where it left off, up to two machine

cycles before the internal reset algorithm takes

control. On-chip hardware inhibits access to inter-

nal RAM in this event, but access to the port pins

is not inhibited. To eliminate the possibility of an

unexpected write when Idle is terminated by re-

set, the instruction following the one that invokes

Idle should not be one that writes to a port pin or

to external memory.

#

POWER DOWN MODE

To save even more power, a Power Down mode can

be invoked by software. In this mode, the oscillator

is stopped and the instruction that invoked Power

Table 2. Status of the External Pins during Idle and Power Down

Program

Mode

Idle

ALE

PSEN

PORT0

PORT1

PORT2

PORT3

Memory

Internal

External

Internal

External

1

0

1

0

Data

Float

Data

Float

Data

Address

Data

Idle

Power Down

Data

NOTE:

For more detailed information on the reduced power modes refer to current Embedded Microcontrollers and Processors

Handbook Volume I, and Application Note AP-252 (Embedded Applications Handbook), ``Designingwith the 80C51BH.''

6

8XC51FX

ONCE MODE

The EXPRESS program includes the commercial

standard temperature range with burn-in and an ex-

tended temperature range with or without burn-in.

The ONCE (``On-CircuitEmulation'') Mode facilitates

testing and debugging of systems using the

8XC51FX without the 8XC51FX having to be re-

moved from the circuit. The ONCE Mode is invoked

by:

With the commercial standard temperature range,

operational characteristics are guaranteed over the

temperature range of 0°C to 70 °C. With the extend-

ed temperature range option, operational character-

1) Pull ALE low while the device is in reset and

PSEN is high;

b

istics are guaranteed over the range of 40°C to

a

85°C.

2) Hold ALE low as RST is deactivated.

The optional burn-in is dynamic for a minimum time

While the device is in ONCE Mode, the Port 0 pins

float, and the other port pins and ALE and PSEN are

weakly pulled high. The oscillator circuit remains ac-

tive. While the 8XC51FX is in this mode, an emulator

or test CPU can be used to drive the circuit. Normal

operation is restored when a normal reset is applied.

g

of 168 hours at 125 C with V

6.9V 0.25V,

°

CC =

following guidelines in MlL-STD-883, Method 1015.

For the extended temperature range option, this

data sheet specifies the parameters which deviate

from their commercial temperature range limits.

NOTE:

8XC51FX EXPRESS

Intel offers Express Temperature specifica-

tions for all 8XC51FX speed options except

for 33 MHz.

The Intel EXPRESSsystem offers enhancements to

the operational specifications of the MCS-51 family

of microcontrollers. These EXPRESS products are

designed to meet the needs of those applications

whose operating requirements exceed commercial

standards.

Table 3. Package Identification

Package Type

Cerdip

PLCC

Temperature Range

Commercial

Extended

Burn-In

No

Plastic

QFP

No

Cerdip

PLCC

Yes

No

Extended

Plastic

QFP

Extended

Cerdip

PLCC

Extended

No

Plastic

QFP

Extended

No

Extended

No

7

8XC51FX

ABSOLUTE MAXIMUM RATINGS*

NOTICE: This data sheet contains preliminary infor-

mation on new products in production. It is valid for

the devices indicated in the revision history. The

specifications are subject to change without notice.

–

..

+

40 C to 85 C

° °

Ambient Temperature Under Bias

–

+

Storage Temperature................... 65 C to 150 C

°

+

0V to

Voltage on EA/V

Pin to V ............

13.0V

PP

SS

*WARNING:Stressing the device beyond theA" bsolute

Maximum Ratings'' may cause permanent damage.

These are stress ratings only. Operation beyond the

``Operating Conditions'' is not recommended and ex-

tended exposure beyond the ``Operating Conditions''

may affect device reliability.

– +

... 0.5V to 6.5V

Voltage on Any Other Pin to V

SS

15mA

per I/O Pin..................................................

I

OL

1.5W

Power Dissipation...............................................

(based on PACKAGE heat transfer limitations, not

device power consumption)

OPERATING CONDITIONS

Symbol

Description

Min

Max

Units

T

A

Ambient Temperature Under Bias

Commercial

+

0

40

70

°C

-

+

Express

85

V

CC

Supply Voltage

8XC51FX-33

All Others

4.5

4.0

5.5

6.0

V

f

Oscillator Frequency

8XC51FX

OSC

3.5

0.5

3.5

12

16

12

24

33

8XC51FX-1

8XC51FX-2

8XC51FX-24

8XC51FX-33

MHz

DC CHARACTERISTICS (Over Operating Conditions)

All parameter values apply to all devices unless otherwise indicated.

Typical

(Note 4)

Symbol

Parameter

Input Low Voltage

Min

Max

0.2 V -0.1

Units

Test Conditions

-

V

0.5

0

V

IL

CC

-

Input Low Voltage EA

0.2 V

0.3

0.5

V

IL1

IH

CC

+

Input High Voltage

0.2 V

0.9

V

CC

V

CC

(Except XTAL1, RST)

+

0.5

V

Input High Voltage

(XTAL1, RST)

0.7 V

V

CC

V

IH1

OL

CC

Output Low Voltage (Note 5)

(Ports 1, 2 and 3)

0.3

0.45

1.0

I

100 A

1.6 mA (Note 1)

3.5 mA

OL =

=

V

OL

=

OL

=

V

Output Low Voltage (Note 5)

(Port 0, ALE/PROG, PSEN)

0.3

0.45

1.0

I

200 A

3.2 mA (Note 1)

7.0 mA

OL1

OH

OL

=

OL

=

OL

–

= –

10 A

Output High Voltage

(Ports 1, 2 and 3

ALE/PROG and PSEN)

V

CC

V

CC

V

CC

0.3

0.7

1.5

I

OH

= –

V

30 A (Note 2)

60 A

OH

= –

–

= –

Output High Voltage

(Port 0 in External Bus Mode)

V

CC

V

CC

V

CC

0.3

0.7

1.5

I

200 A

3.2 mA (Note 2)

7.0 mA

OH1

OH

V

83C51FA/80C51FA (Express)

6.0 mA

-

=

0.45V

I

IL

Logical 0 Input Current

(Ports 1, 2 and 3)

50

A

V

IN

8

8XC51FX

DC CHARACTERISTICS (Over Operating Conditions)

All parameter values apply to all devices unless otherwise indicated. (Continued)

Typical

(Note 4)

Symbol

Parameter

Min

Max

Units

Test Conditions

e

g

I

Input leakage Current (Port 0)

10

mA

V

V or V

IL IH

LI

IN

e

Logical 1 to 0 Transition Current

(Ports 1, 2 and 3)

Express

2V

TL

IN

b

750

650

mA

Commercial

RRST

CIO

RST Pulldown Resistor

Pin Capacitance

40

225

KX

10

pF

^ꢃ1MHz, 25 C

ꢂ

I

Power Supply Current:

Active Mode

(Note 3)

CC

At 12 MHz (Figure 5)

At 16 MHz

At 24 MHz

15

20

28

35

30

38

56

mA

At 33 MHz

Idle Mode

At 12 MHz (Figure 5)

At 16 MHz

At 24 MHz

At 33 MHz

5

6

7

5

7.5

9.5

13.5

15

mA

Power Down Mode

75

NOTES:

1. Capacitive loading on Ports 0 and 2 may cause noise pulses above 0.4V to be superimposed on the V s of ALE and

OL

Ports 1, 2 and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins

change from 1 to 0. In applications where capacitance loading exceeds 100 pF, the noise pulses on these signals may

exceed 0.8V. It may be desirable to qualify ALE or other signals with a Schmitt Trigger, or CMOS-level input logic.

2. Capacitive loading on Ports 0 and 2 cause the V

address lines are stabilizing.

on ALE and PSEN to drop below the 0.9 V specification when the

OH

CC

3. See Figures 6±9 for test conditions. Minimum V

for power down is 2V.

CC

4. Typicals are based on limited number of samples, and are not guaranteed. The values listed are at room temperature and 5V.

5. Under steady state (non-transient) conditions, I must be externally limited as follows:

OL

10 mA

Maximum I per port pin:

OL

Maximum I per 8-bit port -

OL

Port 0:

Ports 1, 2, and 3:

Maximum total I for all output pins:

26 mA

15 mA

71 mA

OL

If I exceeds the test condition, V may exceed the related specification. Pins are not guaranteed to sink current greater

OL

than the listed test conditions.

272322±5

NOTE:

g

I

max at 33 MHz is at 5V 10% V , while I

max at 24 MHz and below is at 5V 20% V .

CC

CC CC

CC

Figure 5. 8XC51FA/FB/FC I vs Frequency

CC

9

8XC51FX

272322±6

272322±7

All other pins disconnected

TCLCH

e

TCHCL 5 ns

TCLCH

TCHCL

5 ns

Figure 6. I Test Condition, Active Mode

CC

Figure 7. I Test Condition Idle Mode

CC

272322±8

All other pins disconnected

Figure 8. I Test Condition, Power Down Mode.

CC

e

V

2.0V to 6.0V.

CC

272322±19

e

5 ns.

Figure 9. Clock Signal Waveform for I Tests in Active and Idle Modes. TCLCH

TCHCL

CC

10

8XC51FX

L: Logic level LOW, or ALE

P: PSEN

EXPLANATION OF THE AC SYMBOLS

Each timing symbol has 5 characters. The first char-

acter is always a `T' (stands for time). The other

characters, depending on their positions, stand for

the name of a signal or the logical status of that

signal. The following is a list of all the characters and

what they stand for.

Q: Output Data

R: RD signal

T: Time

V: Valid

W: WR signal

X: No longer a valid logic level

Z: Float

A: Address

C: Clock

D: Input Data

For example,

H: Logic level HIGH

I: Instruction (program memory contents)

e

TAVLL

TLLPL

Time from Address Valid to ALE Low

Time from ALE Low to PSEN Low

AC CHARACTERISTICS (Over Operating Conditions, Load Capacitance for Port 0, ALE/PROG and

e

80 pF)

PSEN 100 pF, Load Capacitance for All Other Outputs

EXTERNAL MEMORY CHARACTERISTICS

All parameter values apply to all devices unless otherwise indicated. In this table, 8XC51FX refers to

8XC51FX, 8XC51FX-1 and 8XC51FX-2.

Oscillator

Symbol

Parameter

Units

12 MHz

24 MHz

33 MHz

Variable

Min Max Min Max Min Max

Min

Max

1/TCLCL Oscillator Frequency

8XC51FX

3.5

0.5

3.5

12

16

12

24

33

8XC51FX-1

8XC51FX-2

8XC51FX-24

8XC51FX-33

MHz

ns

b

2TCLCL 40

TLHLL

TAVLL

ALE Pulse Width

127

43

12

21

Address Valid to ALE Low

8XC51FX

8XC51FX-24

b

TCLCL 40

ns

b

TCLCL 30

b

TCLCL 25

8XC51FX-33

5

TLLAX

TLLIV

Address Hold After ALE Low

8XC51FX/-24

8XC51FX-33

b

53

TCLCL 30

ns

b

TCLCL 25

ALE Low to Valid Instr In

8XC51FX

8XC51FX-24

b

4TCLCL 100 ns

4TCLCL 75 ns

4TCLCL 65 ns

234

b

91

8XC51FX-33

56

TLLPL

ALE Low to PSEN Low

8XC51FX/-24

8XC51FX-33

b

53

12

80

TCLCL 30

ns

b

TCLCL 25

5

b

TPLPH PSEN Pulse Width

205

46

3TCLCL 45

TPLIV

PSEN Low to Valid Instr In

8XC51FX

8XC51FX-24

8XC51FX-33

b

3TCLCL 105 ns

145

b

35

3TCLCL 90 ns

b

35

3TCLCL 55 ns

TPXIX

Input Instr Hold after PSEN

0

ns

11

8XC51FX

EXTERNAL MEMORY CHARACTERISTICS (Continued)

All parameter values apply to all devices unless otherwise indicated

Oscillator

33 MHz

Symbol

Parameter

Units

12 MHz

24 MHz

Variable

Min Max Min Max Min Max

Min

Max

TPXIZ Input Instr Float After PSEN

8XC51FX

59

21

5

TCLCL-25

TCLCL-20

TCLCL-25

ns

8XC51FX-24

8XC51FX-33

TAVIV Address to Valid Instr In

8XC51FX/-24

b

5TCLCL 105 ns

312

10

103

10

b

5TCLCL 80 ns

8XC51FX-33

71

10

TPLAZ PSEN Low to Address Float

TRLRH RD Pulse Width

10

ns

b

6TCLCL 100

400

150

82

b

TWLWH WR Pulse Width

6TCLCL 100

TRLDV RD Low to Valid Data In

8XC51FX

b

5TCLCL 165 ns

252

b

8XC51FX-24

8XC51FX-33

113

23

5TCLCL 95 ns

b

61

5TCLCL 90 ns

TRHDX Data Hold After RD

0

ns

TRHDZ Data Float After RD

8XC51FX/24

b

2TCLCL 60 ns

b

2TCLCL 25 ns

107

517

585

8XC51FX-33

35

TLLDV ALE Low to Valid Data In

8XC51FX

b

8TCLCL 150 ns

b

8TCLCL 90 ns

8XC51FX-24/33

243

285

150

180

TAVDV Address to Valid Data In

8XC51FX

b

9TCLCL 165 ns

b

9TCLCL 90 ns

8XC51FX-24/33

b

a

TLLWL ALE Low to RD or WR Low 200 300 75 175 41 140 3TCLCL 50 3TCLCL 50 ns

TAVWL Address to RD or WR Low

b

8XC51FX

8XC51FX-24

8XC51FX-33

203

4TCLCL 130

ns

b

4TCLCL 90

77

b

4TCLCL 75

46

0

TQVWX Data Valid to WR Transition

8XC51FX

b

33

TCLCL 50

ns

b

TCLCL 30

8XC51FX-24/33

12

7

TWHQX Data Hold After WR

8XC51FX

b

TCLCL 50

ns

b

TCLCL 35

8XC51FX-24

8XC51FX-33

b

TCLCL 27

3

TQVWH Data Valid to WR High

8XC51FX

b

433

7TCLCL 150

ns

b

7TCLCL 70

8XC51FX-24/33

222

142

TRLAZ RD Low to Address Float

0

ns

TWHLH RD or WR High to ALE High

8XC51FX

b

a

43 123

TCLCL 40

ns

b

a

TCLCL 30

8XC51FX-24

8XC51FX-33

12 71

TCLCL 30

b

a

TCLCL 25

5

55

TCLCL 25

12

8XC51FX

EXTERNAL PROGRAM MEMORY READ CYCLE

272322±9

EXTERNAL DATA MEMORY READ CYCLE

272322±10

EXTERNAL DATA MEMORY WRITE CYCLE

272322±11

13

8XC51FX

SERIAL PORT TIMINGÐSHIFT REGISTER MODE

e

Test Conditions: Over Operating Conditions; Load Capacitance

80 pF

Oscillator

Symbol

Parameter

Units

12 MHz

24 MHz

33 MHz

Variable

Max

Min Max Min Max Min Max

Min

TXLXL Serial Port

Clock

1

0.50

284

0.36

167

12TCLCL

ms

Cycle Time

b

TQVXH Output Data

Setup to Clock

700

10TCLCL 133

ns

Rising Edge

TXHQX Output Data

Hold After Clock

Rising Edge

b

8XC51FX

8XC51FX-24/33

50

0

2TCLCL 117

ns

b

34

10

2TCLCL 50

TXHDX Input Data Hold

After Clock

0

ns

Rising Edge

b

10TCLCL 133

TXHDV Clock Rising

Edge to Input

700

283

167

ns

Data Valid

SHIFT REGISTER MODE TIMING WAVEFORMS

272322±12

14

8XC51FX

Units

EXTERNAL CLOCK DRIVE

Symbol

Parameter

Min

3.5

0.5

3.5

Max

1/TCLCL

Oscillator Frequency

8XC51FX

MHz

12

16

12

24

33

8XC51FX-1

8XC51FX-2

8XC51FX-24

8XC51FX-33

TCHCX

TCLCX

TCLCH

High Time

8XC51FX-24/33

20

ns

0.35 T

0.65 T

OSC

Low Time

8XC51FX-24/33

20

ns

0.35 T

0.65 T

OSC

Rise Time

8XC51FX-24

8XC51FX-33

20

10

5

ns

TCHCL

Fall Time

8XC51FX-24

8XC51FX-33

20

10

5

ns

EXTERNAL CLOCK DRIVE WAVEFORM

272322±13

AC TESTING INPUT, OUTPUT WAVEFORMS

FLOAT WAVEFORMS

272322±15

272322±14

For timing purposes

100 mV change from load voltage occurs, and begins to float

when a 100 mV change from the loaded V /V level occurs.

a port pin is no longer floating when a

b

AC Inputs during testing are driven at V

0.5V for a Logic ``1''

and 0.45V for a Logic ``0''. Timing measurements are made at V

CC

IH

OH OL

min for a Logic ``1'' and V max for a Logic ``0''.

OL

e

g

I

/I

20 mA.

OL OH

15

8XC51FX

Normally EA/V

fore ALE/PROG is to be pulsed. Then EA/V

is held at logic high until just be-

PP

PROGRAMMING THE EPROM/OTP

is

PP

raised to V , ALE/PROG is pulsed low, and then

To be programmed, the part must be running with a

4 to 6 MHz oscillator. (The reason the oscillator

needs to be running is that the internal bus is being

used to transfer address and program data to appro-

priate internal EPROM locations.) The address of an

EPROM location to be programmed is applied to

Port 1 and pins P2.0 - P2.4 of Port 2, while the code

byte to be programmed into that location is applied

to Port 0. The other Port 2 and 3 pins, RST PSEN,

PP

EA/V

is returned to a valid high voltage. The volt-

PP

age on the EA/V

pin must be at the valid EA/V

PP

high level before a verify is attempted. Waveforms

and detailed timing specifications are shown in later

sections of this data sheet.

NOTE:

EA/V

pin must not be allowed to go above the

#

PP

and EA/V

should be held at the ``Program'' levels

PP

maximum specified V level for any amount of

PP

indicated in Table 4. ALE/PROG is pulsed low to

program the code byte into the addressed EPROM

location. The setup is shown in Figure 10.

time. Even a narrow glitch above that voltage lev-

el can cause permanent damage to the device.

The V source should be well regulated and free

PP

of glitches.

Table 4. EPROM Programming Modes

ALE/

PROG

EA/

V

PP

Mode

RST

PSEN

P2.6

P2.7

P3.3

P3.6

P3.7

Program Code Data

Verify Code Data

H

L

ꢀ

H

12.75V

H

L

H

L

H

L

H

L

H

Program Encryption

ꢀ

12.75V

H

Array Address 0±3FH

Program Lock

Bits

Bit 1

Bit 2

Bit 3

H

L

ꢀ

H

12.75V

H

L

H

L

H

L

H

L

H

L

H

L

Read Signature Byte

L

272322±20

ꢀSee Table 4 for proper input on these pins

Figure 10. Programming the EPROM

16

8XC51FX

Repeat 1 through 5 changing the address and data

for the entire array or until the end of the object file is

reached.

PROGRAMMING ALGORITHM

Refer to Table 4 and Figures 10 and 11 for address,

data, and control signals set up. To program the

87C51FX the following sequence must be exercised.

PROGRAM VERIFY

1. Input the valid address on the address lines.

2. Input the appropriate data byte on the data

lines.

Program verify may be done after each byte or block

of bytes is programmed. In either case a complete

verify of the programmed array will ensure reliable

programming of the 87C51FX.

3. Activate the correct combination of control sig-

nals.

g

from V to 12.75V 0.25V.

CC

4. Raise EA/V

PP

The lock bits cannot be directly verified. Verification

of the lock bits is done by observing that their fea-

tures are enabled.

5. Pulse, ALE/PROG 5 times for the EPROM ar-

ray, and 25 times for the encryption table and

the lock bits.

272322±21

Figure 11. Programming Signals Waveforms

lock-bit and encryption array are programmed by the

factory. The encryption array is not available without

the lock bit. For the lock bit to be programmed, the

user must submit an encryption table. The 83C51FA

does not have protection features.

ROM and EPROM Lock System

The 87C51FX program lock system, when pro-

grammed, protects the onboard program against

software piracy.

The 87C51FX has a 3-level program lock system

and a 64-byte encryption array. Since this is an

EPROM device, all locations are user-programma-

ble. See Table 5.

The 83C51FX has a one-level program lock system

and a 64-byte encryption table. See line 2 of Table

5. If program protection is desired, the user submits

the encryption table with their code, and both the

Table 5. Program Lock Bits and the Features

Program Lock Bits

LB1 LB2 LB3

ProtectIon Type

1

U

No Program Lock features enabled. (Code verify will still be encrypted by the

Encryption Array if programmed.)

2

P

U

MOVC instructions executed from external program memory are disabled from

fetching code bytes from internal memory, EA is sampled and latched on Reset, and

further programming of the EPROM is disabled.

3

4

P

U

P

Same as 2, also verify is disabled.

Same as 3, also external execution is disabled.

Any other combination of the lock bits is not defined.

17

8XC51FX

bytes in locations 30H and 31H. To read these bytes

follow the procedure for EPROM verify, but activate

the control lines provided in Table 4 for Read Signa-

ture Byte.

Encryption Array

Within the EPROM array are 64 bytes of Encryption

Array that are initially unprogrammed (all 1's). Every

time that a byte is addressed during a verify, 6 ad-

dress lines are used to select a byte of the Encryp-

tion Array. This byte is then exclusive-NOR'ed

(XNOR) with the code byte, creating an Encryption

Verify byte. The algorithm, with the array in the un-

programmed state (all 1's), will return the code in its

original, unmodified form. For programming the En-

cryption Array, refer to Table 4 (Programming the

EPROM).

Location

30H

Device

All

Contents

89H

31H

All

58H

60H

83C51FA

87C51FA

83C51FB

87C51FB

83C51FC

87C51FC

7AH/FAH

FAH

7BH/FBH

FBH

When using the encryption array, one important fac-

tor needs to be considered. If a code byte has the

value 0FFH, verifying the byte will produce the en-

7CH/FCH

FCH

l

cryption byte value. lf a large block ( 64 bytes) of

code is left unprogrammed, a verification routine will

display the contents of the encryption array. For this

reason all unused code bytes should be pro-

grammed with some value other than 0FFH, and not

all of them the same value. This will ensure maxi-

mum program protection.

Erasure Characteristics (Windowed

Packages Only)

Erasure of the EPROM begins to occur when the

chip is exposed to light with wavelength shorter than

approximately 4,000 Angstroms. Since sunlight and

fluorescent lighting have wavelengths in this range,

exposure to these light sources over an extended

time (about 1 week in sunlight, or 3 years in room-

level fluorescent lighting) could cause inadvertent

erasure. If an application subjects the device to this

type of exposure, it is suggested that an opaque la-

bel be placed over the window.

Program Lock Bits

The 87C51FX has 3 programmable lock bits that

when programmed according to Table 5 will provide

different levels of protection for the on-chip code

and data.

Erasing the EPROM also erases the encryption ar-

ray and the program lock bits, returning the part to

full functionality.

The recommended erasure procedure is exposure

to ultraviolet light (at 2537 Angstroms) to an integrat-

ed dose of at least 15 W-sec/cm. Exposing the

EPROM to an ultraviolet lamp of 12,000 mW/cm rat-

ing for 30 minutes, at a distance of about 1 inch,

should be sufficient.

Reading the Signature Bytes

The 87C51FX has 3 signature bytes in locations

30H, 31H, and 60H. The 83C51FA has 2 signature

Erasure leaves all the EPROM Cells in a 1's state.

18

8XC51FX

EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS

e

0V)

SS

g

(T

A

21 C to 27 C; V

5V 20%; V

ꢂ

CC

Symbol

Parameter

Min

Max

13.0

75

Units

V

PP

Programming Supply Voltage

Programming Supply Current

Oscillator Frequency

12.5

I

mA

PP

1/TCLCL

TAVGL

TGHAX

TDVGL

TGHDX

TEHSH

TSHGL

TGHSL

TGLGH

TAVQV

TELQV

TEHQZ

TGHGL

4

6

MHz

Address Setup to PROG Low

Address Hold after PROG

Data Setup to PROG Low

Data Hold after PROG

48TCLCL

10

P2.7 (ENABLE) High to V

PP

V

PP

V

PP

Setup to PROG Low

Hold after PROG

ms

10

PROG Width

90

110

Address to Data Valid

48TCLCL

ENABLE Low to Data Valid

Data Float after ENABLE

PROG High to PROG Low

0

10

ms

EPROM PROGRAMMING AND VERIFICATION WAVEFORMS

272322±18

NOTE:

ꢀ5 pulses for the EPROM array, 25 pulses for the encryption table and lock bits.

19

8XC51FX

Thermal Impedance

Device

i

JC

JA

All thermal impedance data is approximate for static

air conditions at 1W of power dissipation. Values will

change depending on operating conditions and ap-

plications. See the Intel Packaging Handbook (Order

No. 240800) for a description of Intel's thermal im-

pedance test methodology.

All 45 C/W 16 C/W

°

80C51FA, 83C51FA, 36 C/W 13 C/W

°

8XC51FC

87C51FA, 8XC51FB 45 C/W 15 C/W

°

All 46 C/W 16 C/W

FA 97 C/W 24 C/W

°

FB 96 C/W 24 C/W

°

FC 87 C/W 18 C/W

°

DATA SHEET REVISION HISTORY

Data sheets are changed as new device information becomes available. Verify with your local Intel sales office

that you have the latest version before finalizing a design or ordering devices.

The following differences exist between this datasheet (272322-005) and the previous version (272322-004):

1. Product prefix variables are now indicated with an x.

The following differences exist between this datasheet (272322-003) and the previous version (272322-002):

1. Removed 8XC51FX-3 and 8XC51FX-20, replaced with 8XC51FX-24.

2. Included 8XC51FX-24 and 8XC51FX-33 devices.

3. 80C51FA and 83C51FA now have the same features as 87C51FA, 8XC51FB and 8XC51FC; same DC spec

used for all devices.

The following differences exist between the ``-002'' and ``-001'' version of 8XC51FX datasheet:

1. Removed 8XC51FX-L from datasheet.

2. Include V

for 83C51FA (Express)/80C51FA (Express).

OH1

This 8XC51FX datasheet (272322-001) replaces the following datasheets:

87C51FA/83C51FA/80C51FA

83C51FA/80C51FA EXPRESS

87C51FA EXPRESS

270258-007

270620-001

270619-001

272081-002

270563-005

272080-002

270767-002

270789-004

270903-001

272028-002

87C51FA-20/-3

87C51FB/83C51FB

87C51FB-20/-3 83C51FB-20/-3

87C51FB/83C51FB EXPRESS

87C51FC/83C51FC

87C51FC/83C51FC EXPRESS

87C51FC-20/-3 83C51FC-20/-3

20


型号：	S80C51FA
厂家：	Rochester Electronics
描述：	Microcontroller, 8-Bit, 12MHz, CMOS, PQFP44, QFP-44 微控制器
文件：	总21页 (文件大小：609K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

S80C51FA [ROCHESTER]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E