SN74AS162N [ROCHESTER]
Decade Counter, AS Series, Synchronous, Positive Edge Triggered, 4-Bit, Up Direction, TTL, PDIP16, 0.300 INCH, PLASTIC, DIP-16;
| 型号： | SN74AS162N |
| 厂家： | 
Rochester Electronics |
| 描述： | Decade Counter, AS Series, Synchronous, Positive Edge Triggered, 4-Bit, Up Direction, TTL, PDIP16, 0.300 INCH, PLASTIC, DIP-16 光电二极管 输出元件 逻辑集成电路 触发器 |
| 文件： | 总14页 (文件大小：1015K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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ꢀ ꢁꢑ ꢃ ꢄꢅꢀ ꢆ ꢇꢈ ꢉꢊ ꢋ ꢌꢍꢎꢊ ꢀꢁꢑ ꢃ ꢄ ꢅꢀ ꢆ ꢇ ꢏ ꢉꢐꢊ ꢀꢁꢑ ꢃꢄꢀ ꢆ ꢇꢈ ꢊ ꢋꢌ ꢍꢎꢊ ꢀ ꢁꢑ ꢃꢄꢀ ꢆꢇ
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SDAS024A − D2661, APRIL 1982 − REVISED MAY 1986
SN54ALS’, SN54AS’ . . . J PACKAGE
SN74ALS’, SN74AS’ . . . D OR N PACKAGE
• Internal Look-Ahead for Fast Counting
• Carry Output for n-Bit Cascading
• Synchronous Counting
(TOP VIEW)
• Synchronously Programmable
• Package Options include Plastic Small
V
RCO
Q
Q
B
Q
Q
D
ENT
LOAD
CLR
CLK
A
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CC
Outline Packages, Ceramic Chip Carriers,
and Standard Plastic and Ceramic 300-mil
DIPs
A
B
C
D
C
• Dependable Texas Instruments Quality and
ENP
GND
Reliability
description
SN54ALS’, SN54AS’ . . . FK PACKAGE
(TOP VIEW)
These synchronous, presettable counters feature
an internal carry look-ahead for application in
high-speed counting designs. The ’ALS160B,
’ALS162B, ’AS160, and ’AS162 are decade
counters, and the ’ALS161B, ’ALS163B, ’AS161,
and ’AS163 are 4-bit binary counters. Synchro-
nous operation is provided by having all flip-flops
clocked simultaneously so that the outputs
change coincident with each other when so
instructed by the count-enable inputs and internal
gating. This mode of operation eliminates the
output counting spikes that are normally asso-
ciated with asynchronous (ripple clock)
counters. A buffered clock input triggers the four
flip-flops on the rising (positive-going) edge of the
clock input waveform.
3
2
1
20 19
18
Q
Q
A
B
4
5
6
7
8
A
B
17
16
15
14
NC
NC
C
Q
C
Q
D
D
9 10 11 12 13
NC−No internal connection
These counters are fully programmable; that is, they may be preset to any number between 0 and 9, or 15. As
presetting is synchronous, setting up a low level at the load input disables the counter and causes the outputs
to agree with the setup data after the next clock pulse regardless of the levels of the enable inputs.
The clear function for the ’ALS160B, ’ALS161B, ’AS160, and ’AS161 is asynchronous and a low level at the clear
input sets all four of the flip-flop outputs low regardless of the levels of the clock, load, or enable inputs. This
synchronous clear allows the count length to be modified easily by decoding the Q outputs for the maximum
count desired. The active-low output of the gate used for decoding is connected to the clear input to
synchronously clear the counter to 0000 (LLLL).
The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without
additional gating. Instrumental in accomplishing this function are two count-enable inputs and a ripple carry
output. Both count-enable inputs (ENP and ENT) must be high to count, and ENT is fed forward to enable the
ripple carry output. The ripple carry output (RCO) thus enabled will produce a high-level pulse while the count
is maximum (9 or 15 with Q high). This high-level overflow ripple carry pulse can be used to enable successive
A
cascaded stages. Transitions at the ENP or ENT are allowed regardless of the level of the clock input.
These counters feature a fully independent clock circuit. Changes at control inputs (ENP, ENT, or LOAD) that
will modify the operating mode have no effect on the contents of the counter until clocking occurs. The function
of the counter (whether enabled, disabled, loading, or counting) will be dictated solely by the conditions meeting
the stable setup and hold times.
The SN54ALS160B through SN54ALS163B and SN54AS160 through SN54AS163 are characterized for
operation over the full military temperature range of −55°C to 125°C. The SN74ALS160B through
SN74ALS163B and SN74AS160 through SN74AS163 are characterized for operation from 0°C to 70°C.
ꢚꢍ ꢔ ꢗꢎ ꢓ ꢋꢖ ꢔꢁ ꢗ ꢄꢋꢄ ꢛꢜ ꢝ ꢞꢟ ꢠꢡ ꢢꢛꢞ ꢜ ꢛꢣ ꢤꢥ ꢟ ꢟ ꢦꢜꢢ ꢡꢣ ꢞꢝ ꢧꢥꢨ ꢩꢛꢤ ꢡꢢ ꢛꢞꢜ ꢪꢡ ꢢꢦ ꢫ
ꢚꢟ ꢞ ꢪꢥꢤ ꢢ ꢣ ꢤ ꢞꢜ ꢝꢞ ꢟ ꢠ ꢢ ꢞ ꢣ ꢧꢦ ꢤ ꢛꢝ ꢛꢤꢡ ꢢꢛ ꢞꢜꢣ ꢧꢦ ꢟ ꢢꢬ ꢦ ꢢꢦ ꢟ ꢠꢣ ꢞꢝ ꢋꢦꢭ ꢡꢣ ꢖꢜꢣ ꢢꢟ ꢥꢠ ꢦꢜꢢ ꢣ
ꢣ ꢢ ꢡ ꢜꢪ ꢡ ꢟꢪ ꢮ ꢡ ꢟꢟ ꢡ ꢜ ꢢꢯꢫ ꢚꢟ ꢞ ꢪꢥꢤ ꢢꢛꢞꢜ ꢧꢟ ꢞꢤ ꢦꢣ ꢣꢛ ꢜꢰ ꢪꢞꢦ ꢣ ꢜꢞꢢ ꢜꢦ ꢤꢦ ꢣꢣ ꢡꢟ ꢛꢩ ꢯ ꢛꢜꢤ ꢩꢥꢪ ꢦ
ꢢ ꢦ ꢣ ꢢꢛ ꢜꢰ ꢞꢝ ꢡ ꢩꢩ ꢧꢡ ꢟ ꢡ ꢠ ꢦ ꢢ ꢦ ꢟ ꢣ ꢫ
Copyright 1986, Texas Instruments Incorporated
5BASIC
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
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SDAS024A − D2661, APRIL 1982 − REVISED MAY 1986
†
logic symbols
’ALS160B AND ’AS160 BINARY
’ALS162B AND ’AS162 BINARY
COUNTERS WITH DIRECT CLEAR
COUNTERS WITH SYNCHRONOUS CLEAR
CTRDIV10
CT=0
CTRDIV10
1
1
9
CLR
CLR
5CT=0
M1
9
LOAD
M1
LOAD
M2
M2
15
15
RCO
RCO
3CT = 9
3CT = 9
10
7
10
7
ENT
ENP
CLK
G3
G4
ENT
ENP
CLK
G3
G4
2
2
C5/2,3,4+
C5/2,3,4+
14
14
3
3
A
1,5D
[1]
Q
A
1,5D
[1]
Q
A
A
13
12
11
13
12
11
4
5
6
4
5
6
B
C
D
[2]
[4]
[8]
Q
Q
Q
B
C
D
[2]
[4]
[8]
Q
Q
Q
B
C
D
B
C
D
’ALS160B and ’AS160 logic diagram (positive logic)
1
9
10
7
CLR
LOAD
ENT
ENP
15
14
RCO
2
CLK
C1
1D
R
Q
A
3
A
13
12
C1
1D
R
Q
Q
B
C
4
B
C1
1D
R
5
C
11
C1
Q
D
1D
R
6
D
†
These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for D, J, and N packages.
’ALS162B and ’AS162 decade counters are similar; however the clear is synchronous as shown for the ’ALS163B and ’AS163 binary counters.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
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SDAS024A − D2661, APRIL 1982 − REVISED MAY 1986
†
logic symbols
’ALS161B AND ’AS161 BINARY
COUNTERS WITH DIRECT CLEAR
’ALS163B AND ’AS163 BINARY
COUNTERS WITH SYNCHRONOUS CLEAR
CTRDIV16
CT=0
CTRDIV16
1
9
1
CLR
CLR
5CT=0
9
LOAD
M1
LOAD
M1
M2
M2
15
14
15
14
RCO
RCO
3CT = 15
3CT = 15
10
7
10
7
ENT
ENP
CLK
G3
G4
ENT
ENP
CLK
G3
G4
2
2
C5/2,3,4+
C5/2,3,4+
3
3
A
1,5D [1]
Q
A
1,5D [1]
Q
A
A
13
12
11
13
12
11
4
5
6
4
5
6
B
C
D
[2]
[4]
[8]
Q
Q
Q
B
C
D
[2]
[4]
[8]
Q
Q
Q
B
C
D
B
C
D
’ALS163B and ’AS163 logic diagram (positive logic)
1
9
CLR
LOAD
10
7
15
14
ENT
ENP
RCO
2
CLK
C1
1D
Q
A
3
A
13
12
C1
1D
Q
Q
B
C
4
B
C1
1D
5
C
11
C1
1D
Q
D
6
D
†
These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for D, J, and N packages.
’ALS161B and ’AS161 synchronous binary counters are similar; however the clear is asynchronous as shown for the ’ALS160B and ’AS160 decade
counters.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
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ꢁ ꢂ ꢃꢄ ꢅ ꢀꢆ ꢇ ꢈꢉ ꢐ ꢊ ꢀꢁ ꢂꢃ ꢄꢅ ꢀ ꢆ ꢇ ꢱ ꢉꢐ ꢊ ꢀꢁꢂ ꢃ ꢄ ꢀꢆ ꢇ ꢈ ꢐꢊ ꢀ ꢁꢂ ꢃ ꢄꢀ ꢆ ꢇ ꢱ
ꢁ ꢑ ꢃꢄ ꢅ ꢀꢆ ꢇ ꢈꢉ ꢐ ꢊ ꢀꢁ ꢑꢃ ꢄꢅ ꢀ ꢆ ꢇ ꢱ ꢉꢐ ꢊ ꢀꢁꢑ ꢃ ꢄ ꢀꢆ ꢇ ꢈ ꢐꢊ ꢀ ꢁꢑ ꢃ ꢄꢀ ꢆ ꢇ ꢱ
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SDAS024A − D2661, APRIL 1982 − REVISED MAY 1986
typical clear, preset, count, and inhibit sequences
’ALS160B, ’AS160, ’ALS162B, ’AS162
Illustrated below is the following sequence:
1. Clear outputs to zero (’ALS160B and ’AS160 are asynchronous; ’ALS162B and ’AS1162 are synchronous)
2. Preset to BCD seven
3. Count to eight, nine, zero, one, two, and three
4. Inhibit
CLR
LOAD
A
B
Data
Inputs
C
D
CLK
ENP
ENT
Q
Q
A
B
Outputs
Q
Q
C
D
RCO
7
8
9
0
1
2
3
Count
Inhibit
Sync Preset
Clear
Async
Clear
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
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ꢆꢇ
ꢆꢐ
ꢁꢑ
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SDAS024A − D2661, APRIL 1982 − REVISED MAY 1986
typical clear, preset, count, and inhibit sequences
’ALS161B, ’AS161, ’ALS163B, ’AS163
Illustrated below is the following sequence:
1. Clear outputs to zero (’ALS161B and ’AS161 are asynchronous; ’ALS163B and ’AS163 are synchronous)
2. Preset to binary twelve
3. Count to thirteen, fourteen, fiften, zero, one, and two
4. Inhibit
CLR
LOAD
A
B
Data
Inputs
C
D
CLK
ENP
ENT
Q
Q
A
B
Outputs
Q
Q
C
D
RCO
12
13 14
0
1
2
3
Count
Inhibit
Sync Preset
Clear
Async
Clear
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
ꢀ
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ꢁ ꢂ ꢃꢄ ꢅ ꢀꢆ ꢇ ꢈꢉ ꢊ ꢋꢌ ꢍꢎ ꢊꢀ ꢁꢂ ꢃ ꢄꢅ ꢀꢆ ꢇ ꢏ ꢉ
ꢁ ꢑ ꢃꢄ ꢅ ꢀꢆ ꢇ ꢈꢉ ꢊ ꢋꢌ ꢍꢎ ꢊꢀ ꢁꢑ ꢃ ꢄꢅ ꢀꢆ ꢇ ꢏ ꢉ
ꢙ
ꢒ
ꢁꢓ
ꢌ
ꢍ
ꢔ
ꢁ
ꢔꢎ
ꢀ
ꢊ
ꢃ
ꢕ
ꢉ
ꢖ
ꢋ
ꢊꢗ
ꢘ
ꢓ
ꢄ
ꢗ
ꢘ
ꢊ
ꢓ
ꢔꢎ
ꢁ
ꢋ
ꢘ
ꢍ
ꢀ
SDAS024A − D2661, APRIL 1982 − REVISED MAY 1986
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
CC
Input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Operating free-air temperature range: SN54ALS160B thru SN54ALS163B . . . . . . . . . . . . −55°C to 125°C
SN74ALS160B thru SN74ALS163B . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
recommended operating conditions
SN54ALS160B
THRU
SN54ALS163B
SN74ALS160B
THRU
SN74ALS163B
UNIT
MIN NOM
MAX
MIN NOM
MAX
V
V
V
Supply voltage
4.5
2
5
5.5
4.5
2
5
5.5
V
V
CC
IH
High-level input voltage
Low-level input voltage
High-level output current
Low-level output current
Clock frequency
0.7
−0.4
4
0.8
−0.4
8
V
IL
I
I
f
mA
mA
MHz
OH
OL
clock
0
20
20
50
20
25
20
10
20
10
0
22
0
12.5
15
15
15
15
15
10
15
10
0
40
CLR high or low
t
w
Pulse duration
ns
’ALS160B, ’ALS161B CLR low
A, B, C, D
LOAD
’ALS160B, ’ALS161B
Setup time
before CLK↑
ENP, ENT
t
su
’ALS162B, ’ALS163B
CLR inactive
ns
’ALS160B, ’ALS161B
CLR low
’ALS162B, ’ALS163B
CLR high (inactive)
t
h
Hold time, all synchronous inputs after CLK↑
ns
T
A
Operating free-air temperature
−55
125
0
70
°C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54ALS160B
THRU
SN54ALS163B
SN74ALS160B
THRU
SN74ALS163B
PARAMETER
TEST CONDITIONS
UNIT
†
TYP
†
TYP
MIN
MAX
MIN
MAX
V
V
V
V
V
V
V
V
V
V
V
= 4.5 V,
I = −18 mA
−1.5
−1.5
V
V
IK
CC
I
= 4.5 V to 5.5 V,
= 4.5 V,
I
I
I
= −0.4 mA
= 4 mA
V
−2
V
−2
OH
CC
OH
OL
OL
CC
CC
0.25
0.4
0.25
0.35
0.4
0.5
CC
V
OL
V
= 4.5 V,
= 8 mA
CC
I
I
I
I
I
5.5 V,
V = 7 V
I
V = 2.7 V
I
V = 0.4 V
I
0.1
20
0.1
mA
µA
I
CC =
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V
20
IH
IL
CC
CC
CC
CC
−0.2
−112
21
−0.2
−112
21
mA
mA
mA
‡
V
O
= 2.25 V
−30
−30
O
12
12
CC
†
‡
All typical values are at V
= 5 V, T = 25°C.
CC
A
The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, I
.
OS
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
ꢀ
ꢀ
ꢁ
ꢁ
ꢂ
ꢑ
ꢃ
ꢃ
ꢄ
ꢄ
ꢅ
ꢅ
ꢀ
ꢀ
ꢆ
ꢇ
ꢈ
ꢈ
ꢉ
ꢉ
ꢊ
ꢊ
ꢋ
ꢋ
ꢌ
ꢌ
ꢍ
ꢍ
ꢎ
ꢎ
ꢊ
ꢊ
ꢀ
ꢀ
ꢁ
ꢁ
ꢂ
ꢑ
ꢃ
ꢃ
ꢄ
ꢅ
ꢀ
ꢆ
ꢇ
ꢇ
ꢏ
ꢏ
ꢉ
ꢉ
ꢙ
ꢆꢇ
ꢄꢅ
ꢀꢆ
ꢀ
ꢒ
ꢁ
ꢓ
ꢌ
ꢍ
ꢔ
ꢁ
ꢔ
ꢎ
ꢀ
ꢊ
ꢃ
ꢕ
ꢉ
ꢖ
ꢋ
ꢊ
ꢉ
ꢖ
ꢁ
ꢄ
ꢍ
ꢒ
ꢊ
ꢓ
ꢔ
ꢎ
ꢁ
ꢋ
ꢘ
ꢍ
ꢀ
SDAS024A − D2661, APRIL 1982 − REVISED MAY 1986
’ALS160B, ’ALS161B switching characteristics (see Note 1)
V
C
= 4.5 V to 5.5 V,
= 50 pF,
CC
L
L
R
= 500 Ω,
T
A
= MIN to MAX
FROM
TO
PARAMETER
UNIT
(INPUT)
(OUTPUT)
SN54ALS160B
SN54ALS161B
SN74ALS160B
SN74ALS161B
MIN
22
5
MAX
MIN
40
5
MAX
f
t
t
t
t
t
t
t
t
MHz
ns
max
PLH
PHL
PLH
PHL
PLH
PHL
PHL
PHL
34
27
19
25
18
17
27
32
20
20
15
20
13
13
24
23
CLK
CLK
ENT
RCO
5
5
4
4
Any Q
ns
ns
6
6
3
3
RCO
3
3
CLR
CLR
Any Q
RCO
8
8
ns
ns
11
11
’ALS162B, ’ALS163B switching characteristics (see Note 1)
V
C
= 4.5 V to 5.5 V,
= 50 pF,
CC
L
L
R
= 500 Ω,
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
T
A
= MIN to MAX
SN54ALS162B
SN54ALS163B
SN74ALS162B
SN74ALS163B
MIN
35
5
MAX
MIN
40
5
MAX
f
t
t
t
t
t
t
MHz
ns
max
PLH
PHL
PLH
PHL
PLH
PHL
25
25
18
25
16
16
20
20
15
20
13
13
CLK
CLK
ENT
RCO
5
5
4
4
Any Q
ns
ns
6
6
3
3
RCO
3
3
NOTE 1: Load circuit and voltage waveforms are shown in Section 1.
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
ꢀ
ꢀ
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢀ
ꢆ
ꢇ
ꢈ
ꢊ
ꢋ
ꢌ
ꢍ
ꢎ
ꢊ
ꢀ
ꢁ
ꢂ
ꢁ ꢑ ꢃꢄ ꢀꢆ ꢇꢈ ꢊ ꢋꢌ ꢍꢎ ꢊ ꢀꢁ ꢑ ꢃ ꢄ ꢀꢆ ꢇ
ꢃ
ꢄ
ꢀ
ꢆ
ꢇ
ꢏ
ꢏ
ꢙ
ꢒ
ꢁ
ꢓ
ꢌ
ꢍ
ꢔ
ꢁ
ꢔ
ꢎ
ꢀꢊ
ꢃ
ꢕ
ꢉ
ꢖ
ꢋ
ꢊꢗ
ꢘ
ꢓ
ꢄ
ꢗ
ꢘ
ꢊ
ꢓ
ꢔ
ꢎ
ꢁ
ꢋ
ꢘ
ꢍ
ꢀ
SDAS024A − D2661, APRIL 1982 − REVISED MAY 1986
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
CC
Input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Operating free-air temperature range: SN54AS160 thru SN54AS163 . . . . . . . . . . . . . . . . . −55°C to 125°C
SN74AS160 thru SN74AS163 . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
recommended operating conditions
SN54AS160
THRU
SN54AS163
SN74AS160
THRU
SN74AS163
UNIT
MIN NOM
MAX
MIN NOM
MAX
V
V
V
Supply voltage
4.5
2
5
5.5
4.5
2
5
5.5
V
V
CC
IH
High-level input voltage
Low-level input voltage
High-level output current
Low-level output current
Clock frequency
0.8
−2
20
65
0.8
−2
20
75
V
IL
I
I
f
mA
mA
MHz
OH
OL
clock
0
7.7
10
10
10
10
10
14
10
2
0
6.7
8
CLR high or low
t
w
Pulse duration
ns
’ALS160, ’ALS161 CLR low
A, B, C, D
8
LOAD
8
ENP, ENT
8
Setup time
before CLK↑
t
su
ns
’ALS160, ’ALS161 CLR inactive
8
CLR low
CLR high (inactive)
12
9
’ALS162, ’ALS163
t
h
Hold time, all synchronous inputs after CLK↑
0
ns
T
A
Operating free-air temperature
−55
125
0
70
°C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54AS160
THRU
SN54AS163
SN74AS160
THRU
SN74AS163
PARAMETER
TEST CONDITIONS
UNIT
†
TYP
†
TYP
MIN
MAX
MIN
MAX
V
V
V
V
V
V
= 4.5 V,
I = −18 mA
−1.2
−1.2
V
V
V
IK
CC
CC
CC
I
= 4.5 V to 5.5 V,
= 4.5 V,
I
I
= −2 mA
= 20 mA
V
CC
−2
V
CC
−2
OH
OL
OH
OL
0.25
0.5
0.3
0.25
0.5
0.3
LOAD
ENT
I
I
I
V
CC
V
CC
V
CC
= 5.5 V,
= 5.5 V,
= 5.5 V,
V = 7 V
I
0.2
0.2
mA
I
All other
LOAD
ENT
0.1
0.1
60
60
V = 2.7 V
I
40
40
µA
IH
IL
All other
LOAD
ENT
20
20
−1.5
−1
−1.5
−1
V = 0.4 V
I
mA
mA
All other
−0.5
−112
53
−0.5
−112
53
‡
I
I
V
V
= 5.5 V,
= 5.5 V
V = 2.25 V
O
−30
−30
O
CC
35
35
CC
CC
†
‡
All typical values are at V
= 5 V, T = 25°C.
A
CC
The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, I
.
OS
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
ꢀ
ꢀ
ꢁ
ꢁ
ꢀ
ꢂ
ꢃ
ꢄ
ꢄ
ꢀ
ꢀ
ꢖ
ꢆ
ꢆ
ꢋ
ꢇ
ꢇ
ꢈ
ꢊ
ꢋ
ꢋ
ꢌ
ꢌ
ꢄ
ꢍ
ꢍ
ꢍ
ꢎ
ꢎ
ꢒꢊ
ꢊ
ꢊ
ꢓ
ꢀ
ꢀ
ꢁ
ꢂ
ꢃ
ꢃ
ꢁ
ꢄ
ꢄ
ꢋ
ꢀ
ꢀ
ꢘ
ꢆ
ꢆ
ꢍ
ꢇ
ꢇ
ꢀ
ꢏ
ꢏ
ꢙ
ꢑꢃ
ꢈꢊ
ꢁꢑ
ꢀ
ꢒ
ꢁ
ꢓ
ꢌ
ꢍ
ꢔ
ꢁ
ꢔ
ꢎ
ꢊ
ꢃ
ꢕ
ꢉ
ꢊ
ꢉ
ꢖ
ꢁ
ꢔ
ꢎ
SDAS024A − D2661, APRIL 1982 − REVISED MAY 1986
’AS160, ’AS161 switching characteristics (see Note 1)
V
= 4.5 V to 5.5 V,
= 50 pF,
= 50 pF,
CC
C
C
R
L
L
L
FROM
(INPUT)
TO
(OUTPUT)
= 500 Ω,
UNIT
PARAMETER
T
A
= MIN to MAX
SN54AS160
SN54AS161
SN74AS160
SN74AS161
MIN
65
2
MAX
MIN
75
2
MAX
f
t
t
t
t
t
t
t
t
t
MHz
ns
max
PHL
PLH
PLH
PLH
PHL
PLH
PHL
PHL
PHL
RCO
14
8.5
17.5
7.5
14
12.5
8
CLK
RCO (with LOAD high)
RCO (with LOAD low)
1
1
3
3
16.5
7
1
1
CLK
ENT
Any Q
ns
ns
2
2
13
1.5
1
10
1.5
1
9
RCO
9.5
14
8.5
13
CLR
CLR
Any Q
RCO
2
2
ns
ns
2
14
2
12.5
’AS162, ’AS163 switching characteristics (see Note 1)
V
= 4.5 V to 5.5 V,
= 50 pF,
CC
L
L
C
R
T
= 500 Ω,
= MIN to MAX
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
A
SN54AS162
SN54AS163
SN74AS162
SN74AS163
MIN
65
2
MAX
MIN
75
2
MAX
f
t
t
t
t
t
t
t
MHz
ns
max
PHL
PLH
PLH
PLH
PHL
PLH
PHL
RCO
14
8.5
17.5
7.5
14
12.5
8
CLK
RCO (with LOAD high)
RCO (with LOAD low)
1
1
3
3
16.5
7
1
1
Any Q
ns
ns
CLK
ENT
2
2
13
9
1.5
1
10
1.5
1
RCO
9.5
8.5
NOTE 1: Load circuit and voltage waveforms are shown in Section 1.
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
ꢀ
ꢀ
ꢀ
ꢁ ꢂ ꢃꢄ ꢅ ꢀꢆ ꢇ ꢈꢉ ꢊ ꢋꢌ ꢍꢎ ꢊꢀ ꢁꢂ ꢃ ꢄꢅ ꢀꢆ ꢇ ꢏ ꢉ ꢐꢊꢀ ꢁꢂꢃ ꢄꢀꢆ ꢇ ꢈꢊ ꢋ ꢌꢍꢎꢊ ꢀꢁꢂ ꢃꢄꢀ ꢆꢇ ꢏ
ꢁ ꢑ ꢃꢄ ꢅ ꢀꢆ ꢇ ꢈꢉ ꢊ ꢋꢌ ꢍꢎ ꢊꢀ ꢁꢑ ꢃ ꢄꢅ ꢀꢆ ꢇ ꢏ ꢉ ꢐꢊꢀ ꢁꢑꢃ ꢄꢀꢆ ꢇ ꢈꢊ ꢋ ꢌꢍꢎꢊ ꢀꢁꢑ ꢃꢄꢀ ꢆꢇ ꢏ
ꢙ
ꢒ
ꢁꢓ
ꢌ
ꢍ
ꢔ
ꢁ
ꢔ
ꢎ
ꢀꢊ
ꢃ
ꢕ
ꢉ
ꢖ
ꢋ
ꢊꢗ
ꢘ
ꢓ
ꢄ
ꢗ
ꢘ
ꢊ
ꢓ
ꢔꢎ
ꢁ
ꢋ
ꢘ
ꢍ
ꢀ
SDAS024A − D2661, APRIL 1982 − REVISED MAY 1986
APPLICATION INFORMATION
N−bit synchronous counters
This application demonstrates how the ripple mode carry circuit (Figure 1) and the carry-look-ahead circuit
(Figure 2) can be used to implement a high-speed N-bit counter. The ’ALS160B, ’AS160, ’ALS162B, and ’AS162
will count in BCD and the ’ALS161B, ’AS161, ’ALS163B, and ’AS163 will count in binary. When additional stages
are added, the f
decreases in Figure 1 , but remains unchanged in Figure 2.
MAX
LSB
LSB
CTR
CTR
CLR
CLR
CLEAR (L)
CT=0
CLEAR (L)
CT=0
LOAD
ENT
ENP
CLK
LOAD
ENT
ENP
CLK
M1
G3
G4
M1
G3
G4
COUNT (H)
DISABLE (L)
COUNT (H)
DISABLE (L)
RCO
RCO
3CT=MAX
3CT=MAX
C5/T,3,4+
CLOCK
C5/T,3,4+
A
1,5D
Q
A
Q
B
A
1,5D
Q
A
Q
B
LOAD (L)
B
B
C
D
Q
C
Q
D
C
D
Q
C
Q
D
COUNT (H)
DISABLE (L)
LOAD (L)
CTR
CTR
CLR
CLR
CLOCK
CT=0
CT=0
LOAD
ENT
ENP
CLK
LOAD
ENT
ENP
CLK
M1
G3
G4
M1
G3
G4
RCO
RCO
3CT=MAX
3CT=MAX
C5/T,3,4+
C5/T,3,4+
A
1,5D
Q
A
Q
B
A
1,5D
Q
A
Q
B
B
B
C
D
Q
C
Q
D
C
D
Q
C
Q
D
CTR
CTR
CLR
CLR
CT=0
CT=0
LOAD
ENT
ENP
CLK
LOAD
ENT
ENP
CLK
M1
G3
G4
M1
G3
G4
RCO
RCO
3CT=MAX
3CT=MAX
C5/T,3,4+
C5/T,3,4+
A
1,5D
Q
A
Q
B
A
1,5D
Q
A
Q
B
B
B
C
D
Q
C
Q
D
C
D
Q
C
Q
D
CTR
CTR
CLR
CLR
CT=0
CT=0
LOAD
ENT
ENP
CLK
LOAD
ENT
ENP
CLK
M1
G3
G4
M1
G3
G4
RCO
RCO
3CT=MAX
3CT=MAX
C5/T,3,4+
C5/T,3,4+
A
1,5D
Q
A
Q
B
A
1,5D
Q
A
Q
B
B
B
C
D
Q
C
Q
D
C
D
Q
C
Q
D
To More Significant Stages
To More Significant Stages
f
= 1/(CLK to RCO
) + (ENP t )
su
f
= 1/(CLK to RCO t
PLH
) + (ENT to RCO t
PLH
) (N−2) + (ENT t )
su
MAX
tPLH
MAX
Figure 1. Ripple Mode Carry Circuit
Figure 2. Carry-Look-Ahesd Circuit
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Jul-2009
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74ALS161BDR
SN74ALS161BNSR
SN74ALS163BDR
SN74ALS163BNSR
SN74AS161NSR
SN74AS163NSR
SOIC
SO
D
16
16
16
16
16
16
2500
2000
2500
2000
2000
2000
330.0
330.0
330.0
330.0
330.0
330.0
16.4
16.4
16.4
16.4
16.4
16.4
6.5
8.2
6.5
8.2
8.2
8.2
10.3
10.5
10.3
10.5
10.5
10.5
2.1
2.5
2.1
2.5
2.5
2.5
8.0
12.0
8.0
16.0
16.0
16.0
16.0
16.0
16.0
Q1
Q1
Q1
Q1
Q1
Q1
NS
D
SOIC
SO
NS
NS
NS
12.0
12.0
12.0
SO
SO
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Jul-2009
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN74ALS161BDR
SN74ALS161BNSR
SN74ALS163BDR
SN74ALS163BNSR
SN74AS161NSR
SN74AS163NSR
SOIC
SO
D
16
16
16
16
16
16
2500
2000
2500
2000
2000
2000
333.2
346.0
333.2
346.0
346.0
346.0
345.9
346.0
345.9
346.0
346.0
346.0
28.6
33.0
28.6
33.0
33.0
33.0
NS
D
SOIC
SO
NS
NS
NS
SO
SO
Pack Materials-Page 2
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