SN74F169DE4 [ROCHESTER]
Binary Counter, F/FAST Series, Synchronous, Positive Edge Triggered, 4-Bit, Bidirectional, TTL, PDSO16, GREEN, PLASTIC, MS-012AC, SOIC-16;
| 型号： | SN74F169DE4 |
| 厂家： | 
Rochester Electronics |
| 描述： | Binary Counter, F/FAST Series, Synchronous, Positive Edge Triggered, 4-Bit, Bidirectional, TTL, PDSO16, GREEN, PLASTIC, MS-012AC, SOIC-16 光电二极管 输出元件 逻辑集成电路 触发器 |
| 文件： | 总13页 (文件大小：295K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ꢀꢁ ꢂꢃ ꢄꢅꢆ ꢇ
ꢀꢈ ꢁꢉꢊꢋꢌ ꢁꢌ ꢍꢀ ꢎꢃ ꢏꢐꢑꢒ ꢎ ꢍꢓꢔꢕ ꢌꢖ ꢁꢎꢐꢑ ꢁꢗꢋꢈꢎꢉꢌ ꢍ ꢁꢒ ꢘꢋ
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SDFS089 − MARCH 1987 − REVISED OCTOBER 1993
D OR N PACKAGE
(TOP VIEW)
• Fully Synchronous Operation for Counting
and Programming
• Internal Look-Ahead Circuitry for Fast
V
RCO
Q
U/D
CLK
A
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CC
Counting
• Carry Output for N-Bit Cascading
• Fully Independent Clock Circuit
A
Q
B
Q
B
C
D
• Package Options Include Plastic
Small-Outline Packages and Standard
Plastic 300-mil DIPs
C
Q
D
ENT
ENP
GND
LOAD
description
This synchronous, presettable, 4-bit up/down binary counter features an internal carry look-ahead circuitry for
cascading in high-speed counting applications. Synchronous operation is provided by having all flip-flops
clocked simultaneously so that the outputs change coincident with each other when so instructed by the
count-enable (ENP, ENT) inputs and internal gating. This mode of operation eliminates the output counting
spikes that are normally associated with asynchronous (ripple-clock) counters. A buffered clock (CLK) input
triggers the four flip-flops on the rising (positive-going) edge of the clock waveform.
This counter is fully programmable; that is, it may be preset to any number between 0 and its maximum count.
The load-input circuitry allows loading with the carry-enable output of cascaded counters. As loading is
synchronous, setting up a low level at the load (LOAD) input disables the counter and causes the outputs to
agree with the data inputs after the next clock pulse.
The carry look-ahead circuitry provides for cascading counters for n-bit synchronous application without
additional gating. Instrumental in accomplishing this function are two count-enable (ENP, ENT) inputs and a
ripple-carry (RCO) output. Both ENP and ENT must be low to count. The direction of the count is determined
by the level of the up/down (U/D) input. When U/D is high, the counter counts up; when low, it counts down. Input
ENT is fed forward to enable the RCO. RCO thus enabled will produce a low-level pulse while the count is zero
(all inputs low) counting down or maximum (9 or 15) counting up. This low-level overflow ripple-carry pulse can
be used to enable successive cascaded stages. Transitions at ENP or ENT are allowed regardless of the level
of the clock input. All inputs are diode clamped to minimize transmission-line effects, thereby simplifying system
design.
The SN74F169 features a fully independent clock circuit. Changes at control inputs (ENP, ENT, LOAD or U/D)
that will modify the operating mode have no effect on the contents of the counter until clocking occurs. The
function of the counter (whether enabled, disabled, loading, or counting) will be dictated solely by the conditions
meeting the setup and hold times.
The SN74F169 is characterized for operation from 0°C to 70°C.
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Copyright 1993, Texas Instruments Incorporated
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2−1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢇ
ꢀꢈ ꢁꢉ ꢊ ꢋ ꢌꢁ ꢌꢍ ꢀꢎ ꢃ ꢏꢐꢑ ꢒ ꢎꢍꢓ ꢔ ꢕꢌꢖꢁ ꢎ ꢐꢑꢁꢗ ꢋꢈꢎꢉ ꢌꢍ ꢁꢒꢘ ꢋ
ꢙ
SDFS089 − MARCH 1987 − REVISED OCTOBER 1993
†
logic symbol
CTRDIV16
9
M1 [LOAD]
M2 [COUNT]
LOAD
1
M3 [UP]
U/D
M4 [DOWN]
15
10
RCO
3,5CT = 15
4,5CT = 0
G5
G6
ENT
7
ENP
2
CLK
2,3,5,6+/C7
2,4,5,6 −
3
14
13
12
11
Q
A
1
2
4
8
A
4
1, 7D
Q
B
B
5
Q
C
C
6
Q
D
D
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
2−2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁꢂ ꢃꢄ ꢅꢆꢇ
ꢀꢈ ꢁꢉꢊꢋꢌ ꢁꢌ ꢍꢀ ꢎꢃ ꢏꢐꢑꢒ ꢎ ꢍꢓꢔꢕ ꢌꢖ ꢁꢎꢐꢑ ꢁꢗꢋꢈꢎꢉꢌ ꢍ ꢁꢒ ꢘꢋ
ꢙ
SDFS089 − MARCH 1987 − REVISED OCTOBER 1993
logic diagram (positive logic)
9
LOAD
1
U/D
10
ENT
7
ENP
15
RCO
2
CLK
G2
1, 2T/C3
14
13
12
11
Q
A
Q
B
Q
C
Q
D
3
1, 3D
M1
A
G2
1, 2T/C3
4
1, 3D
M1
B
G2
1, 2T/C3
5
1, 3D
M1
C
G2
1, 2T/C3
6
1, 3D
M1
D
2−3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢇ
ꢀꢈ ꢁꢉ ꢊ ꢋ ꢌꢁ ꢌꢍ ꢀꢎ ꢃ ꢏꢐꢑ ꢒ ꢎꢍꢓ ꢔ ꢕꢌꢖꢁ ꢎ ꢐꢑꢁꢗ ꢋꢈꢎꢉ ꢌꢍ ꢁꢒꢘ ꢋ
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SDFS089 − MARCH 1987 − REVISED OCTOBER 1993
logic symbol, each flip-flop
TE
G2
1, 2T/C3
1, 3D
M1
Q1
Q2
Q1
Q2
CLK
DATA
LOAD
logic diagram, each flip-flop (positive logic)
TE
(Toggle
Enable)
CLK
Q1
Q2
DATA
LOAD
Q1
Q2
FUNCTION TABLE
(each flip-flop)
COUNTER
INPUTS
FLIP-FLOP INPUTS
OUTPUTS
LOAD CLK LOAD
TE
L
CLK DATA
Q
H
L
Q
L
L
L
↑
↑
↑
↑
H
H
L
↓
↓
↓
↓
H
L
L
H
H
H
H
L
X
X
Q
Q
0
0
0
0
L
Q
Q
2−4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁꢂ ꢃꢄ ꢅꢆꢇ
ꢀꢈ ꢁꢉꢊꢋꢌ ꢁꢌ ꢍꢀ ꢎꢃ ꢏꢐꢑꢒ ꢎ ꢍꢓꢔꢕ ꢌꢖ ꢁꢎꢐꢑ ꢁꢗꢋꢈꢎꢉꢌ ꢍ ꢁꢒ ꢘꢋ
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SDFS089 − MARCH 1987 − REVISED OCTOBER 1993
typical load, count, and inhibit sequences
Illustrated below is the following sequence:
1. Load (preset) to binary thirteen
2. Count up to fourteen, fifteen (maximum), zero, one, and two
3. Inhibit
4. Count down to one, zero (minimum), fifteen, fourteen, and thirteen
LOAD
A
B
Data
Inputs
C
D
CLK
U/D
ENP and ENT
Q
A
Q
Q
Q
B
C
D
Data
Outputs
RCO
13
14
15
0
1
2
2
2
1
0
15
14
13
Count Up
Inhibit
Count Down
Load
2−5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢇ
ꢀꢈ ꢁꢉ ꢊ ꢋ ꢌꢁ ꢌꢍ ꢀꢎ ꢃ ꢏꢐꢑ ꢒ ꢎꢍꢓ ꢔ ꢕꢌꢖꢁ ꢎ ꢐꢑꢁꢗ ꢋꢈꢎꢉ ꢌꢍ ꢁꢒꢘ ꢋ
ꢙ
SDFS089 − MARCH 1987 − REVISED OCTOBER 1993
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −1.2 V to 7 V
I
Input current range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −30 mA to 5 mA
Voltage range applied to any output in the high state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V
CC
Current into any output in the low state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 mA
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input voltage ratings may be exceeded provided the input current ratings are observed.
recommended operating conditions
MIN NOM
MAX
UNIT
V
V
V
V
Supply voltage
4.5
2
5
5.5
CC
IH
IL
High-level input voltage
Low-level input voltage
Input clamp current
V
0.8
−18
− 1
20
V
I
I
I
mA
mA
mA
°C
IK
High-level output current
Low-level output current
Operating free-air temperature
OH
OL
T
A
0
70
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
‡
PARAMETER
TEST CONDITIONS
I = −18 mA
MIN TYP
MAX
UNIT
V
IK
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 4.5 V,
= 4.5 V,
= 4.75 V,
= 4.5 V,
= 5.5 V,
= 5.5 V,
−1.2
V
I
I
I
I
= − 1 mA
= − 1 mA
= 20 mA
2.5
2.7
3.4
0.3
OH
OH
OL
V
V
OH
OL
V
0.5
0.1
V
I
I
V = 7 V
I
mA
µA
I
V = 2.7 V
I
20
IH
ENT
All others
− 1.2
− 0.6
−150
52
I
V
= 5.5 V,
V = 0.5 V
mA
IL
CC
I
§
I
I
V
V
= 5.5 V,
= 5.5 V,
V = 0
O
−60
mA
mA
OS
CC
CC
See Note 2
38
CC
‡
§
All typical values are at V
CC
= 5 V, T = 25°C.
A
Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.
NOTE 2:
I
is measured after applying a momentary 4.5 V, then ground, to the clock input with B and ENT inputs high and all other inputs low.
CC
2−6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁꢂ ꢃꢄ ꢅꢆꢇ
ꢀꢈ ꢁꢉꢊꢋꢌ ꢁꢌ ꢍꢀ ꢎꢃ ꢏꢐꢑꢒ ꢎ ꢍꢓꢔꢕ ꢌꢖ ꢁꢎꢐꢑ ꢁꢗꢋꢈꢎꢉꢌ ꢍ ꢁꢒ ꢘꢋ
ꢙ
SDFS089 − MARCH 1987 − REVISED OCTOBER 1993
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
V
T
= 5 V,
= 25°C
CC
A
MIN
MAX
UNIT
MIN
0
MAX
f
t
Clock frequency
Pulse duration
100
0
5.5
4.5
9
90
MHz
ns
clock
CLK high or low
5
w
Data before CLK↑
High or low
High or low
High or low
High
4
8
LOAD before CLK↑
ENP and ENT before CLK↑
t
su
Setup time
Hold time
5
6
ns
ns
11
7
12.5
8
U/D before CLK↑
Low
Data after CLK↑
High or low
High or low
High or low
High or low
3
3.5
0
0
LOAD after CLK↑
ENP and ENT after CLK↑
U/D after CLK↑
t
h
0
0
0
0
switching characteristics (see Note 3)
V
C
R
= 5 V,
= 50 pF,
= 500 Ω,
= 25°C
V
C
R
= 4.5 V to 5.5 V,
= 50 pF,
CC
L
L
CC
L
L
FROM
PARAMETER
TO
(OUTPUT)
= 500Ω,
= MIN to MAX
UNIT
(INPUT)
†
T
A
T
A
MIN
100
2.2
3.2
4.7
3.2
1.7
1.7
2.7
3.2
TYP
115
6.1
8.6
11.6
8.1
4.1
5.6
8.1
7.6
MAX
MIN
90
MAX
f
MHz
ns
max
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
t
t
t
t
t
t
t
t
8.5
11.5
15.5
11
2.2
3.2
4.7
3.2
1.7
1.7
2.7
3.2
9.5
13
CLK
CLK
ENT
U/D
Q
17
RCO
RCO
RCO
ns
ns
ns
12.5
7
6
8
9
11
12.5
12
10.5
†
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
NOTE 3: Load circuits and waveforms are shown in Section 1.
2−7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
2−8
PACKAGE OPTION ADDENDUM
www.ti.com
29-Apr-2010
PACKAGING INFORMATION
Orderable Device
SN74F169D
Status (1)
NRND
NRND
NRND
NRND
NRND
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOIC
D
16
16
16
16
16
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74F169DE4
SN74F169DG4
SN74F169N
SOIC
SOIC
PDIP
PDIP
D
D
N
N
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
SN74F169NE4
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
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reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
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information may not be available for release.
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Addendum-Page 1
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