SN74LVC3G04YZPR

更新时间:2024-10-29 18:36:02
品牌:ROCHESTER
描述:LVC/LCX/Z SERIES, TRIPLE 1-INPUT INVERT GATE, BGA8, GREEN, WCSP-8

SN74LVC3G04YZPR 概述

LVC/LCX/Z SERIES, TRIPLE 1-INPUT INVERT GATE, BGA8, GREEN, WCSP-8 栅极

SN74LVC3G04YZPR 规格参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:BGA
包装说明:GREEN, WCSP-8针数:8
Reach Compliance Code:unknown风险等级:5.69
系列:LVC/LCX/ZJESD-30 代码:R-XBGA-B8
JESD-609代码:e1长度:1.9 mm
逻辑集成电路类型:INVERTER湿度敏感等级:1
功能数量:3输入次数:1
端子数量:8最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
封装主体材料:UNSPECIFIED封装代码:VFBGA
封装形状:RECTANGULAR封装形式:GRID ARRAY, VERY THIN PROFILE, FINE PITCH
峰值回流温度(摄氏度):260传播延迟(tpd):7.9 ns
座面最大高度:0.5 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):1.65 V标称供电电压 (Vsup):1.8 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:TIN SILVER COPPER
端子形式:BALL端子节距:0.5 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:0.9 mmBase Number Matches:1

SN74LVC3G04YZPR 数据手册

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SN74LVC3G04  
TRIPLE INVERTER GATE  
www.ti.com  
SCES363IAUGUST 2001REVISED OCTOBER 2006  
FEATURES  
Available in the Texas Instruments  
NanoStar™ and NanoFree™ Packages  
Ioff Supports Partial-Power-Down Mode  
Operation  
Supports 5-V VCC Operation  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
Inputs Accept Voltages to 5.5 V  
Max tpd of 4.1 ns at 3.3 V  
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
Low Power Consumption, 10-µA Max ICC  
±24-mA Output Drive at 3.3 V  
– 1000-V Charged-Device Model (C101)  
Typical VOLP (Output Ground Bounce) <0.8 V  
at VCC = 3.3 V, TA = 25°C  
Typical VOHV (Output VOH Undershoot) >2 V at  
VCC = 3.3 V, TA = 25°C  
DCT PACKAGE  
(TOP VIEW)  
DCU PACKAGE  
(TOP VIEW)  
YEP OR YZP PACKAGE  
(BOTTOM VIEW)  
4 5  
2Y  
3A  
1Y  
GND  
2A  
3Y  
1A  
3B  
2A  
V
CC  
1
2
3
4
8
7
6
5
3 6  
1
2
8
7
1A  
3Y  
V
CC  
1Y  
3A  
2Y  
2
7
1A  
1 8  
V
CC  
1Y  
GND  
3
4
6
5
2A  
3A  
2Y  
GND  
See mechanical drawings for dimensions.  
DESCRIPTION/ORDERING INFORMATION  
This triple inverter is designed for 1.65-V to 5.5-V VCC operation. The SN74LVC3G04 performs the Boolean  
function Y = A.  
NanoStar™ and NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the  
die as the package.  
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,  
preventing damaging current backflow through the device when it is powered down.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
NanoStar, NanoFree are trademarks of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2001–2006, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
SN74LVC3G04  
TRIPLE INVERTER GATE  
www.ti.com  
SCES363IAUGUST 2001REVISED OCTOBER 2006  
ORDERING INFORMATION  
TA  
PACKAGE(1)  
ORDERABLE PART NUMBER TOP-SIDE MARKING(2)  
NanoStar™ – WCSP (DSBGA)  
0.17-mm Small Bump – YEA  
SN74LVC3G04YEAR  
NanoFree™ – WCSP (DSBGA)  
0.17-mm Small Bump – YZA (Pb-free)  
SN74LVC3G04YZAR  
_ _ _CC_  
Reel of 3000  
NanoStar™ – WCSP (DSBGA)  
0.23-mm Large Bump – YEP  
SN74LVC3G04YEPR  
–40°C to 85°C  
NanoFree™ – WCSP (DSBGA)  
0.23-mm Large Bump – YZP (Pb-free)  
SN74LVC3G04YZPR  
SSOP – DCT  
Reel of 3000  
Reel of 3000  
Reel of 250  
SN74LVC3G04DCTR  
SN74LVC3G04DCUR  
SN74LVC3G04DCUT  
C04_ _ _  
C04_  
VSSOP – DCU  
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
(2) DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site.  
DCU: The actual top-side marking has one additional character that designates the assembly/test site.  
YEA/YZA, YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one  
following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, = Pb-free).  
FUNCTION TABLE  
(EACH INVERTER)  
INPUT  
A
OUTPUT  
Y
H
L
L
H
LOGIC DIAGRAM (POSITIVE LOGIC)  
1
3
6
7
5
2
1A  
2A  
3A  
1Y  
2Y  
3Y  
2
Submit Documentation Feedback  
SN74LVC3G04  
TRIPLE INVERTER GATE  
www.ti.com  
SCES363IAUGUST 2001REVISED OCTOBER 2006  
Absolute Maximum Ratings(1)  
over operating free-air temperature range (unless otherwise noted)  
MIN  
–0.5  
–0.5  
MAX UNIT  
VCC  
VI  
Supply voltage range  
Input voltage range(2)  
6.5  
6.5  
V
V
Voltage range applied to any output  
VO  
–0.5  
–0.5  
6.5  
V
when the output is in the high-impedance or power-off state(2)  
VO  
IIK  
Voltage range applied to any output when the output is in the high or low state(2)(3)  
VCC + 0.5  
–50  
V
Input clamp current  
VI < 0  
mA  
mA  
mA  
mA  
IOK  
IO  
Output clamp current  
VO < 0  
–50  
Continuous output current  
Continuous current through VCC or GND  
±50  
±100  
220  
DCT package  
DCU package  
227  
θJA  
Package thermal impedance(4)  
°C/W  
°C  
YEA/YZA package  
YEP/YZP package  
140  
102  
Tstg  
Storage temperature range  
–65  
150  
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings  
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating  
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.  
(3) The value of VCC is provided in the recommended operating conditions table.  
(4) The package thermal impedance is calculated in accordance with JESD 51-7.  
3
Submit Documentation Feedback  
SN74LVC3G04  
TRIPLE INVERTER GATE  
www.ti.com  
SCES363IAUGUST 2001REVISED OCTOBER 2006  
Recommended Operating Conditions(1)  
MIN  
1.65  
MAX UNIT  
Operating  
5.5  
V
VCC  
Supply voltage  
Data retention only  
VCC = 1.65 V to 1.95 V  
VCC = 2.3 V to 2.7 V  
VCC = 3 V to 3.6 V  
VCC = 4.5 V to 5.5 V  
VCC = 1.65 V to 1.95 V  
VCC = 2.3 V to 2.7 V  
VCC = 3 V to 3.6 V  
VCC = 4.5 V to 5.5 V  
1.5  
0.65 × VCC  
1.7  
VIH  
High-level input voltage  
V
2
0.7 × VCC  
0.35 × VCC  
0.7  
VIL  
Low-level input voltage  
V
0.8  
0.3 × VCC  
5.5  
VCC  
–4  
VI  
Input voltage  
0
0
V
V
VO  
Output voltage  
VCC = 1.65 V  
VCC = 2.3 V  
–8  
IOH  
High-level output current  
Low-level output current  
–16  
–24  
–32  
4
mA  
mA  
VCC = 3 V  
VCC = 4.5 V  
VCC = 1.65 V  
VCC = 2.3 V  
8
IOL  
16  
VCC = 3 V  
24  
VCC = 4.5 V  
32  
VCC = 1.8 V ± 0.15 V, 2.5 V ± 0.2 V  
VCC = 3.3 V ± 0.3 V  
VCC = 5 V ± 0.5 V  
20  
t/v  
Input transition rise or fall rate  
Operating free-air temperature  
10  
ns/V  
°C  
5
TA  
–40  
85  
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,  
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.  
4
Submit Documentation Feedback  
SN74LVC3G04  
TRIPLE INVERTER GATE  
www.ti.com  
SCES363IAUGUST 2001REVISED OCTOBER 2006  
Electrical Characteristics  
over recommended operating free-air temperature range (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
VCC  
1.65 V to 5.5 V  
1.65 V  
MIN TYP(1)  
VCC – 0.1  
MAX UNIT  
IOH = –100 µA  
IOH = –4 mA  
1.2  
1.9  
2.4  
2.3  
3.8  
IOH = –8 mA  
2.3 V  
VOH  
V
IOH = –16 mA  
3 V  
IOH = –24 mA  
IOH = –32 mA  
4.5 V  
1.65 V to 5.5 V  
1.65 V  
IOL = 100 µA  
0.1  
IOL = 4 mA  
0.45  
IOL = 8 mA  
2.3 V  
0.3  
V
VOL  
IOL = 16 mA  
0.4  
3 V  
IOL = 24 mA  
0.55  
0.55  
IOL = 32 mA  
4.5 V  
0 to 5.5 V  
0
II  
A inputs VI = 5.5 V or GND  
VI or VO = 5.5 V  
VI = 5.5 V or GND,  
±5  
±10  
10  
µA  
µA  
µA  
µA  
pF  
Ioff  
ICC  
ICC  
Ci  
IO = 0  
1.65 V to 5.5 V  
3 V to 5.5 V  
3.3 V  
One input at VCC – 0.6 V,  
VI = VCC or GND  
Other inputs at VCC or GND  
500  
3.5  
(1) All typical values are at VCC = 3.3 V, TA = 25°C.  
Switching Characteristics  
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)  
VCC = 1.8 V  
± 0.15 V  
VCC = 2.5 V  
± 0.2 V  
VCC = 3.3 V  
± 0.3 V  
VCC = 5 V  
± 0.5 V  
FROM  
(INPUT)  
TO  
(OUTPUT)  
PARAMETER  
UNIT  
MIN  
MAX  
MIN  
MAX  
4.4  
MIN MAX  
1.4 4.1  
MIN  
MAX  
3.2  
tpd  
A
Y
3.2  
7.9  
1.5  
1.1  
ns  
Operating Characteristics  
TA = 25°C  
VCC = 1.8 V  
TYP  
VCC = 2.5 V  
TYP  
VCC = 3.3 V  
TYP  
VCC = 5 V  
TYP  
PARAMETER  
TEST CONDITIONS  
UNIT  
Cpd  
Power dissipation capacitance  
f = 10 MHz  
16  
16  
16  
18  
pF  
5
Submit Documentation Feedback  
SN74LVC3G04  
TRIPLE INVERTER GATE  
www.ti.com  
SCES363IAUGUST 2001REVISED OCTOBER 2006  
PARAMETER MEASUREMENT INFORMATION  
V
LOAD  
S1  
Open  
R
L
From Output  
Under Test  
TEST  
/t  
S1  
GND  
t
t
Open  
PLH PHL  
C
L
t
/t  
V
R
L
PLZ PZL  
LOAD  
GND  
(see Note A)  
/t  
PHZ PZH  
LOAD CIRCUIT  
INPUTS  
V
CC  
V
M
V
LOAD  
C
L
R
L
V
V
I
t /t  
r f  
1.8 V ± 0.15 V  
2.5 V ± 0.2 V  
3.3 V ± 0.3 V  
5 V ± 0.5 V  
V
V
3 V  
2 ns  
2 ns  
2.5 ns  
2.5 ns  
V
/2  
/2  
2 × V  
2 × V  
6 V  
2 × V  
CC  
30 pF  
30 pF  
50 pF  
50 pF  
1 kΩ  
500 Ω  
500 Ω  
500 Ω  
0.15 V  
0.15 V  
0.3 V  
CC  
CC  
CC  
V
CC  
CC  
CC  
1.5 V  
/2  
V
CC  
V
CC  
0.3 V  
V
I
Timing Input  
Data Input  
V
M
0 V  
t
w
t
t
h
su  
V
I
V
I
Input  
V
M
V
M
V
M
V
M
0 V  
0 V  
VOLTAGE WAVEFORMS  
PULSE DURATION  
VOLTAGE WAVEFORMS  
SETUP AND HOLD TIMES  
V
I
V
I
Output  
Control  
V
M
V
M
Input  
V
M
V
M
0 V  
0 V  
t
t
t
t
t
PHL  
PZL  
PLZ  
PLH  
Output  
Waveform 1  
V
V
OH  
V
V
/2  
LOAD  
V
V
V
M
M
Output  
V
V
M
S1 at V  
LOAD  
V
OL  
+ V  
OL  
(see Note B)  
OL  
t
PHL  
PLH  
t
t
PHZ  
PZH  
Output  
Waveform 2  
S1 at GND  
V
V
OH  
V
OH  
V
− V  
V
M
OH  
M
Output  
M
0 V  
OL  
(see Note B)  
VOLTAGE WAVEFORMS  
PROPAGATION DELAY TIMES  
INVERTING AND NONINVERTING OUTPUTS  
VOLTAGE WAVEFORMS  
ENABLE AND DISABLE TIMES  
LOW- AND HIGH-LEVEL ENABLING  
NOTES: A. C includes probe and jig capacitance.  
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.  
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.  
C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, Z = 50 .  
O
D. The outputs are measured one at a time, with one transition per measurement.  
E.  
F.  
G.  
t
t
t
and t  
and t  
and t  
are the same as t  
.
dis  
.
PLZ  
PZL  
PLH  
PHZ  
are the same as t  
PZH  
en  
are the same as t .  
PHL pd  
H. All parameters and waveforms are not applicable to all devices.  
Figure 1. Load Circuit and Voltage Waveforms  
6
Submit Documentation Feedback  
PACKAGE OPTION ADDENDUM  
www.ti.com  
18-Jul-2006  
PACKAGING INFORMATION  
Orderable Device  
SN74LVC3G04DCTR  
SN74LVC3G04DCTRE4  
SN74LVC3G04DCUR  
SN74LVC3G04DCURE4  
SN74LVC3G04DCUT  
SN74LVC3G04DCUTE4  
Status (1)  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
Package Package  
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)  
Qty  
Type  
Drawing  
SM8  
DCT  
8
8
8
8
8
8
3000  
Pb-Free  
(RoHS)  
CU NIPDAU Level-1-260C-UNLIM  
SM8  
US8  
US8  
US8  
US8  
DCT  
DCU  
DCU  
DCU  
DCU  
3000  
Pb-Free  
(RoHS)  
CU NIPDAU Level-1-260C-UNLIM  
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
SN74LVC3G04YEAR  
SN74LVC3G04YEPR  
SN74LVC3G04YZAR  
NRND  
NRND  
NRND  
WCSP  
WCSP  
WCSP  
YEA  
YEP  
YZA  
8
8
8
3000  
3000  
TBD  
TBD  
SNPB  
SNPB  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
3000 Green (RoHS &  
no Sb/Br)  
SNAGCU  
SN74LVC3G04YZPR  
ACTIVE  
WCSP  
YZP  
8
3000 Green (RoHS &  
no Sb/Br)  
SNAGCU  
Level-1-260C-UNLIM  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in  
a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2)  
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check  
http://www.ti.com/productcontent for the latest availability information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements  
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered  
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and  
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS  
compatible) as defined above.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame  
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)  
(3)  
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder  
temperature.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is  
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the  
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take  
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on  
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited  
information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI  
to Customer on an annual basis.  
Addendum-Page 1  
MECHANICAL DATA  
MPDS049B – MAY 1999 – REVISED OCTOBER 2002  
DCT (R-PDSO-G8)  
PLASTIC SMALL-OUTLINE PACKAGE  
0,30  
0,15  
M
0,13  
0,65  
8
5
0,15 NOM  
2,90  
2,70  
4,25  
3,75  
Gage Plane  
PIN 1  
INDEX AREA  
0,25  
1
4
0° – 8°  
0,60  
0,20  
3,15  
2,75  
1,30 MAX  
Seating Plane  
0,10  
0,10  
0,00  
4188781/C 09/02  
NOTES: A. All linear dimensions are in millimeters.  
B. This drawing is subject to change without notice.  
C. Body dimensions do not include mold flash or protrusion  
D. Falls within JEDEC MO-187 variation DA.  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
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